From 355f637b952396e1a1fef8c5596d8097397482f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ayberk=20=C3=96zg=C3=BCr?= Date: Sun, 18 Aug 2019 17:25:16 +0200 Subject: [PATCH] README improvement --- README.md | 43 +++++++++++++++++++++++++++++++------------ 1 file changed, 31 insertions(+), 12 deletions(-) diff --git a/README.md b/README.md index f53afcb..5aea0c1 100644 --- a/README.md +++ b/README.md @@ -3,21 +3,39 @@ jlcpcb-design-rules-stackups JLCPCB design rules and stackups for Altium Designer. -Design rules include: +Design rules +------------ - - **2 layer** - - **1 oz copper**: 5mil trace & clearance, 0.3mm hole, 0.6mm via diameter, 0.25mm hole clearance - - **2 oz copper**: 8mil trace & clearance, 0.3mm hole, 0.6mm via diameter, 0.25mm hole clearance - - **4 layer** - - **1 oz copper** on top & bottom layers: 3.5mil trace & clearance on all layers, 5mil via clearance, 0.2mm hole, 0.45mm via diameter, 0.25mm hole clearance - - **2 oz copper** on top & bottom layers: 3.5mil trace & clearance on mid layers, 5mil via clearance, 8mil trace & clearance on top & bottom layers, 0.2mm hole, 0.45mm via diameter, 0.25mm hole clearance - - **6 layer** - - **1 oz copper** on top & bottom layers: 3.5mil trace & clearance on all layers, 5mil via clearance, 0.2mm hole, 0.45mm via diameter, 0.25mm hole clearance - - **2 oz copper** on top & bottom layers: 3.5mil trace & clearance on mid layers, 5mil via clearance, 8mil trace & clearance on top & bottom layers, 0.2mm hole, 0.45mm via diameter, 0.25mm hole clearance + - 2 layer + - 1 oz copper + - 5mil trace with & clearance + - 0.3mm min. hole diameter + - 0.6mm min. via diameter + - 0.25mm hole clearance + - 2 oz copper + - 8mil trace width & clearance + - 0.3mm min. hole diameter + - 0.6mm min. via diameter + - 0.25mm hole clearance + - 4 layer / 6 layer + - 1 oz copper on top & bottom layers, 0.5 oz copper on mid layers + - 3.5mil trace width & clearance on all layers + - 0.2mm min. hole diameter + - 0.45mm min. via diameter + - 5mil via clearance + - 0.25mm hole clearance + - 2 oz copper on top & bottom layers, 0.5 oz copper on mid layers + - 3.5mil trace width & clearance on mid layers + - 8mil trace width & clearance on top & bottom layers + - 0.2mm min. hole diameter + - 0.45mm min. via diameter + - 5mil via clearance + - 0.25mm hole clearance All design rules include a `PowerPads` pad class for easy direct polygon pour connection. -Layer stackups include: +Layer stackups +-------------- - 2 layer - 1 oz copper @@ -42,7 +60,8 @@ Layer stackups include: - 2 oz copper on top & bottom layers - 1.6mm, 2.0mm -Information compiled from: +References +---------- - https://jlcpcb.com/capabilities/Capabilities - https://jlcpcb.com/client/index.html#/impedance