
// <h> Advanced settings

// <q> Disable Leading Zero Optimization
// <i> Leading zero optimization makes division faster but cycles to take varias according to input values
// <i> With leading zero optimization the clock cycles are 2-8 for 16-bit and 2-16 for 32-bit
// <i> Disable leading zero optimization will force the division to take a fixed time of maximum number of cycles
// <id> divas_arch_dlz
#ifndef CONF_DIVAS_DLZ
#define CONF_DIVAS_DLZ 0
#endif

// </h>
