/*
 * configuration.h
 *
 * Created: 03/03/2021 08:38:13
 *  Author: Nick-XMG
 */ 


#ifndef CONFIGURATION_H_
#define CONFIGURATION_H_
#include <atmel_start.h>
//#include <tc_lite.h>



#include "pins.h"
#include "bldc.h"

#define DMAC_CHANNEL_ADC_SEQ 2U
#define DMAC_CHANNEL_ADC_SRAM 3U


//void dummy2 (void){
	//while(1);
//}
//
//void dummy3 (void){
	//while(1);
//}
//
//void dummy4 (void){
	//while(1);
//}
//void dummy5 (void){
	//while(1);
//}
//
//void dummy6 (void){
	//while(1);
//}

inline static void configure_tcc_pwm(void)
{
	
	/* TCC0 */
	hri_tcc_set_WEXCTRL_OTMX_bf(TCC0, 0);
	hri_tcc_write_PER_reg(TCC0,1200);
	
	hri_tcc_set_WAVE_POL0_bit(TCC0);
	hri_tcc_set_WAVE_POL1_bit(TCC0);
	hri_tcc_set_WAVE_POL2_bit(TCC0);
	hri_tcc_set_WAVE_POL3_bit(TCC0);
	hri_tcc_set_WAVE_POL4_bit(TCC0);
	hri_tcc_set_WAVE_POL5_bit(TCC0);
	hri_tcc_write_CC_CC_bf(TCC0, 0, 0);
	hri_tcc_write_CC_CC_bf(TCC0, 1, 0);
	hri_tcc_write_CC_CC_bf(TCC0, 2, 0);
	hri_tcc_write_CC_CC_bf(TCC0, 3, 0);
	hri_tcc_write_CC_CC_bf(TCC0, 4, 0);
	hri_tcc_write_CC_CC_bf(TCC0, 5, 0);
	
	hri_tcc_write_CTRLA_ENABLE_bit(TCC0, 1 << TCC_CTRLA_ENABLE_Pos);
	
	
	/* TCC1 */
	hri_tcc_set_WEXCTRL_OTMX_bf(TCC1, 3);
 	hri_tcc_write_CC_CC_bf(TCC1, 0, 0);
	hri_tcc_write_CC_CC_bf(TCC1, 1, 0);
	hri_tcc_write_CC_CC_bf(TCC1, 2, 0);
	hri_tcc_write_CC_CC_bf(TCC1, 3, 0);
	//hri_tcc_write_CC_CC_bf(TCC1, 0, 0);
	hri_tcc_write_PER_reg(TCC1,1200);
	//pwm_set_parameters(&TCC_PWM, 1000, 250);
	
	hri_tcc_set_WAVE_POL0_bit(TCC1);
	hri_tcc_set_WAVE_POL1_bit(TCC1);
	hri_tcc_set_WAVE_POL2_bit(TCC1);
	hri_tcc_set_WAVE_POL3_bit(TCC1);
	hri_tcc_set_WAVE_POL4_bit(TCC1);
	hri_tcc_set_WAVE_POL5_bit(TCC1);
	
	hri_tcc_clear_CTRLA_ENABLE_bit(TCC1);
	hri_tcc_write_CTRLA_MSYNC_bit(TCC1, true);
	//hri_tcc_write_CTRLA_ENABLE_bit(TCC1, 1 << TCC_CTRLA_ENABLE_Pos); /* Enable: enabled */
	
	pwm_register_callback(&TCC_PWM, PWM_PERIOD_CB, pwm_cb);	
	pwm_enable(&TCC_PWM);

}

inline void configure_adc(void)
{
	adc_sync_enable_channel(&ADC_0, 0);
	//adc_sync_enable_channel(&ADC_1, 0);
	
	//adc_async_register_callback(&ADC_0, 0, ADC_ASYNC_CONVERT_CB, adc_cb);
	//adc_async_register_callback(&ADC_1, 0, ADC_ASYNC_CONVERT_CB, convert_cb_ADC_1);
	//adc_async_start_conversion(&ADC_0);
	//adc_async_start_conversion(&ADC_1);
}

void config_pins(void)
{
	//gpio_set_pin_direction(DBG_PIN1, GPIO_DIRECTION_OUT);
	//gpio_set_pin_function(DBG_PIN1, GPIO_PIN_FUNCTION_OFF);
}


inline void configure_TC_CCL_SPEED(void)
{
		/* Enable TC1 Clock for 32-bit timer.  Linked to TC0 in driver_init.c 
		Could also add a hri_gclk_write_PCHCTRL_reg call for TC1 but it is redundant (for SAME54) since TC0 and TC1 share the GCLK index.*/
		//hri_gclk_write_PCHCTRL_reg(GCLK, TC1_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
		//event_system_enable_generator(
	
}

inline static void adc_init_dma(void)
{
	adc_sram_dmac_init();
	adc_dmac_sequence_init();
	hri_adc_set_DSEQCTRL_INPUTCTRL_bit(ADC0);
	hri_adc_set_DSEQCTRL_AUTOSTART_bit(ADC0);
}

inline void adc_dmac_sequence_init()
{
	/* Configure the DMAC source address, destination address,
	 * next descriptor address, data count and Enable the DMAC Channel */
	_dma_set_source_address(DMAC_CHANNEL_ADC_SEQ, (const void *)adc_seq_regs);
	_dma_set_destination_address(DMAC_CHANNEL_ADC_SEQ, (const void *)&ADC0->DSEQDATA.reg);
	_dma_set_data_amount(DMAC_CHANNEL_ADC_SEQ, 4);
	_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SEQ, DMAC_CHANNEL_ADC_SEQ);
	_dma_enable_transaction(DMAC_CHANNEL_ADC_SEQ, false);
	//_dma_get_channel_resource(&adc_dmac_sequence_resource, DMAC_CHANNEL_ADC_SEQ);
	//adc_dmac_sequence_resource[0].dma_cb.error = dummy2;
	//adc_dmac_sequence_resource[0].dma_cb.suspend = dummy3;
	//adc_dmac_sequence_resource[0].dma_cb.transfer_done = dummy4;
	

	hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[2], 0x01);	//Suspend
}

inline void adc_sram_dmac_init()
{
	/* Configure the DMAC source address, destination address,
	 * next descriptor address, data count and Enable the DMAC Channel */
	_dma_set_source_address(DMAC_CHANNEL_ADC_SRAM, (const void *)&ADC0->RESULT.reg);
	_dma_set_destination_address(DMAC_CHANNEL_ADC_SRAM, (const void *)adc_res);
	_dma_set_data_amount(DMAC_CHANNEL_ADC_SRAM, 4);
	_dma_set_irq_state(DMAC_CHANNEL_ADC_SRAM, DMA_TRANSFER_COMPLETE_CB, true);
	_dma_get_channel_resource(&adc_sram_dma_resource, DMAC_CHANNEL_ADC_SRAM);
	adc_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback;
	//adc_sram_dma_resource[0].dma_cb.error = dummy6;
	//adc_sram_dma_resource[0].dma_cb.suspend = dummy5;
	_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SRAM, DMAC_CHANNEL_ADC_SRAM);
	_dma_enable_transaction(DMAC_CHANNEL_ADC_SRAM, false);
}




#endif /* CONFIGURATION_H_ */