/*
 * ethercat_qspi.c
 *
 * Created: 15/07/2021 19:30:41
 *  Author: Nick-XMG
 */ 

#include "ethercat_qspi.h"

#define ECAT_SIZE_WR			64 //max fifo size
#define ECAT_SIZE_RD			ECAT_SIZE_WR
#define ECAT_SIZE_WR_REG		ECAT_SIZE_WR/4
#define ECAT_SIZE_RD_REG		ECAT_SIZE_WR/4

#define SQI_READ				(0x0B<<16)
#define SQI_WRITE				(0x02<<16)
#define SQI_INC					(0x40<<8)
#define SQI_DEC					(0x80<<8)
#define ECAT_PRAM_RD_DATA		0x0000
#define ECAT_PRAM_WR_DATA		0x0020
#define HW_CFG					0x0074
#define	BYTE_TEST				0x0064
#define ECAT_PRAM_RD_ADDR_LEN	0x0308
#define ECAT_PRAM_RD_CMD		0x030C
#define ECAT_PRAM_WR_ADDR_LEN	0x0310
#define ECAT_PRAM_WR_CMD		0x0314

#define LAN9252_RDY				(1<<27)

#define PDRAM_RD_ADDRESS		0x1100
#define PDRAM_RD_LENGTH			ECAT_SIZE_RD //do the math later to automatize. fixed to 64 for now.
#define PDRAM_WR_ADDRESS		0x1800
#define PDRAM_WR_LENGTH			ECAT_SIZE_WR
#define PDRAM_LENGTH_MAX		64
#define PDRAM_LENGTH_SHORT		32
#define FIFO_DEPTH				16
#define PDRAM_REG_MAX			PDRAM_LENGTH_SHORT/4
#define PRAM_X_ABORT			(1<<30)
#define CSR_BUSY				0x80000000

#define buffer_size			3*ECAT_SIZE_WR_REG  //changed to double
#define motor_buffer_size	buffer_size/3

uint32_t QSPI_tx_buffer[buffer_size]={0};
uint32_t QSPI_rx_buffer[buffer_size]={0};
	

struct SPI_Slave S1 = {
	.SPI_Sn = &SPI_0,
	.state = 0,
	.SS_pin = SPI_CS,
	.tx_buffer = &QSPI_rx_buffer[0],
	.rx_buffer = &QSPI_tx_buffer[0],
};

uint32_t QSPI_cmds[]=	{0,PRAM_X_ABORT,0,PRAM_X_ABORT,
						((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS,						CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS,CSR_BUSY,
						((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX,		CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX,CSR_BUSY,
						((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX*2,	CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX*2,CSR_BUSY,
						};

uint32_t zero[FIFO_DEPTH]={0};

struct _qspi_command rd_cmd = {
	.inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
	.inst_frame.bits.inst_en = 0,
	.inst_frame.bits.data_en = 1,
	.inst_frame.bits.addr_en = 1,
	.inst_frame.bits.dummy_cycles = 6,
	.inst_frame.bits.tfr_type = QSPI_READMEM_ACCESS,
};

struct _qspi_command wr_cmd = {
	.inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
	.inst_frame.bits.inst_en = 0,
	.inst_frame.bits.data_en = 1,
	.inst_frame.bits.addr_en = 1,
	.inst_frame.bits.dummy_cycles = 0,
	.inst_frame.bits.tfr_type = QSPI_WRITEMEM_ACCESS,
};

struct _qspi_command qspi_cmd = {
	.inst_frame.bits.width = QSPI_INST1_ADDR1_DATA1,
	.inst_frame.bits.inst_en = 1,
	.inst_frame.bits.data_en = 0,
	.inst_frame.bits.addr_en = 0,
	.inst_frame.bits.dummy_cycles = 0,
	.instruction = 0x38,
	.inst_frame.bits.tfr_type = QSPI_WRITE_ACCESS,
};

volatile uint8_t SPI_S1_SS_state = 0;
volatile uint8_t* M1_tx_cnt = &QSPI_rx_buffer[0];
volatile uint8_t* M1_rx_cnt = &QSPI_tx_buffer[0];
uint8_t sync_rx_buffer[2*2*buffer_size/3]={0};
uint8_t sync_tx_buffer[2*2*buffer_size/3]={0xED};
volatile uint32_t status = 0;

struct _qspi_command *spi_cmd= &wr_cmd;
volatile uint8_t tx_complete=3;
volatile uint32_t *ECAT_BYTE_TEST =	QSPI_AHB+BYTE_TEST+SQI_READ;
volatile uint32_t *ECAT_FIFO_RD_RD			=	QSPI_AHB+SQI_READ +ECAT_PRAM_RD_DATA;
volatile uint32_t *ECAT_FIFO_WR_WR			=	QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_DATA;
volatile uint32_t *ECAT_HW_CFG_RD			=	QSPI_AHB+SQI_READ+HW_CFG;
volatile uint32_t *ECAT_FIFO_RD_ADLEN_WR	=   QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_RD_ADDR_LEN;
volatile uint32_t *ECAT_FIFO_WR_ADLEN_WR	=   QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
volatile uint32_t *ECAT_FIFO_WR_ADLEN_RD	=   QSPI_AHB+SQI_READ+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
volatile uint32_t *ECAT_FIFO_WR_CMD_RD		=	QSPI_AHB+SQI_READ+ECAT_PRAM_WR_CMD;
volatile uint32_t *ECAT_FIFO_WR_CMD_WR		=	QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_CMD;

volatile enum ecat_states ecat_state = wait;
volatile enum ecat_states next_ecat_state = wait;