/*
 * configuration.h
 *
 * Created: 03/03/2021 08:38:13
 *  Author: Nick-XMG
 */ 


#ifndef CONFIGURATION_H_
#define CONFIGURATION_H_
#include <atmel_start.h>
//#include <tc_lite.h>



#include "pins.h"
#include "bldc.h"


inline void configure_tcc_pwm(void)
{
	hri_tcc_set_WEXCTRL_OTMX_bf(TCC1, 2);
 	hri_tcc_write_CC_CC_bf(TCC1, 0, 150);
	//hri_tcc_write_CC_CC_bf(TCC1, 0, 0);
	hri_tcc_write_PER_reg(TCC1,1000);
	//pwm_set_parameters(&TCC_PWM, 1000, 250);
	
	hri_tcc_set_WAVE_POL0_bit(TCC1);
	hri_tcc_set_WAVE_POL1_bit(TCC1);
	hri_tcc_set_WAVE_POL2_bit(TCC1);
	hri_tcc_set_WAVE_POL3_bit(TCC1);
	hri_tcc_set_WAVE_POL4_bit(TCC1);
	
	hri_tcc_clear_CTRLA_ENABLE_bit(TCC1);
	hri_tcc_write_CTRLA_MSYNC_bit(TCC1, true);
	hri_tcc_write_CTRLA_ENABLE_bit(TCC1, 1 << TCC_CTRLA_ENABLE_Pos); /* Enable: enabled */
	
	//pwm_register_callback(&TCC_PWM, PWM_PERIOD_CB, pwm_cb);	
	//pwm_enable(&TCC_PWM);

}

inline void configure_adc(void)
{
	adc_async_enable_channel(&ADC_0, 0);
	adc_async_enable_channel(&ADC_1, 0);
	
	adc_async_register_callback(&ADC_0, 0, ADC_ASYNC_CONVERT_CB, adc_cb);
	//adc_async_register_callback(&ADC_1, 0, ADC_ASYNC_CONVERT_CB, convert_cb_ADC_1);
	//adc_async_start_conversion(&ADC_0);
	//adc_async_start_conversion(&ADC_1);
}

void config_pins(void)
{
	//gpio_set_pin_direction(DBG_PIN1, GPIO_DIRECTION_OUT);
	//gpio_set_pin_function(DBG_PIN1, GPIO_PIN_FUNCTION_OFF);
}


inline void configure_TC_CCL_SPEED(void)
{
		/* Enable TC1 Clock for 32-bit timer.  Linked to TC0 in driver_init.c 
		Could also add a hri_gclk_write_PCHCTRL_reg call for TC1 but it is redundant (for SAME54) since TC0 and TC1 share the GCLK index.*/
		//hri_gclk_write_PCHCTRL_reg(GCLK, TC1_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
		//event_system_enable_generator(
	
}





#endif /* CONFIGURATION_H_ */