
BLDC_E54.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         00003f88  00000000  00000000  00010000  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .relocate     000000bc  20000000  00003f88  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  2 .bkupram      00000000  47000000  47000000  000200bc  2**0
                  CONTENTS
  3 .qspi         00000000  04000000  04000000  000200bc  2**0
                  CONTENTS
  4 .bss          00000a30  200000c0  00004050  000200c0  2**4
                  ALLOC
  5 .stack        00010000  20000af0  00004a80  000200c0  2**0
                  ALLOC
  6 .ARM.attributes 00000030  00000000  00000000  000200bc  2**0
                  CONTENTS, READONLY
  7 .comment      00000059  00000000  00000000  000200ec  2**0
                  CONTENTS, READONLY
  8 .debug_info   0004c002  00000000  00000000  00020145  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_abbrev 00005083  00000000  00000000  0006c147  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_loc    00014af6  00000000  00000000  000711ca  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_aranges 000010b8  00000000  00000000  00085cc0  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_ranges 00001320  00000000  00000000  00086d78  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_macro  00039157  00000000  00000000  00088098  2**0
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_line   0001b6c9  00000000  00000000  000c11ef  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_str    00129b9b  00000000  00000000  000dc8b8  2**0
                  CONTENTS, READONLY, DEBUGGING
 16 .debug_frame  00002ac8  00000000  00000000  00206454  2**2
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

00000000 <exception_table>:
       0:	f0 0a 01 20 f1 0b 00 00 ed 0b 00 00 ed 0b 00 00     ... ............
      10:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 00 00 00 00     ................
	...
      2c:	ed 0b 00 00 ed 0b 00 00 00 00 00 00 ed 0b 00 00     ................
      3c:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
      4c:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
      5c:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
      6c:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
      7c:	ed 0b 00 00 ed 0b 00 00 79 29 00 00 ed 0b 00 00     ........y)......
      8c:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
      9c:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
      ac:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
      bc:	7d 27 00 00 89 27 00 00 95 27 00 00 a1 27 00 00     }'...'...'...'..
      cc:	ad 27 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     .'..............
      dc:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 00 00 00 00     ................
	...
      f4:	09 2d 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     .-..............
     104:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     114:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     124:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     134:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     144:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     154:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     164:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     174:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     184:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     194:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     1a4:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 fd 34 00 00     .............4..
     1b4:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     1c4:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     1d4:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     1e4:	ed 0b 00 00 ed 0b 00 00 3d 37 00 00 ed 0b 00 00     ........=7......
     1f4:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     204:	ed 0b 00 00 15 37 00 00 89 2c 00 00 ed 0b 00 00     .....7...,......
     214:	ed 0b 00 00 35 23 00 00 49 23 00 00 5d 23 00 00     ....5#..I#..]#..
     224:	71 23 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     q#..............
     234:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     244:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................
     254:	ed 0b 00 00 ed 0b 00 00 ed 0b 00 00 ed 0b 00 00     ................

00000264 <__do_global_dtors_aux>:
     264:	b510      	push	{r4, lr}
     266:	4c05      	ldr	r4, [pc, #20]	; (27c <__do_global_dtors_aux+0x18>)
     268:	7823      	ldrb	r3, [r4, #0]
     26a:	b933      	cbnz	r3, 27a <__do_global_dtors_aux+0x16>
     26c:	4b04      	ldr	r3, [pc, #16]	; (280 <__do_global_dtors_aux+0x1c>)
     26e:	b113      	cbz	r3, 276 <__do_global_dtors_aux+0x12>
     270:	4804      	ldr	r0, [pc, #16]	; (284 <__do_global_dtors_aux+0x20>)
     272:	f3af 8000 	nop.w
     276:	2301      	movs	r3, #1
     278:	7023      	strb	r3, [r4, #0]
     27a:	bd10      	pop	{r4, pc}
     27c:	200000c0 	.word	0x200000c0
     280:	00000000 	.word	0x00000000
     284:	00003f88 	.word	0x00003f88

00000288 <frame_dummy>:
     288:	4b0c      	ldr	r3, [pc, #48]	; (2bc <frame_dummy+0x34>)
     28a:	b143      	cbz	r3, 29e <frame_dummy+0x16>
     28c:	480c      	ldr	r0, [pc, #48]	; (2c0 <frame_dummy+0x38>)
     28e:	490d      	ldr	r1, [pc, #52]	; (2c4 <frame_dummy+0x3c>)
     290:	b510      	push	{r4, lr}
     292:	f3af 8000 	nop.w
     296:	480c      	ldr	r0, [pc, #48]	; (2c8 <frame_dummy+0x40>)
     298:	6803      	ldr	r3, [r0, #0]
     29a:	b923      	cbnz	r3, 2a6 <frame_dummy+0x1e>
     29c:	bd10      	pop	{r4, pc}
     29e:	480a      	ldr	r0, [pc, #40]	; (2c8 <frame_dummy+0x40>)
     2a0:	6803      	ldr	r3, [r0, #0]
     2a2:	b933      	cbnz	r3, 2b2 <frame_dummy+0x2a>
     2a4:	4770      	bx	lr
     2a6:	4b09      	ldr	r3, [pc, #36]	; (2cc <frame_dummy+0x44>)
     2a8:	2b00      	cmp	r3, #0
     2aa:	d0f7      	beq.n	29c <frame_dummy+0x14>
     2ac:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
     2b0:	4718      	bx	r3
     2b2:	4b06      	ldr	r3, [pc, #24]	; (2cc <frame_dummy+0x44>)
     2b4:	2b00      	cmp	r3, #0
     2b6:	d0f5      	beq.n	2a4 <frame_dummy+0x1c>
     2b8:	4718      	bx	r3
     2ba:	bf00      	nop
     2bc:	00000000 	.word	0x00000000
     2c0:	00003f88 	.word	0x00003f88
     2c4:	200000c4 	.word	0x200000c4
     2c8:	00003f88 	.word	0x00003f88
     2cc:	00000000 	.word	0x00000000

000002d0 <atmel_start_init>:

/**
 * Initializes MCU, drivers and middleware in the project
 **/
void atmel_start_init(void)
{
     2d0:	b508      	push	{r3, lr}
	system_init();
     2d2:	4b01      	ldr	r3, [pc, #4]	; (2d8 <atmel_start_init+0x8>)
     2d4:	4798      	blx	r3
     2d6:	bd08      	pop	{r3, pc}
     2d8:	00001195 	.word	0x00001195

000002dc <select_active_phase>:
// Current Selection Based on Hall State
// Direction":
// CW  -> Always positive current
// CCW -> Always negative current
void select_active_phase(volatile BLDCMotor_t *Motor, volatile uint8_t hall_state)
{
     2dc:	b084      	sub	sp, #16
     2de:	f88d 1007 	strb.w	r1, [sp, #7]
	volatile float32_t phase_current = 0;
     2e2:	2300      	movs	r3, #0
     2e4:	9303      	str	r3, [sp, #12]
	switch(hall_state)
     2e6:	f89d 3007 	ldrb.w	r3, [sp, #7]
     2ea:	3b01      	subs	r3, #1
     2ec:	2b05      	cmp	r3, #5
     2ee:	d806      	bhi.n	2fe <select_active_phase+0x22>
     2f0:	e8df f003 	tbb	[pc, r3]
     2f4:	0c030903 	.word	0x0c030903
     2f8:	090c      	.short	0x090c
	{
		case 0b001:	case 0b011:
		phase_current = Motor->Iphase_pu.C;
     2fa:	6a43      	ldr	r3, [r0, #36]	; 0x24
     2fc:	9303      	str	r3, [sp, #12]
		default : 
		//phase_current = 0;	// Invalid hall code
		break;
	}
	
	Motor->Iphase_pu.Bus = phase_current;
     2fe:	9b03      	ldr	r3, [sp, #12]
     300:	6283      	str	r3, [r0, #40]	; 0x28
}
     302:	b004      	add	sp, #16
     304:	4770      	bx	lr
		phase_current = Motor->Iphase_pu.B;
     306:	6a03      	ldr	r3, [r0, #32]
     308:	9303      	str	r3, [sp, #12]
		break;
     30a:	e7f8      	b.n	2fe <select_active_phase+0x22>
		phase_current = Motor->Iphase_pu.A;
     30c:	69c3      	ldr	r3, [r0, #28]
     30e:	9303      	str	r3, [sp, #12]
		break;
     310:	e7f5      	b.n	2fe <select_active_phase+0x22>
	...

00000314 <BLDC_init>:

void BLDC_init(BLDCMotor_t *motor)
{
     314:	b410      	push	{r4}
	// ----------------------------------------------------------------------
	//  Initialize all voltage and current objects, variables and helpers:
	motor->actualDirection = 0;
     316:	2200      	movs	r2, #0
     318:	7202      	strb	r2, [r0, #8]
	motor->desiredDirection = 0;
     31a:	7242      	strb	r2, [r0, #9]
	motor->duty_cycle = 0;
     31c:	8142      	strh	r2, [r0, #10]
	motor->calc_rpm = 0;
     31e:	2300      	movs	r3, #0
     320:	60c3      	str	r3, [r0, #12]
	motor->Num_Steps = 0;
     322:	6102      	str	r2, [r0, #16]
	motor->cur_comm_step = 0;
     324:	7502      	strb	r2, [r0, #20]
	motor->currentHallPattern = 1;
     326:	2101      	movs	r1, #1
     328:	75c1      	strb	r1, [r0, #23]
	motor->nextHallPattern = 3;
     32a:	2403      	movs	r4, #3
     32c:	7604      	strb	r4, [r0, #24]
	motor->directionOffset = 0;
     32e:	7682      	strb	r2, [r0, #26]
		
	//motor->hall_state = 1;
	motor->dir_hall_code = 1;
     330:	7641      	strb	r1, [r0, #25]
	
	motor->Iphase_pu.A = 0;
     332:	61c3      	str	r3, [r0, #28]
	motor->Iphase_pu.B = 0;
     334:	6203      	str	r3, [r0, #32]
	motor->Iphase_pu.C = 0;
     336:	6243      	str	r3, [r0, #36]	; 0x24
	motor->Iphase_pu.Bus = 0;
     338:	6283      	str	r3, [r0, #40]	; 0x28
	
	motor->Voffset_lsb.A = 0;
     33a:	8582      	strh	r2, [r0, #44]	; 0x2c
	motor->Voffset_lsb.B = 0;
     33c:	85c2      	strh	r2, [r0, #46]	; 0x2e
	motor->timerflags.pwm_cycle_tic = false;
     33e:	f880 2038 	strb.w	r2, [r0, #56]	; 0x38
	motor->timerflags.control_loop_tic = false;
     342:	f880 203a 	strb.w	r2, [r0, #58]	; 0x3a
	motor->timerflags.motor_telemetry_flag = false;
     346:	f880 203b 	strb.w	r2, [r0, #59]	; 0x3b
	motor->timerflags.control_loop_tic = false;
     34a:	f880 203a 	strb.w	r2, [r0, #58]	; 0x3a
	motor->regulation_loop_count = 0;
     34e:	f880 203c 	strb.w	r2, [r0, #60]	; 0x3c

	
	motor->VdcBus_pu = DEVICE_DC_VOLTAGE_V;
     352:	492f      	ldr	r1, [pc, #188]	; (410 <BLDC_init+0xfc>)
     354:	6301      	str	r1, [r0, #48]	; 0x30
	motor->VoneByDcBus_pu = 1.0f/DEVICE_DC_VOLTAGE_V;
     356:	492f      	ldr	r1, [pc, #188]	; (414 <BLDC_init+0x100>)
     358:	6341      	str	r1, [r0, #52]	; 0x34
	motor->motor_commutation_Pattern = COMMUTATION_PATTERN;
     35a:	492f      	ldr	r1, [pc, #188]	; (418 <BLDC_init+0x104>)
     35c:	6041      	str	r1, [r0, #4]
	
	motor->desired_torque	= 0.0;
     35e:	f8c0 30c8 	str.w	r3, [r0, #200]	; 0xc8
	motor->desired_speed	= 0;
     362:	f8a0 20cc 	strh.w	r2, [r0, #204]	; 0xcc
	motor->desired_position = 0;
     366:	f8a0 20ce 	strh.w	r2, [r0, #206]	; 0xce
	motor->max_current		= 0.0;
     36a:	f8c0 30d0 	str.w	r3, [r0, #208]	; 0xd0
	motor->max_torque		= 0.0;
     36e:	f8c0 30d4 	str.w	r3, [r0, #212]	; 0xd4
	motor->max_velocity		= 0;
     372:	f8a0 20d8 	strh.w	r2, [r0, #216]	; 0xd8
{
	PI_t *obj = (PI_t *)pPi_obj;

	// Function initializes the object with default values
	//fix16_t Kp = fix16_from_float(1.0);
	obj->Kp			= 0.0f;
     376:	6403      	str	r3, [r0, #64]	; 0x40
	obj->Ki			= 0.0f;
     378:	6443      	str	r3, [r0, #68]	; 0x44
	obj->Fbk_pu		= 0.0f;
     37a:	64c3      	str	r3, [r0, #76]	; 0x4c
	obj->Ref_pu		= 0.0f;
     37c:	6483      	str	r3, [r0, #72]	; 0x48
	obj->Ff_pu		= 0.0f;
     37e:	6503      	str	r3, [r0, #80]	; 0x50
	obj->Out_pu		= 0.0f;
     380:	65c3      	str	r3, [r0, #92]	; 0x5c
	obj->OutMax_pu	= 0.0f;
     382:	6583      	str	r3, [r0, #88]	; 0x58
	obj->OutMin_pu	= 0.0f;
     384:	6543      	str	r3, [r0, #84]	; 0x54
	obj->Ui			= 0.0f;
     386:	6603      	str	r3, [r0, #96]	; 0x60
	obj->SatFlag	= false;
     388:	f880 2068 	strb.w	r2, [r0, #104]	; 0x68
	//// ------------------------------------------------------------------------------
	////  pi current control init
	PI_objectInit(&motor->controllers.Pi_Idc);
	float motorLs_H   = MOTOR_LQ_H   * 2.0f;
	float motorRs_OHM = MOTOR_RS_OHM * 2.0f;
	motor->controllers.Pi_Idc.Kp = PI_calcKp(motorLs_H, DEVICE_SHUNT_CURRENT_A, DEVICE_DC_VOLTAGE_V, DEVICE_ISR_PERIOD_Sec);
     38c:	4923      	ldr	r1, [pc, #140]	; (41c <BLDC_init+0x108>)
     38e:	6401      	str	r1, [r0, #64]	; 0x40
	//Pi_Idc.Ki = 0;
	motor->controllers.Pi_Idc.Ki = PI_calcKi(motorRs_OHM, motorLs_H, DEVICE_ISR_PERIOD_Sec);
     390:	4923      	ldr	r1, [pc, #140]	; (420 <BLDC_init+0x10c>)
     392:	6441      	str	r1, [r0, #68]	; 0x44
{
	PID_t *obj = (PID_t *)pPiD_obj;

	// Function initializes the object with default values
	//fix16_t Kp = fix16_from_float(1.0);
	obj->Kp			= 0.0f;
     394:	66c3      	str	r3, [r0, #108]	; 0x6c
	obj->Ki			= 0.0f;
     396:	6703      	str	r3, [r0, #112]	; 0x70
	obj->Kd			= 0.0f;
     398:	6743      	str	r3, [r0, #116]	; 0x74
	obj->Fbk_pu		= 0.0f;
     39a:	67c3      	str	r3, [r0, #124]	; 0x7c
	obj->Ref_pu		= 0.0f;
     39c:	6783      	str	r3, [r0, #120]	; 0x78
	obj->Ff_pu		= 0.0f;
     39e:	f8c0 3080 	str.w	r3, [r0, #128]	; 0x80
	obj->Out_pu		= 0.0f;
     3a2:	f8c0 308c 	str.w	r3, [r0, #140]	; 0x8c
	obj->OutMax_pu	= 0.0f;
     3a6:	f8c0 3088 	str.w	r3, [r0, #136]	; 0x88
	obj->OutMin_pu	= 0.0f;
     3aa:	f8c0 3084 	str.w	r3, [r0, #132]	; 0x84
	obj->Ui			= 0.0f;
     3ae:	f8c0 3090 	str.w	r3, [r0, #144]	; 0x90
	obj->Ud			= 0.0f;
     3b2:	f8c0 3094 	str.w	r3, [r0, #148]	; 0x94
	//motor->controllers.Pid_Speed.Ki = 0.01f;
	
	/* VI Control Gains */
	//motor->controllers.Pid_Speed.Kp = 0.0003f;
	//motor->controllers.Pid_Speed.Ki = 0.001f;
	motor->controllers.Pid_Speed.Kp = 0.0005f;
     3b6:	491b      	ldr	r1, [pc, #108]	; (424 <BLDC_init+0x110>)
     3b8:	66c1      	str	r1, [r0, #108]	; 0x6c
	motor->controllers.Pid_Speed.Ki = 0.0f;
     3ba:	6703      	str	r3, [r0, #112]	; 0x70
	motor->controllers.Pid_Speed.Kd = 0.0001f;
     3bc:	491a      	ldr	r1, [pc, #104]	; (428 <BLDC_init+0x114>)
     3be:	6741      	str	r1, [r0, #116]	; 0x74
	
	
	//motor->controllers.Pid_Speed.Ki = 0.0001f;
	motor->controllers.Pid_Speed.OutMax_pu = (MOTOR_MAX_CURRENT_IDC_A);
     3c0:	491a      	ldr	r1, [pc, #104]	; (42c <BLDC_init+0x118>)
     3c2:	f8c0 1088 	str.w	r1, [r0, #136]	; 0x88
	motor->controllers.Pid_Speed.OutMin_pu = -(MOTOR_MAX_CURRENT_IDC_A);
     3c6:	491a      	ldr	r1, [pc, #104]	; (430 <BLDC_init+0x11c>)
     3c8:	f8c0 1084 	str.w	r1, [r0, #132]	; 0x84
	obj->Kp			= 0.0f;
     3cc:	f8c0 309c 	str.w	r3, [r0, #156]	; 0x9c
	obj->Ki			= 0.0f;
     3d0:	f8c0 30a0 	str.w	r3, [r0, #160]	; 0xa0
	obj->Fbk_pu		= 0.0f;
     3d4:	f8c0 30a8 	str.w	r3, [r0, #168]	; 0xa8
	obj->Ref_pu		= 0.0f;
     3d8:	f8c0 30a4 	str.w	r3, [r0, #164]	; 0xa4
	obj->Ff_pu		= 0.0f;
     3dc:	f8c0 30ac 	str.w	r3, [r0, #172]	; 0xac
	obj->Out_pu		= 0.0f;
     3e0:	f8c0 30b8 	str.w	r3, [r0, #184]	; 0xb8
	obj->OutMax_pu	= 0.0f;
     3e4:	f8c0 30b4 	str.w	r3, [r0, #180]	; 0xb4
	obj->OutMin_pu	= 0.0f;
     3e8:	f8c0 30b0 	str.w	r3, [r0, #176]	; 0xb0
	obj->Ui			= 0.0f;
     3ec:	f8c0 30bc 	str.w	r3, [r0, #188]	; 0xbc
	obj->SatFlag	= false;
     3f0:	f880 20c4 	strb.w	r2, [r0, #196]	; 0xc4
	
	//// ------------------------------------------------------------------------------
	////  pi position control init
	PI_objectInit(&motor->controllers.Pi_Pos);
	motor->controllers.Pi_Pos.Kp = 40.0f;
     3f4:	4a0f      	ldr	r2, [pc, #60]	; (434 <BLDC_init+0x120>)
     3f6:	f8c0 209c 	str.w	r2, [r0, #156]	; 0x9c
	motor->controllers.Pi_Pos.Ki = 0.0f;
     3fa:	f8c0 30a0 	str.w	r3, [r0, #160]	; 0xa0

	//motor->controllers.Pi_Pos.Ki = 0.00015f;
	//Pi_Pos.Kp = 500000;
	//Pi_Pos.Kp = 0;
	
	motor->controllers.Pi_Pos.OutMax_pu = MOTOR_MAX_SPD_RPM;
     3fe:	4b0e      	ldr	r3, [pc, #56]	; (438 <BLDC_init+0x124>)
     400:	f8c0 30b4 	str.w	r3, [r0, #180]	; 0xb4
	motor->controllers.Pi_Pos.OutMin_pu = -MOTOR_MAX_SPD_RPM;
     404:	4b0d      	ldr	r3, [pc, #52]	; (43c <BLDC_init+0x128>)
     406:	f8c0 30b0 	str.w	r3, [r0, #176]	; 0xb0
}
     40a:	f85d 4b04 	ldr.w	r4, [sp], #4
     40e:	4770      	bx	lr
     410:	41c00000 	.word	0x41c00000
     414:	3d2aaaab 	.word	0x3d2aaaab
     418:	00003b60 	.word	0x00003b60
     41c:	4056ffff 	.word	0x4056ffff
     420:	3dd60210 	.word	0x3dd60210
     424:	3a03126f 	.word	0x3a03126f
     428:	38d1b717 	.word	0x38d1b717
     42c:	3f99999a 	.word	0x3f99999a
     430:	bf99999a 	.word	0xbf99999a
     434:	42200000 	.word	0x42200000
     438:	45834000 	.word	0x45834000
     43c:	c5834000 	.word	0xc5834000

00000440 <read_zero_current_offset_value>:
// Before Power up, Measure and average offset voltage for Current Sensor
// This voltage is subtracted from all reading for Bi-Directional Current
// Measurement
// ----------------------------------------------------------------------
void read_zero_current_offset_value(void)
{
     440:	b530      	push	{r4, r5, lr}
     442:	b083      	sub	sp, #12
	uint32_t phase_A_zero_current_offset_temp = 0;
	uint32_t phase_B_zero_current_offset_temp = 0;
	uint8_t samples = 16;
	int16_t i;
	
	adc_async_enable_channel(&ADC_0, 0);
     444:	2100      	movs	r1, #0
     446:	4832      	ldr	r0, [pc, #200]	; (510 <read_zero_current_offset_value+0xd0>)
     448:	4c32      	ldr	r4, [pc, #200]	; (514 <read_zero_current_offset_value+0xd4>)
     44a:	47a0      	blx	r4
	adc_async_enable_channel(&ADC_1, 0);
     44c:	2100      	movs	r1, #0
     44e:	4832      	ldr	r0, [pc, #200]	; (518 <read_zero_current_offset_value+0xd8>)
     450:	47a0      	blx	r4
	
	for (i=0; i<samples; i++)
     452:	2100      	movs	r1, #0
	uint8_t samples = 16;
     454:	2210      	movs	r2, #16
	uint32_t phase_B_zero_current_offset_temp = 0;
     456:	4608      	mov	r0, r1
	uint32_t phase_A_zero_current_offset_temp = 0;
     458:	460c      	mov	r4, r1
	for (i=0; i<samples; i++)
     45a:	e044      	b.n	4e6 <read_zero_current_offset_value+0xa6>
	{
		volatile uint16_t zero_current_offset_temp[2] = {0,0};
     45c:	2300      	movs	r3, #0
     45e:	f8ad 3004 	strh.w	r3, [sp, #4]
     462:	f8ad 3006 	strh.w	r3, [sp, #6]
			
		while (ADC0->STATUS.bit.ADCBUSY) {};			/* Wait for bus synchronization. */
     466:	4b2d      	ldr	r3, [pc, #180]	; (51c <read_zero_current_offset_value+0xdc>)
     468:	f893 302f 	ldrb.w	r3, [r3, #47]	; 0x2f
     46c:	f013 0f01 	tst.w	r3, #1
     470:	d1f9      	bne.n	466 <read_zero_current_offset_value+0x26>
		ADC0->SWTRIG.bit.START = true;					/* Start the ADC using a software trigger. */
     472:	4d2a      	ldr	r5, [pc, #168]	; (51c <read_zero_current_offset_value+0xdc>)
     474:	7d2b      	ldrb	r3, [r5, #20]
     476:	f043 0302 	orr.w	r3, r3, #2
     47a:	752b      	strb	r3, [r5, #20]
		while (ADC0->INTFLAG.bit.RESRDY == 0);			/* Wait for the result ready flag to be set. */
     47c:	4b27      	ldr	r3, [pc, #156]	; (51c <read_zero_current_offset_value+0xdc>)
     47e:	f893 302e 	ldrb.w	r3, [r3, #46]	; 0x2e
     482:	f013 0f01 	tst.w	r3, #1
     486:	d0f9      	beq.n	47c <read_zero_current_offset_value+0x3c>
		ADC0->INTFLAG.reg = ADC_INTFLAG_RESRDY;			/* Clear the flag. */
     488:	4b24      	ldr	r3, [pc, #144]	; (51c <read_zero_current_offset_value+0xdc>)
     48a:	2501      	movs	r5, #1
     48c:	f883 502e 	strb.w	r5, [r3, #46]	; 0x2e
		zero_current_offset_temp[0]	= ADC0->RESULT.reg; /* Read the value. */
     490:	f8b3 3040 	ldrh.w	r3, [r3, #64]	; 0x40
     494:	b29b      	uxth	r3, r3
     496:	f8ad 3004 	strh.w	r3, [sp, #4]
		
		while (ADC1->STATUS.bit.ADCBUSY) {};			/* Wait for bus synchronization. */
     49a:	4b21      	ldr	r3, [pc, #132]	; (520 <read_zero_current_offset_value+0xe0>)
     49c:	f893 302f 	ldrb.w	r3, [r3, #47]	; 0x2f
     4a0:	f013 0f01 	tst.w	r3, #1
     4a4:	d1f9      	bne.n	49a <read_zero_current_offset_value+0x5a>
		ADC1->SWTRIG.bit.START = true;					/* Start the ADC using a software trigger. */
     4a6:	4d1e      	ldr	r5, [pc, #120]	; (520 <read_zero_current_offset_value+0xe0>)
     4a8:	7d2b      	ldrb	r3, [r5, #20]
     4aa:	f043 0302 	orr.w	r3, r3, #2
     4ae:	752b      	strb	r3, [r5, #20]
		while (ADC1->INTFLAG.bit.RESRDY == 0);			/* Wait for the result ready flag to be set. */
     4b0:	4b1b      	ldr	r3, [pc, #108]	; (520 <read_zero_current_offset_value+0xe0>)
     4b2:	f893 302e 	ldrb.w	r3, [r3, #46]	; 0x2e
     4b6:	f013 0f01 	tst.w	r3, #1
     4ba:	d0f9      	beq.n	4b0 <read_zero_current_offset_value+0x70>
		ADC1->INTFLAG.reg = ADC_INTFLAG_RESRDY;			/* Clear the flag. */
     4bc:	4b18      	ldr	r3, [pc, #96]	; (520 <read_zero_current_offset_value+0xe0>)
     4be:	2501      	movs	r5, #1
     4c0:	f883 502e 	strb.w	r5, [r3, #46]	; 0x2e
		zero_current_offset_temp[1]	= ADC1->RESULT.reg; /* Read the value. */
     4c4:	f8b3 3040 	ldrh.w	r3, [r3, #64]	; 0x40
     4c8:	b29b      	uxth	r3, r3
     4ca:	f8ad 3006 	strh.w	r3, [sp, #6]
			
		phase_A_zero_current_offset_temp += zero_current_offset_temp[0];
     4ce:	f8bd 3004 	ldrh.w	r3, [sp, #4]
     4d2:	fa14 f483 	uxtah	r4, r4, r3
		phase_B_zero_current_offset_temp += zero_current_offset_temp[1];
     4d6:	f8bd 3006 	ldrh.w	r3, [sp, #6]
     4da:	fa10 f083 	uxtah	r0, r0, r3
		samples--;
     4de:	3a01      	subs	r2, #1
     4e0:	b2d2      	uxtb	r2, r2
	for (i=0; i<samples; i++)
     4e2:	4429      	add	r1, r5
     4e4:	b209      	sxth	r1, r1
     4e6:	4291      	cmp	r1, r2
     4e8:	dbb8      	blt.n	45c <read_zero_current_offset_value+0x1c>
	}
	Motor1.Voffset_lsb.A = phase_A_zero_current_offset_temp/samples;
     4ea:	fbb4 f3f2 	udiv	r3, r4, r2
     4ee:	b21b      	sxth	r3, r3
     4f0:	490c      	ldr	r1, [pc, #48]	; (524 <read_zero_current_offset_value+0xe4>)
     4f2:	858b      	strh	r3, [r1, #44]	; 0x2c
	Motor1.Voffset_lsb.B = phase_B_zero_current_offset_temp/samples;
     4f4:	fbb0 f3f2 	udiv	r3, r0, r2
     4f8:	b21b      	sxth	r3, r3
     4fa:	85cb      	strh	r3, [r1, #46]	; 0x2e
	adc_async_disable_channel(&ADC_0, 0);
     4fc:	2100      	movs	r1, #0
     4fe:	4804      	ldr	r0, [pc, #16]	; (510 <read_zero_current_offset_value+0xd0>)
     500:	4c09      	ldr	r4, [pc, #36]	; (528 <read_zero_current_offset_value+0xe8>)
     502:	47a0      	blx	r4
	adc_async_disable_channel(&ADC_1, 0);
     504:	2100      	movs	r1, #0
     506:	4804      	ldr	r0, [pc, #16]	; (518 <read_zero_current_offset_value+0xd8>)
     508:	47a0      	blx	r4
}
     50a:	b003      	add	sp, #12
     50c:	bd30      	pop	{r4, r5, pc}
     50e:	bf00      	nop
     510:	20000438 	.word	0x20000438
     514:	00001a19 	.word	0x00001a19
     518:	200004c8 	.word	0x200004c8
     51c:	43001c00 	.word	0x43001c00
     520:	43002000 	.word	0x43002000
     524:	20000328 	.word	0x20000328
     528:	00001a59 	.word	0x00001a59

0000052c <HALLPatternGet>:
			(_gpio_get_level(HALL_B_PIN) << 1)	|
			(_gpio_get_level(HALL_C_PIN) << 0));
}

uint8_t HALLPatternGet(void)
{
     52c:	b082      	sub	sp, #8
	
	
	volatile uint8_t motor_read = 0;
     52e:	2300      	movs	r3, #0
     530:	f88d 3007 	strb.w	r3, [sp, #7]
	motor_read = (motor_read & HALL_A_MASK) | (uint8_t)((PORT->Group[HALL_A_GROUP].IN.reg & HALL_A_PORT)>>(HALL_A_LSR)); 
     534:	f89d 3007 	ldrb.w	r3, [sp, #7]
     538:	f003 03fb 	and.w	r3, r3, #251	; 0xfb
     53c:	b259      	sxtb	r1, r3
     53e:	4a13      	ldr	r2, [pc, #76]	; (58c <HALLPatternGet+0x60>)
     540:	6a13      	ldr	r3, [r2, #32]
     542:	091b      	lsrs	r3, r3, #4
     544:	f003 0304 	and.w	r3, r3, #4
     548:	430b      	orrs	r3, r1
     54a:	b2db      	uxtb	r3, r3
     54c:	f88d 3007 	strb.w	r3, [sp, #7]
	motor_read = (motor_read & HALL_B_MASK) | (uint8_t)((PORT->Group[HALL_B_GROUP].IN.reg & HALL_B_PORT)>>(HALL_B_LSR)); 
     550:	f89d 3007 	ldrb.w	r3, [sp, #7]
     554:	f003 03fd 	and.w	r3, r3, #253	; 0xfd
     558:	b259      	sxtb	r1, r3
     55a:	6a13      	ldr	r3, [r2, #32]
     55c:	091b      	lsrs	r3, r3, #4
     55e:	f003 0302 	and.w	r3, r3, #2
     562:	430b      	orrs	r3, r1
     564:	b2db      	uxtb	r3, r3
     566:	f88d 3007 	strb.w	r3, [sp, #7]
	motor_read = (motor_read & HALL_C_MASK) | (uint8_t)((PORT->Group[HALL_C_GROUP].IN.reg & HALL_C_PORT)>>(HALL_C_LSR)); 
     56a:	f89d 3007 	ldrb.w	r3, [sp, #7]
     56e:	f003 03fe 	and.w	r3, r3, #254	; 0xfe
     572:	b25b      	sxtb	r3, r3
     574:	6a12      	ldr	r2, [r2, #32]
     576:	f3c2 1200 	ubfx	r2, r2, #4, #1
     57a:	4313      	orrs	r3, r2
     57c:	b2db      	uxtb	r3, r3
     57e:	f88d 3007 	strb.w	r3, [sp, #7]
	
	return motor_read;
     582:	f89d 0007 	ldrb.w	r0, [sp, #7]
	
	//return ((gpio_get_pin_level(HALL_A_PIN) << 2)|
			//(gpio_get_pin_level(HALL_B_PIN) << 1)|
			//(gpio_get_pin_level(HALL_C_PIN) << 0));
}
     586:	b002      	add	sp, #8
     588:	4770      	bx	lr
     58a:	bf00      	nop
     58c:	41008000 	.word	0x41008000

00000590 <exec_commutation>:
	
    return (uint8_t)(PDEC->COUNT.reg & 0x07);	
}

void exec_commutation(void)
	{
     590:	b500      	push	{lr}
     592:	b083      	sub	sp, #12
	//CRITICAL_SECTION_ENTER();
	Motor1.currentHallPattern = HALLPatternGet();
     594:	4b1e      	ldr	r3, [pc, #120]	; (610 <exec_commutation+0x80>)
     596:	4798      	blx	r3
     598:	4b1e      	ldr	r3, [pc, #120]	; (614 <exec_commutation+0x84>)
     59a:	75d8      	strb	r0, [r3, #23]
		///* Check the Hall pattern is a valid pattern */
		//hri_tcc_write_PATTBUF_reg(TCC1, (COMMUTATION_PATTERN[(Motor1.currentHallPattern + Motor1.directionOffset)]));
	//}
	
	
	TCC1->PATTBUF.reg = COMMUTATION_PATTERN[(Motor1.currentHallPattern + Motor1.directionOffset)];
     59c:	7dda      	ldrb	r2, [r3, #23]
     59e:	7e99      	ldrb	r1, [r3, #26]
     5a0:	4411      	add	r1, r2
     5a2:	4a1d      	ldr	r2, [pc, #116]	; (618 <exec_commutation+0x88>)
     5a4:	f832 0011 	ldrh.w	r0, [r2, r1, lsl #1]
     5a8:	491c      	ldr	r1, [pc, #112]	; (61c <exec_commutation+0x8c>)
     5aa:	f8a1 0064 	strh.w	r0, [r1, #100]	; 0x64
	TCC1->CCBUF->reg = (uint16_t)Motor1.duty_cycle;
     5ae:	8959      	ldrh	r1, [r3, #10]
     5b0:	b289      	uxth	r1, r1
     5b2:	481b      	ldr	r0, [pc, #108]	; (620 <exec_commutation+0x90>)
     5b4:	6001      	str	r1, [r0, #0]
	//Motor1.nextHallPattern = HALL_PATTERN_ARRAY[(Motor1.currentHallPattern+Motor1.directionOffset)];
	//}

	//volatile uint8_t curHallState = hallCode & 0x07;  //ABC format
	//volatile uint8_t curHallState = get_hall_state();  //ABC format
	Motor1.cur_comm_step = MOTOR_COMMUTATION_STEPS[Motor1.currentHallPattern];
     5b6:	7dd9      	ldrb	r1, [r3, #23]
     5b8:	440a      	add	r2, r1
     5ba:	f892 2020 	ldrb.w	r2, [r2, #32]
     5be:	751a      	strb	r2, [r3, #20]
	volatile int8_t step_change = Motor1.cur_comm_step - Motor1.prev_comm_step; 
     5c0:	7d1a      	ldrb	r2, [r3, #20]
     5c2:	7d5b      	ldrb	r3, [r3, #21]
     5c4:	1ad3      	subs	r3, r2, r3
     5c6:	b25b      	sxtb	r3, r3
     5c8:	f88d 3007 	strb.w	r3, [sp, #7]
	
	switch(step_change)
     5cc:	f89d 3007 	ldrb.w	r3, [sp, #7]
     5d0:	b25b      	sxtb	r3, r3
     5d2:	3305      	adds	r3, #5
     5d4:	2b0a      	cmp	r3, #10
     5d6:	d80d      	bhi.n	5f4 <exec_commutation+0x64>
     5d8:	e8df f003 	tbb	[pc, r3]
     5dc:	0c0c0c06 	.word	0x0c0c0c06
     5e0:	0c060c13 	.word	0x0c060c13
     5e4:	0c0c      	.short	0x0c0c
     5e6:	13          	.byte	0x13
     5e7:	00          	.byte	0x00
	{
		case 1:
		case -5:
			Motor1.Num_Steps = Motor1.Num_Steps+1;
     5e8:	4b0a      	ldr	r3, [pc, #40]	; (614 <exec_commutation+0x84>)
     5ea:	691a      	ldr	r2, [r3, #16]
     5ec:	3201      	adds	r2, #1
     5ee:	611a      	str	r2, [r3, #16]
			Motor1.actualDirection = CW;
     5f0:	2200      	movs	r2, #0
     5f2:	721a      	strb	r2, [r3, #8]
		break;
		default: 
		// do nothing
		break;
	}
	Motor1.prev_comm_step = Motor1.cur_comm_step;
     5f4:	4a07      	ldr	r2, [pc, #28]	; (614 <exec_commutation+0x84>)
     5f6:	7d13      	ldrb	r3, [r2, #20]
     5f8:	b2db      	uxtb	r3, r3
     5fa:	7553      	strb	r3, [r2, #21]
	//calculate_motor_speed();
	//toc(DEBUG_3);
	//toc(DEBUG_4);
	//CRITICAL_SECTION_LEAVE();
}
     5fc:	b003      	add	sp, #12
     5fe:	f85d fb04 	ldr.w	pc, [sp], #4
			Motor1.Num_Steps = Motor1.Num_Steps-1;
     602:	4b04      	ldr	r3, [pc, #16]	; (614 <exec_commutation+0x84>)
     604:	691a      	ldr	r2, [r3, #16]
     606:	3a01      	subs	r2, #1
     608:	611a      	str	r2, [r3, #16]
			Motor1.actualDirection = CCW;
     60a:	2201      	movs	r2, #1
     60c:	721a      	strb	r2, [r3, #8]
		break;
     60e:	e7f1      	b.n	5f4 <exec_commutation+0x64>
     610:	0000052d 	.word	0x0000052d
     614:	20000328 	.word	0x20000328
     618:	00003b60 	.word	0x00003b60
     61c:	41018000 	.word	0x41018000
     620:	41018070 	.word	0x41018070

00000624 <calculate_motor_speed>:

void calculate_motor_speed(void)
{	
     624:	b082      	sub	sp, #8
	volatile uint32_t temp_rpm = 0;
     626:	2300      	movs	r3, #0
     628:	9301      	str	r3, [sp, #4]
typedef uint8_t  hri_tccount8_per_reg_t;
typedef uint8_t  hri_tccount8_perbuf_reg_t;

static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg)
{
	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
     62a:	4b26      	ldr	r3, [pc, #152]	; (6c4 <calculate_motor_speed+0xa0>)
     62c:	691b      	ldr	r3, [r3, #16]
     62e:	f013 0fc0 	tst.w	r3, #192	; 0xc0
     632:	d1fa      	bne.n	62a <calculate_motor_speed+0x6>
}

static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index)
{
	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
	return ((Tc *)hw)->COUNT32.CC[index].reg;
     634:	4b23      	ldr	r3, [pc, #140]	; (6c4 <calculate_motor_speed+0xa0>)
     636:	69db      	ldr	r3, [r3, #28]
	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
     638:	4b22      	ldr	r3, [pc, #136]	; (6c4 <calculate_motor_speed+0xa0>)
     63a:	691b      	ldr	r3, [r3, #16]
     63c:	f013 0fc0 	tst.w	r3, #192	; 0xc0
     640:	d1fa      	bne.n	638 <calculate_motor_speed+0x14>
	return ((Tc *)hw)->COUNT32.CC[index].reg;
     642:	4b20      	ldr	r3, [pc, #128]	; (6c4 <calculate_motor_speed+0xa0>)
     644:	6a1b      	ldr	r3, [r3, #32]
	hri_tccount32_read_CC_reg(TC0, 0); /* Read CC0 but throw away)*/
	volatile uint32_t period_after_capture = hri_tccount32_read_CC_reg(TC0, 1);
     646:	9300      	str	r3, [sp, #0]
	if((period_after_capture > UINT32_MAX)|| (period_after_capture > 10712046)) {
     648:	9b00      	ldr	r3, [sp, #0]
     64a:	9a00      	ldr	r2, [sp, #0]
     64c:	4b1e      	ldr	r3, [pc, #120]	; (6c8 <calculate_motor_speed+0xa4>)
     64e:	429a      	cmp	r2, r3
     650:	d921      	bls.n	696 <calculate_motor_speed+0x72>
		Motor1.calc_rpm = 0;
     652:	2200      	movs	r2, #0
     654:	4b1d      	ldr	r3, [pc, #116]	; (6cc <calculate_motor_speed+0xa8>)
     656:	60da      	str	r2, [r3, #12]
		temp_rpm = (muti) / (period_after_capture*MOTOR_COMUTATION_STATES);
	}
	
	#ifdef AVERAGE_SPEED_MEASURE
		// To avoid noise an average is realized on 8 samples
		speed_average += temp_rpm;
     658:	9b01      	ldr	r3, [sp, #4]
     65a:	4a1d      	ldr	r2, [pc, #116]	; (6d0 <calculate_motor_speed+0xac>)
     65c:	6811      	ldr	r1, [r2, #0]
     65e:	440b      	add	r3, r1
     660:	6013      	str	r3, [r2, #0]
		if(count >= n_SAMPLE)
     662:	4a1c      	ldr	r2, [pc, #112]	; (6d4 <calculate_motor_speed+0xb0>)
     664:	7812      	ldrb	r2, [r2, #0]
     666:	2a07      	cmp	r2, #7
     668:	d926      	bls.n	6b8 <calculate_motor_speed+0x94>
		{
			count = 1;
     66a:	2101      	movs	r1, #1
     66c:	4a19      	ldr	r2, [pc, #100]	; (6d4 <calculate_motor_speed+0xb0>)
     66e:	7011      	strb	r1, [r2, #0]
			Motor1.calc_rpm = (speed_average >> 3); // divide by 32
     670:	08db      	lsrs	r3, r3, #3
     672:	ee07 3a90 	vmov	s15, r3
     676:	eef8 7a67 	vcvt.f32.u32	s15, s15
     67a:	4b14      	ldr	r3, [pc, #80]	; (6cc <calculate_motor_speed+0xa8>)
     67c:	edc3 7a03 	vstr	s15, [r3, #12]
			speed_average = 0;
     680:	2100      	movs	r1, #0
     682:	4a13      	ldr	r2, [pc, #76]	; (6d0 <calculate_motor_speed+0xac>)
     684:	6011      	str	r1, [r2, #0]
			//*Spare_byte1 = motorState.actualDirection;
			if(Motor1.actualDirection == CCW) /* Changed from CCW */
     686:	7a1b      	ldrb	r3, [r3, #8]
     688:	b2db      	uxtb	r3, r3
     68a:	2b01      	cmp	r3, #1
     68c:	d00c      	beq.n	6a8 <calculate_motor_speed+0x84>
			{
				//*motor_speed = -1* Motor1.calc_rpm;
				Motor1.calc_rpm = -1* Motor1.calc_rpm;
			} else { 
				//*motor_speed = Motor1.calc_rpm;
				Motor1.calc_rpm = Motor1.calc_rpm;
     68e:	4b0f      	ldr	r3, [pc, #60]	; (6cc <calculate_motor_speed+0xa8>)
     690:	68da      	ldr	r2, [r3, #12]
     692:	60da      	str	r2, [r3, #12]
     694:	e013      	b.n	6be <calculate_motor_speed+0x9a>
		temp_rpm = (muti) / (period_after_capture*MOTOR_COMUTATION_STATES);
     696:	9a00      	ldr	r2, [sp, #0]
     698:	232a      	movs	r3, #42	; 0x2a
     69a:	fb03 f202 	mul.w	r2, r3, r2
     69e:	4b0e      	ldr	r3, [pc, #56]	; (6d8 <calculate_motor_speed+0xb4>)
     6a0:	fbb3 f3f2 	udiv	r3, r3, r2
     6a4:	9301      	str	r3, [sp, #4]
     6a6:	e7d7      	b.n	658 <calculate_motor_speed+0x34>
				Motor1.calc_rpm = -1* Motor1.calc_rpm;
     6a8:	4b08      	ldr	r3, [pc, #32]	; (6cc <calculate_motor_speed+0xa8>)
     6aa:	edd3 7a03 	vldr	s15, [r3, #12]
     6ae:	eef1 7a67 	vneg.f32	s15, s15
     6b2:	edc3 7a03 	vstr	s15, [r3, #12]
     6b6:	e002      	b.n	6be <calculate_motor_speed+0x9a>
			}
			return;
		}
		else count++;
     6b8:	3201      	adds	r2, #1
     6ba:	4b06      	ldr	r3, [pc, #24]	; (6d4 <calculate_motor_speed+0xb0>)
     6bc:	701a      	strb	r2, [r3, #0]
	#else
		Motor1.calc_rpm = (int16_t)temp_rpm;
	#endif	
}
     6be:	b002      	add	sp, #8
     6c0:	4770      	bx	lr
     6c2:	bf00      	nop
     6c4:	40003800 	.word	0x40003800
     6c8:	00a373ee 	.word	0x00a373ee
     6cc:	20000328 	.word	0x20000328
     6d0:	200000dc 	.word	0x200000dc
     6d4:	20000000 	.word	0x20000000
     6d8:	59682f00 	.word	0x59682f00

000006dc <BLDC_runCurrentCntl>:

//------------------------------------------------------------------------------
// pi current control
// Current Feedback
void BLDC_runCurrentCntl(BLDCMotor_t *motor, volatile float curfbk, volatile float curRef)
{
     6dc:	b086      	sub	sp, #24
     6de:	ed8d 0a01 	vstr	s0, [sp, #4]
     6e2:	edcd 0a00 	vstr	s1, [sp]
	
	motor->controllers.Pi_Idc.Fbk_pu = f_clamp(curfbk, -DEVICE_SHUNT_CURRENT_A, DEVICE_SHUNT_CURRENT_A);	// Clamped to max current sensor readingspeedfbk;
     6e6:	eddd 7a01 	vldr	s15, [sp, #4]
static inline float32_t f_clamp(const float32_t in, const float32_t min, const float32_t max)
{
	float32_t out = in;


	if(in < min)
     6ea:	eeb8 7a04 	vmov.f32	s14, #132	; 0xc0200000 -2.5
     6ee:	eef4 7ac7 	vcmpe.f32	s15, s14
     6f2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     6f6:	d409      	bmi.n	70c <BLDC_runCurrentCntl+0x30>
	{
		out = min;
	}
	else if(in > max)
     6f8:	eeb0 7a04 	vmov.f32	s14, #4	; 0x40200000  2.5
     6fc:	eef4 7ac7 	vcmpe.f32	s15, s14
     700:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     704:	dd04      	ble.n	710 <BLDC_runCurrentCntl+0x34>
	{
		out = max;
     706:	eef0 7a04 	vmov.f32	s15, #4	; 0x40200000  2.5
     70a:	e001      	b.n	710 <BLDC_runCurrentCntl+0x34>
		out = min;
     70c:	eef8 7a04 	vmov.f32	s15, #132	; 0xc0200000 -2.5
     710:	edc0 7a13 	vstr	s15, [r0, #76]	; 0x4c
	motor->controllers.Pi_Idc.Ref_pu = f_clamp(curRef, -MOTOR_MAX_CURRENT_IDC_A, MOTOR_MAX_CURRENT_IDC_A); // Clamp desired to Motor Max Current i_ref_clamped;
     714:	eddd 7a00 	vldr	s15, [sp]
	if(in < min)
     718:	ed9f 7a54 	vldr	s14, [pc, #336]	; 86c <BLDC_runCurrentCntl+0x190>
     71c:	eef4 7ac7 	vcmpe.f32	s15, s14
     720:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     724:	d409      	bmi.n	73a <BLDC_runCurrentCntl+0x5e>
	else if(in > max)
     726:	ed9f 7a52 	vldr	s14, [pc, #328]	; 870 <BLDC_runCurrentCntl+0x194>
     72a:	eef4 7ac7 	vcmpe.f32	s15, s14
     72e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     732:	dd04      	ble.n	73e <BLDC_runCurrentCntl+0x62>
		out = max;
     734:	eddf 7a4e 	vldr	s15, [pc, #312]	; 870 <BLDC_runCurrentCntl+0x194>
     738:	e001      	b.n	73e <BLDC_runCurrentCntl+0x62>
		out = min;
     73a:	eddf 7a4c 	vldr	s15, [pc, #304]	; 86c <BLDC_runCurrentCntl+0x190>
     73e:	edc0 7a12 	vstr	s15, [r0, #72]	; 0x48
	
	//*Spare_1 = (int16_t)(motor->controllers.Pi_Idc.Ref_pu * 1000);  // Send Req Current to TC

	motor->controllers.Pi_Idc.OutMax_pu = motor->VdcBus_pu;
     742:	6b03      	ldr	r3, [r0, #48]	; 0x30
     744:	6583      	str	r3, [r0, #88]	; 0x58
	motor->controllers.Pi_Idc.OutMin_pu = -motor->VdcBus_pu;
     746:	edd0 7a0c 	vldr	s15, [r0, #48]	; 0x30
     74a:	eef1 7a67 	vneg.f32	s15, s15
     74e:	edc0 7a15 	vstr	s15, [r0, #84]	; 0x54
	PI_run_series(&motor->controllers.Pi_Idc);
     752:	f100 0340 	add.w	r3, r0, #64	; 0x40
{
	PI_t *obj = (PI_t *)pPi_obj;
	volatile float32_t Up, preOut;

	// Compute the controller error
	obj->error = obj->Ref_pu - obj->Fbk_pu;
     756:	edd3 7a02 	vldr	s15, [r3, #8]
     75a:	ed93 7a03 	vldr	s14, [r3, #12]
     75e:	ee77 7ac7 	vsub.f32	s15, s15, s14
     762:	edc3 7a09 	vstr	s15, [r3, #36]	; 0x24

	// Compute the proportional term
	Up = obj->Kp *obj->error;
     766:	edd0 7a10 	vldr	s15, [r0, #64]	; 0x40
     76a:	ed93 7a09 	vldr	s14, [r3, #36]	; 0x24
     76e:	ee67 7a87 	vmul.f32	s15, s15, s14
     772:	edcd 7a03 	vstr	s15, [sp, #12]

	// Compute the integral term in series form and saturate	
	obj->Ui = f_clamp((obj->Ui + (obj->Ki * Up)), obj->OutMin_pu, obj->OutMax_pu);
     776:	edd3 7a08 	vldr	s15, [r3, #32]
     77a:	ed93 7a01 	vldr	s14, [r3, #4]
     77e:	eddd 6a03 	vldr	s13, [sp, #12]
     782:	ee27 7a26 	vmul.f32	s14, s14, s13
     786:	ee77 7a87 	vadd.f32	s15, s15, s14
     78a:	ed93 7a05 	vldr	s14, [r3, #20]
     78e:	edd3 6a06 	vldr	s13, [r3, #24]
	if(in < min)
     792:	eef4 7ac7 	vcmpe.f32	s15, s14
     796:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     79a:	d406      	bmi.n	7aa <BLDC_runCurrentCntl+0xce>
	else if(in > max)
     79c:	eef4 7ae6 	vcmpe.f32	s15, s13
     7a0:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     7a4:	dc51      	bgt.n	84a <BLDC_runCurrentCntl+0x16e>
	float32_t out = in;
     7a6:	eeb0 7a67 	vmov.f32	s14, s15
     7aa:	ed83 7a08 	vstr	s14, [r3, #32]

	// Saturate the output
 	obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu);
     7ae:	edd3 7a08 	vldr	s15, [r3, #32]
     7b2:	ed9d 7a03 	vldr	s14, [sp, #12]
     7b6:	ee77 7a87 	vadd.f32	s15, s15, s14
     7ba:	ed93 7a04 	vldr	s14, [r3, #16]
     7be:	ee77 7a87 	vadd.f32	s15, s15, s14
     7c2:	ed93 7a05 	vldr	s14, [r3, #20]
     7c6:	edd3 6a06 	vldr	s13, [r3, #24]
	if(in < min)
     7ca:	eef4 7ac7 	vcmpe.f32	s15, s14
     7ce:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     7d2:	d406      	bmi.n	7e2 <BLDC_runCurrentCntl+0x106>
	else if(in > max)
     7d4:	eef4 7ae6 	vcmpe.f32	s15, s13
     7d8:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     7dc:	dd38      	ble.n	850 <BLDC_runCurrentCntl+0x174>
		out = max;
     7de:	eeb0 7a66 	vmov.f32	s14, s13
     7e2:	ed83 7a07 	vstr	s14, [r3, #28]
	
	if(motor->controllers.Pi_Idc.Out_pu > 0) {
     7e6:	edd0 7a17 	vldr	s15, [r0, #92]	; 0x5c
     7ea:	eef5 7ac0 	vcmpe.f32	s15, #0.0
     7ee:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     7f2:	dd30      	ble.n	856 <BLDC_runCurrentCntl+0x17a>
		motor->desiredDirection = 0; 
     7f4:	2300      	movs	r3, #0
     7f6:	7243      	strb	r3, [r0, #9]
		motor->directionOffset = 0;
     7f8:	7683      	strb	r3, [r0, #26]
	} else {
		motor->desiredDirection = 1;
		motor->directionOffset = 8;
	}

	volatile float duty_pu = f_abs((motor->controllers.Pi_Idc.Out_pu * motor->VoneByDcBus_pu));
     7fa:	edd0 7a17 	vldr	s15, [r0, #92]	; 0x5c
     7fe:	ed90 7a0d 	vldr	s14, [r0, #52]	; 0x34
     802:	ee67 7a87 	vmul.f32	s15, s15, s14
//! \param[in] in   The input value
//! \return    The absolute value
static inline float32_t f_abs(const float32_t in)
{
	float32_t out = in;
	if(in < (float32_t)0.0)
     806:	eef5 7ac0 	vcmpe.f32	s15, #0.0
     80a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     80e:	d427      	bmi.n	860 <BLDC_runCurrentCntl+0x184>
     810:	edcd 7a05 	vstr	s15, [sp, #20]
	volatile duty_cycle = f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
     814:	eddd 7a05 	vldr	s15, [sp, #20]
     818:	ed9f 7a16 	vldr	s14, [pc, #88]	; 874 <BLDC_runCurrentCntl+0x198>
     81c:	ee67 7a87 	vmul.f32	s15, s15, s14
	if(in < min)
     820:	eef5 7ac0 	vcmpe.f32	s15, #0.0
     824:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     828:	d41d      	bmi.n	866 <BLDC_runCurrentCntl+0x18a>
	else if(in > max)
     82a:	eef4 7ac7 	vcmpe.f32	s15, s14
     82e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     832:	dd01      	ble.n	838 <BLDC_runCurrentCntl+0x15c>
		out = max;
     834:	eddf 7a0f 	vldr	s15, [pc, #60]	; 874 <BLDC_runCurrentCntl+0x198>
     838:	eefd 7ae7 	vcvt.s32.f32	s15, s15
     83c:	edcd 7a04 	vstr	s15, [sp, #16]
	motor->duty_cycle = (uint16_t)duty_cycle;
     840:	9b04      	ldr	r3, [sp, #16]
     842:	b29b      	uxth	r3, r3
     844:	8143      	strh	r3, [r0, #10]
	// Remove Low duty cycle values
	//if(duty_cycle < 80.0) motor->duty_cycle = (uint16_t)0;
	//else motor->duty_cycle = (uint16_t)duty_cycle;
	
}
     846:	b006      	add	sp, #24
     848:	4770      	bx	lr
     84a:	eeb0 7a66 	vmov.f32	s14, s13
     84e:	e7ac      	b.n	7aa <BLDC_runCurrentCntl+0xce>
	float32_t out = in;
     850:	eeb0 7a67 	vmov.f32	s14, s15
     854:	e7c5      	b.n	7e2 <BLDC_runCurrentCntl+0x106>
		motor->desiredDirection = 1;
     856:	2301      	movs	r3, #1
     858:	7243      	strb	r3, [r0, #9]
		motor->directionOffset = 8;
     85a:	2308      	movs	r3, #8
     85c:	7683      	strb	r3, [r0, #26]
     85e:	e7cc      	b.n	7fa <BLDC_runCurrentCntl+0x11e>
	{
		out = -in;
     860:	eef1 7a67 	vneg.f32	s15, s15
     864:	e7d4      	b.n	810 <BLDC_runCurrentCntl+0x134>
		out = min;
     866:	eddf 7a04 	vldr	s15, [pc, #16]	; 878 <BLDC_runCurrentCntl+0x19c>
     86a:	e7e5      	b.n	838 <BLDC_runCurrentCntl+0x15c>
     86c:	bf99999a 	.word	0xbf99999a
     870:	3f99999a 	.word	0x3f99999a
     874:	442f0000 	.word	0x442f0000
     878:	00000000 	.word	0x00000000

0000087c <BLDC_runSpeedCntl>:

//// ------------------------------------------------------------------------------
// Speed Control: Input in RPM units (int16_t)
void BLDC_runSpeedCntl(BLDCMotor_t *motor, volatile float speedfbk, volatile float speedRef)
{
     87c:	b088      	sub	sp, #32
     87e:	ed8d 0a01 	vstr	s0, [sp, #4]
     882:	edcd 0a00 	vstr	s1, [sp]
	
	motor->controllers.Pid_Speed.Fbk_pu = speedfbk; 
     886:	9b01      	ldr	r3, [sp, #4]
     888:	67c3      	str	r3, [r0, #124]	; 0x7c
	motor->controllers.Pid_Speed.Ref_pu = f_clamp(speedRef, -MAX_VEL, MAX_VEL);	// Convert Speed Ref to Q16 Format
     88a:	eddd 7a00 	vldr	s15, [sp]
	if(in < min)
     88e:	ed9f 7a9a 	vldr	s14, [pc, #616]	; af8 <BLDC_runSpeedCntl+0x27c>
     892:	eef4 7ac7 	vcmpe.f32	s15, s14
     896:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     89a:	d409      	bmi.n	8b0 <BLDC_runSpeedCntl+0x34>
	else if(in > max)
     89c:	ed9f 7a97 	vldr	s14, [pc, #604]	; afc <BLDC_runSpeedCntl+0x280>
     8a0:	eef4 7ac7 	vcmpe.f32	s15, s14
     8a4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     8a8:	dd04      	ble.n	8b4 <BLDC_runSpeedCntl+0x38>
		out = max;
     8aa:	eddf 7a94 	vldr	s15, [pc, #592]	; afc <BLDC_runSpeedCntl+0x280>
     8ae:	e001      	b.n	8b4 <BLDC_runSpeedCntl+0x38>
		out = min;
     8b0:	eddf 7a91 	vldr	s15, [pc, #580]	; af8 <BLDC_runSpeedCntl+0x27c>
     8b4:	edc0 7a1e 	vstr	s15, [r0, #120]	; 0x78
	
	if (applicationStatus.currentstate == MOTOR_V_CTRL_STATE)
     8b8:	4b91      	ldr	r3, [pc, #580]	; (b00 <BLDC_runSpeedCntl+0x284>)
     8ba:	781b      	ldrb	r3, [r3, #0]
     8bc:	2b04      	cmp	r3, #4
     8be:	d06b      	beq.n	998 <BLDC_runSpeedCntl+0x11c>
		volatile float32_t duty_pu = f_abs((motor->controllers.Pid_Speed.Out_pu * motor->VoneByDcBus_pu));
		volatile duty_cycle = f_clamp(duty_pu *  (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
		motor->duty_cycle = (uint16_t)duty_cycle;
	} else 	{
		/* Pu in Current (Amps) */
		motor->controllers.Pid_Speed.OutMax_pu = (MOTOR_MAX_CURRENT_IDC_A);
     8c0:	4b90      	ldr	r3, [pc, #576]	; (b04 <BLDC_runSpeedCntl+0x288>)
     8c2:	f8c0 3088 	str.w	r3, [r0, #136]	; 0x88
		motor->controllers.Pid_Speed.OutMin_pu = -(MOTOR_MAX_CURRENT_IDC_A);
     8c6:	4b90      	ldr	r3, [pc, #576]	; (b08 <BLDC_runSpeedCntl+0x28c>)
     8c8:	f8c0 3084 	str.w	r3, [r0, #132]	; 0x84
		PID_run_parallel(&motor->controllers.Pid_Speed);
     8cc:	f100 036c 	add.w	r3, r0, #108	; 0x6c
	PID_t *obj = (PID_t *)pPid_obj;
	volatile float32_t Up, Ud_tmp, preOut;

	
	// Compute the controller error
	obj->error = obj->Ref_pu - obj->Fbk_pu;
     8d0:	edd3 7a03 	vldr	s15, [r3, #12]
     8d4:	ed93 7a04 	vldr	s14, [r3, #16]
     8d8:	ee77 7ac7 	vsub.f32	s15, s15, s14
     8dc:	edc3 7a0b 	vstr	s15, [r3, #44]	; 0x2c
	
	// Compute the proportional term
	Up = obj->Kp * obj->error;
     8e0:	edd0 7a1b 	vldr	s15, [r0, #108]	; 0x6c
     8e4:	ed93 7a0b 	vldr	s14, [r3, #44]	; 0x2c
     8e8:	ee67 7a87 	vmul.f32	s15, s15, s14
     8ec:	edcd 7a06 	vstr	s15, [sp, #24]
	
	if(obj->Ki>0.0){
     8f0:	edd3 7a01 	vldr	s15, [r3, #4]
     8f4:	eef5 7ac0 	vcmpe.f32	s15, #0.0
     8f8:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     8fc:	dd1c      	ble.n	938 <BLDC_runSpeedCntl+0xbc>
		// Compute the integral term in parallel form and saturate
		obj->Ui = f_clamp((obj->Ui + (obj->Ki * obj->error)), obj->OutMin_pu, obj->OutMax_pu);
     8fe:	edd3 7a09 	vldr	s15, [r3, #36]	; 0x24
     902:	ed93 7a01 	vldr	s14, [r3, #4]
     906:	edd3 6a0b 	vldr	s13, [r3, #44]	; 0x2c
     90a:	ee27 7a26 	vmul.f32	s14, s14, s13
     90e:	ee77 7a87 	vadd.f32	s15, s15, s14
     912:	ed93 7a06 	vldr	s14, [r3, #24]
     916:	edd3 6a07 	vldr	s13, [r3, #28]
	if(in < min)
     91a:	eef4 7ac7 	vcmpe.f32	s15, s14
     91e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     922:	d407      	bmi.n	934 <BLDC_runSpeedCntl+0xb8>
	else if(in > max)
     924:	eef4 7ae6 	vcmpe.f32	s15, s13
     928:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     92c:	f300 80de 	bgt.w	aec <BLDC_runSpeedCntl+0x270>
	float32_t out = in;
     930:	eeb0 7a67 	vmov.f32	s14, s15
     934:	ed83 7a09 	vstr	s14, [r3, #36]	; 0x24
	}
	
	Ud_tmp = obj->Kd * obj->error;   // Compute the derivative term
     938:	edd3 7a02 	vldr	s15, [r3, #8]
     93c:	ed93 7a0b 	vldr	s14, [r3, #44]	; 0x2c
     940:	ee67 7a87 	vmul.f32	s15, s15, s14
     944:	edcd 7a07 	vstr	s15, [sp, #28]

	obj->Ud = Ud_tmp; // Replace with filter
     948:	9a07      	ldr	r2, [sp, #28]
     94a:	629a      	str	r2, [r3, #40]	; 0x28

	obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ud + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu);  // Saturate the output
     94c:	edd3 7a09 	vldr	s15, [r3, #36]	; 0x24
     950:	ed9d 7a06 	vldr	s14, [sp, #24]
     954:	ee77 7a87 	vadd.f32	s15, s15, s14
     958:	ed93 7a0a 	vldr	s14, [r3, #40]	; 0x28
     95c:	ee77 7a87 	vadd.f32	s15, s15, s14
     960:	ed93 7a05 	vldr	s14, [r3, #20]
     964:	ee77 7a87 	vadd.f32	s15, s15, s14
     968:	ed93 7a06 	vldr	s14, [r3, #24]
     96c:	edd3 6a07 	vldr	s13, [r3, #28]
	if(in < min)
     970:	eef4 7ac7 	vcmpe.f32	s15, s14
     974:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     978:	d407      	bmi.n	98a <BLDC_runSpeedCntl+0x10e>
	else if(in > max)
     97a:	eef4 7ae6 	vcmpe.f32	s15, s13
     97e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     982:	f340 80b6 	ble.w	af2 <BLDC_runSpeedCntl+0x276>
		out = max;
     986:	eeb0 7a66 	vmov.f32	s14, s13
     98a:	ed83 7a08 	vstr	s14, [r3, #32]
		motor->controllers.Pi_Idc.Ref_pu = motor->controllers.Pid_Speed.Out_pu;
     98e:	f8d0 308c 	ldr.w	r3, [r0, #140]	; 0x8c
     992:	6483      	str	r3, [r0, #72]	; 0x48
	}

}
     994:	b008      	add	sp, #32
     996:	4770      	bx	lr
		motor->controllers.Pid_Speed.OutMax_pu = motor->VdcBus_pu;
     998:	6b03      	ldr	r3, [r0, #48]	; 0x30
     99a:	f8c0 3088 	str.w	r3, [r0, #136]	; 0x88
		motor->controllers.Pid_Speed.OutMin_pu = -motor->VdcBus_pu;
     99e:	edd0 7a0c 	vldr	s15, [r0, #48]	; 0x30
     9a2:	eef1 7a67 	vneg.f32	s15, s15
     9a6:	edc0 7a21 	vstr	s15, [r0, #132]	; 0x84
		PID_run_parallel(&motor->controllers.Pid_Speed);
     9aa:	f100 036c 	add.w	r3, r0, #108	; 0x6c
	obj->error = obj->Ref_pu - obj->Fbk_pu;
     9ae:	edd3 7a03 	vldr	s15, [r3, #12]
     9b2:	ed93 7a04 	vldr	s14, [r3, #16]
     9b6:	ee77 7ac7 	vsub.f32	s15, s15, s14
     9ba:	edc3 7a0b 	vstr	s15, [r3, #44]	; 0x2c
	Up = obj->Kp * obj->error;
     9be:	edd0 7a1b 	vldr	s15, [r0, #108]	; 0x6c
     9c2:	ed93 7a0b 	vldr	s14, [r3, #44]	; 0x2c
     9c6:	ee67 7a87 	vmul.f32	s15, s15, s14
     9ca:	edcd 7a04 	vstr	s15, [sp, #16]
	if(obj->Ki>0.0){
     9ce:	edd3 7a01 	vldr	s15, [r3, #4]
     9d2:	eef5 7ac0 	vcmpe.f32	s15, #0.0
     9d6:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     9da:	dd1b      	ble.n	a14 <BLDC_runSpeedCntl+0x198>
		obj->Ui = f_clamp((obj->Ui + (obj->Ki * obj->error)), obj->OutMin_pu, obj->OutMax_pu);
     9dc:	edd3 7a09 	vldr	s15, [r3, #36]	; 0x24
     9e0:	ed93 7a01 	vldr	s14, [r3, #4]
     9e4:	edd3 6a0b 	vldr	s13, [r3, #44]	; 0x2c
     9e8:	ee27 7a26 	vmul.f32	s14, s14, s13
     9ec:	ee77 7a87 	vadd.f32	s15, s15, s14
     9f0:	ed93 7a06 	vldr	s14, [r3, #24]
     9f4:	edd3 6a07 	vldr	s13, [r3, #28]
	if(in < min)
     9f8:	eef4 7ac7 	vcmpe.f32	s15, s14
     9fc:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     a00:	d406      	bmi.n	a10 <BLDC_runSpeedCntl+0x194>
	else if(in > max)
     a02:	eef4 7ae6 	vcmpe.f32	s15, s13
     a06:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     a0a:	dc5e      	bgt.n	aca <BLDC_runSpeedCntl+0x24e>
	float32_t out = in;
     a0c:	eeb0 7a67 	vmov.f32	s14, s15
     a10:	ed83 7a09 	vstr	s14, [r3, #36]	; 0x24
	Ud_tmp = obj->Kd * obj->error;   // Compute the derivative term
     a14:	edd3 7a02 	vldr	s15, [r3, #8]
     a18:	ed93 7a0b 	vldr	s14, [r3, #44]	; 0x2c
     a1c:	ee67 7a87 	vmul.f32	s15, s15, s14
     a20:	edcd 7a05 	vstr	s15, [sp, #20]
	obj->Ud = Ud_tmp; // Replace with filter
     a24:	9a05      	ldr	r2, [sp, #20]
     a26:	629a      	str	r2, [r3, #40]	; 0x28
	obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ud + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu);  // Saturate the output
     a28:	edd3 7a09 	vldr	s15, [r3, #36]	; 0x24
     a2c:	ed9d 7a04 	vldr	s14, [sp, #16]
     a30:	ee77 7a87 	vadd.f32	s15, s15, s14
     a34:	ed93 7a0a 	vldr	s14, [r3, #40]	; 0x28
     a38:	ee77 7a87 	vadd.f32	s15, s15, s14
     a3c:	ed93 7a05 	vldr	s14, [r3, #20]
     a40:	ee77 7a87 	vadd.f32	s15, s15, s14
     a44:	ed93 7a06 	vldr	s14, [r3, #24]
     a48:	edd3 6a07 	vldr	s13, [r3, #28]
	if(in < min)
     a4c:	eef4 7ac7 	vcmpe.f32	s15, s14
     a50:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     a54:	d406      	bmi.n	a64 <BLDC_runSpeedCntl+0x1e8>
	else if(in > max)
     a56:	eef4 7ae6 	vcmpe.f32	s15, s13
     a5a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     a5e:	dd37      	ble.n	ad0 <BLDC_runSpeedCntl+0x254>
		out = max;
     a60:	eeb0 7a66 	vmov.f32	s14, s13
     a64:	ed83 7a08 	vstr	s14, [r3, #32]
		if(motor->controllers.Pid_Speed.Out_pu > 0) {
     a68:	edd0 7a23 	vldr	s15, [r0, #140]	; 0x8c
     a6c:	eef5 7ac0 	vcmpe.f32	s15, #0.0
     a70:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     a74:	dd2f      	ble.n	ad6 <BLDC_runSpeedCntl+0x25a>
			motor->desiredDirection = 0; 
     a76:	2300      	movs	r3, #0
     a78:	7243      	strb	r3, [r0, #9]
			motor->directionOffset = 0;
     a7a:	7683      	strb	r3, [r0, #26]
		volatile float32_t duty_pu = f_abs((motor->controllers.Pid_Speed.Out_pu * motor->VoneByDcBus_pu));
     a7c:	edd0 7a23 	vldr	s15, [r0, #140]	; 0x8c
     a80:	ed90 7a0d 	vldr	s14, [r0, #52]	; 0x34
     a84:	ee67 7a87 	vmul.f32	s15, s15, s14
	if(in < (float32_t)0.0)
     a88:	eef5 7ac0 	vcmpe.f32	s15, #0.0
     a8c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     a90:	d426      	bmi.n	ae0 <BLDC_runSpeedCntl+0x264>
     a92:	edcd 7a02 	vstr	s15, [sp, #8]
		volatile duty_cycle = f_clamp(duty_pu *  (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
     a96:	eddd 7a02 	vldr	s15, [sp, #8]
     a9a:	ed9f 7a1c 	vldr	s14, [pc, #112]	; b0c <BLDC_runSpeedCntl+0x290>
     a9e:	ee67 7a87 	vmul.f32	s15, s15, s14
	if(in < min)
     aa2:	eef5 7ac0 	vcmpe.f32	s15, #0.0
     aa6:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     aaa:	d41c      	bmi.n	ae6 <BLDC_runSpeedCntl+0x26a>
	else if(in > max)
     aac:	eef4 7ac7 	vcmpe.f32	s15, s14
     ab0:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     ab4:	dd01      	ble.n	aba <BLDC_runSpeedCntl+0x23e>
		out = max;
     ab6:	eddf 7a15 	vldr	s15, [pc, #84]	; b0c <BLDC_runSpeedCntl+0x290>
     aba:	eefd 7ae7 	vcvt.s32.f32	s15, s15
     abe:	edcd 7a03 	vstr	s15, [sp, #12]
		motor->duty_cycle = (uint16_t)duty_cycle;
     ac2:	9b03      	ldr	r3, [sp, #12]
     ac4:	b29b      	uxth	r3, r3
     ac6:	8143      	strh	r3, [r0, #10]
     ac8:	e764      	b.n	994 <BLDC_runSpeedCntl+0x118>
     aca:	eeb0 7a66 	vmov.f32	s14, s13
     ace:	e79f      	b.n	a10 <BLDC_runSpeedCntl+0x194>
	float32_t out = in;
     ad0:	eeb0 7a67 	vmov.f32	s14, s15
     ad4:	e7c6      	b.n	a64 <BLDC_runSpeedCntl+0x1e8>
			motor->desiredDirection = 1;
     ad6:	2301      	movs	r3, #1
     ad8:	7243      	strb	r3, [r0, #9]
			motor->directionOffset = 8;
     ada:	2308      	movs	r3, #8
     adc:	7683      	strb	r3, [r0, #26]
     ade:	e7cd      	b.n	a7c <BLDC_runSpeedCntl+0x200>
		out = -in;
     ae0:	eef1 7a67 	vneg.f32	s15, s15
     ae4:	e7d5      	b.n	a92 <BLDC_runSpeedCntl+0x216>
		out = min;
     ae6:	eddf 7a0a 	vldr	s15, [pc, #40]	; b10 <BLDC_runSpeedCntl+0x294>
     aea:	e7e6      	b.n	aba <BLDC_runSpeedCntl+0x23e>
		out = max;
     aec:	eeb0 7a66 	vmov.f32	s14, s13
     af0:	e720      	b.n	934 <BLDC_runSpeedCntl+0xb8>
	float32_t out = in;
     af2:	eeb0 7a67 	vmov.f32	s14, s15
     af6:	e748      	b.n	98a <BLDC_runSpeedCntl+0x10e>
     af8:	c56d8000 	.word	0xc56d8000
     afc:	456d8000 	.word	0x456d8000
     b00:	20000324 	.word	0x20000324
     b04:	3f99999a 	.word	0x3f99999a
     b08:	bf99999a 	.word	0xbf99999a
     b0c:	442f0000 	.word	0x442f0000
     b10:	00000000 	.word	0x00000000

00000b14 <BLDC_runPosCntl>:

//// ------------------------------------------------------------------------------
// Position Control:Input in Hall step units (int16_t)
void BLDC_runPosCntl(BLDCMotor_t *motor, int16_t posfbk, int16_t posRef)
{
     b14:	b082      	sub	sp, #8
	/* Output Pu in RPM */
	motor->controllers.Pi_Pos.OutMax_pu = MAX_VEL;
     b16:	4b33      	ldr	r3, [pc, #204]	; (be4 <BLDC_runPosCntl+0xd0>)
     b18:	f8c0 30b4 	str.w	r3, [r0, #180]	; 0xb4
	motor->controllers.Pi_Pos.OutMin_pu = -MAX_VEL;
     b1c:	4b32      	ldr	r3, [pc, #200]	; (be8 <BLDC_runPosCntl+0xd4>)
     b1e:	f8c0 30b0 	str.w	r3, [r0, #176]	; 0xb0
	motor->controllers.Pi_Pos.Fbk_pu = posfbk;	
     b22:	ee07 1a90 	vmov	s15, r1
     b26:	eef8 7ae7 	vcvt.f32.s32	s15, s15
     b2a:	edc0 7a2a 	vstr	s15, [r0, #168]	; 0xa8
	motor->controllers.Pi_Pos.Ref_pu = posRef;	
     b2e:	ee07 2a90 	vmov	s15, r2
     b32:	eef8 7ae7 	vcvt.f32.s32	s15, s15
     b36:	edc0 7a29 	vstr	s15, [r0, #164]	; 0xa4
	PI_run_series(&motor->controllers.Pi_Pos);
     b3a:	f100 039c 	add.w	r3, r0, #156	; 0x9c
	obj->error = obj->Ref_pu - obj->Fbk_pu;
     b3e:	edd3 7a02 	vldr	s15, [r3, #8]
     b42:	ed93 7a03 	vldr	s14, [r3, #12]
     b46:	ee77 7ac7 	vsub.f32	s15, s15, s14
     b4a:	edc3 7a09 	vstr	s15, [r3, #36]	; 0x24
	Up = obj->Kp *obj->error;
     b4e:	edd0 7a27 	vldr	s15, [r0, #156]	; 0x9c
     b52:	ed93 7a09 	vldr	s14, [r3, #36]	; 0x24
     b56:	ee67 7a87 	vmul.f32	s15, s15, s14
     b5a:	edcd 7a01 	vstr	s15, [sp, #4]
	obj->Ui = f_clamp((obj->Ui + (obj->Ki * Up)), obj->OutMin_pu, obj->OutMax_pu);
     b5e:	edd3 7a08 	vldr	s15, [r3, #32]
     b62:	ed93 7a01 	vldr	s14, [r3, #4]
     b66:	eddd 6a01 	vldr	s13, [sp, #4]
     b6a:	ee27 7a26 	vmul.f32	s14, s14, s13
     b6e:	ee77 7a87 	vadd.f32	s15, s15, s14
     b72:	ed93 7a05 	vldr	s14, [r3, #20]
     b76:	edd3 6a06 	vldr	s13, [r3, #24]
	if(in < min)
     b7a:	eef4 7ac7 	vcmpe.f32	s15, s14
     b7e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     b82:	d406      	bmi.n	b92 <BLDC_runPosCntl+0x7e>
	else if(in > max)
     b84:	eef4 7ae6 	vcmpe.f32	s15, s13
     b88:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     b8c:	dc24      	bgt.n	bd8 <BLDC_runPosCntl+0xc4>
	float32_t out = in;
     b8e:	eeb0 7a67 	vmov.f32	s14, s15
     b92:	ed83 7a08 	vstr	s14, [r3, #32]
 	obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu);
     b96:	edd3 7a08 	vldr	s15, [r3, #32]
     b9a:	ed9d 7a01 	vldr	s14, [sp, #4]
     b9e:	ee77 7a87 	vadd.f32	s15, s15, s14
     ba2:	ed93 7a04 	vldr	s14, [r3, #16]
     ba6:	ee77 7a87 	vadd.f32	s15, s15, s14
     baa:	ed93 7a05 	vldr	s14, [r3, #20]
     bae:	edd3 6a06 	vldr	s13, [r3, #24]
	if(in < min)
     bb2:	eef4 7ac7 	vcmpe.f32	s15, s14
     bb6:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     bba:	d406      	bmi.n	bca <BLDC_runPosCntl+0xb6>
	else if(in > max)
     bbc:	eef4 7ae6 	vcmpe.f32	s15, s13
     bc0:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
     bc4:	dd0b      	ble.n	bde <BLDC_runPosCntl+0xca>
		out = max;
     bc6:	eeb0 7a66 	vmov.f32	s14, s13
     bca:	ed83 7a07 	vstr	s14, [r3, #28]
	motor->controllers.Pid_Speed.Ref_pu = motor->controllers.Pi_Pos.Out_pu;
     bce:	f8d0 30b8 	ldr.w	r3, [r0, #184]	; 0xb8
     bd2:	6783      	str	r3, [r0, #120]	; 0x78
}
     bd4:	b002      	add	sp, #8
     bd6:	4770      	bx	lr
     bd8:	eeb0 7a66 	vmov.f32	s14, s13
     bdc:	e7d9      	b.n	b92 <BLDC_runPosCntl+0x7e>
	float32_t out = in;
     bde:	eeb0 7a67 	vmov.f32	s14, s15
     be2:	e7f2      	b.n	bca <BLDC_runPosCntl+0xb6>
     be4:	456d8000 	.word	0x456d8000
     be8:	c56d8000 	.word	0xc56d8000

00000bec <Dummy_Handler>:

/**
 * \brief Default interrupt handler for unused IRQs.
 */
void Dummy_Handler(void)
{
     bec:	e7fe      	b.n	bec <Dummy_Handler>
	...

00000bf0 <Reset_Handler>:
{
     bf0:	b508      	push	{r3, lr}
        if (pSrc != pDest) {
     bf2:	4b15      	ldr	r3, [pc, #84]	; (c48 <Reset_Handler+0x58>)
     bf4:	4a15      	ldr	r2, [pc, #84]	; (c4c <Reset_Handler+0x5c>)
     bf6:	429a      	cmp	r2, r3
     bf8:	d009      	beq.n	c0e <Reset_Handler+0x1e>
     bfa:	4b13      	ldr	r3, [pc, #76]	; (c48 <Reset_Handler+0x58>)
     bfc:	4a13      	ldr	r2, [pc, #76]	; (c4c <Reset_Handler+0x5c>)
     bfe:	e003      	b.n	c08 <Reset_Handler+0x18>
                        *pDest++ = *pSrc++;
     c00:	6811      	ldr	r1, [r2, #0]
     c02:	6019      	str	r1, [r3, #0]
     c04:	3304      	adds	r3, #4
     c06:	3204      	adds	r2, #4
                for (; pDest < &_erelocate;) {
     c08:	4911      	ldr	r1, [pc, #68]	; (c50 <Reset_Handler+0x60>)
     c0a:	428b      	cmp	r3, r1
     c0c:	d3f8      	bcc.n	c00 <Reset_Handler+0x10>
                        *pDest++ = *pSrc++;
     c0e:	4b11      	ldr	r3, [pc, #68]	; (c54 <Reset_Handler+0x64>)
     c10:	e002      	b.n	c18 <Reset_Handler+0x28>
                *pDest++ = 0;
     c12:	2200      	movs	r2, #0
     c14:	601a      	str	r2, [r3, #0]
     c16:	3304      	adds	r3, #4
        for (pDest = &_szero; pDest < &_ezero;) {
     c18:	4a0f      	ldr	r2, [pc, #60]	; (c58 <Reset_Handler+0x68>)
     c1a:	4293      	cmp	r3, r2
     c1c:	d3f9      	bcc.n	c12 <Reset_Handler+0x22>
        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
     c1e:	4b0f      	ldr	r3, [pc, #60]	; (c5c <Reset_Handler+0x6c>)
     c20:	4a0f      	ldr	r2, [pc, #60]	; (c60 <Reset_Handler+0x70>)
     c22:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
     c26:	609a      	str	r2, [r3, #8]
        SCB->CPACR |=  (0xFu << 20);
     c28:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
     c2c:	f442 0270 	orr.w	r2, r2, #15728640	; 0xf00000
     c30:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
     c34:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
     c38:	f3bf 8f6f 	isb	sy
        __libc_init_array();
     c3c:	4b09      	ldr	r3, [pc, #36]	; (c64 <Reset_Handler+0x74>)
     c3e:	4798      	blx	r3
        main();
     c40:	4b09      	ldr	r3, [pc, #36]	; (c68 <Reset_Handler+0x78>)
     c42:	4798      	blx	r3
     c44:	e7fe      	b.n	c44 <Reset_Handler+0x54>
     c46:	bf00      	nop
     c48:	20000000 	.word	0x20000000
     c4c:	00003f88 	.word	0x00003f88
     c50:	200000bc 	.word	0x200000bc
     c54:	200000c0 	.word	0x200000c0
     c58:	20000af0 	.word	0x20000af0
     c5c:	e000ed00 	.word	0xe000ed00
     c60:	00000000 	.word	0x00000000
     c64:	00003b19 	.word	0x00003b19
     c68:	000037a1 	.word	0x000037a1

00000c6c <ADC_0_init>:
 * \brief ADC initialization function
 *
 * Enables ADC peripheral, clocks and initializes ADC driver
 */
void ADC_0_init(void)
{
     c6c:	b5f0      	push	{r4, r5, r6, r7, lr}
     c6e:	b085      	sub	sp, #20
}

static inline void hri_mclk_set_APBDMASK_ADC0_bit(const void *const hw)
{
	MCLK_CRITICAL_SECTION_ENTER();
	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC0;
     c70:	4a1d      	ldr	r2, [pc, #116]	; (ce8 <ADC_0_init+0x7c>)
     c72:	6a13      	ldr	r3, [r2, #32]
     c74:	f043 0380 	orr.w	r3, r3, #128	; 0x80
     c78:	6213      	str	r3, [r2, #32]
}

static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
{
	GCLK_CRITICAL_SECTION_ENTER();
	((Gclk *)hw)->PCHCTRL[index].reg = data;
     c7a:	2240      	movs	r2, #64	; 0x40
     c7c:	4b1b      	ldr	r3, [pc, #108]	; (cec <ADC_0_init+0x80>)
     c7e:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
	hri_mclk_set_APBDMASK_ADC0_bit(MCLK);
	hri_gclk_write_PCHCTRL_reg(GCLK, ADC0_GCLK_ID, CONF_GCLK_ADC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
	adc_async_init(&ADC_0, ADC0, ADC_0_map, ADC_0_CH_MAX, ADC_0_CH_AMOUNT, &ADC_0_ch[0], (void *)NULL);
     c82:	4e1b      	ldr	r6, [pc, #108]	; (cf0 <ADC_0_init+0x84>)
     c84:	4d1b      	ldr	r5, [pc, #108]	; (cf4 <ADC_0_init+0x88>)
     c86:	2400      	movs	r4, #0
     c88:	9402      	str	r4, [sp, #8]
     c8a:	4b1b      	ldr	r3, [pc, #108]	; (cf8 <ADC_0_init+0x8c>)
     c8c:	9301      	str	r3, [sp, #4]
     c8e:	2301      	movs	r3, #1
     c90:	9300      	str	r3, [sp, #0]
     c92:	4623      	mov	r3, r4
     c94:	4632      	mov	r2, r6
     c96:	4919      	ldr	r1, [pc, #100]	; (cfc <ADC_0_init+0x90>)
     c98:	4628      	mov	r0, r5
     c9a:	4f19      	ldr	r7, [pc, #100]	; (d00 <ADC_0_init+0x94>)
     c9c:	47b8      	blx	r7
	adc_async_register_channel_buffer(&ADC_0, 0, ADC_0_buffer, ADC_0_BUFFER_SIZE);
     c9e:	2310      	movs	r3, #16
     ca0:	1d32      	adds	r2, r6, #4
     ca2:	4621      	mov	r1, r4
     ca4:	4628      	mov	r0, r5
     ca6:	4c17      	ldr	r4, [pc, #92]	; (d04 <ADC_0_init+0x98>)
     ca8:	47a0      	blx	r4
	((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data;
}

static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
{
	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
     caa:	4b17      	ldr	r3, [pc, #92]	; (d08 <ADC_0_init+0x9c>)
     cac:	f44f 7280 	mov.w	r2, #256	; 0x100
     cb0:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84

static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
                                               hri_port_wrconfig_reg_t data)
{
	PORT_CRITICAL_SECTION_ENTER();
	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
     cb4:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
     cb8:	f8c3 20a8 	str.w	r2, [r3, #168]	; 0xa8
     cbc:	f04f 4240 	mov.w	r2, #3221225472	; 0xc0000000
     cc0:	f8c3 20a8 	str.w	r2, [r3, #168]	; 0xa8
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
     cc4:	f893 20c8 	ldrb.w	r2, [r3, #200]	; 0xc8
	tmp &= ~PORT_PINCFG_PMUXEN;
     cc8:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
     ccc:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
     cd0:	f883 20c8 	strb.w	r2, [r3, #200]	; 0xc8
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
     cd4:	f893 20b4 	ldrb.w	r2, [r3, #180]	; 0xb4
	tmp &= ~PORT_PMUX_PMUXE_Msk;
     cd8:	f002 02f0 	and.w	r2, r2, #240	; 0xf0
	tmp |= PORT_PMUX_PMUXE(data);
     cdc:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
     ce0:	f883 20b4 	strb.w	r2, [r3, #180]	; 0xb4

	// Disable digital pin circuitry
	gpio_set_pin_direction(PB08, GPIO_DIRECTION_OFF);

	gpio_set_pin_function(PB08, PINMUX_PB08B_ADC0_AIN2);
}
     ce4:	b005      	add	sp, #20
     ce6:	bdf0      	pop	{r4, r5, r6, r7, pc}
     ce8:	40000800 	.word	0x40000800
     cec:	40001c00 	.word	0x40001c00
     cf0:	200000e0 	.word	0x200000e0
     cf4:	20000438 	.word	0x20000438
     cf8:	20000464 	.word	0x20000464
     cfc:	43001c00 	.word	0x43001c00
     d00:	000018b9 	.word	0x000018b9
     d04:	00001961 	.word	0x00001961
     d08:	41008000 	.word	0x41008000

00000d0c <ADC_1_init>:
 * \brief ADC initialization function
 *
 * Enables ADC peripheral, clocks and initializes ADC driver
 */
void ADC_1_init(void)
{
     d0c:	b5f0      	push	{r4, r5, r6, r7, lr}
     d0e:	b085      	sub	sp, #20
}

static inline void hri_mclk_set_APBDMASK_ADC1_bit(const void *const hw)
{
	MCLK_CRITICAL_SECTION_ENTER();
	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC1;
     d10:	4a1e      	ldr	r2, [pc, #120]	; (d8c <ADC_1_init+0x80>)
     d12:	6a13      	ldr	r3, [r2, #32]
     d14:	f443 7380 	orr.w	r3, r3, #256	; 0x100
     d18:	6213      	str	r3, [r2, #32]
     d1a:	2240      	movs	r2, #64	; 0x40
     d1c:	4b1c      	ldr	r3, [pc, #112]	; (d90 <ADC_1_init+0x84>)
     d1e:	f8c3 2124 	str.w	r2, [r3, #292]	; 0x124
	hri_mclk_set_APBDMASK_ADC1_bit(MCLK);
	hri_gclk_write_PCHCTRL_reg(GCLK, ADC1_GCLK_ID, CONF_GCLK_ADC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
	adc_async_init(&ADC_1, ADC1, ADC_1_map, ADC_1_CH_MAX, ADC_1_CH_AMOUNT, &ADC_1_ch[0], (void *)NULL);
     d22:	4e1c      	ldr	r6, [pc, #112]	; (d94 <ADC_1_init+0x88>)
     d24:	4d1c      	ldr	r5, [pc, #112]	; (d98 <ADC_1_init+0x8c>)
     d26:	2400      	movs	r4, #0
     d28:	9402      	str	r4, [sp, #8]
     d2a:	4b1c      	ldr	r3, [pc, #112]	; (d9c <ADC_1_init+0x90>)
     d2c:	9301      	str	r3, [sp, #4]
     d2e:	2301      	movs	r3, #1
     d30:	9300      	str	r3, [sp, #0]
     d32:	4623      	mov	r3, r4
     d34:	f106 0214 	add.w	r2, r6, #20
     d38:	4919      	ldr	r1, [pc, #100]	; (da0 <ADC_1_init+0x94>)
     d3a:	4628      	mov	r0, r5
     d3c:	4f19      	ldr	r7, [pc, #100]	; (da4 <ADC_1_init+0x98>)
     d3e:	47b8      	blx	r7
	adc_async_register_channel_buffer(&ADC_1, 0, ADC_1_buffer, ADC_1_BUFFER_SIZE);
     d40:	2310      	movs	r3, #16
     d42:	f106 0218 	add.w	r2, r6, #24
     d46:	4621      	mov	r1, r4
     d48:	4628      	mov	r0, r5
     d4a:	4c17      	ldr	r4, [pc, #92]	; (da8 <ADC_1_init+0x9c>)
     d4c:	47a0      	blx	r4
	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
     d4e:	4b17      	ldr	r3, [pc, #92]	; (dac <ADC_1_init+0xa0>)
     d50:	f44f 7200 	mov.w	r2, #512	; 0x200
     d54:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
     d58:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
     d5c:	f8c3 20a8 	str.w	r2, [r3, #168]	; 0xa8
     d60:	f04f 4240 	mov.w	r2, #3221225472	; 0xc0000000
     d64:	f8c3 20a8 	str.w	r2, [r3, #168]	; 0xa8
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
     d68:	f893 20c9 	ldrb.w	r2, [r3, #201]	; 0xc9
	tmp &= ~PORT_PINCFG_PMUXEN;
     d6c:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
     d70:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
     d74:	f883 20c9 	strb.w	r2, [r3, #201]	; 0xc9
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
     d78:	f893 20b4 	ldrb.w	r2, [r3, #180]	; 0xb4
	tmp &= ~PORT_PMUX_PMUXO_Msk;
     d7c:	f002 020f 	and.w	r2, r2, #15
	tmp |= PORT_PMUX_PMUXO(data);
     d80:	f042 0210 	orr.w	r2, r2, #16
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
     d84:	f883 20b4 	strb.w	r2, [r3, #180]	; 0xb4

	// Disable digital pin circuitry
	gpio_set_pin_direction(PB09, GPIO_DIRECTION_OFF);

	gpio_set_pin_function(PB09, PINMUX_PB09B_ADC1_AIN1);
}
     d88:	b005      	add	sp, #20
     d8a:	bdf0      	pop	{r4, r5, r6, r7, pc}
     d8c:	40000800 	.word	0x40000800
     d90:	40001c00 	.word	0x40001c00
     d94:	200000e0 	.word	0x200000e0
     d98:	200004c8 	.word	0x200004c8
     d9c:	20000420 	.word	0x20000420
     da0:	43002000 	.word	0x43002000
     da4:	000018b9 	.word	0x000018b9
     da8:	00001961 	.word	0x00001961
     dac:	41008000 	.word	0x41008000

00000db0 <DIGITAL_GLUE_LOGIC_0_PORT_init>:
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
     db0:	4b18      	ldr	r3, [pc, #96]	; (e14 <DIGITAL_GLUE_LOGIC_0_PORT_init+0x64>)
     db2:	f893 2044 	ldrb.w	r2, [r3, #68]	; 0x44
	tmp &= ~PORT_PINCFG_PMUXEN;
     db6:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
     dba:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
     dbe:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
     dc2:	f893 2032 	ldrb.w	r2, [r3, #50]	; 0x32
	tmp &= ~PORT_PMUX_PMUXE_Msk;
     dc6:	f002 02f0 	and.w	r2, r2, #240	; 0xf0
	tmp |= PORT_PMUX_PMUXE(data);
     dca:	f042 020d 	orr.w	r2, r2, #13
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
     dce:	f883 2032 	strb.w	r2, [r3, #50]	; 0x32
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
     dd2:	f893 2045 	ldrb.w	r2, [r3, #69]	; 0x45
	tmp &= ~PORT_PINCFG_PMUXEN;
     dd6:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
     dda:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
     dde:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
     de2:	f893 2032 	ldrb.w	r2, [r3, #50]	; 0x32
	tmp &= ~PORT_PMUX_PMUXO_Msk;
     de6:	f002 020f 	and.w	r2, r2, #15
	tmp |= PORT_PMUX_PMUXO(data);
     dea:	f042 02d0 	orr.w	r2, r2, #208	; 0xd0
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
     dee:	f883 2032 	strb.w	r2, [r3, #50]	; 0x32
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
     df2:	f893 2046 	ldrb.w	r2, [r3, #70]	; 0x46
	tmp &= ~PORT_PINCFG_PMUXEN;
     df6:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
     dfa:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
     dfe:	f883 2046 	strb.w	r2, [r3, #70]	; 0x46
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
     e02:	f893 2033 	ldrb.w	r2, [r3, #51]	; 0x33
	tmp &= ~PORT_PMUX_PMUXE_Msk;
     e06:	f002 02f0 	and.w	r2, r2, #240	; 0xf0
	tmp |= PORT_PMUX_PMUXE(data);
     e0a:	f042 020d 	orr.w	r2, r2, #13
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
     e0e:	f883 2033 	strb.w	r2, [r3, #51]	; 0x33
     e12:	4770      	bx	lr
     e14:	41008000 	.word	0x41008000

00000e18 <DIGITAL_GLUE_LOGIC_0_CLOCK_init>:
	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL;
     e18:	4a04      	ldr	r2, [pc, #16]	; (e2c <DIGITAL_GLUE_LOGIC_0_CLOCK_init+0x14>)
     e1a:	69d3      	ldr	r3, [r2, #28]
     e1c:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
     e20:	61d3      	str	r3, [r2, #28]
     e22:	2240      	movs	r2, #64	; 0x40
     e24:	4b02      	ldr	r3, [pc, #8]	; (e30 <DIGITAL_GLUE_LOGIC_0_CLOCK_init+0x18>)
     e26:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
     e2a:	4770      	bx	lr
     e2c:	40000800 	.word	0x40000800
     e30:	40001c00 	.word	0x40001c00

00000e34 <DIGITAL_GLUE_LOGIC_0_init>:
	hri_mclk_set_APBCMASK_CCL_bit(MCLK);
	hri_gclk_write_PCHCTRL_reg(GCLK, CCL_GCLK_ID, CONF_GCLK_CCL_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}

void DIGITAL_GLUE_LOGIC_0_init(void)
{
     e34:	b508      	push	{r3, lr}
	DIGITAL_GLUE_LOGIC_0_CLOCK_init();
     e36:	4b03      	ldr	r3, [pc, #12]	; (e44 <DIGITAL_GLUE_LOGIC_0_init+0x10>)
     e38:	4798      	blx	r3
 *  \brief Initialize the custom logic hardware
 *  \return Initialization operation status
 */
static inline int32_t custom_logic_init(void)
{
	return _custom_logic_init();
     e3a:	4b03      	ldr	r3, [pc, #12]	; (e48 <DIGITAL_GLUE_LOGIC_0_init+0x14>)
     e3c:	4798      	blx	r3
	custom_logic_init();
	DIGITAL_GLUE_LOGIC_0_PORT_init();
     e3e:	4b03      	ldr	r3, [pc, #12]	; (e4c <DIGITAL_GLUE_LOGIC_0_init+0x18>)
     e40:	4798      	blx	r3
     e42:	bd08      	pop	{r3, pc}
     e44:	00000e19 	.word	0x00000e19
     e48:	00002385 	.word	0x00002385
     e4c:	00000db1 	.word	0x00000db1

00000e50 <EXTERNAL_IRQ_0_init>:
}

void EXTERNAL_IRQ_0_init(void)
{
     e50:	b508      	push	{r3, lr}
     e52:	2240      	movs	r2, #64	; 0x40
     e54:	4b15      	ldr	r3, [pc, #84]	; (eac <EXTERNAL_IRQ_0_init+0x5c>)
     e56:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC;
     e5a:	4a15      	ldr	r2, [pc, #84]	; (eb0 <EXTERNAL_IRQ_0_init+0x60>)
     e5c:	6953      	ldr	r3, [r2, #20]
     e5e:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
     e62:	6153      	str	r3, [r2, #20]
	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
     e64:	4b13      	ldr	r3, [pc, #76]	; (eb4 <EXTERNAL_IRQ_0_init+0x64>)
     e66:	2220      	movs	r2, #32
     e68:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
     e6c:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
     e70:	f502 3200 	add.w	r2, r2, #131072	; 0x20000
     e74:	f8c3 20a8 	str.w	r2, [r3, #168]	; 0xa8
     e78:	4a0f      	ldr	r2, [pc, #60]	; (eb8 <EXTERNAL_IRQ_0_init+0x68>)
     e7a:	f8c3 20a8 	str.w	r2, [r3, #168]	; 0xa8
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
     e7e:	f893 20c5 	ldrb.w	r2, [r3, #197]	; 0xc5
     e82:	f002 02fb 	and.w	r2, r2, #251	; 0xfb
     e86:	f883 20c5 	strb.w	r2, [r3, #197]	; 0xc5
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
     e8a:	f893 20c5 	ldrb.w	r2, [r3, #197]	; 0xc5
	tmp &= ~PORT_PINCFG_PMUXEN;
     e8e:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
     e92:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
     e96:	f883 20c5 	strb.w	r2, [r3, #197]	; 0xc5
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
     e9a:	f893 20b2 	ldrb.w	r2, [r3, #178]	; 0xb2
	tmp &= ~PORT_PMUX_PMUXO_Msk;
     e9e:	f002 020f 	and.w	r2, r2, #15
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
     ea2:	f883 20b2 	strb.w	r2, [r3, #178]	; 0xb2
	                       // <GPIO_PULL_DOWN"> Pull-down
	                       GPIO_PULL_OFF);

	gpio_set_pin_function(nDRV_RESET, PINMUX_PB05A_EIC_EXTINT5);

	ext_irq_init();
     ea6:	4b05      	ldr	r3, [pc, #20]	; (ebc <EXTERNAL_IRQ_0_init+0x6c>)
     ea8:	4798      	blx	r3
     eaa:	bd08      	pop	{r3, pc}
     eac:	40001c00 	.word	0x40001c00
     eb0:	40000800 	.word	0x40000800
     eb4:	41008000 	.word	0x41008000
     eb8:	c0020000 	.word	0xc0020000
     ebc:	00001b6d 	.word	0x00001b6d

00000ec0 <EVENT_SYSTEM_0_init>:
}

void EVENT_SYSTEM_0_init(void)
{
     ec0:	b508      	push	{r3, lr}
     ec2:	4b07      	ldr	r3, [pc, #28]	; (ee0 <EVENT_SYSTEM_0_init+0x20>)
     ec4:	2240      	movs	r2, #64	; 0x40
     ec6:	f8c3 20ac 	str.w	r2, [r3, #172]	; 0xac
     eca:	f8c3 20b0 	str.w	r2, [r3, #176]	; 0xb0
	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_EVSYS;
     ece:	4a05      	ldr	r2, [pc, #20]	; (ee4 <EVENT_SYSTEM_0_init+0x24>)
     ed0:	6993      	ldr	r3, [r2, #24]
     ed2:	f043 0380 	orr.w	r3, r3, #128	; 0x80
     ed6:	6193      	str	r3, [r2, #24]
	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_0, CONF_GCLK_EVSYS_CHANNEL_0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_1, CONF_GCLK_EVSYS_CHANNEL_1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));

	hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);

	event_system_init();
     ed8:	4b03      	ldr	r3, [pc, #12]	; (ee8 <EVENT_SYSTEM_0_init+0x28>)
     eda:	4798      	blx	r3
     edc:	bd08      	pop	{r3, pc}
     ede:	bf00      	nop
     ee0:	40001c00 	.word	0x40001c00
     ee4:	40000800 	.word	0x40000800
     ee8:	00001b1d 	.word	0x00001b1d

00000eec <POSITION_DECODER_0_CLOCK_init>:
	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PDEC;
     eec:	4a04      	ldr	r2, [pc, #16]	; (f00 <POSITION_DECODER_0_CLOCK_init+0x14>)
     eee:	69d3      	ldr	r3, [r2, #28]
     ef0:	f043 0380 	orr.w	r3, r3, #128	; 0x80
     ef4:	61d3      	str	r3, [r2, #28]
     ef6:	2240      	movs	r2, #64	; 0x40
     ef8:	4b02      	ldr	r3, [pc, #8]	; (f04 <POSITION_DECODER_0_CLOCK_init+0x18>)
     efa:	f8c3 20fc 	str.w	r2, [r3, #252]	; 0xfc
     efe:	4770      	bx	lr
     f00:	40000800 	.word	0x40000800
     f04:	40001c00 	.word	0x40001c00

00000f08 <POSITION_DECODER_0_init>:
	hri_mclk_set_APBCMASK_PDEC_bit(MCLK);
	hri_gclk_write_PCHCTRL_reg(GCLK, PDEC_GCLK_ID, CONF_GCLK_PDEC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}

void POSITION_DECODER_0_init(void)
{
     f08:	b508      	push	{r3, lr}
	POSITION_DECODER_0_CLOCK_init();
     f0a:	4b03      	ldr	r3, [pc, #12]	; (f18 <POSITION_DECODER_0_init+0x10>)
     f0c:	4798      	blx	r3
	pdec_async_init(&POSITION_DECODER_0, PDEC);
     f0e:	4903      	ldr	r1, [pc, #12]	; (f1c <POSITION_DECODER_0_init+0x14>)
     f10:	4803      	ldr	r0, [pc, #12]	; (f20 <POSITION_DECODER_0_init+0x18>)
     f12:	4b04      	ldr	r3, [pc, #16]	; (f24 <POSITION_DECODER_0_init+0x1c>)
     f14:	4798      	blx	r3
     f16:	bd08      	pop	{r3, pc}
     f18:	00000eed 	.word	0x00000eed
     f1c:	42001c00 	.word	0x42001c00
     f20:	200004ac 	.word	0x200004ac
     f24:	00001c6d 	.word	0x00001c6d

00000f28 <SPI_0_PORT_init>:
	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
     f28:	4b2c      	ldr	r3, [pc, #176]	; (fdc <SPI_0_PORT_init+0xb4>)
     f2a:	f44f 3280 	mov.w	r2, #65536	; 0x10000
     f2e:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
     f32:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
     f36:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
     f3a:	f8c3 10a8 	str.w	r1, [r3, #168]	; 0xa8
     f3e:	4a28      	ldr	r2, [pc, #160]	; (fe0 <SPI_0_PORT_init+0xb8>)
     f40:	f8c3 20a8 	str.w	r2, [r3, #168]	; 0xa8
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
     f44:	f893 20d0 	ldrb.w	r2, [r3, #208]	; 0xd0
	tmp &= ~PORT_PINCFG_PMUXEN;
     f48:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
     f4c:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
     f50:	f883 20d0 	strb.w	r2, [r3, #208]	; 0xd0
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
     f54:	f893 20b8 	ldrb.w	r2, [r3, #184]	; 0xb8
	tmp &= ~PORT_PMUX_PMUXE_Msk;
     f58:	f002 02f0 	and.w	r2, r2, #240	; 0xf0
	tmp |= PORT_PMUX_PMUXE(data);
     f5c:	f042 0202 	orr.w	r2, r2, #2
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
     f60:	f883 20b8 	strb.w	r2, [r3, #184]	; 0xb8
	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
     f64:	f44f 3200 	mov.w	r2, #131072	; 0x20000
     f68:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
     f6c:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
     f70:	f8c3 10a8 	str.w	r1, [r3, #168]	; 0xa8
     f74:	4a1b      	ldr	r2, [pc, #108]	; (fe4 <SPI_0_PORT_init+0xbc>)
     f76:	f8c3 20a8 	str.w	r2, [r3, #168]	; 0xa8
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
     f7a:	f893 20d1 	ldrb.w	r2, [r3, #209]	; 0xd1
	tmp &= ~PORT_PINCFG_PMUXEN;
     f7e:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
     f82:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
     f86:	f883 20d1 	strb.w	r2, [r3, #209]	; 0xd1
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
     f8a:	f893 20b8 	ldrb.w	r2, [r3, #184]	; 0xb8
	tmp &= ~PORT_PMUX_PMUXO_Msk;
     f8e:	f002 020f 	and.w	r2, r2, #15
	tmp |= PORT_PMUX_PMUXO(data);
     f92:	f042 0220 	orr.w	r2, r2, #32
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
     f96:	f883 20b8 	strb.w	r2, [r3, #184]	; 0xb8
	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
     f9a:	2202      	movs	r2, #2
     f9c:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
     fa0:	4a11      	ldr	r2, [pc, #68]	; (fe8 <SPI_0_PORT_init+0xc0>)
     fa2:	f8c3 20a8 	str.w	r2, [r3, #168]	; 0xa8
     fa6:	4a11      	ldr	r2, [pc, #68]	; (fec <SPI_0_PORT_init+0xc4>)
     fa8:	f8c3 20a8 	str.w	r2, [r3, #168]	; 0xa8
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
     fac:	f893 20c1 	ldrb.w	r2, [r3, #193]	; 0xc1
     fb0:	f002 02fb 	and.w	r2, r2, #251	; 0xfb
     fb4:	f883 20c1 	strb.w	r2, [r3, #193]	; 0xc1
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
     fb8:	f893 20c1 	ldrb.w	r2, [r3, #193]	; 0xc1
	tmp &= ~PORT_PINCFG_PMUXEN;
     fbc:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
     fc0:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
     fc4:	f883 20c1 	strb.w	r2, [r3, #193]	; 0xc1
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
     fc8:	f893 20b0 	ldrb.w	r2, [r3, #176]	; 0xb0
	tmp &= ~PORT_PMUX_PMUXO_Msk;
     fcc:	f002 020f 	and.w	r2, r2, #15
	tmp |= PORT_PMUX_PMUXO(data);
     fd0:	f042 0230 	orr.w	r2, r2, #48	; 0x30
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
     fd4:	f883 20b0 	strb.w	r2, [r3, #176]	; 0xb0
     fd8:	4770      	bx	lr
     fda:	bf00      	nop
     fdc:	41008000 	.word	0x41008000
     fe0:	c0000001 	.word	0xc0000001
     fe4:	c0000002 	.word	0xc0000002
     fe8:	40020002 	.word	0x40020002
     fec:	c0020000 	.word	0xc0020000

00000ff0 <SPI_0_CLOCK_init>:
     ff0:	4b06      	ldr	r3, [pc, #24]	; (100c <SPI_0_CLOCK_init+0x1c>)
     ff2:	2240      	movs	r2, #64	; 0x40
     ff4:	f8c3 210c 	str.w	r2, [r3, #268]	; 0x10c
     ff8:	2243      	movs	r2, #67	; 0x43
     ffa:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5;
     ffe:	4a04      	ldr	r2, [pc, #16]	; (1010 <SPI_0_CLOCK_init+0x20>)
    1000:	6a13      	ldr	r3, [r2, #32]
    1002:	f043 0302 	orr.w	r3, r3, #2
    1006:	6213      	str	r3, [r2, #32]
    1008:	4770      	bx	lr
    100a:	bf00      	nop
    100c:	40001c00 	.word	0x40001c00
    1010:	40000800 	.word	0x40000800

00001014 <SPI_0_init>:

	hri_mclk_set_APBDMASK_SERCOM5_bit(MCLK);
}

void SPI_0_init(void)
{
    1014:	b508      	push	{r3, lr}
	SPI_0_CLOCK_init();
    1016:	4b04      	ldr	r3, [pc, #16]	; (1028 <SPI_0_init+0x14>)
    1018:	4798      	blx	r3
	spi_m_dma_init(&SPI_0, SERCOM5);
    101a:	4904      	ldr	r1, [pc, #16]	; (102c <SPI_0_init+0x18>)
    101c:	4804      	ldr	r0, [pc, #16]	; (1030 <SPI_0_init+0x1c>)
    101e:	4b05      	ldr	r3, [pc, #20]	; (1034 <SPI_0_init+0x20>)
    1020:	4798      	blx	r3
	SPI_0_PORT_init();
    1022:	4b05      	ldr	r3, [pc, #20]	; (1038 <SPI_0_init+0x24>)
    1024:	4798      	blx	r3
    1026:	bd08      	pop	{r3, pc}
    1028:	00000ff1 	.word	0x00000ff1
    102c:	43000400 	.word	0x43000400
    1030:	2000047c 	.word	0x2000047c
    1034:	00001df9 	.word	0x00001df9
    1038:	00000f29 	.word	0x00000f29

0000103c <TC_SPEED_CLOCK_init>:
	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0;
    103c:	4b07      	ldr	r3, [pc, #28]	; (105c <TC_SPEED_CLOCK_init+0x20>)
    103e:	695a      	ldr	r2, [r3, #20]
    1040:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
    1044:	615a      	str	r2, [r3, #20]
	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC1;
    1046:	695a      	ldr	r2, [r3, #20]
    1048:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
    104c:	615a      	str	r2, [r3, #20]
    104e:	2240      	movs	r2, #64	; 0x40
    1050:	f503 53a0 	add.w	r3, r3, #5120	; 0x1400
    1054:	f8c3 20a4 	str.w	r2, [r3, #164]	; 0xa4
    1058:	4770      	bx	lr
    105a:	bf00      	nop
    105c:	40000800 	.word	0x40000800

00001060 <TC_ECAT_CLOCK_init>:
	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC7;
    1060:	4a04      	ldr	r2, [pc, #16]	; (1074 <TC_ECAT_CLOCK_init+0x14>)
    1062:	6a13      	ldr	r3, [r2, #32]
    1064:	f043 0340 	orr.w	r3, r3, #64	; 0x40
    1068:	6213      	str	r3, [r2, #32]
    106a:	2240      	movs	r2, #64	; 0x40
    106c:	4b02      	ldr	r3, [pc, #8]	; (1078 <TC_ECAT_CLOCK_init+0x18>)
    106e:	f8c3 211c 	str.w	r2, [r3, #284]	; 0x11c
    1072:	4770      	bx	lr
    1074:	40000800 	.word	0x40000800
    1078:	40001c00 	.word	0x40001c00

0000107c <TCC_PWM_PORT_init>:
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
    107c:	4b30      	ldr	r3, [pc, #192]	; (1140 <TCC_PWM_PORT_init+0xc4>)
    107e:	f893 20da 	ldrb.w	r2, [r3, #218]	; 0xda
	tmp &= ~PORT_PINCFG_PMUXEN;
    1082:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
    1086:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
    108a:	f883 20da 	strb.w	r2, [r3, #218]	; 0xda
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
    108e:	f893 20bd 	ldrb.w	r2, [r3, #189]	; 0xbd
	tmp &= ~PORT_PMUX_PMUXE_Msk;
    1092:	f002 02f0 	and.w	r2, r2, #240	; 0xf0
	tmp |= PORT_PMUX_PMUXE(data);
    1096:	f042 0205 	orr.w	r2, r2, #5
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
    109a:	f883 20bd 	strb.w	r2, [r3, #189]	; 0xbd
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
    109e:	f893 20db 	ldrb.w	r2, [r3, #219]	; 0xdb
	tmp &= ~PORT_PINCFG_PMUXEN;
    10a2:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
    10a6:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
    10aa:	f883 20db 	strb.w	r2, [r3, #219]	; 0xdb
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
    10ae:	f893 20bd 	ldrb.w	r2, [r3, #189]	; 0xbd
	tmp &= ~PORT_PMUX_PMUXO_Msk;
    10b2:	f002 020f 	and.w	r2, r2, #15
	tmp |= PORT_PMUX_PMUXO(data);
    10b6:	f042 0250 	orr.w	r2, r2, #80	; 0x50
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
    10ba:	f883 20bd 	strb.w	r2, [r3, #189]	; 0xbd
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
    10be:	f893 20dc 	ldrb.w	r2, [r3, #220]	; 0xdc
	tmp &= ~PORT_PINCFG_PMUXEN;
    10c2:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
    10c6:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
    10ca:	f883 20dc 	strb.w	r2, [r3, #220]	; 0xdc
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
    10ce:	f893 20be 	ldrb.w	r2, [r3, #190]	; 0xbe
	tmp &= ~PORT_PMUX_PMUXE_Msk;
    10d2:	f002 02f0 	and.w	r2, r2, #240	; 0xf0
	tmp |= PORT_PMUX_PMUXE(data);
    10d6:	f042 0205 	orr.w	r2, r2, #5
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
    10da:	f883 20be 	strb.w	r2, [r3, #190]	; 0xbe
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
    10de:	f893 20dd 	ldrb.w	r2, [r3, #221]	; 0xdd
	tmp &= ~PORT_PINCFG_PMUXEN;
    10e2:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
    10e6:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
    10ea:	f883 20dd 	strb.w	r2, [r3, #221]	; 0xdd
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
    10ee:	f893 20be 	ldrb.w	r2, [r3, #190]	; 0xbe
	tmp &= ~PORT_PMUX_PMUXO_Msk;
    10f2:	f002 020f 	and.w	r2, r2, #15
	tmp |= PORT_PMUX_PMUXO(data);
    10f6:	f042 0250 	orr.w	r2, r2, #80	; 0x50
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
    10fa:	f883 20be 	strb.w	r2, [r3, #190]	; 0xbe
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
    10fe:	f893 2056 	ldrb.w	r2, [r3, #86]	; 0x56
	tmp &= ~PORT_PINCFG_PMUXEN;
    1102:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
    1106:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
    110a:	f883 2056 	strb.w	r2, [r3, #86]	; 0x56
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
    110e:	f893 203b 	ldrb.w	r2, [r3, #59]	; 0x3b
	tmp &= ~PORT_PMUX_PMUXE_Msk;
    1112:	f002 02f0 	and.w	r2, r2, #240	; 0xf0
	tmp |= PORT_PMUX_PMUXE(data);
    1116:	f042 0205 	orr.w	r2, r2, #5
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
    111a:	f883 203b 	strb.w	r2, [r3, #59]	; 0x3b
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
    111e:	f893 2057 	ldrb.w	r2, [r3, #87]	; 0x57
	tmp &= ~PORT_PINCFG_PMUXEN;
    1122:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
    1126:	f042 0201 	orr.w	r2, r2, #1
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
    112a:	f883 2057 	strb.w	r2, [r3, #87]	; 0x57
	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
    112e:	f893 203b 	ldrb.w	r2, [r3, #59]	; 0x3b
	tmp &= ~PORT_PMUX_PMUXO_Msk;
    1132:	f002 020f 	and.w	r2, r2, #15
	tmp |= PORT_PMUX_PMUXO(data);
    1136:	f042 0250 	orr.w	r2, r2, #80	; 0x50
	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
    113a:	f883 203b 	strb.w	r2, [r3, #59]	; 0x3b
    113e:	4770      	bx	lr
    1140:	41008000 	.word	0x41008000

00001144 <TCC_PWM_CLOCK_init>:
	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC1;
    1144:	4a04      	ldr	r2, [pc, #16]	; (1158 <TCC_PWM_CLOCK_init+0x14>)
    1146:	6993      	ldr	r3, [r2, #24]
    1148:	f443 5380 	orr.w	r3, r3, #4096	; 0x1000
    114c:	6193      	str	r3, [r2, #24]
    114e:	2240      	movs	r2, #64	; 0x40
    1150:	4b02      	ldr	r3, [pc, #8]	; (115c <TCC_PWM_CLOCK_init+0x18>)
    1152:	f8c3 20e4 	str.w	r2, [r3, #228]	; 0xe4
    1156:	4770      	bx	lr
    1158:	40000800 	.word	0x40000800
    115c:	40001c00 	.word	0x40001c00

00001160 <TCC_PWM_init>:
	hri_mclk_set_APBBMASK_TCC1_bit(MCLK);
	hri_gclk_write_PCHCTRL_reg(GCLK, TCC1_GCLK_ID, CONF_GCLK_TCC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}

void TCC_PWM_init(void)
{
    1160:	b508      	push	{r3, lr}
	TCC_PWM_CLOCK_init();
    1162:	4b06      	ldr	r3, [pc, #24]	; (117c <TCC_PWM_init+0x1c>)
    1164:	4798      	blx	r3
	TCC_PWM_PORT_init();
    1166:	4b06      	ldr	r3, [pc, #24]	; (1180 <TCC_PWM_init+0x20>)
    1168:	4798      	blx	r3
	pwm_init(&TCC_PWM, TCC1, _tcc_get_pwm());
    116a:	4b06      	ldr	r3, [pc, #24]	; (1184 <TCC_PWM_init+0x24>)
    116c:	4798      	blx	r3
    116e:	4602      	mov	r2, r0
    1170:	4905      	ldr	r1, [pc, #20]	; (1188 <TCC_PWM_init+0x28>)
    1172:	4806      	ldr	r0, [pc, #24]	; (118c <TCC_PWM_init+0x2c>)
    1174:	4b06      	ldr	r3, [pc, #24]	; (1190 <TCC_PWM_init+0x30>)
    1176:	4798      	blx	r3
    1178:	bd08      	pop	{r3, pc}
    117a:	bf00      	nop
    117c:	00001145 	.word	0x00001145
    1180:	0000107d 	.word	0x0000107d
    1184:	000034f9 	.word	0x000034f9
    1188:	41018000 	.word	0x41018000
    118c:	20000404 	.word	0x20000404
    1190:	00001cc9 	.word	0x00001cc9

00001194 <system_init>:
}

void system_init(void)
{
    1194:	b510      	push	{r4, lr}
 * Currently the following initialization functions are supported:
 *  - System clock initialization
 */
static inline void init_mcu(void)
{
	_init_chip();
    1196:	4b56      	ldr	r3, [pc, #344]	; (12f0 <system_init+0x15c>)
    1198:	4798      	blx	r3
	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
    119a:	4b56      	ldr	r3, [pc, #344]	; (12f4 <system_init+0x160>)
    119c:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
    11a0:	615a      	str	r2, [r3, #20]
	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
    11a2:	609a      	str	r2, [r3, #8]
	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
    11a4:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    11a8:	629a      	str	r2, [r3, #40]	; 0x28
    11aa:	4953      	ldr	r1, [pc, #332]	; (12f8 <system_init+0x164>)
    11ac:	6299      	str	r1, [r3, #40]	; 0x28
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
    11ae:	f893 105b 	ldrb.w	r1, [r3, #91]	; 0x5b
	tmp &= ~PORT_PINCFG_PMUXEN;
    11b2:	f001 01fe 	and.w	r1, r1, #254	; 0xfe
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
    11b6:	f883 105b 	strb.w	r1, [r3, #91]	; 0x5b
	((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
    11ba:	2101      	movs	r1, #1
    11bc:	f8c3 1098 	str.w	r1, [r3, #152]	; 0x98
	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
    11c0:	f8c3 1088 	str.w	r1, [r3, #136]	; 0x88
	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
    11c4:	f101 4180 	add.w	r1, r1, #1073741824	; 0x40000000
    11c8:	f8c3 10a8 	str.w	r1, [r3, #168]	; 0xa8
    11cc:	f04f 4140 	mov.w	r1, #3221225472	; 0xc0000000
    11d0:	f8c3 10a8 	str.w	r1, [r3, #168]	; 0xa8
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
    11d4:	f893 00c0 	ldrb.w	r0, [r3, #192]	; 0xc0
	tmp &= ~PORT_PINCFG_PMUXEN;
    11d8:	f000 00fe 	and.w	r0, r0, #254	; 0xfe
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
    11dc:	f883 00c0 	strb.w	r0, [r3, #192]	; 0xc0
	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
    11e0:	f04f 4000 	mov.w	r0, #2147483648	; 0x80000000
    11e4:	f8c3 0084 	str.w	r0, [r3, #132]	; 0x84
	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
    11e8:	4c44      	ldr	r4, [pc, #272]	; (12fc <system_init+0x168>)
    11ea:	f8c3 40a8 	str.w	r4, [r3, #168]	; 0xa8
    11ee:	f104 2480 	add.w	r4, r4, #2147516416	; 0x80008000
    11f2:	f8c3 40a8 	str.w	r4, [r3, #168]	; 0xa8
	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
    11f6:	f8c3 0084 	str.w	r0, [r3, #132]	; 0x84
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN;
    11fa:	f893 40df 	ldrb.w	r4, [r3, #223]	; 0xdf
    11fe:	f044 0404 	orr.w	r4, r4, #4
    1202:	f883 40df 	strb.w	r4, [r3, #223]	; 0xdf
	((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
    1206:	f8c3 0098 	str.w	r0, [r3, #152]	; 0x98
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
    120a:	f893 00df 	ldrb.w	r0, [r3, #223]	; 0xdf
	tmp &= ~PORT_PINCFG_PMUXEN;
    120e:	f000 00fe 	and.w	r0, r0, #254	; 0xfe
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
    1212:	f883 00df 	strb.w	r0, [r3, #223]	; 0xdf
	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
    1216:	2002      	movs	r0, #2
    1218:	f8c3 0114 	str.w	r0, [r3, #276]	; 0x114
	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
    121c:	f8c3 0108 	str.w	r0, [r3, #264]	; 0x108
	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
    1220:	f100 4080 	add.w	r0, r0, #1073741824	; 0x40000000
    1224:	f8c3 0128 	str.w	r0, [r3, #296]	; 0x128
    1228:	f8c3 1128 	str.w	r1, [r3, #296]	; 0x128
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
    122c:	f893 0141 	ldrb.w	r0, [r3, #321]	; 0x141
	tmp &= ~PORT_PINCFG_PMUXEN;
    1230:	f000 00fe 	and.w	r0, r0, #254	; 0xfe
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
    1234:	f883 0141 	strb.w	r0, [r3, #321]	; 0x141
	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
    1238:	2004      	movs	r0, #4
    123a:	f8c3 0114 	str.w	r0, [r3, #276]	; 0x114
	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
    123e:	f8c3 0108 	str.w	r0, [r3, #264]	; 0x108
	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
    1242:	f100 4080 	add.w	r0, r0, #1073741824	; 0x40000000
    1246:	f8c3 0128 	str.w	r0, [r3, #296]	; 0x128
    124a:	f8c3 1128 	str.w	r1, [r3, #296]	; 0x128
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
    124e:	f893 0142 	ldrb.w	r0, [r3, #322]	; 0x142
	tmp &= ~PORT_PINCFG_PMUXEN;
    1252:	f000 00fe 	and.w	r0, r0, #254	; 0xfe
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
    1256:	f883 0142 	strb.w	r0, [r3, #322]	; 0x142
	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
    125a:	2008      	movs	r0, #8
    125c:	f8c3 0114 	str.w	r0, [r3, #276]	; 0x114
	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
    1260:	f8c3 0108 	str.w	r0, [r3, #264]	; 0x108
	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
    1264:	f100 4080 	add.w	r0, r0, #1073741824	; 0x40000000
    1268:	f8c3 0128 	str.w	r0, [r3, #296]	; 0x128
    126c:	f8c3 1128 	str.w	r1, [r3, #296]	; 0x128
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
    1270:	f893 1143 	ldrb.w	r1, [r3, #323]	; 0x143
	tmp &= ~PORT_PINCFG_PMUXEN;
    1274:	f001 01fe 	and.w	r1, r1, #254	; 0xfe
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
    1278:	f883 1143 	strb.w	r1, [r3, #323]	; 0x143
	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
    127c:	f44f 2180 	mov.w	r1, #262144	; 0x40000
    1280:	f8c3 1114 	str.w	r1, [r3, #276]	; 0x114
	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
    1284:	f8c3 1108 	str.w	r1, [r3, #264]	; 0x108
	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
    1288:	f8c3 2128 	str.w	r2, [r3, #296]	; 0x128
    128c:	491c      	ldr	r1, [pc, #112]	; (1300 <system_init+0x16c>)
    128e:	f8c3 1128 	str.w	r1, [r3, #296]	; 0x128
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
    1292:	f893 1152 	ldrb.w	r1, [r3, #338]	; 0x152
	tmp &= ~PORT_PINCFG_PMUXEN;
    1296:	f001 01fe 	and.w	r1, r1, #254	; 0xfe
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
    129a:	f883 1152 	strb.w	r1, [r3, #338]	; 0x152
	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
    129e:	f8c3 2114 	str.w	r2, [r3, #276]	; 0x114
	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
    12a2:	f8c3 2108 	str.w	r2, [r3, #264]	; 0x108
	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
    12a6:	f8c3 2128 	str.w	r2, [r3, #296]	; 0x128
    12aa:	4a16      	ldr	r2, [pc, #88]	; (1304 <system_init+0x170>)
    12ac:	f8c3 2128 	str.w	r2, [r3, #296]	; 0x128
	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
    12b0:	f893 215e 	ldrb.w	r2, [r3, #350]	; 0x15e
	tmp &= ~PORT_PINCFG_PMUXEN;
    12b4:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
    12b8:	f883 215e 	strb.w	r2, [r3, #350]	; 0x15e
	// Set pin direction to output
	gpio_set_pin_direction(DEBUG_4, GPIO_DIRECTION_OUT);

	gpio_set_pin_function(DEBUG_4, GPIO_PIN_FUNCTION_OFF);

	ADC_0_init();
    12bc:	4b12      	ldr	r3, [pc, #72]	; (1308 <system_init+0x174>)
    12be:	4798      	blx	r3
	ADC_1_init();
    12c0:	4b12      	ldr	r3, [pc, #72]	; (130c <system_init+0x178>)
    12c2:	4798      	blx	r3

	DIGITAL_GLUE_LOGIC_0_init();
    12c4:	4b12      	ldr	r3, [pc, #72]	; (1310 <system_init+0x17c>)
    12c6:	4798      	blx	r3

	EXTERNAL_IRQ_0_init();
    12c8:	4b12      	ldr	r3, [pc, #72]	; (1314 <system_init+0x180>)
    12ca:	4798      	blx	r3

	EVENT_SYSTEM_0_init();
    12cc:	4b12      	ldr	r3, [pc, #72]	; (1318 <system_init+0x184>)
    12ce:	4798      	blx	r3

	POSITION_DECODER_0_init();
    12d0:	4b12      	ldr	r3, [pc, #72]	; (131c <system_init+0x188>)
    12d2:	4798      	blx	r3

	SPI_0_init();
    12d4:	4b12      	ldr	r3, [pc, #72]	; (1320 <system_init+0x18c>)
    12d6:	4798      	blx	r3

	TC_SPEED_CLOCK_init();
    12d8:	4b12      	ldr	r3, [pc, #72]	; (1324 <system_init+0x190>)
    12da:	4798      	blx	r3

	TC_SPEED_init();
    12dc:	4b12      	ldr	r3, [pc, #72]	; (1328 <system_init+0x194>)
    12de:	4798      	blx	r3

	TC_ECAT_CLOCK_init();
    12e0:	4b12      	ldr	r3, [pc, #72]	; (132c <system_init+0x198>)
    12e2:	4798      	blx	r3

	TC_ECAT_init();
    12e4:	4b12      	ldr	r3, [pc, #72]	; (1330 <system_init+0x19c>)
    12e6:	4798      	blx	r3

	TCC_PWM_init();
    12e8:	4b12      	ldr	r3, [pc, #72]	; (1334 <system_init+0x1a0>)
    12ea:	4798      	blx	r3
    12ec:	bd10      	pop	{r4, pc}
    12ee:	bf00      	nop
    12f0:	000023e9 	.word	0x000023e9
    12f4:	41008000 	.word	0x41008000
    12f8:	c0000800 	.word	0xc0000800
    12fc:	40020000 	.word	0x40020000
    1300:	c0000004 	.word	0xc0000004
    1304:	c0004000 	.word	0xc0004000
    1308:	00000c6d 	.word	0x00000c6d
    130c:	00000d0d 	.word	0x00000d0d
    1310:	00000e35 	.word	0x00000e35
    1314:	00000e51 	.word	0x00000e51
    1318:	00000ec1 	.word	0x00000ec1
    131c:	00000f09 	.word	0x00000f09
    1320:	00001015 	.word	0x00001015
    1324:	0000103d 	.word	0x0000103d
    1328:	00003511 	.word	0x00003511
    132c:	00001061 	.word	0x00001061
    1330:	000035ad 	.word	0x000035ad
    1334:	00001161 	.word	0x00001161

00001338 <LAN9252_rx_susp>:
	((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
    1338:	2201      	movs	r2, #1
    133a:	4b0e      	ldr	r3, [pc, #56]	; (1374 <LAN9252_rx_susp+0x3c>)
    133c:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
static void LAN9252_rx_susp(struct _dma_resource *resource)
{
	gpio_set_pin_level(ECAT_SPI_CS_PIN, true);
	
	//volatile uint32_t *pointer = ((DMAC->WRBADDR.reg)+0x10*resource->channel_id+12);
	volatile uint32_t *pointer = ((DMAC->WRBADDR.reg)+12);
    1340:	f503 5300 	add.w	r3, r3, #8192	; 0x2000
    1344:	6b9b      	ldr	r3, [r3, #56]	; 0x38

	if (*pointer != &spi_rx_write_fifo_dma_descriptor){
    1346:	68da      	ldr	r2, [r3, #12]
    1348:	4b0b      	ldr	r3, [pc, #44]	; (1378 <LAN9252_rx_susp+0x40>)
    134a:	429a      	cmp	r2, r3
    134c:	d00d      	beq.n	136a <LAN9252_rx_susp+0x32>
		//_dma_enable_transaction(0,false);
		DMAC->Channel[0].CHCTRLB.reg = 0x2; // Resume
    134e:	4b0b      	ldr	r3, [pc, #44]	; (137c <LAN9252_rx_susp+0x44>)
    1350:	2202      	movs	r2, #2
    1352:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
    1356:	2001      	movs	r0, #1
    1358:	4906      	ldr	r1, [pc, #24]	; (1374 <LAN9252_rx_susp+0x3c>)
    135a:	f8c1 0094 	str.w	r0, [r1, #148]	; 0x94
		gpio_set_pin_level(ECAT_SPI_CS_PIN, false);
		//_dma_enable_transaction(1,false); //TX Channel
		DMAC->Channel[1].CHCTRLB.reg = 0x2; // Resume
    135e:	f883 2054 	strb.w	r2, [r3, #84]	; 0x54
		tx_ethercat_done = false;
    1362:	2200      	movs	r2, #0
    1364:	4b06      	ldr	r3, [pc, #24]	; (1380 <LAN9252_rx_susp+0x48>)
    1366:	701a      	strb	r2, [r3, #0]
    1368:	4770      	bx	lr
	}
	else{
		tx_ethercat_done = true;
    136a:	2201      	movs	r2, #1
    136c:	4b04      	ldr	r3, [pc, #16]	; (1380 <LAN9252_rx_susp+0x48>)
    136e:	701a      	strb	r2, [r3, #0]
    1370:	4770      	bx	lr
    1372:	bf00      	nop
    1374:	41008000 	.word	0x41008000
    1378:	200006c8 	.word	0x200006c8
    137c:	4100a000 	.word	0x4100a000
    1380:	200006d8 	.word	0x200006d8

00001384 <setup_transfer_descriptor>:
	
}

static void setup_transfer_descriptor(enum dma_transfer_descriptor_type type, DmacDescriptor *descriptor, const uint32_t start, 
										const uint32_t lenght, const uint32_t next_descriptor, uint16_t block_action)
{
    1384:	b430      	push	{r4, r5}
}

static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw)
{
	DMAC_CRITICAL_SECTION_ENTER();
	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID;
    1386:	880c      	ldrh	r4, [r1, #0]
    1388:	b2a4      	uxth	r4, r4
    138a:	f044 0401 	orr.w	r4, r4, #1
    138e:	800c      	strh	r4, [r1, #0]

static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
{
	uint16_t tmp;
	DMAC_CRITICAL_SECTION_ENTER();
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    1390:	880c      	ldrh	r4, [r1, #0]
    1392:	b2a4      	uxth	r4, r4
	tmp &= ~DMAC_BTCTRL_EVOSEL_Msk;
	tmp |= DMAC_BTCTRL_EVOSEL(data);
    1394:	f044 0406 	orr.w	r4, r4, #6
	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
    1398:	800c      	strh	r4, [r1, #0]
static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const               hw,
                                                               hri_dmacdescriptor_btctrl_reg_t data)
{
	uint16_t tmp;
	DMAC_CRITICAL_SECTION_ENTER();
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    139a:	880c      	ldrh	r4, [r1, #0]
    139c:	b2a4      	uxth	r4, r4
	tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk;
    139e:	f024 0418 	bic.w	r4, r4, #24
	tmp |= DMAC_BTCTRL_BLOCKACT(data);
    13a2:	f8bd 500c 	ldrh.w	r5, [sp, #12]
    13a6:	00ed      	lsls	r5, r5, #3
    13a8:	f005 0518 	and.w	r5, r5, #24
    13ac:	432c      	orrs	r4, r5
	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
    13ae:	800c      	strh	r4, [r1, #0]
static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const               hw,
                                                               hri_dmacdescriptor_btctrl_reg_t data)
{
	uint16_t tmp;
	DMAC_CRITICAL_SECTION_ENTER();
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    13b0:	880c      	ldrh	r4, [r1, #0]
    13b2:	b2a4      	uxth	r4, r4
	tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk;
    13b4:	f424 7440 	bic.w	r4, r4, #768	; 0x300
    13b8:	b2a4      	uxth	r4, r4
	tmp |= DMAC_BTCTRL_BEATSIZE(data);
	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
    13ba:	800c      	strh	r4, [r1, #0]
	hri_dmacdescriptor_set_BTCTRL_VALID_bit(descriptor);										// 1.Validate the Descriptor
	hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(descriptor, DMAC_BTCTRL_EVOSEL_BURST_Val);		// 2. Define mentions 0x3 as Burst, but 0x3 = BEAT (Event strobe when beat transfer complete)
	hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(descriptor, block_action);						// 3. block_action
	hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(descriptor, DMAC_BTCTRL_BEATSIZE_BYTE_Val);		// 4. beat_size
		
	switch (type){
    13bc:	2803      	cmp	r0, #3
    13be:	d814      	bhi.n	13ea <setup_transfer_descriptor+0x66>
    13c0:	e8df f000 	tbb	[pc, r0]
    13c4:	4b253902 	.word	0x4b253902
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    13c8:	8808      	ldrh	r0, [r1, #0]
    13ca:	b280      	uxth	r0, r0
	tmp |= value << DMAC_BTCTRL_SRCINC_Pos;
    13cc:	f440 6080 	orr.w	r0, r0, #1024	; 0x400
	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
    13d0:	8008      	strh	r0, [r1, #0]
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    13d2:	8808      	ldrh	r0, [r1, #0]
    13d4:	b280      	uxth	r0, r0
	tmp &= ~DMAC_BTCTRL_DSTINC;
    13d6:	f420 6000 	bic.w	r0, r0, #2048	; 0x800
    13da:	b280      	uxth	r0, r0
	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
    13dc:	8008      	strh	r0, [r1, #0]
		case DMA_TRANSFER_DESCRIPTOR_TX:
			hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(descriptor, true);						// 5. src_increment_enable = true
			hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(descriptor, false);						// 6. dst_increment_enable = false
			hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(descriptor, start+lenght);				// 10. source_address
    13de:	441a      	add	r2, r3
static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const                hw,
                                                               hri_dmacdescriptor_srcaddr_reg_t data)
{
	uint32_t tmp;
	DMAC_CRITICAL_SECTION_ENTER();
	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
    13e0:	6848      	ldr	r0, [r1, #4]
	tmp &= ~DMAC_SRCADDR_SRCADDR_Msk;
	tmp |= DMAC_SRCADDR_SRCADDR(data);
	((DmacDescriptor *)hw)->SRCADDR.reg = tmp;
    13e2:	604a      	str	r2, [r1, #4]
static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const                hw,
                                                               hri_dmacdescriptor_dstaddr_reg_t data)
{
	uint32_t tmp;
	DMAC_CRITICAL_SECTION_ENTER();
	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
    13e4:	688a      	ldr	r2, [r1, #8]
	tmp &= ~DMAC_DSTADDR_DSTADDR_Msk;
	tmp |= DMAC_DSTADDR_DSTADDR(data);
	((DmacDescriptor *)hw)->DSTADDR.reg = tmp;
    13e6:	4a26      	ldr	r2, [pc, #152]	; (1480 <setup_transfer_descriptor+0xfc>)
    13e8:	608a      	str	r2, [r1, #8]
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    13ea:	880a      	ldrh	r2, [r1, #0]
    13ec:	b292      	uxth	r2, r2
	tmp &= ~DMAC_BTCTRL_STEPSEL;
    13ee:	f422 5280 	bic.w	r2, r2, #4096	; 0x1000
    13f2:	b292      	uxth	r2, r2
	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
    13f4:	800a      	strh	r2, [r1, #0]
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    13f6:	880a      	ldrh	r2, [r1, #0]
	tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk;
    13f8:	f3c2 020c 	ubfx	r2, r2, #0, #13
	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
    13fc:	800a      	strh	r2, [r1, #0]
		break;		
	}
	
	hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(descriptor, false);								// 7. step_selection = DMA_STEPSEL_DST
	hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(descriptor, DMAC_BTCTRL_STEPSIZE_X1_Val);		// 8. step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1
	hri_dmacdescriptor_write_BTCNT_BTCNT_bf(descriptor, lenght);								// 9. block_transfer_count;
    13fe:	b29b      	uxth	r3, r3
	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
    1400:	884a      	ldrh	r2, [r1, #2]
	((DmacDescriptor *)hw)->BTCNT.reg = tmp;
    1402:	804b      	strh	r3, [r1, #2]
static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const                 hw,
                                                                 hri_dmacdescriptor_descaddr_reg_t data)
{
	uint32_t tmp;
	DMAC_CRITICAL_SECTION_ENTER();
	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
    1404:	68cb      	ldr	r3, [r1, #12]
	tmp &= ~DMAC_DESCADDR_DESCADDR_Msk;
	tmp |= DMAC_DESCADDR_DESCADDR(data);
	((DmacDescriptor *)hw)->DESCADDR.reg = tmp;
    1406:	9b02      	ldr	r3, [sp, #8]
    1408:	60cb      	str	r3, [r1, #12]
	hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(descriptor, next_descriptor);					// 12. next_descriptor_address = 0;
    140a:	bc30      	pop	{r4, r5}
    140c:	4770      	bx	lr
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    140e:	880a      	ldrh	r2, [r1, #0]
    1410:	b292      	uxth	r2, r2
	tmp &= ~DMAC_BTCTRL_SRCINC;
    1412:	f422 6280 	bic.w	r2, r2, #1024	; 0x400
    1416:	b292      	uxth	r2, r2
	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
    1418:	800a      	strh	r2, [r1, #0]
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    141a:	880a      	ldrh	r2, [r1, #0]
    141c:	b292      	uxth	r2, r2
	tmp &= ~DMAC_BTCTRL_DSTINC;
    141e:	f422 6200 	bic.w	r2, r2, #2048	; 0x800
    1422:	b292      	uxth	r2, r2
	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
    1424:	800a      	strh	r2, [r1, #0]
			hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(descriptor, dummy_register);			// 10. source_address
    1426:	4a17      	ldr	r2, [pc, #92]	; (1484 <setup_transfer_descriptor+0x100>)
    1428:	6812      	ldr	r2, [r2, #0]
	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
    142a:	6848      	ldr	r0, [r1, #4]
	((DmacDescriptor *)hw)->SRCADDR.reg = tmp;
    142c:	604a      	str	r2, [r1, #4]
	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
    142e:	688a      	ldr	r2, [r1, #8]
	((DmacDescriptor *)hw)->DSTADDR.reg = tmp;
    1430:	4a13      	ldr	r2, [pc, #76]	; (1480 <setup_transfer_descriptor+0xfc>)
    1432:	608a      	str	r2, [r1, #8]
    1434:	e7d9      	b.n	13ea <setup_transfer_descriptor+0x66>
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    1436:	8808      	ldrh	r0, [r1, #0]
    1438:	b280      	uxth	r0, r0
	tmp &= ~DMAC_BTCTRL_SRCINC;
    143a:	f420 6080 	bic.w	r0, r0, #1024	; 0x400
    143e:	b280      	uxth	r0, r0
	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
    1440:	8008      	strh	r0, [r1, #0]
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    1442:	8808      	ldrh	r0, [r1, #0]
    1444:	b280      	uxth	r0, r0
	tmp |= value << DMAC_BTCTRL_DSTINC_Pos;
    1446:	f440 6000 	orr.w	r0, r0, #2048	; 0x800
	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
    144a:	8008      	strh	r0, [r1, #0]
	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
    144c:	6848      	ldr	r0, [r1, #4]
	((DmacDescriptor *)hw)->SRCADDR.reg = tmp;
    144e:	480c      	ldr	r0, [pc, #48]	; (1480 <setup_transfer_descriptor+0xfc>)
    1450:	6048      	str	r0, [r1, #4]
			hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(descriptor, start+lenght);				// 11. destination_address
    1452:	441a      	add	r2, r3
	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
    1454:	6888      	ldr	r0, [r1, #8]
	((DmacDescriptor *)hw)->DSTADDR.reg = tmp;
    1456:	608a      	str	r2, [r1, #8]
    1458:	e7c7      	b.n	13ea <setup_transfer_descriptor+0x66>
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    145a:	880a      	ldrh	r2, [r1, #0]
    145c:	b292      	uxth	r2, r2
	tmp &= ~DMAC_BTCTRL_SRCINC;
    145e:	f422 6280 	bic.w	r2, r2, #1024	; 0x400
    1462:	b292      	uxth	r2, r2
	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
    1464:	800a      	strh	r2, [r1, #0]
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    1466:	880a      	ldrh	r2, [r1, #0]
    1468:	b292      	uxth	r2, r2
	tmp &= ~DMAC_BTCTRL_DSTINC;
    146a:	f422 6200 	bic.w	r2, r2, #2048	; 0x800
    146e:	b292      	uxth	r2, r2
	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
    1470:	800a      	strh	r2, [r1, #0]
	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
    1472:	684a      	ldr	r2, [r1, #4]
	((DmacDescriptor *)hw)->SRCADDR.reg = tmp;
    1474:	4a02      	ldr	r2, [pc, #8]	; (1480 <setup_transfer_descriptor+0xfc>)
    1476:	604a      	str	r2, [r1, #4]
	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
    1478:	688a      	ldr	r2, [r1, #8]
	((DmacDescriptor *)hw)->DSTADDR.reg = tmp;
    147a:	4a03      	ldr	r2, [pc, #12]	; (1488 <setup_transfer_descriptor+0x104>)
    147c:	608a      	str	r2, [r1, #8]
    147e:	e7b4      	b.n	13ea <setup_transfer_descriptor+0x66>
    1480:	43000428 	.word	0x43000428
    1484:	00003b88 	.word	0x00003b88
    1488:	20000550 	.word	0x20000550

0000148c <update_telemetry>:
{
    148c:	b082      	sub	sp, #8
	*state				= applicationStatus.currentstate;
    148e:	4a28      	ldr	r2, [pc, #160]	; (1530 <update_telemetry+0xa4>)
    1490:	7811      	ldrb	r1, [r2, #0]
    1492:	4b28      	ldr	r3, [pc, #160]	; (1534 <update_telemetry+0xa8>)
    1494:	7059      	strb	r1, [r3, #1]
	*status				= applicationStatus.fault;
    1496:	7892      	ldrb	r2, [r2, #2]
    1498:	701a      	strb	r2, [r3, #0]
	*motor_rel_position = Motor1.Num_Steps;
    149a:	4a27      	ldr	r2, [pc, #156]	; (1538 <update_telemetry+0xac>)
    149c:	6911      	ldr	r1, [r2, #16]
    149e:	b209      	sxth	r1, r1
    14a0:	81d9      	strh	r1, [r3, #14]
	*motor_abs_position = 0;
    14a2:	2000      	movs	r0, #0
    14a4:	8218      	strh	r0, [r3, #16]
	*motor_dutyCycle	= Motor1.duty_cycle;
    14a6:	8951      	ldrh	r1, [r2, #10]
    14a8:	b209      	sxth	r1, r1
    14aa:	8259      	strh	r1, [r3, #18]
	*motor_speed		= (int16_t)Motor1.calc_rpm;
    14ac:	edd2 7a03 	vldr	s15, [r2, #12]
    14b0:	eefd 7ae7 	vcvt.s32.f32	s15, s15
    14b4:	edcd 7a01 	vstr	s15, [sp, #4]
    14b8:	f9bd 1004 	ldrsh.w	r1, [sp, #4]
    14bc:	8299      	strh	r1, [r3, #20]
	*motor_torque		= 0;
    14be:	82d8      	strh	r0, [r3, #22]
	*motor_currentPHA	= convert_to_mA(Motor1.Iphase_pu.A);
    14c0:	ed92 7a07 	vldr	s14, [r2, #28]
		return (int16_t)(current_PU*1000);
    14c4:	eddf 7a1d 	vldr	s15, [pc, #116]	; 153c <update_telemetry+0xb0>
    14c8:	ee27 7a27 	vmul.f32	s14, s14, s15
    14cc:	eebd 7ac7 	vcvt.s32.f32	s14, s14
    14d0:	ed8d 7a01 	vstr	s14, [sp, #4]
    14d4:	f9bd 1004 	ldrsh.w	r1, [sp, #4]
	*motor_currentPHA	= convert_to_mA(Motor1.Iphase_pu.A);
    14d8:	8319      	strh	r1, [r3, #24]
	*motor_currentPHB	= convert_to_mA(Motor1.Iphase_pu.B);
    14da:	ed92 7a08 	vldr	s14, [r2, #32]
		return (int16_t)(current_PU*1000);
    14de:	ee27 7a27 	vmul.f32	s14, s14, s15
    14e2:	eebd 7ac7 	vcvt.s32.f32	s14, s14
    14e6:	ed8d 7a01 	vstr	s14, [sp, #4]
    14ea:	f9bd 1004 	ldrsh.w	r1, [sp, #4]
	*motor_currentPHB	= convert_to_mA(Motor1.Iphase_pu.B);
    14ee:	8359      	strh	r1, [r3, #26]
	*motor_currentPHC	= convert_to_mA(Motor1.Iphase_pu.C);
    14f0:	ed92 7a09 	vldr	s14, [r2, #36]	; 0x24
		return (int16_t)(current_PU*1000);
    14f4:	ee27 7a27 	vmul.f32	s14, s14, s15
    14f8:	eebd 7ac7 	vcvt.s32.f32	s14, s14
    14fc:	ed8d 7a01 	vstr	s14, [sp, #4]
    1500:	f9bd 1004 	ldrsh.w	r1, [sp, #4]
	*motor_currentPHC	= convert_to_mA(Motor1.Iphase_pu.C);
    1504:	8399      	strh	r1, [r3, #28]
	*motor_currentBUS	= convert_to_mA(Motor1.Iphase_pu.Bus);
    1506:	ed92 7a0a 	vldr	s14, [r2, #40]	; 0x28
		return (int16_t)(current_PU*1000);
    150a:	ee67 7a27 	vmul.f32	s15, s14, s15
    150e:	eefd 7ae7 	vcvt.s32.f32	s15, s15
    1512:	edcd 7a01 	vstr	s15, [sp, #4]
    1516:	f9bd 1004 	ldrsh.w	r1, [sp, #4]
	*motor_currentBUS	= convert_to_mA(Motor1.Iphase_pu.Bus);
    151a:	83d9      	strh	r1, [r3, #30]
	*hall_state			= Motor1.currentHallPattern;
    151c:	7dd1      	ldrb	r1, [r2, #23]
    151e:	b2c9      	uxtb	r1, r1
    1520:	f883 1020 	strb.w	r1, [r3, #32]
	*Spare_byte1		= Motor1.actualDirection;
    1524:	7a12      	ldrb	r2, [r2, #8]
    1526:	b2d2      	uxtb	r2, r2
    1528:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21
}
    152c:	b002      	add	sp, #8
    152e:	4770      	bx	lr
    1530:	20000324 	.word	0x20000324
    1534:	20000590 	.word	0x20000590
    1538:	20000328 	.word	0x20000328
    153c:	447a0000 	.word	0x447a0000

00001540 <update_setpoints>:
	Motor1.desired_position			= *desired_position;
    1540:	4a18      	ldr	r2, [pc, #96]	; (15a4 <update_setpoints+0x64>)
    1542:	f8b2 1042 	ldrh.w	r1, [r2, #66]	; 0x42
    1546:	4b18      	ldr	r3, [pc, #96]	; (15a8 <update_setpoints+0x68>)
    1548:	f8a3 10ce 	strh.w	r1, [r3, #206]	; 0xce
	Motor1.desired_speed			= *desired_speed;
    154c:	f8b2 1044 	ldrh.w	r1, [r2, #68]	; 0x44
    1550:	f8a3 10cc 	strh.w	r1, [r3, #204]	; 0xcc
	Motor1.desired_torque			= convert_int_to_PU(*desired_torque);
    1554:	f8b2 1046 	ldrh.w	r1, [r2, #70]	; 0x46
    1558:	b209      	sxth	r1, r1
		return ((float32_t)input/1000.0);
    155a:	ee07 1a90 	vmov	s15, r1
    155e:	eef8 7ae7 	vcvt.f32.s32	s15, s15
    1562:	ed9f 7a12 	vldr	s14, [pc, #72]	; 15ac <update_setpoints+0x6c>
    1566:	eec7 6a87 	vdiv.f32	s13, s15, s14
	Motor1.desired_torque			= convert_int_to_PU(*desired_torque);
    156a:	edc3 6a32 	vstr	s13, [r3, #200]	; 0xc8
	Motor1.max_velocity				= *max_velocity;
    156e:	f8b2 105a 	ldrh.w	r1, [r2, #90]	; 0x5a
    1572:	f8a3 10d8 	strh.w	r1, [r3, #216]	; 0xd8
	Motor1.max_current				= convert_int_to_PU(*max_current);
    1576:	f8b2 1058 	ldrh.w	r1, [r2, #88]	; 0x58
    157a:	b209      	sxth	r1, r1
		return ((float32_t)input/1000.0);
    157c:	ee07 1a90 	vmov	s15, r1
    1580:	eef8 7ae7 	vcvt.f32.s32	s15, s15
    1584:	eec7 6a87 	vdiv.f32	s13, s15, s14
	Motor1.max_current				= convert_int_to_PU(*max_current);
    1588:	edc3 6a34 	vstr	s13, [r3, #208]	; 0xd0
	Motor1.max_torque				= convert_int_to_PU(*max_torque);	 
    158c:	f8b2 2056 	ldrh.w	r2, [r2, #86]	; 0x56
    1590:	b212      	sxth	r2, r2
		return ((float32_t)input/1000.0);
    1592:	ee07 2a90 	vmov	s15, r2
    1596:	eef8 7ae7 	vcvt.f32.s32	s15, s15
    159a:	eec7 6a87 	vdiv.f32	s13, s15, s14
	Motor1.max_torque				= convert_int_to_PU(*max_torque);	 
    159e:	edc3 6a35 	vstr	s13, [r3, #212]	; 0xd4
    15a2:	4770      	bx	lr
    15a4:	20000590 	.word	0x20000590
    15a8:	20000328 	.word	0x20000328
    15ac:	447a0000 	.word	0x447a0000

000015b0 <One_ms_cycle_callback>:
{
    15b0:	b5f0      	push	{r4, r5, r6, r7, lr}
    15b2:	b083      	sub	sp, #12
	REG_PORT_OUTSET2 = port;
    15b4:	2204      	movs	r2, #4
    15b6:	4b20      	ldr	r3, [pc, #128]	; (1638 <One_ms_cycle_callback+0x88>)
    15b8:	601a      	str	r2, [r3, #0]
	tx_ethercat = true;
    15ba:	2201      	movs	r2, #1
    15bc:	4b1f      	ldr	r3, [pc, #124]	; (163c <One_ms_cycle_callback+0x8c>)
    15be:	701a      	strb	r2, [r3, #0]
	if(tx_ethercat_done){
    15c0:	4b1f      	ldr	r3, [pc, #124]	; (1640 <One_ms_cycle_callback+0x90>)
    15c2:	781b      	ldrb	r3, [r3, #0]
    15c4:	b32b      	cbz	r3, 1612 <One_ms_cycle_callback+0x62>
		volatile int i=0;
    15c6:	2300      	movs	r3, #0
    15c8:	9301      	str	r3, [sp, #4]
		for (i=0;i<ram_rd_start;i++){
    15ca:	9301      	str	r3, [sp, #4]
    15cc:	e00b      	b.n	15e6 <One_ms_cycle_callback+0x36>
			ram_buffer[ram_real_wr_start+i] = ram_buffer[ram_wr_start+i];
    15ce:	9b01      	ldr	r3, [sp, #4]
    15d0:	3340      	adds	r3, #64	; 0x40
    15d2:	9a01      	ldr	r2, [sp, #4]
    15d4:	491b      	ldr	r1, [pc, #108]	; (1644 <One_ms_cycle_callback+0x94>)
    15d6:	f831 2012 	ldrh.w	r2, [r1, r2, lsl #1]
    15da:	b292      	uxth	r2, r2
    15dc:	f821 2013 	strh.w	r2, [r1, r3, lsl #1]
		for (i=0;i<ram_rd_start;i++){
    15e0:	9b01      	ldr	r3, [sp, #4]
    15e2:	3301      	adds	r3, #1
    15e4:	9301      	str	r3, [sp, #4]
    15e6:	9b01      	ldr	r3, [sp, #4]
    15e8:	2b1f      	cmp	r3, #31
    15ea:	ddf0      	ble.n	15ce <One_ms_cycle_callback+0x1e>
    15ec:	2201      	movs	r2, #1
    15ee:	4b16      	ldr	r3, [pc, #88]	; (1648 <One_ms_cycle_callback+0x98>)
    15f0:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
		DMAC->Channel[0].CHCTRLB.reg = 0x2; // Resume		
    15f4:	f503 5300 	add.w	r3, r3, #8192	; 0x2000
    15f8:	2202      	movs	r2, #2
    15fa:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
		DMAC->Channel[1].CHCTRLB.reg = 0x2; // Resume
    15fe:	f883 2054 	strb.w	r2, [r3, #84]	; 0x54
		tx_ethercat_done = false;
    1602:	2200      	movs	r2, #0
    1604:	4b0e      	ldr	r3, [pc, #56]	; (1640 <One_ms_cycle_callback+0x90>)
    1606:	701a      	strb	r2, [r3, #0]
	REG_PORT_OUTCLR2 = port;
    1608:	2204      	movs	r2, #4
    160a:	4b10      	ldr	r3, [pc, #64]	; (164c <One_ms_cycle_callback+0x9c>)
    160c:	601a      	str	r2, [r3, #0]
}
    160e:	b003      	add	sp, #12
    1610:	bdf0      	pop	{r4, r5, r6, r7, pc}
	((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
    1612:	4b0d      	ldr	r3, [pc, #52]	; (1648 <One_ms_cycle_callback+0x98>)
    1614:	2501      	movs	r5, #1
    1616:	f8c3 5098 	str.w	r5, [r3, #152]	; 0x98
		tx_ethercat_done = false;
    161a:	4e09      	ldr	r6, [pc, #36]	; (1640 <One_ms_cycle_callback+0x90>)
    161c:	2400      	movs	r4, #0
    161e:	7034      	strb	r4, [r6, #0]
	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
    1620:	f8c3 5094 	str.w	r5, [r3, #148]	; 0x94
		_dma_enable_transaction(0,false);
    1624:	4621      	mov	r1, r4
    1626:	4620      	mov	r0, r4
    1628:	4f09      	ldr	r7, [pc, #36]	; (1650 <One_ms_cycle_callback+0xa0>)
    162a:	47b8      	blx	r7
		_dma_enable_transaction(1,false);
    162c:	4621      	mov	r1, r4
    162e:	4628      	mov	r0, r5
    1630:	47b8      	blx	r7
		tx_ethercat_done = false;
    1632:	7034      	strb	r4, [r6, #0]
    1634:	e7e8      	b.n	1608 <One_ms_cycle_callback+0x58>
    1636:	bf00      	nop
    1638:	41008118 	.word	0x41008118
    163c:	20000690 	.word	0x20000690
    1640:	200006d8 	.word	0x200006d8
    1644:	20000590 	.word	0x20000590
    1648:	41008000 	.word	0x41008000
    164c:	41008114 	.word	0x41008114
    1650:	00002705 	.word	0x00002705

00001654 <ethercat_update>:
	if (tx_ethercat){
    1654:	4b03      	ldr	r3, [pc, #12]	; (1664 <ethercat_update+0x10>)
    1656:	781b      	ldrb	r3, [r3, #0]
    1658:	b113      	cbz	r3, 1660 <ethercat_update+0xc>
		tx_ethercat = false;
    165a:	2200      	movs	r2, #0
    165c:	4b01      	ldr	r3, [pc, #4]	; (1664 <ethercat_update+0x10>)
    165e:	701a      	strb	r2, [r3, #0]
    1660:	4770      	bx	lr
    1662:	bf00      	nop
    1664:	20000690 	.word	0x20000690

00001668 <configure_ethercat_dma_descriptors>:
{
    1668:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    166c:	b083      	sub	sp, #12
	TC_ECAT_init();
    166e:	4b5d      	ldr	r3, [pc, #372]	; (17e4 <configure_ethercat_dma_descriptors+0x17c>)
    1670:	4798      	blx	r3
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX, &spi_abort_fifo_dma_descriptor, abort_fifo_start, abort_fifo_length, &spi_clear_rd_fifo_dma_descriptor, DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);			//DMA_BLOCK_ACTION_SUSPEND
    1672:	f8df 819c 	ldr.w	r8, [pc, #412]	; 1810 <configure_ethercat_dma_descriptors+0x1a8>
    1676:	4f5c      	ldr	r7, [pc, #368]	; (17e8 <configure_ethercat_dma_descriptors+0x180>)
    1678:	2602      	movs	r6, #2
    167a:	9601      	str	r6, [sp, #4]
    167c:	f8df 9194 	ldr.w	r9, [pc, #404]	; 1814 <configure_ethercat_dma_descriptors+0x1ac>
    1680:	f8cd 9000 	str.w	r9, [sp]
    1684:	2313      	movs	r3, #19
    1686:	f8d8 2004 	ldr.w	r2, [r8, #4]
    168a:	4639      	mov	r1, r7
    168c:	2000      	movs	r0, #0
    168e:	4d57      	ldr	r5, [pc, #348]	; (17ec <configure_ethercat_dma_descriptors+0x184>)
    1690:	47a8      	blx	r5
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_clear_rd_fifo_dma_descriptor,wr_pdram_start,wr_pdram_lenght+2*write_var_num,&spi_write_cl_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);	//DMA_BLOCK_ACTION_SUSPEND
    1692:	f8d8 b008 	ldr.w	fp, [r8, #8]
    1696:	9601      	str	r6, [sp, #4]
    1698:	4c55      	ldr	r4, [pc, #340]	; (17f0 <configure_ethercat_dma_descriptors+0x188>)
    169a:	9400      	str	r4, [sp, #0]
    169c:	2343      	movs	r3, #67	; 0x43
    169e:	465a      	mov	r2, fp
    16a0:	4649      	mov	r1, r9
    16a2:	2000      	movs	r0, #0
    16a4:	47a8      	blx	r5
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_write_cl_fifo_dma_descriptor,cl_pdram_start,cl_pdram_lenght,&spi_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);						//DMA_BLOCK_ACTION_SUSPEND
    16a6:	4b53      	ldr	r3, [pc, #332]	; (17f4 <configure_ethercat_dma_descriptors+0x18c>)
    16a8:	681a      	ldr	r2, [r3, #0]
    16aa:	f8df 916c 	ldr.w	r9, [pc, #364]	; 1818 <configure_ethercat_dma_descriptors+0x1b0>
    16ae:	9601      	str	r6, [sp, #4]
    16b0:	f8cd 9000 	str.w	r9, [sp]
    16b4:	230b      	movs	r3, #11
    16b6:	4621      	mov	r1, r4
    16b8:	2000      	movs	r0, #0
    16ba:	47a8      	blx	r5
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_write_fifo_dma_descriptor,wr_pdram_start,wr_pdram_lenght,&spi_write2ram_dma_descriptor,DMAC_BTCTRL_BLOCKACT_NOACT_Val);							//DMA_BLOCK_ACTION_NOACT
    16bc:	2400      	movs	r4, #0
    16be:	9401      	str	r4, [sp, #4]
    16c0:	f8df a158 	ldr.w	sl, [pc, #344]	; 181c <configure_ethercat_dma_descriptors+0x1b4>
    16c4:	f8cd a000 	str.w	sl, [sp]
    16c8:	2303      	movs	r3, #3
    16ca:	465a      	mov	r2, fp
    16cc:	4649      	mov	r1, r9
    16ce:	4620      	mov	r0, r4
    16d0:	47a8      	blx	r5
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_write2ram_dma_descriptor,&ram_buffer[ram_real_wr_start],2*write_var_num,&spi_config_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);		//DMA_BLOCK_ACTION_SUSPEND
    16d2:	9601      	str	r6, [sp, #4]
    16d4:	f8df b148 	ldr.w	fp, [pc, #328]	; 1820 <configure_ethercat_dma_descriptors+0x1b8>
    16d8:	f8cd b000 	str.w	fp, [sp]
    16dc:	2340      	movs	r3, #64	; 0x40
    16de:	4a46      	ldr	r2, [pc, #280]	; (17f8 <configure_ethercat_dma_descriptors+0x190>)
    16e0:	4651      	mov	r1, sl
    16e2:	4620      	mov	r0, r4
    16e4:	47a8      	blx	r5
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_config_fifo_dma_descriptor,cf_pdram_start,cf_pdram_lenght,&spi_read_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);						//DMA_BLOCK_ACTION_SUSPEND		
    16e6:	9601      	str	r6, [sp, #4]
    16e8:	f8df a138 	ldr.w	sl, [pc, #312]	; 1824 <configure_ethercat_dma_descriptors+0x1bc>
    16ec:	f8cd a000 	str.w	sl, [sp]
    16f0:	2313      	movs	r3, #19
    16f2:	f8d8 200c 	ldr.w	r2, [r8, #12]
    16f6:	4659      	mov	r1, fp
    16f8:	4620      	mov	r0, r4
    16fa:	47a8      	blx	r5
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_read_fifo_dma_descriptor,rd_pdram_start,rd_pdram_lenght,&spi_read2ram_dma_descriptor,DMAC_BTCTRL_BLOCKACT_NOACT_Val);								//DMA_BLOCK_ACTION_NOACT
    16fc:	f8d8 2010 	ldr.w	r2, [r8, #16]
    1700:	9401      	str	r4, [sp, #4]
    1702:	f8df 8124 	ldr.w	r8, [pc, #292]	; 1828 <configure_ethercat_dma_descriptors+0x1c0>
    1706:	f8cd 8000 	str.w	r8, [sp]
    170a:	2303      	movs	r3, #3
    170c:	4651      	mov	r1, sl
    170e:	4620      	mov	r0, r4
    1710:	47a8      	blx	r5
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX_DUMMY,&spi_read2ram_dma_descriptor,0,2*read_var_num,&spi_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);									//DMA_BLOCK_ACTION_SUSPEND
    1712:	9601      	str	r6, [sp, #4]
    1714:	f8cd 9000 	str.w	r9, [sp]
    1718:	2340      	movs	r3, #64	; 0x40
    171a:	4622      	mov	r2, r4
    171c:	4641      	mov	r1, r8
    171e:	4630      	mov	r0, r6
    1720:	47a8      	blx	r5
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_abort_fifo_dma_descriptor,0,cf_pdram_lenght,&spi_rx_clear_rd_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);						//DMA_BLOCK_ACTION_SUSPEND
    1722:	f8df 8108 	ldr.w	r8, [pc, #264]	; 182c <configure_ethercat_dma_descriptors+0x1c4>
    1726:	9601      	str	r6, [sp, #4]
    1728:	f8df 9104 	ldr.w	r9, [pc, #260]	; 1830 <configure_ethercat_dma_descriptors+0x1c8>
    172c:	f8cd 9000 	str.w	r9, [sp]
    1730:	2313      	movs	r3, #19
    1732:	4622      	mov	r2, r4
    1734:	4641      	mov	r1, r8
    1736:	2003      	movs	r0, #3
    1738:	47a8      	blx	r5
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_clear_rd_fifo_dma_descriptor,0,wr_pdram_lenght+2*write_var_num,&spi_rx_write_cl_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);	//DMA_BLOCK_ACTION_SUSPEND
    173a:	9601      	str	r6, [sp, #4]
    173c:	f8df a0f4 	ldr.w	sl, [pc, #244]	; 1834 <configure_ethercat_dma_descriptors+0x1cc>
    1740:	f8cd a000 	str.w	sl, [sp]
    1744:	2343      	movs	r3, #67	; 0x43
    1746:	4622      	mov	r2, r4
    1748:	4649      	mov	r1, r9
    174a:	2003      	movs	r0, #3
    174c:	47a8      	blx	r5
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_write_cl_fifo_dma_descriptor,0,cl_pdram_lenght,&spi_rx_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);						//DMA_BLOCK_ACTION_SUSPEND
    174e:	f8df 90e8 	ldr.w	r9, [pc, #232]	; 1838 <configure_ethercat_dma_descriptors+0x1d0>
    1752:	9601      	str	r6, [sp, #4]
    1754:	f8cd 9000 	str.w	r9, [sp]
    1758:	230b      	movs	r3, #11
    175a:	4622      	mov	r2, r4
    175c:	4651      	mov	r1, sl
    175e:	2003      	movs	r0, #3
    1760:	47a8      	blx	r5
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_write_fifo_dma_descriptor,0,spi_head+2*write_var_num,&spi_rx_config_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);				//DMA_BLOCK_ACTION_SUSPEND
    1762:	9601      	str	r6, [sp, #4]
    1764:	f8df a0d4 	ldr.w	sl, [pc, #212]	; 183c <configure_ethercat_dma_descriptors+0x1d4>
    1768:	f8cd a000 	str.w	sl, [sp]
    176c:	2343      	movs	r3, #67	; 0x43
    176e:	4622      	mov	r2, r4
    1770:	4649      	mov	r1, r9
    1772:	2003      	movs	r0, #3
    1774:	47a8      	blx	r5
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_config_fifo_dma_descriptor,0,cf_pdram_lenght,&spi_rx_read_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);							//DMA_BLOCK_ACTION_SUSPEND
    1776:	9601      	str	r6, [sp, #4]
    1778:	f8df b0c4 	ldr.w	fp, [pc, #196]	; 1840 <configure_ethercat_dma_descriptors+0x1d8>
    177c:	f8cd b000 	str.w	fp, [sp]
    1780:	2313      	movs	r3, #19
    1782:	4622      	mov	r2, r4
    1784:	4651      	mov	r1, sl
    1786:	2003      	movs	r0, #3
    1788:	47a8      	blx	r5
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_read_fifo_dma_descriptor,0,spi_head,&spi_rx_read2ram_dma_descriptor,DMAC_BTCTRL_BLOCKACT_NOACT_Val);										//DMA_BLOCK_ACTION_NOACT
    178a:	9401      	str	r4, [sp, #4]
    178c:	f8df a0b4 	ldr.w	sl, [pc, #180]	; 1844 <configure_ethercat_dma_descriptors+0x1dc>
    1790:	f8cd a000 	str.w	sl, [sp]
    1794:	2303      	movs	r3, #3
    1796:	4622      	mov	r2, r4
    1798:	4659      	mov	r1, fp
    179a:	4618      	mov	r0, r3
    179c:	47a8      	blx	r5
	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX,&spi_rx_read2ram_dma_descriptor,&ram_buffer[ram_rd_start],2*read_var_num,&spi_rx_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);			//DMA_BLOCK_ACTION_SUSPEND
    179e:	9601      	str	r6, [sp, #4]
    17a0:	f8cd 9000 	str.w	r9, [sp]
    17a4:	2340      	movs	r3, #64	; 0x40
    17a6:	4a14      	ldr	r2, [pc, #80]	; (17f8 <configure_ethercat_dma_descriptors+0x190>)
    17a8:	3a40      	subs	r2, #64	; 0x40
    17aa:	4651      	mov	r1, sl
    17ac:	2001      	movs	r0, #1
    17ae:	47a8      	blx	r5
	spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_SUSPEND, LAN9252_rx_susp);
    17b0:	4d12      	ldr	r5, [pc, #72]	; (17fc <configure_ethercat_dma_descriptors+0x194>)
    17b2:	4a13      	ldr	r2, [pc, #76]	; (1800 <configure_ethercat_dma_descriptors+0x198>)
    17b4:	2104      	movs	r1, #4
    17b6:	4628      	mov	r0, r5
    17b8:	4b12      	ldr	r3, [pc, #72]	; (1804 <configure_ethercat_dma_descriptors+0x19c>)
    17ba:	4798      	blx	r3
	_dma_set_descriptor(0, spi_rx_abort_fifo_dma_descriptor);
    17bc:	f8d8 300c 	ldr.w	r3, [r8, #12]
    17c0:	9300      	str	r3, [sp, #0]
    17c2:	e898 000e 	ldmia.w	r8, {r1, r2, r3}
    17c6:	4620      	mov	r0, r4
    17c8:	4c0f      	ldr	r4, [pc, #60]	; (1808 <configure_ethercat_dma_descriptors+0x1a0>)
    17ca:	47a0      	blx	r4
	_dma_set_descriptor(1, spi_abort_fifo_dma_descriptor);
    17cc:	68fb      	ldr	r3, [r7, #12]
    17ce:	9300      	str	r3, [sp, #0]
    17d0:	e897 000e 	ldmia.w	r7, {r1, r2, r3}
    17d4:	2001      	movs	r0, #1
    17d6:	47a0      	blx	r4
	spi_m_dma_enable(&SPI_0);
    17d8:	4628      	mov	r0, r5
    17da:	4b0c      	ldr	r3, [pc, #48]	; (180c <configure_ethercat_dma_descriptors+0x1a4>)
    17dc:	4798      	blx	r3
}
    17de:	b003      	add	sp, #12
    17e0:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    17e4:	000035ad 	.word	0x000035ad
    17e8:	20000680 	.word	0x20000680
    17ec:	00001385 	.word	0x00001385
    17f0:	200006a8 	.word	0x200006a8
    17f4:	20000004 	.word	0x20000004
    17f8:	20000610 	.word	0x20000610
    17fc:	2000047c 	.word	0x2000047c
    1800:	00001339 	.word	0x00001339
    1804:	00001e6d 	.word	0x00001e6d
    1808:	00002741 	.word	0x00002741
    180c:	00001e45 	.word	0x00001e45
    1810:	00003b88 	.word	0x00003b88
    1814:	20000570 	.word	0x20000570
    1818:	20000520 	.word	0x20000520
    181c:	20000540 	.word	0x20000540
    1820:	20000670 	.word	0x20000670
    1824:	200006b8 	.word	0x200006b8
    1828:	20000530 	.word	0x20000530
    182c:	20000580 	.word	0x20000580
    1830:	20000650 	.word	0x20000650
    1834:	20000660 	.word	0x20000660
    1838:	200006c8 	.word	0x200006c8
    183c:	20000500 	.word	0x20000500
    1840:	20000510 	.word	0x20000510
    1844:	20000698 	.word	0x20000698

00001848 <adc_async_window_threshold_reached>:
		descr_ch->adc_async_ch_cb.convert_done(descr, channel);
	}
}

static void adc_async_window_threshold_reached(struct _adc_async_device *device, const uint8_t channel)
{
    1848:	b508      	push	{r3, lr}
	struct adc_async_descriptor *const descr = CONTAINER_OF(device, struct adc_async_descriptor, device);

	if (descr->adc_async_cb.monitor) {
    184a:	6983      	ldr	r3, [r0, #24]
    184c:	b103      	cbz	r3, 1850 <adc_async_window_threshold_reached+0x8>
		descr->adc_async_cb.monitor(descr, channel);
    184e:	4798      	blx	r3
    1850:	bd08      	pop	{r3, pc}

00001852 <adc_async_error_occured>:
	}
}

static void adc_async_error_occured(struct _adc_async_device *device, const uint8_t channel)
{
    1852:	b508      	push	{r3, lr}
	struct adc_async_descriptor *const descr = CONTAINER_OF(device, struct adc_async_descriptor, device);

	if (descr->adc_async_cb.error) {
    1854:	69c3      	ldr	r3, [r0, #28]
    1856:	b103      	cbz	r3, 185a <adc_async_error_occured+0x8>
		descr->adc_async_cb.error(descr, channel);
    1858:	4798      	blx	r3
    185a:	bd08      	pop	{r3, pc}

0000185c <adc_async_channel_conversion_done>:
{
    185c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    1860:	4605      	mov	r5, r0
    1862:	4688      	mov	r8, r1
    1864:	4691      	mov	r9, r2
	uint8_t                              index    = descr->channel_map[channel];
    1866:	6a03      	ldr	r3, [r0, #32]
    1868:	5c5b      	ldrb	r3, [r3, r1]
	struct adc_async_channel_descriptor *descr_ch = &descr->descr_ch[index];
    186a:	6a87      	ldr	r7, [r0, #40]	; 0x28
    186c:	eb03 0343 	add.w	r3, r3, r3, lsl #1
    1870:	00de      	lsls	r6, r3, #3
    1872:	19bc      	adds	r4, r7, r6
	ringbuffer_put(&descr_ch->convert, data);
    1874:	f104 0a04 	add.w	sl, r4, #4
    1878:	b2d1      	uxtb	r1, r2
    187a:	4650      	mov	r0, sl
    187c:	4b0c      	ldr	r3, [pc, #48]	; (18b0 <adc_async_channel_conversion_done+0x54>)
    187e:	4798      	blx	r3
	if (1 < _adc_async_get_data_size(&descr->device)) {
    1880:	4628      	mov	r0, r5
    1882:	4b0c      	ldr	r3, [pc, #48]	; (18b4 <adc_async_channel_conversion_done+0x58>)
    1884:	4798      	blx	r3
    1886:	2801      	cmp	r0, #1
    1888:	d907      	bls.n	189a <adc_async_channel_conversion_done+0x3e>
		ringbuffer_put(&descr_ch->convert, data >> 8);
    188a:	ea4f 2119 	mov.w	r1, r9, lsr #8
    188e:	4650      	mov	r0, sl
    1890:	4b07      	ldr	r3, [pc, #28]	; (18b0 <adc_async_channel_conversion_done+0x54>)
    1892:	4798      	blx	r3
		++descr_ch->bytes_in_buffer;
    1894:	8aa3      	ldrh	r3, [r4, #20]
    1896:	3301      	adds	r3, #1
    1898:	82a3      	strh	r3, [r4, #20]
	++descr_ch->bytes_in_buffer;
    189a:	8aa3      	ldrh	r3, [r4, #20]
    189c:	3301      	adds	r3, #1
    189e:	82a3      	strh	r3, [r4, #20]
	if (descr_ch->adc_async_ch_cb.convert_done) {
    18a0:	59bb      	ldr	r3, [r7, r6]
    18a2:	b113      	cbz	r3, 18aa <adc_async_channel_conversion_done+0x4e>
		descr_ch->adc_async_ch_cb.convert_done(descr, channel);
    18a4:	4641      	mov	r1, r8
    18a6:	4628      	mov	r0, r5
    18a8:	4798      	blx	r3
    18aa:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    18ae:	bf00      	nop
    18b0:	00001ee9 	.word	0x00001ee9
    18b4:	000022df 	.word	0x000022df

000018b8 <adc_async_init>:
{
    18b8:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    18bc:	4689      	mov	r9, r1
    18be:	4616      	mov	r6, r2
    18c0:	461c      	mov	r4, r3
    18c2:	f89d 8028 	ldrb.w	r8, [sp, #40]	; 0x28
    18c6:	9d0b      	ldr	r5, [sp, #44]	; 0x2c
	ASSERT(descr && hw && channel_map && channel_amount && descr_ch);
    18c8:	4607      	mov	r7, r0
    18ca:	b148      	cbz	r0, 18e0 <adc_async_init+0x28>
    18cc:	b151      	cbz	r1, 18e4 <adc_async_init+0x2c>
    18ce:	b15a      	cbz	r2, 18e8 <adc_async_init+0x30>
    18d0:	f1b8 0f00 	cmp.w	r8, #0
    18d4:	d00a      	beq.n	18ec <adc_async_init+0x34>
    18d6:	b10d      	cbz	r5, 18dc <adc_async_init+0x24>
    18d8:	2001      	movs	r0, #1
    18da:	e008      	b.n	18ee <adc_async_init+0x36>
    18dc:	2000      	movs	r0, #0
    18de:	e006      	b.n	18ee <adc_async_init+0x36>
    18e0:	2000      	movs	r0, #0
    18e2:	e004      	b.n	18ee <adc_async_init+0x36>
    18e4:	2000      	movs	r0, #0
    18e6:	e002      	b.n	18ee <adc_async_init+0x36>
    18e8:	2000      	movs	r0, #0
    18ea:	e000      	b.n	18ee <adc_async_init+0x36>
    18ec:	2000      	movs	r0, #0
    18ee:	f8df b068 	ldr.w	fp, [pc, #104]	; 1958 <adc_async_init+0xa0>
    18f2:	223f      	movs	r2, #63	; 0x3f
    18f4:	4659      	mov	r1, fp
    18f6:	f8df a064 	ldr.w	sl, [pc, #100]	; 195c <adc_async_init+0xa4>
    18fa:	47d0      	blx	sl
	ASSERT(channel_amount <= (channel_max + 1));
    18fc:	1c60      	adds	r0, r4, #1
    18fe:	2240      	movs	r2, #64	; 0x40
    1900:	4659      	mov	r1, fp
    1902:	4580      	cmp	r8, r0
    1904:	bfcc      	ite	gt
    1906:	2000      	movgt	r0, #0
    1908:	2001      	movle	r0, #1
    190a:	47d0      	blx	sl
	for (uint8_t i = 0; i <= channel_max; i++) {
    190c:	2300      	movs	r3, #0
    190e:	e003      	b.n	1918 <adc_async_init+0x60>
		channel_map[i] = 0xFF;
    1910:	22ff      	movs	r2, #255	; 0xff
    1912:	54f2      	strb	r2, [r6, r3]
	for (uint8_t i = 0; i <= channel_max; i++) {
    1914:	3301      	adds	r3, #1
    1916:	b2db      	uxtb	r3, r3
    1918:	42a3      	cmp	r3, r4
    191a:	d9f9      	bls.n	1910 <adc_async_init+0x58>
	descr->channel_map    = channel_map;
    191c:	623e      	str	r6, [r7, #32]
	descr->channel_max    = channel_max;
    191e:	f887 4024 	strb.w	r4, [r7, #36]	; 0x24
	descr->channel_amount = channel_amount;
    1922:	f887 8025 	strb.w	r8, [r7, #37]	; 0x25
	descr->descr_ch       = descr_ch;
    1926:	62bd      	str	r5, [r7, #40]	; 0x28
	init_status           = _adc_async_init(device, hw);
    1928:	4649      	mov	r1, r9
    192a:	4638      	mov	r0, r7
    192c:	4b06      	ldr	r3, [pc, #24]	; (1948 <adc_async_init+0x90>)
    192e:	4798      	blx	r3
	if (init_status) {
    1930:	4603      	mov	r3, r0
    1932:	b928      	cbnz	r0, 1940 <adc_async_init+0x88>
	device->adc_async_ch_cb.convert_done = adc_async_channel_conversion_done;
    1934:	4a05      	ldr	r2, [pc, #20]	; (194c <adc_async_init+0x94>)
    1936:	60ba      	str	r2, [r7, #8]
	device->adc_async_cb.window_cb       = adc_async_window_threshold_reached;
    1938:	4a05      	ldr	r2, [pc, #20]	; (1950 <adc_async_init+0x98>)
    193a:	603a      	str	r2, [r7, #0]
	device->adc_async_cb.error_cb        = adc_async_error_occured;
    193c:	4a05      	ldr	r2, [pc, #20]	; (1954 <adc_async_init+0x9c>)
    193e:	607a      	str	r2, [r7, #4]
}
    1940:	4618      	mov	r0, r3
    1942:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
    1946:	bf00      	nop
    1948:	0000219d 	.word	0x0000219d
    194c:	0000185d 	.word	0x0000185d
    1950:	00001849 	.word	0x00001849
    1954:	00001853 	.word	0x00001853
    1958:	00003b9c 	.word	0x00003b9c
    195c:	00001e9d 	.word	0x00001e9d

00001960 <adc_async_register_channel_buffer>:
{
    1960:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    1964:	460e      	mov	r6, r1
    1966:	4617      	mov	r7, r2
    1968:	4698      	mov	r8, r3
	ASSERT(descr && convert_buffer && convert_buffer_length);
    196a:	4605      	mov	r5, r0
    196c:	b1c0      	cbz	r0, 19a0 <adc_async_register_channel_buffer+0x40>
    196e:	b1ca      	cbz	r2, 19a4 <adc_async_register_channel_buffer+0x44>
    1970:	b9d3      	cbnz	r3, 19a8 <adc_async_register_channel_buffer+0x48>
    1972:	2000      	movs	r0, #0
    1974:	f8df 909c 	ldr.w	r9, [pc, #156]	; 1a14 <adc_async_register_channel_buffer+0xb4>
    1978:	2266      	movs	r2, #102	; 0x66
    197a:	4649      	mov	r1, r9
    197c:	4c23      	ldr	r4, [pc, #140]	; (1a0c <adc_async_register_channel_buffer+0xac>)
    197e:	47a0      	blx	r4
	ASSERT(descr->channel_max >= channel);
    1980:	f895 0024 	ldrb.w	r0, [r5, #36]	; 0x24
    1984:	2267      	movs	r2, #103	; 0x67
    1986:	4649      	mov	r1, r9
    1988:	42b0      	cmp	r0, r6
    198a:	bf34      	ite	cc
    198c:	2000      	movcc	r0, #0
    198e:	2001      	movcs	r0, #1
    1990:	47a0      	blx	r4
	if (descr->channel_map[channel] != 0xFF) {
    1992:	6a29      	ldr	r1, [r5, #32]
    1994:	5d8b      	ldrb	r3, [r1, r6]
    1996:	2bff      	cmp	r3, #255	; 0xff
    1998:	d12f      	bne.n	19fa <adc_async_register_channel_buffer+0x9a>
    199a:	2400      	movs	r4, #0
    199c:	4623      	mov	r3, r4
    199e:	e007      	b.n	19b0 <adc_async_register_channel_buffer+0x50>
	ASSERT(descr && convert_buffer && convert_buffer_length);
    19a0:	2000      	movs	r0, #0
    19a2:	e7e7      	b.n	1974 <adc_async_register_channel_buffer+0x14>
    19a4:	2000      	movs	r0, #0
    19a6:	e7e5      	b.n	1974 <adc_async_register_channel_buffer+0x14>
    19a8:	2001      	movs	r0, #1
    19aa:	e7e3      	b.n	1974 <adc_async_register_channel_buffer+0x14>
	for (i = 0; i <= descr->channel_max; i++) {
    19ac:	3301      	adds	r3, #1
    19ae:	b2db      	uxtb	r3, r3
    19b0:	f895 2024 	ldrb.w	r2, [r5, #36]	; 0x24
    19b4:	4293      	cmp	r3, r2
    19b6:	d805      	bhi.n	19c4 <adc_async_register_channel_buffer+0x64>
		if (descr->channel_map[i] != 0xFF) {
    19b8:	5cca      	ldrb	r2, [r1, r3]
    19ba:	2aff      	cmp	r2, #255	; 0xff
    19bc:	d0f6      	beq.n	19ac <adc_async_register_channel_buffer+0x4c>
			index++;
    19be:	3401      	adds	r4, #1
    19c0:	b2e4      	uxtb	r4, r4
    19c2:	e7f3      	b.n	19ac <adc_async_register_channel_buffer+0x4c>
	if (index > descr->channel_amount) {
    19c4:	f895 3025 	ldrb.w	r3, [r5, #37]	; 0x25
    19c8:	429c      	cmp	r4, r3
    19ca:	d819      	bhi.n	1a00 <adc_async_register_channel_buffer+0xa0>
	if (ERR_NONE != ringbuffer_init(&descr->descr_ch[index].convert, convert_buffer, convert_buffer_length)) {
    19cc:	6aa8      	ldr	r0, [r5, #40]	; 0x28
    19ce:	eb04 0344 	add.w	r3, r4, r4, lsl #1
    19d2:	ea4f 09c3 	mov.w	r9, r3, lsl #3
    19d6:	4448      	add	r0, r9
    19d8:	4642      	mov	r2, r8
    19da:	4639      	mov	r1, r7
    19dc:	3004      	adds	r0, #4
    19de:	4b0c      	ldr	r3, [pc, #48]	; (1a10 <adc_async_register_channel_buffer+0xb0>)
    19e0:	4798      	blx	r3
    19e2:	4602      	mov	r2, r0
    19e4:	b978      	cbnz	r0, 1a06 <adc_async_register_channel_buffer+0xa6>
	descr->channel_map[channel]            = index;
    19e6:	6a2b      	ldr	r3, [r5, #32]
    19e8:	559c      	strb	r4, [r3, r6]
	descr->descr_ch[index].bytes_in_buffer = 0;
    19ea:	6aab      	ldr	r3, [r5, #40]	; 0x28
    19ec:	4499      	add	r9, r3
    19ee:	2300      	movs	r3, #0
    19f0:	f8a9 3014 	strh.w	r3, [r9, #20]
}
    19f4:	4610      	mov	r0, r2
    19f6:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		return ERR_INVALID_ARG;
    19fa:	f06f 020c 	mvn.w	r2, #12
    19fe:	e7f9      	b.n	19f4 <adc_async_register_channel_buffer+0x94>
		return ERR_NO_RESOURCE;
    1a00:	f06f 021b 	mvn.w	r2, #27
    1a04:	e7f6      	b.n	19f4 <adc_async_register_channel_buffer+0x94>
		return ERR_INVALID_ARG;
    1a06:	f06f 020c 	mvn.w	r2, #12
    1a0a:	e7f3      	b.n	19f4 <adc_async_register_channel_buffer+0x94>
    1a0c:	00001e9d 	.word	0x00001e9d
    1a10:	00001ea5 	.word	0x00001ea5
    1a14:	00003b9c 	.word	0x00003b9c

00001a18 <adc_async_enable_channel>:
{
    1a18:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    1a1a:	460d      	mov	r5, r1
	ASSERT(descr);
    1a1c:	4f0b      	ldr	r7, [pc, #44]	; (1a4c <adc_async_enable_channel+0x34>)
    1a1e:	4604      	mov	r4, r0
    1a20:	2283      	movs	r2, #131	; 0x83
    1a22:	4639      	mov	r1, r7
    1a24:	3000      	adds	r0, #0
    1a26:	bf18      	it	ne
    1a28:	2001      	movne	r0, #1
    1a2a:	4e09      	ldr	r6, [pc, #36]	; (1a50 <adc_async_enable_channel+0x38>)
    1a2c:	47b0      	blx	r6
	ASSERT(descr->channel_max >= channel);
    1a2e:	f894 0024 	ldrb.w	r0, [r4, #36]	; 0x24
    1a32:	2284      	movs	r2, #132	; 0x84
    1a34:	4639      	mov	r1, r7
    1a36:	42a8      	cmp	r0, r5
    1a38:	bf34      	ite	cc
    1a3a:	2000      	movcc	r0, #0
    1a3c:	2001      	movcs	r0, #1
    1a3e:	47b0      	blx	r6
	_adc_async_enable_channel(&descr->device, channel);
    1a40:	4629      	mov	r1, r5
    1a42:	4620      	mov	r0, r4
    1a44:	4b03      	ldr	r3, [pc, #12]	; (1a54 <adc_async_enable_channel+0x3c>)
    1a46:	4798      	blx	r3
}
    1a48:	2000      	movs	r0, #0
    1a4a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    1a4c:	00003b9c 	.word	0x00003b9c
    1a50:	00001e9d 	.word	0x00001e9d
    1a54:	000022b1 	.word	0x000022b1

00001a58 <adc_async_disable_channel>:
{
    1a58:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    1a5a:	460d      	mov	r5, r1
	ASSERT(descr);
    1a5c:	4f0b      	ldr	r7, [pc, #44]	; (1a8c <adc_async_disable_channel+0x34>)
    1a5e:	4604      	mov	r4, r0
    1a60:	228f      	movs	r2, #143	; 0x8f
    1a62:	4639      	mov	r1, r7
    1a64:	3000      	adds	r0, #0
    1a66:	bf18      	it	ne
    1a68:	2001      	movne	r0, #1
    1a6a:	4e09      	ldr	r6, [pc, #36]	; (1a90 <adc_async_disable_channel+0x38>)
    1a6c:	47b0      	blx	r6
	ASSERT(descr->channel_max >= channel);
    1a6e:	f894 0024 	ldrb.w	r0, [r4, #36]	; 0x24
    1a72:	2290      	movs	r2, #144	; 0x90
    1a74:	4639      	mov	r1, r7
    1a76:	42a8      	cmp	r0, r5
    1a78:	bf34      	ite	cc
    1a7a:	2000      	movcc	r0, #0
    1a7c:	2001      	movcs	r0, #1
    1a7e:	47b0      	blx	r6
	_adc_async_disable_channel(&descr->device, channel);
    1a80:	4629      	mov	r1, r5
    1a82:	4620      	mov	r0, r4
    1a84:	4b03      	ldr	r3, [pc, #12]	; (1a94 <adc_async_disable_channel+0x3c>)
    1a86:	4798      	blx	r3
}
    1a88:	2000      	movs	r0, #0
    1a8a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    1a8c:	00003b9c 	.word	0x00003b9c
    1a90:	00001e9d 	.word	0x00001e9d
    1a94:	000022c7 	.word	0x000022c7

00001a98 <adc_async_register_callback>:
{
    1a98:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    1a9c:	460e      	mov	r6, r1
    1a9e:	4615      	mov	r5, r2
    1aa0:	4699      	mov	r9, r3
	ASSERT(descr);
    1aa2:	f8df 8074 	ldr.w	r8, [pc, #116]	; 1b18 <adc_async_register_callback+0x80>
    1aa6:	4604      	mov	r4, r0
    1aa8:	229c      	movs	r2, #156	; 0x9c
    1aaa:	4641      	mov	r1, r8
    1aac:	3000      	adds	r0, #0
    1aae:	bf18      	it	ne
    1ab0:	2001      	movne	r0, #1
    1ab2:	4f17      	ldr	r7, [pc, #92]	; (1b10 <adc_async_register_callback+0x78>)
    1ab4:	47b8      	blx	r7
	ASSERT(descr->channel_max >= channel);
    1ab6:	f894 0024 	ldrb.w	r0, [r4, #36]	; 0x24
    1aba:	229d      	movs	r2, #157	; 0x9d
    1abc:	4641      	mov	r1, r8
    1abe:	42b0      	cmp	r0, r6
    1ac0:	bf34      	ite	cc
    1ac2:	2000      	movcc	r0, #0
    1ac4:	2001      	movcs	r0, #1
    1ac6:	47b8      	blx	r7
	uint8_t index = descr->channel_map[channel];
    1ac8:	6a23      	ldr	r3, [r4, #32]
    1aca:	5d9b      	ldrb	r3, [r3, r6]
	switch (type) {
    1acc:	2d01      	cmp	r5, #1
    1ace:	d018      	beq.n	1b02 <adc_async_register_callback+0x6a>
    1ad0:	b12d      	cbz	r5, 1ade <adc_async_register_callback+0x46>
    1ad2:	2d02      	cmp	r5, #2
    1ad4:	d018      	beq.n	1b08 <adc_async_register_callback+0x70>
		return ERR_INVALID_ARG;
    1ad6:	f06f 000c 	mvn.w	r0, #12
}
    1ada:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		descr->descr_ch[index].adc_async_ch_cb.convert_done = cb;
    1ade:	6aa1      	ldr	r1, [r4, #40]	; 0x28
    1ae0:	eb03 0343 	add.w	r3, r3, r3, lsl #1
    1ae4:	00da      	lsls	r2, r3, #3
    1ae6:	f841 9002 	str.w	r9, [r1, r2]
	_adc_async_set_irq_state(&descr->device, channel, (enum _adc_async_callback_type)type, cb != NULL);
    1aea:	f119 0300 	adds.w	r3, r9, #0
    1aee:	bf18      	it	ne
    1af0:	2301      	movne	r3, #1
    1af2:	462a      	mov	r2, r5
    1af4:	4631      	mov	r1, r6
    1af6:	4620      	mov	r0, r4
    1af8:	4c06      	ldr	r4, [pc, #24]	; (1b14 <adc_async_register_callback+0x7c>)
    1afa:	47a0      	blx	r4
	return ERR_NONE;
    1afc:	2000      	movs	r0, #0
    1afe:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		descr->adc_async_cb.monitor = cb;
    1b02:	f8c4 9018 	str.w	r9, [r4, #24]
		break;
    1b06:	e7f0      	b.n	1aea <adc_async_register_callback+0x52>
		descr->adc_async_cb.error = cb;
    1b08:	f8c4 901c 	str.w	r9, [r4, #28]
		break;
    1b0c:	e7ed      	b.n	1aea <adc_async_register_callback+0x52>
    1b0e:	bf00      	nop
    1b10:	00001e9d 	.word	0x00001e9d
    1b14:	000022f3 	.word	0x000022f3
    1b18:	00003b9c 	.word	0x00003b9c

00001b1c <event_system_init>:

/**
 * \brief Initialize event system.
 */
int32_t event_system_init(void)
{
    1b1c:	b508      	push	{r3, lr}
	return _event_system_init();
    1b1e:	4b01      	ldr	r3, [pc, #4]	; (1b24 <event_system_init+0x8>)
    1b20:	4798      	blx	r3
}
    1b22:	bd08      	pop	{r3, pc}
    1b24:	00002985 	.word	0x00002985

00001b28 <process_ext_irq>:
 * \brief Interrupt processing routine
 *
 * \param[in] pin The pin which triggered the interrupt
 */
static void process_ext_irq(const uint32_t pin)
{
    1b28:	b538      	push	{r3, r4, r5, lr}
	uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT;
    1b2a:	2501      	movs	r5, #1
    1b2c:	2400      	movs	r4, #0

	while (upper >= lower) {
    1b2e:	e007      	b.n	1b40 <process_ext_irq+0x18>
		if (middle >= EXT_IRQ_AMOUNT) {
			return;
		}

		if (ext_irqs[middle].pin == pin) {
			if (ext_irqs[middle].cb) {
    1b30:	4a0d      	ldr	r2, [pc, #52]	; (1b68 <process_ext_irq+0x40>)
    1b32:	f852 3033 	ldr.w	r3, [r2, r3, lsl #3]
    1b36:	b1b3      	cbz	r3, 1b66 <process_ext_irq+0x3e>
				ext_irqs[middle].cb();
    1b38:	4798      	blx	r3
    1b3a:	bd38      	pop	{r3, r4, r5, pc}
		}

		if (ext_irqs[middle].pin < pin) {
			lower = middle + 1;
		} else {
			upper = middle - 1;
    1b3c:	3901      	subs	r1, #1
    1b3e:	b2cd      	uxtb	r5, r1
	while (upper >= lower) {
    1b40:	42ac      	cmp	r4, r5
    1b42:	d810      	bhi.n	1b66 <process_ext_irq+0x3e>
		middle = (upper + lower) >> 1;
    1b44:	192b      	adds	r3, r5, r4
    1b46:	105b      	asrs	r3, r3, #1
		if (middle >= EXT_IRQ_AMOUNT) {
    1b48:	f013 01ff 	ands.w	r1, r3, #255	; 0xff
    1b4c:	d10b      	bne.n	1b66 <process_ext_irq+0x3e>
    1b4e:	b2db      	uxtb	r3, r3
		if (ext_irqs[middle].pin == pin) {
    1b50:	4a05      	ldr	r2, [pc, #20]	; (1b68 <process_ext_irq+0x40>)
    1b52:	eb02 02c3 	add.w	r2, r2, r3, lsl #3
    1b56:	6852      	ldr	r2, [r2, #4]
    1b58:	4282      	cmp	r2, r0
    1b5a:	d0e9      	beq.n	1b30 <process_ext_irq+0x8>
		if (ext_irqs[middle].pin < pin) {
    1b5c:	4282      	cmp	r2, r0
    1b5e:	d2ed      	bcs.n	1b3c <process_ext_irq+0x14>
			lower = middle + 1;
    1b60:	3101      	adds	r1, #1
    1b62:	b2cc      	uxtb	r4, r1
    1b64:	e7ec      	b.n	1b40 <process_ext_irq+0x18>
    1b66:	bd38      	pop	{r3, r4, r5, pc}
    1b68:	20000108 	.word	0x20000108

00001b6c <ext_irq_init>:
{
    1b6c:	b508      	push	{r3, lr}
	for (i = 0; i < EXT_IRQ_AMOUNT; i++) {
    1b6e:	2300      	movs	r3, #0
    1b70:	b11b      	cbz	r3, 1b7a <ext_irq_init+0xe>
	return _ext_irq_init(process_ext_irq);
    1b72:	4808      	ldr	r0, [pc, #32]	; (1b94 <ext_irq_init+0x28>)
    1b74:	4b08      	ldr	r3, [pc, #32]	; (1b98 <ext_irq_init+0x2c>)
    1b76:	4798      	blx	r3
}
    1b78:	bd08      	pop	{r3, pc}
		ext_irqs[i].pin = 0xFFFFFFFF;
    1b7a:	4a08      	ldr	r2, [pc, #32]	; (1b9c <ext_irq_init+0x30>)
    1b7c:	eb02 01c3 	add.w	r1, r2, r3, lsl #3
    1b80:	f04f 30ff 	mov.w	r0, #4294967295
    1b84:	6048      	str	r0, [r1, #4]
		ext_irqs[i].cb  = NULL;
    1b86:	2100      	movs	r1, #0
    1b88:	f842 1033 	str.w	r1, [r2, r3, lsl #3]
	for (i = 0; i < EXT_IRQ_AMOUNT; i++) {
    1b8c:	3301      	adds	r3, #1
    1b8e:	b29b      	uxth	r3, r3
    1b90:	e7ee      	b.n	1b70 <ext_irq_init+0x4>
    1b92:	bf00      	nop
    1b94:	00001b29 	.word	0x00001b29
    1b98:	00002871 	.word	0x00002871
    1b9c:	20000108 	.word	0x20000108

00001ba0 <ext_irq_register>:
{
    1ba0:	b5f0      	push	{r4, r5, r6, r7, lr}
    1ba2:	b083      	sub	sp, #12
    1ba4:	4605      	mov	r5, r0
	uint8_t i = 0, j = 0;
    1ba6:	2300      	movs	r3, #0
	for (; i < EXT_IRQ_AMOUNT; i++) {
    1ba8:	b163      	cbz	r3, 1bc4 <ext_irq_register+0x24>
	bool    found = false;
    1baa:	2600      	movs	r6, #0
	if (NULL == cb) {
    1bac:	b1c9      	cbz	r1, 1be2 <ext_irq_register+0x42>
	if (!found) {
    1bae:	2e00      	cmp	r6, #0
    1bb0:	d141      	bne.n	1c36 <ext_irq_register+0x96>
    1bb2:	2300      	movs	r3, #0
		for (i = 0; i < EXT_IRQ_AMOUNT; i++) {
    1bb4:	bb0b      	cbnz	r3, 1bfa <ext_irq_register+0x5a>
			if (NULL == ext_irqs[i].cb) {
    1bb6:	4a26      	ldr	r2, [pc, #152]	; (1c50 <ext_irq_register+0xb0>)
    1bb8:	f852 2033 	ldr.w	r2, [r2, r3, lsl #3]
    1bbc:	b1b2      	cbz	r2, 1bec <ext_irq_register+0x4c>
		for (i = 0; i < EXT_IRQ_AMOUNT; i++) {
    1bbe:	3301      	adds	r3, #1
    1bc0:	b2db      	uxtb	r3, r3
    1bc2:	e7f7      	b.n	1bb4 <ext_irq_register+0x14>
		if (ext_irqs[i].pin == pin) {
    1bc4:	4618      	mov	r0, r3
    1bc6:	4a22      	ldr	r2, [pc, #136]	; (1c50 <ext_irq_register+0xb0>)
    1bc8:	eb02 02c3 	add.w	r2, r2, r3, lsl #3
    1bcc:	6852      	ldr	r2, [r2, #4]
    1bce:	42aa      	cmp	r2, r5
    1bd0:	d002      	beq.n	1bd8 <ext_irq_register+0x38>
	for (; i < EXT_IRQ_AMOUNT; i++) {
    1bd2:	3301      	adds	r3, #1
    1bd4:	b2db      	uxtb	r3, r3
    1bd6:	e7e7      	b.n	1ba8 <ext_irq_register+0x8>
			ext_irqs[i].cb = cb;
    1bd8:	4b1d      	ldr	r3, [pc, #116]	; (1c50 <ext_irq_register+0xb0>)
    1bda:	f843 1030 	str.w	r1, [r3, r0, lsl #3]
			found          = true;
    1bde:	2601      	movs	r6, #1
			break;
    1be0:	e7e4      	b.n	1bac <ext_irq_register+0xc>
		if (!found) {
    1be2:	b37e      	cbz	r6, 1c44 <ext_irq_register+0xa4>
		return _ext_irq_enable(pin, false);
    1be4:	4628      	mov	r0, r5
    1be6:	4b1b      	ldr	r3, [pc, #108]	; (1c54 <ext_irq_register+0xb4>)
    1be8:	4798      	blx	r3
    1bea:	e029      	b.n	1c40 <ext_irq_register+0xa0>
				ext_irqs[i].cb  = cb;
    1bec:	4a18      	ldr	r2, [pc, #96]	; (1c50 <ext_irq_register+0xb0>)
    1bee:	f842 1033 	str.w	r1, [r2, r3, lsl #3]
				ext_irqs[i].pin = pin;
    1bf2:	eb02 00c3 	add.w	r0, r2, r3, lsl #3
    1bf6:	6045      	str	r5, [r0, #4]
				found           = true;
    1bf8:	2601      	movs	r6, #1
    1bfa:	2200      	movs	r2, #0
    1bfc:	e001      	b.n	1c02 <ext_irq_register+0x62>
		for (; (j < EXT_IRQ_AMOUNT) && (i < EXT_IRQ_AMOUNT); j++) {
    1bfe:	3201      	adds	r2, #1
    1c00:	b2d2      	uxtb	r2, r2
    1c02:	b9c2      	cbnz	r2, 1c36 <ext_irq_register+0x96>
    1c04:	b9bb      	cbnz	r3, 1c36 <ext_irq_register+0x96>
			if ((ext_irqs[i].pin < ext_irqs[j].pin) && (ext_irqs[j].pin != 0xFFFFFFFF)) {
    1c06:	469e      	mov	lr, r3
    1c08:	4911      	ldr	r1, [pc, #68]	; (1c50 <ext_irq_register+0xb0>)
    1c0a:	eb01 00c3 	add.w	r0, r1, r3, lsl #3
    1c0e:	6847      	ldr	r7, [r0, #4]
    1c10:	eb01 01c2 	add.w	r1, r1, r2, lsl #3
    1c14:	6849      	ldr	r1, [r1, #4]
    1c16:	428f      	cmp	r7, r1
    1c18:	d2f1      	bcs.n	1bfe <ext_irq_register+0x5e>
    1c1a:	f1b1 3fff 	cmp.w	r1, #4294967295
    1c1e:	d0ee      	beq.n	1bfe <ext_irq_register+0x5e>
				struct ext_irq tmp = ext_irqs[j];
    1c20:	4c0b      	ldr	r4, [pc, #44]	; (1c50 <ext_irq_register+0xb0>)
    1c22:	eb04 00c2 	add.w	r0, r4, r2, lsl #3
    1c26:	c803      	ldmia	r0, {r0, r1}
    1c28:	e88d 0003 	stmia.w	sp, {r0, r1}
				ext_irqs[i] = tmp;
    1c2c:	eb04 04c3 	add.w	r4, r4, r3, lsl #3
    1c30:	e884 0003 	stmia.w	r4, {r0, r1}
    1c34:	e7e3      	b.n	1bfe <ext_irq_register+0x5e>
	if (!found) {
    1c36:	b146      	cbz	r6, 1c4a <ext_irq_register+0xaa>
	return _ext_irq_enable(pin, true);
    1c38:	2101      	movs	r1, #1
    1c3a:	4628      	mov	r0, r5
    1c3c:	4b05      	ldr	r3, [pc, #20]	; (1c54 <ext_irq_register+0xb4>)
    1c3e:	4798      	blx	r3
}
    1c40:	b003      	add	sp, #12
    1c42:	bdf0      	pop	{r4, r5, r6, r7, pc}
			return ERR_INVALID_ARG;
    1c44:	f06f 000c 	mvn.w	r0, #12
    1c48:	e7fa      	b.n	1c40 <ext_irq_register+0xa0>
		return ERR_INVALID_ARG;
    1c4a:	f06f 000c 	mvn.w	r0, #12
    1c4e:	e7f7      	b.n	1c40 <ext_irq_register+0xa0>
    1c50:	20000108 	.word	0x20000108
    1c54:	00002931 	.word	0x00002931

00001c58 <pdec_async_pos_changed>:
 * \internal Position Decoder position changed handler
 *
 * \param[in] device The pointer to Position Decoder device structure
 */
static void pdec_async_pos_changed(const struct _pdec_async_device *const device, uint8_t ch)
{
    1c58:	b508      	push	{r3, lr}
	struct pdec_async_descriptor *const descr = CONTAINER_OF(device, struct pdec_async_descriptor, device);

	if (descr->pdec_async_cb.pos_changed) {
    1c5a:	6943      	ldr	r3, [r0, #20]
    1c5c:	b103      	cbz	r3, 1c60 <pdec_async_pos_changed+0x8>
		descr->pdec_async_cb.pos_changed(descr, ch);
    1c5e:	4798      	blx	r3
    1c60:	bd08      	pop	{r3, pc}

00001c62 <pdec_async_irq_handler>:
 * \param[in] device The pointer to Position Decoder device structure
 * \param[in] type The type of Position Decoder interrupt
 */
static void pdec_async_irq_handler(const struct _pdec_async_device *const device, enum pdec_async_interrupt_type type,
                                   uint8_t ch)
{
    1c62:	b508      	push	{r3, lr}
	struct pdec_async_descriptor *const descr = CONTAINER_OF(device, struct pdec_async_descriptor, device);

	if (descr->pdec_async_cb.irq_handler) {
    1c64:	6983      	ldr	r3, [r0, #24]
    1c66:	b103      	cbz	r3, 1c6a <pdec_async_irq_handler+0x8>
		descr->pdec_async_cb.irq_handler(descr, type, ch);
    1c68:	4798      	blx	r3
    1c6a:	bd08      	pop	{r3, pc}

00001c6c <pdec_async_init>:
{
    1c6c:	b538      	push	{r3, r4, r5, lr}
    1c6e:	460d      	mov	r5, r1
	ASSERT(descr && hw);
    1c70:	4604      	mov	r4, r0
    1c72:	b198      	cbz	r0, 1c9c <pdec_async_init+0x30>
    1c74:	b181      	cbz	r1, 1c98 <pdec_async_init+0x2c>
    1c76:	2001      	movs	r0, #1
    1c78:	2237      	movs	r2, #55	; 0x37
    1c7a:	4909      	ldr	r1, [pc, #36]	; (1ca0 <pdec_async_init+0x34>)
    1c7c:	4b09      	ldr	r3, [pc, #36]	; (1ca4 <pdec_async_init+0x38>)
    1c7e:	4798      	blx	r3
	init_status = _pdec_async_init(&descr->device, hw);
    1c80:	4629      	mov	r1, r5
    1c82:	4620      	mov	r0, r4
    1c84:	4b08      	ldr	r3, [pc, #32]	; (1ca8 <pdec_async_init+0x3c>)
    1c86:	4798      	blx	r3
	if (init_status) {
    1c88:	4603      	mov	r3, r0
    1c8a:	b918      	cbnz	r0, 1c94 <pdec_async_init+0x28>
	device->pdec_async_cb.pos_changed = pdec_async_pos_changed;
    1c8c:	4a07      	ldr	r2, [pc, #28]	; (1cac <pdec_async_init+0x40>)
    1c8e:	6022      	str	r2, [r4, #0]
	device->pdec_async_cb.irq_handler = pdec_async_irq_handler;
    1c90:	4a07      	ldr	r2, [pc, #28]	; (1cb0 <pdec_async_init+0x44>)
    1c92:	6062      	str	r2, [r4, #4]
}
    1c94:	4618      	mov	r0, r3
    1c96:	bd38      	pop	{r3, r4, r5, pc}
	ASSERT(descr && hw);
    1c98:	2000      	movs	r0, #0
    1c9a:	e7ed      	b.n	1c78 <pdec_async_init+0xc>
    1c9c:	2000      	movs	r0, #0
    1c9e:	e7eb      	b.n	1c78 <pdec_async_init+0xc>
    1ca0:	00003bb8 	.word	0x00003bb8
    1ca4:	00001e9d 	.word	0x00001e9d
    1ca8:	00002c35 	.word	0x00002c35
    1cac:	00001c59 	.word	0x00001c59
    1cb0:	00001c63 	.word	0x00001c63

00001cb4 <pwm_period_expired>:

/**
 * \internal Process interrupts caused by period experied
 */
static void pwm_period_expired(struct _pwm_device *device)
{
    1cb4:	b508      	push	{r3, lr}
	struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device);

	if (descr->pwm_cb.period) {
    1cb6:	6943      	ldr	r3, [r0, #20]
    1cb8:	b103      	cbz	r3, 1cbc <pwm_period_expired+0x8>
		descr->pwm_cb.period(descr);
    1cba:	4798      	blx	r3
    1cbc:	bd08      	pop	{r3, pc}

00001cbe <pwm_detect_fault>:

/**
 * \internal Process interrupts caused by pwm fault
 */
static void pwm_detect_fault(struct _pwm_device *device)
{
    1cbe:	b508      	push	{r3, lr}
	struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device);

	if (descr->pwm_cb.error) {
    1cc0:	6983      	ldr	r3, [r0, #24]
    1cc2:	b103      	cbz	r3, 1cc6 <pwm_detect_fault+0x8>
		descr->pwm_cb.error(descr);
    1cc4:	4798      	blx	r3
    1cc6:	bd08      	pop	{r3, pc}

00001cc8 <pwm_init>:
{
    1cc8:	b538      	push	{r3, r4, r5, lr}
    1cca:	460d      	mov	r5, r1
	ASSERT(descr && hw);
    1ccc:	4604      	mov	r4, r0
    1cce:	b188      	cbz	r0, 1cf4 <pwm_init+0x2c>
    1cd0:	b171      	cbz	r1, 1cf0 <pwm_init+0x28>
    1cd2:	2001      	movs	r0, #1
    1cd4:	2233      	movs	r2, #51	; 0x33
    1cd6:	4908      	ldr	r1, [pc, #32]	; (1cf8 <pwm_init+0x30>)
    1cd8:	4b08      	ldr	r3, [pc, #32]	; (1cfc <pwm_init+0x34>)
    1cda:	4798      	blx	r3
	_pwm_init(&descr->device, hw);
    1cdc:	4629      	mov	r1, r5
    1cde:	4620      	mov	r0, r4
    1ce0:	4b07      	ldr	r3, [pc, #28]	; (1d00 <pwm_init+0x38>)
    1ce2:	4798      	blx	r3
	descr->device.callback.pwm_period_cb = pwm_period_expired;
    1ce4:	4b07      	ldr	r3, [pc, #28]	; (1d04 <pwm_init+0x3c>)
    1ce6:	6023      	str	r3, [r4, #0]
	descr->device.callback.pwm_error_cb  = pwm_detect_fault;
    1ce8:	4b07      	ldr	r3, [pc, #28]	; (1d08 <pwm_init+0x40>)
    1cea:	6063      	str	r3, [r4, #4]
}
    1cec:	2000      	movs	r0, #0
    1cee:	bd38      	pop	{r3, r4, r5, pc}
	ASSERT(descr && hw);
    1cf0:	2000      	movs	r0, #0
    1cf2:	e7ef      	b.n	1cd4 <pwm_init+0xc>
    1cf4:	2000      	movs	r0, #0
    1cf6:	e7ed      	b.n	1cd4 <pwm_init+0xc>
    1cf8:	00003bd4 	.word	0x00003bd4
    1cfc:	00001e9d 	.word	0x00001e9d
    1d00:	000032ed 	.word	0x000032ed
    1d04:	00001cb5 	.word	0x00001cb5
    1d08:	00001cbf 	.word	0x00001cbf

00001d0c <pwm_enable>:
{
    1d0c:	b510      	push	{r4, lr}
	ASSERT(descr);
    1d0e:	4604      	mov	r4, r0
    1d10:	224a      	movs	r2, #74	; 0x4a
    1d12:	4909      	ldr	r1, [pc, #36]	; (1d38 <pwm_enable+0x2c>)
    1d14:	3000      	adds	r0, #0
    1d16:	bf18      	it	ne
    1d18:	2001      	movne	r0, #1
    1d1a:	4b08      	ldr	r3, [pc, #32]	; (1d3c <pwm_enable+0x30>)
    1d1c:	4798      	blx	r3
	if (_pwm_is_enabled(&descr->device)) {
    1d1e:	4620      	mov	r0, r4
    1d20:	4b07      	ldr	r3, [pc, #28]	; (1d40 <pwm_enable+0x34>)
    1d22:	4798      	blx	r3
    1d24:	b920      	cbnz	r0, 1d30 <pwm_enable+0x24>
	_pwm_enable(&descr->device);
    1d26:	4620      	mov	r0, r4
    1d28:	4b06      	ldr	r3, [pc, #24]	; (1d44 <pwm_enable+0x38>)
    1d2a:	4798      	blx	r3
	return ERR_NONE;
    1d2c:	2000      	movs	r0, #0
    1d2e:	bd10      	pop	{r4, pc}
		return ERR_DENIED;
    1d30:	f06f 0010 	mvn.w	r0, #16
}
    1d34:	bd10      	pop	{r4, pc}
    1d36:	bf00      	nop
    1d38:	00003bd4 	.word	0x00003bd4
    1d3c:	00001e9d 	.word	0x00001e9d
    1d40:	0000349d 	.word	0x0000349d
    1d44:	00003489 	.word	0x00003489

00001d48 <pwm_register_callback>:
{
    1d48:	b570      	push	{r4, r5, r6, lr}
	switch (type) {
    1d4a:	460d      	mov	r5, r1
    1d4c:	b121      	cbz	r1, 1d58 <pwm_register_callback+0x10>
    1d4e:	2901      	cmp	r1, #1
    1d50:	d015      	beq.n	1d7e <pwm_register_callback+0x36>
		return ERR_INVALID_ARG;
    1d52:	f06f 000c 	mvn.w	r0, #12
}
    1d56:	bd70      	pop	{r4, r5, r6, pc}
		descr->pwm_cb.period = cb;
    1d58:	6142      	str	r2, [r0, #20]
    1d5a:	4616      	mov	r6, r2
    1d5c:	4604      	mov	r4, r0
	ASSERT(descr);
    1d5e:	2272      	movs	r2, #114	; 0x72
    1d60:	4908      	ldr	r1, [pc, #32]	; (1d84 <pwm_register_callback+0x3c>)
    1d62:	3000      	adds	r0, #0
    1d64:	bf18      	it	ne
    1d66:	2001      	movne	r0, #1
    1d68:	4b07      	ldr	r3, [pc, #28]	; (1d88 <pwm_register_callback+0x40>)
    1d6a:	4798      	blx	r3
	_pwm_set_irq_state(&descr->device, (enum _pwm_callback_type)type, NULL != cb);
    1d6c:	1c32      	adds	r2, r6, #0
    1d6e:	bf18      	it	ne
    1d70:	2201      	movne	r2, #1
    1d72:	4629      	mov	r1, r5
    1d74:	4620      	mov	r0, r4
    1d76:	4b05      	ldr	r3, [pc, #20]	; (1d8c <pwm_register_callback+0x44>)
    1d78:	4798      	blx	r3
	return ERR_NONE;
    1d7a:	2000      	movs	r0, #0
    1d7c:	bd70      	pop	{r4, r5, r6, pc}
		descr->pwm_cb.error = cb;
    1d7e:	6182      	str	r2, [r0, #24]
		break;
    1d80:	e7eb      	b.n	1d5a <pwm_register_callback+0x12>
    1d82:	bf00      	nop
    1d84:	00003bd4 	.word	0x00003bd4
    1d88:	00001e9d 	.word	0x00001e9d
    1d8c:	000034b1 	.word	0x000034b1

00001d90 <_spi_m_dma_io_write>:
 *  \return ERR_NONE on success, or an error code on failure.
 *  \retval ERR_NONE Success, transfer started.
 *  \retval ERR_BUSY Busy.
 */
static int32_t _spi_m_dma_io_write(struct io_descriptor *io, const uint8_t *const buf, const uint16_t length)
{
    1d90:	b570      	push	{r4, r5, r6, lr}
    1d92:	460d      	mov	r5, r1
    1d94:	4616      	mov	r6, r2
	ASSERT(io);
    1d96:	4604      	mov	r4, r0
    1d98:	2298      	movs	r2, #152	; 0x98
    1d9a:	4907      	ldr	r1, [pc, #28]	; (1db8 <_spi_m_dma_io_write+0x28>)
    1d9c:	3000      	adds	r0, #0
    1d9e:	bf18      	it	ne
    1da0:	2001      	movne	r0, #1
    1da2:	4b06      	ldr	r3, [pc, #24]	; (1dbc <_spi_m_dma_io_write+0x2c>)
    1da4:	4798      	blx	r3

	struct spi_m_dma_descriptor *spi = CONTAINER_OF(io, struct spi_m_dma_descriptor, io);
	return _spi_m_dma_transfer(&spi->dev, buf, NULL, length);
    1da6:	4633      	mov	r3, r6
    1da8:	2200      	movs	r2, #0
    1daa:	4629      	mov	r1, r5
    1dac:	f1a4 0020 	sub.w	r0, r4, #32
    1db0:	4c03      	ldr	r4, [pc, #12]	; (1dc0 <_spi_m_dma_io_write+0x30>)
    1db2:	47a0      	blx	r4
}
    1db4:	bd70      	pop	{r4, r5, r6, pc}
    1db6:	bf00      	nop
    1db8:	00003bec 	.word	0x00003bec
    1dbc:	00001e9d 	.word	0x00001e9d
    1dc0:	00003121 	.word	0x00003121

00001dc4 <_spi_m_dma_io_read>:
{
    1dc4:	b570      	push	{r4, r5, r6, lr}
    1dc6:	460d      	mov	r5, r1
    1dc8:	4616      	mov	r6, r2
	ASSERT(io);
    1dca:	4604      	mov	r4, r0
    1dcc:	2281      	movs	r2, #129	; 0x81
    1dce:	4907      	ldr	r1, [pc, #28]	; (1dec <_spi_m_dma_io_read+0x28>)
    1dd0:	3000      	adds	r0, #0
    1dd2:	bf18      	it	ne
    1dd4:	2001      	movne	r0, #1
    1dd6:	4b06      	ldr	r3, [pc, #24]	; (1df0 <_spi_m_dma_io_read+0x2c>)
    1dd8:	4798      	blx	r3
	return _spi_m_dma_transfer(&spi->dev, NULL, buf, length);
    1dda:	4633      	mov	r3, r6
    1ddc:	462a      	mov	r2, r5
    1dde:	2100      	movs	r1, #0
    1de0:	f1a4 0020 	sub.w	r0, r4, #32
    1de4:	4c03      	ldr	r4, [pc, #12]	; (1df4 <_spi_m_dma_io_read+0x30>)
    1de6:	47a0      	blx	r4
}
    1de8:	bd70      	pop	{r4, r5, r6, pc}
    1dea:	bf00      	nop
    1dec:	00003bec 	.word	0x00003bec
    1df0:	00001e9d 	.word	0x00001e9d
    1df4:	00003121 	.word	0x00003121

00001df8 <spi_m_dma_init>:
{
    1df8:	b538      	push	{r3, r4, r5, lr}
    1dfa:	460c      	mov	r4, r1
	ASSERT(spi && hw);
    1dfc:	4605      	mov	r5, r0
    1dfe:	b1a8      	cbz	r0, 1e2c <spi_m_dma_init+0x34>
    1e00:	b191      	cbz	r1, 1e28 <spi_m_dma_init+0x30>
    1e02:	2001      	movs	r0, #1
    1e04:	223b      	movs	r2, #59	; 0x3b
    1e06:	490a      	ldr	r1, [pc, #40]	; (1e30 <spi_m_dma_init+0x38>)
    1e08:	4b0a      	ldr	r3, [pc, #40]	; (1e34 <spi_m_dma_init+0x3c>)
    1e0a:	4798      	blx	r3
	spi->dev.prvt = (void *)hw;
    1e0c:	4628      	mov	r0, r5
    1e0e:	f840 4f04 	str.w	r4, [r0, #4]!
	rc            = _spi_m_dma_init(&spi->dev, hw);
    1e12:	4621      	mov	r1, r4
    1e14:	4b08      	ldr	r3, [pc, #32]	; (1e38 <spi_m_dma_init+0x40>)
    1e16:	4798      	blx	r3
	if (rc) {
    1e18:	4603      	mov	r3, r0
    1e1a:	b918      	cbnz	r0, 1e24 <spi_m_dma_init+0x2c>
	spi->io.read  = _spi_m_dma_io_read;
    1e1c:	4a07      	ldr	r2, [pc, #28]	; (1e3c <spi_m_dma_init+0x44>)
    1e1e:	62aa      	str	r2, [r5, #40]	; 0x28
	spi->io.write = _spi_m_dma_io_write;
    1e20:	4a07      	ldr	r2, [pc, #28]	; (1e40 <spi_m_dma_init+0x48>)
    1e22:	626a      	str	r2, [r5, #36]	; 0x24
}
    1e24:	4618      	mov	r0, r3
    1e26:	bd38      	pop	{r3, r4, r5, pc}
	ASSERT(spi && hw);
    1e28:	2000      	movs	r0, #0
    1e2a:	e7eb      	b.n	1e04 <spi_m_dma_init+0xc>
    1e2c:	2000      	movs	r0, #0
    1e2e:	e7e9      	b.n	1e04 <spi_m_dma_init+0xc>
    1e30:	00003bec 	.word	0x00003bec
    1e34:	00001e9d 	.word	0x00001e9d
    1e38:	00002ee9 	.word	0x00002ee9
    1e3c:	00001dc5 	.word	0x00001dc5
    1e40:	00001d91 	.word	0x00001d91

00001e44 <spi_m_dma_enable>:
{
    1e44:	b510      	push	{r4, lr}
	ASSERT(spi);
    1e46:	4604      	mov	r4, r0
    1e48:	2251      	movs	r2, #81	; 0x51
    1e4a:	4905      	ldr	r1, [pc, #20]	; (1e60 <spi_m_dma_enable+0x1c>)
    1e4c:	3000      	adds	r0, #0
    1e4e:	bf18      	it	ne
    1e50:	2001      	movne	r0, #1
    1e52:	4b04      	ldr	r3, [pc, #16]	; (1e64 <spi_m_dma_enable+0x20>)
    1e54:	4798      	blx	r3
	_spi_m_dma_enable(&spi->dev);
    1e56:	1d20      	adds	r0, r4, #4
    1e58:	4b03      	ldr	r3, [pc, #12]	; (1e68 <spi_m_dma_enable+0x24>)
    1e5a:	4798      	blx	r3
    1e5c:	bd10      	pop	{r4, pc}
    1e5e:	bf00      	nop
    1e60:	00003bec 	.word	0x00003bec
    1e64:	00001e9d 	.word	0x00001e9d
    1e68:	00003065 	.word	0x00003065

00001e6c <spi_m_dma_register_callback>:
	return _spi_m_dma_transfer(&spi->dev, txbuf, rxbuf, length);
}

void spi_m_dma_register_callback(struct spi_m_dma_descriptor *spi, const enum spi_m_dma_cb_type type,
                                 spi_m_dma_cb_t func)
{
    1e6c:	b570      	push	{r4, r5, r6, lr}
    1e6e:	460d      	mov	r5, r1
    1e70:	4616      	mov	r6, r2
	ASSERT(spi);
    1e72:	4604      	mov	r4, r0
    1e74:	22a8      	movs	r2, #168	; 0xa8
    1e76:	4906      	ldr	r1, [pc, #24]	; (1e90 <spi_m_dma_register_callback+0x24>)
    1e78:	3000      	adds	r0, #0
    1e7a:	bf18      	it	ne
    1e7c:	2001      	movne	r0, #1
    1e7e:	4b05      	ldr	r3, [pc, #20]	; (1e94 <spi_m_dma_register_callback+0x28>)
    1e80:	4798      	blx	r3
	_spi_m_dma_register_callback(&spi->dev, (enum _spi_dma_dev_cb_type)type, func);
    1e82:	4632      	mov	r2, r6
    1e84:	4629      	mov	r1, r5
    1e86:	1d20      	adds	r0, r4, #4
    1e88:	4b03      	ldr	r3, [pc, #12]	; (1e98 <spi_m_dma_register_callback+0x2c>)
    1e8a:	4798      	blx	r3
    1e8c:	bd70      	pop	{r4, r5, r6, pc}
    1e8e:	bf00      	nop
    1e90:	00003bec 	.word	0x00003bec
    1e94:	00001e9d 	.word	0x00001e9d
    1e98:	00003099 	.word	0x00003099

00001e9c <assert>:
/**
 * \brief Assert function
 */
void assert(const bool condition, const char *const file, const int line)
{
	if (!(condition)) {
    1e9c:	b900      	cbnz	r0, 1ea0 <assert+0x4>
		__asm("BKPT #0");
    1e9e:	be00      	bkpt	0x0000
    1ea0:	4770      	bx	lr
	...

00001ea4 <ringbuffer_init>:

/**
 * \brief Ringbuffer init
 */
int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size)
{
    1ea4:	b570      	push	{r4, r5, r6, lr}
    1ea6:	460e      	mov	r6, r1
    1ea8:	4615      	mov	r5, r2
	ASSERT(rb && buf && size);
    1eaa:	4604      	mov	r4, r0
    1eac:	b178      	cbz	r0, 1ece <ringbuffer_init+0x2a>
    1eae:	b181      	cbz	r1, 1ed2 <ringbuffer_init+0x2e>
    1eb0:	b98a      	cbnz	r2, 1ed6 <ringbuffer_init+0x32>
    1eb2:	2000      	movs	r0, #0
    1eb4:	2228      	movs	r2, #40	; 0x28
    1eb6:	490a      	ldr	r1, [pc, #40]	; (1ee0 <ringbuffer_init+0x3c>)
    1eb8:	4b0a      	ldr	r3, [pc, #40]	; (1ee4 <ringbuffer_init+0x40>)
    1eba:	4798      	blx	r3

	/*
	 * buf size must be aligned to power of 2
	 */
	if ((size & (size - 1)) != 0) {
    1ebc:	1e6b      	subs	r3, r5, #1
    1ebe:	421d      	tst	r5, r3
    1ec0:	d10b      	bne.n	1eda <ringbuffer_init+0x36>
		return ERR_INVALID_ARG;
	}

	/* size - 1 is faster in calculation */
	rb->size        = size - 1;
    1ec2:	6063      	str	r3, [r4, #4]
	rb->read_index  = 0;
    1ec4:	2000      	movs	r0, #0
    1ec6:	60a0      	str	r0, [r4, #8]
	rb->write_index = rb->read_index;
    1ec8:	60e0      	str	r0, [r4, #12]
	rb->buf         = (uint8_t *)buf;
    1eca:	6026      	str	r6, [r4, #0]

	return ERR_NONE;
    1ecc:	bd70      	pop	{r4, r5, r6, pc}
	ASSERT(rb && buf && size);
    1ece:	2000      	movs	r0, #0
    1ed0:	e7f0      	b.n	1eb4 <ringbuffer_init+0x10>
    1ed2:	2000      	movs	r0, #0
    1ed4:	e7ee      	b.n	1eb4 <ringbuffer_init+0x10>
    1ed6:	2001      	movs	r0, #1
    1ed8:	e7ec      	b.n	1eb4 <ringbuffer_init+0x10>
		return ERR_INVALID_ARG;
    1eda:	f06f 000c 	mvn.w	r0, #12
}
    1ede:	bd70      	pop	{r4, r5, r6, pc}
    1ee0:	00003c08 	.word	0x00003c08
    1ee4:	00001e9d 	.word	0x00001e9d

00001ee8 <ringbuffer_put>:
/**
 * \brief Put one byte to ringbuffer
 *
 */
int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data)
{
    1ee8:	b538      	push	{r3, r4, r5, lr}
    1eea:	460d      	mov	r5, r1
	ASSERT(rb);
    1eec:	4604      	mov	r4, r0
    1eee:	2251      	movs	r2, #81	; 0x51
    1ef0:	490b      	ldr	r1, [pc, #44]	; (1f20 <ringbuffer_put+0x38>)
    1ef2:	3000      	adds	r0, #0
    1ef4:	bf18      	it	ne
    1ef6:	2001      	movne	r0, #1
    1ef8:	4b0a      	ldr	r3, [pc, #40]	; (1f24 <ringbuffer_put+0x3c>)
    1efa:	4798      	blx	r3

	rb->buf[rb->write_index & rb->size] = data;
    1efc:	6822      	ldr	r2, [r4, #0]
    1efe:	68e3      	ldr	r3, [r4, #12]
    1f00:	6861      	ldr	r1, [r4, #4]
    1f02:	400b      	ands	r3, r1
    1f04:	54d5      	strb	r5, [r2, r3]

	/*
	 * buffer full strategy: new data will overwrite the oldest data in
	 * the buffer
	 */
	if ((rb->write_index - rb->read_index) > rb->size) {
    1f06:	68e3      	ldr	r3, [r4, #12]
    1f08:	68a2      	ldr	r2, [r4, #8]
    1f0a:	1a9a      	subs	r2, r3, r2
    1f0c:	6861      	ldr	r1, [r4, #4]
    1f0e:	428a      	cmp	r2, r1
    1f10:	d901      	bls.n	1f16 <ringbuffer_put+0x2e>
		rb->read_index = rb->write_index - rb->size;
    1f12:	1a59      	subs	r1, r3, r1
    1f14:	60a1      	str	r1, [r4, #8]
	}

	rb->write_index++;
    1f16:	3301      	adds	r3, #1
    1f18:	60e3      	str	r3, [r4, #12]

	return ERR_NONE;
}
    1f1a:	2000      	movs	r0, #0
    1f1c:	bd38      	pop	{r3, r4, r5, pc}
    1f1e:	bf00      	nop
    1f20:	00003c08 	.word	0x00003c08
    1f24:	00001e9d 	.word	0x00001e9d

00001f28 <_adc_get_hardware_index>:
/**
 * \brief Retrieve ordinal number of the given adc hardware instance
 */
static uint8_t _adc_get_hardware_index(const void *const hw)
{
	return ((uint32_t)hw - (uint32_t)ADC0) >> 10;
    1f28:	f100 403d 	add.w	r0, r0, #3170893824	; 0xbd000000
    1f2c:	f5a0 50e0 	sub.w	r0, r0, #7168	; 0x1c00
}
    1f30:	f3c0 2087 	ubfx	r0, r0, #10, #8
    1f34:	4770      	bx	lr
	...

00001f38 <_adc_get_irq_num>:

/**
 * \brief Retrieve IRQ number for the given hardware instance
 */
static uint8_t _adc_get_irq_num(const struct _adc_async_device *const device)
{
    1f38:	b508      	push	{r3, lr}

	return ADC0_0_IRQn + (_adc_get_hardware_index(device->hw) << 1);
    1f3a:	6940      	ldr	r0, [r0, #20]
    1f3c:	4b03      	ldr	r3, [pc, #12]	; (1f4c <_adc_get_irq_num+0x14>)
    1f3e:	4798      	blx	r3
    1f40:	0040      	lsls	r0, r0, #1
    1f42:	b2c0      	uxtb	r0, r0
    1f44:	3076      	adds	r0, #118	; 0x76
}
    1f46:	f000 00fe 	and.w	r0, r0, #254	; 0xfe
    1f4a:	bd08      	pop	{r3, pc}
    1f4c:	00001f29 	.word	0x00001f29

00001f50 <_adc_init_irq_param>:
/**
 * \brief Init irq param with the given afec hardware instance
 */
static void _adc_init_irq_param(const void *const hw, struct _adc_async_device *dev)
{
	if (hw == ADC0) {
    1f50:	4b06      	ldr	r3, [pc, #24]	; (1f6c <_adc_init_irq_param+0x1c>)
    1f52:	4298      	cmp	r0, r3
    1f54:	d003      	beq.n	1f5e <_adc_init_irq_param+0xe>
		_adc0_dev = dev;
	}
	if (hw == ADC1) {
    1f56:	4b06      	ldr	r3, [pc, #24]	; (1f70 <_adc_init_irq_param+0x20>)
    1f58:	4298      	cmp	r0, r3
    1f5a:	d003      	beq.n	1f64 <_adc_init_irq_param+0x14>
    1f5c:	4770      	bx	lr
		_adc0_dev = dev;
    1f5e:	4b05      	ldr	r3, [pc, #20]	; (1f74 <_adc_init_irq_param+0x24>)
    1f60:	6019      	str	r1, [r3, #0]
    1f62:	e7f8      	b.n	1f56 <_adc_init_irq_param+0x6>
		_adc1_dev = dev;
    1f64:	4b03      	ldr	r3, [pc, #12]	; (1f74 <_adc_init_irq_param+0x24>)
    1f66:	6059      	str	r1, [r3, #4]
	}
}
    1f68:	e7f8      	b.n	1f5c <_adc_init_irq_param+0xc>
    1f6a:	bf00      	nop
    1f6c:	43001c00 	.word	0x43001c00
    1f70:	43002000 	.word	0x43002000
    1f74:	20000110 	.word	0x20000110

00001f78 <_adc_init>:
 *
 * \param[in] hw The pointer to hardware instance
 * \param[in] i The number of hardware instance
 */
static int32_t _adc_init(void *const hw, const uint8_t i)
{
    1f78:	b410      	push	{r4}
	uint16_t calib_reg = 0;
	if (hw == ADC0) {
    1f7a:	4b60      	ldr	r3, [pc, #384]	; (20fc <_adc_init+0x184>)
    1f7c:	4298      	cmp	r0, r3
    1f7e:	f000 809c 	beq.w	20ba <_adc_init+0x142>
		calib_reg = ADC_CALIB_BIASREFBUF((*(uint32_t *)ADC0_FUSES_BIASREFBUF_ADDR >> ADC0_FUSES_BIASREFBUF_Pos))
		            | ADC_CALIB_BIASR2R((*(uint32_t *)ADC0_FUSES_BIASR2R_ADDR >> ADC0_FUSES_BIASR2R_Pos))
		            | ADC_CALIB_BIASCOMP((*(uint32_t *)ADC0_FUSES_BIASCOMP_ADDR >> ADC0_FUSES_BIASCOMP_Pos));
	} else if (hw == ADC1) {
    1f82:	4b5f      	ldr	r3, [pc, #380]	; (2100 <_adc_init+0x188>)
    1f84:	4298      	cmp	r0, r3
    1f86:	f000 80a8 	beq.w	20da <_adc_init+0x162>
	uint16_t calib_reg = 0;
    1f8a:	2200      	movs	r2, #0
	};
}

static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg)
{
	return ((Adc *)hw)->SYNCBUSY.reg & reg;
    1f8c:	6b03      	ldr	r3, [r0, #48]	; 0x30
		calib_reg = ADC_CALIB_BIASREFBUF((*(uint32_t *)ADC1_FUSES_BIASREFBUF_ADDR >> ADC1_FUSES_BIASREFBUF_Pos))
		            | ADC_CALIB_BIASR2R((*(uint32_t *)ADC1_FUSES_BIASR2R_ADDR >> ADC1_FUSES_BIASR2R_Pos))
		            | ADC_CALIB_BIASCOMP((*(uint32_t *)ADC1_FUSES_BIASCOMP_ADDR >> ADC1_FUSES_BIASCOMP_Pos));
	}

	if (!hri_adc_is_syncing(hw, ADC_SYNCBUSY_SWRST)) {
    1f8e:	f013 0f01 	tst.w	r3, #1
    1f92:	d11b      	bne.n	1fcc <_adc_init+0x54>
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    1f94:	6b03      	ldr	r3, [r0, #48]	; 0x30
    1f96:	f013 0f03 	tst.w	r3, #3
    1f9a:	d1fb      	bne.n	1f94 <_adc_init+0x1c>

static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
{
	uint16_t tmp;
	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
	tmp = ((Adc *)hw)->CTRLA.reg;
    1f9c:	8803      	ldrh	r3, [r0, #0]
		if (hri_adc_get_CTRLA_reg(hw, ADC_CTRLA_ENABLE)) {
    1f9e:	f013 0f02 	tst.w	r3, #2
    1fa2:	d00d      	beq.n	1fc0 <_adc_init+0x48>
	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
    1fa4:	8803      	ldrh	r3, [r0, #0]
    1fa6:	b29b      	uxth	r3, r3
    1fa8:	f023 0302 	bic.w	r3, r3, #2
    1fac:	b29b      	uxth	r3, r3
    1fae:	8003      	strh	r3, [r0, #0]
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    1fb0:	6b03      	ldr	r3, [r0, #48]	; 0x30
    1fb2:	f013 0f03 	tst.w	r3, #3
    1fb6:	d1fb      	bne.n	1fb0 <_adc_init+0x38>
    1fb8:	6b03      	ldr	r3, [r0, #48]	; 0x30
    1fba:	f013 0f02 	tst.w	r3, #2
    1fbe:	d1fb      	bne.n	1fb8 <_adc_init+0x40>
}

static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data)
{
	ADC_CRITICAL_SECTION_ENTER();
	((Adc *)hw)->CTRLA.reg = data;
    1fc0:	2301      	movs	r3, #1
    1fc2:	8003      	strh	r3, [r0, #0]
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    1fc4:	6b03      	ldr	r3, [r0, #48]	; 0x30
    1fc6:	f013 0f03 	tst.w	r3, #3
    1fca:	d1fb      	bne.n	1fc4 <_adc_init+0x4c>
    1fcc:	6b03      	ldr	r3, [r0, #48]	; 0x30
    1fce:	f013 0f01 	tst.w	r3, #1
    1fd2:	d1fb      	bne.n	1fcc <_adc_init+0x54>
}

static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data)
{
	ADC_CRITICAL_SECTION_ENTER();
	((Adc *)hw)->CALIB.reg = data;
    1fd4:	f8a0 2048 	strh.w	r2, [r0, #72]	; 0x48
		hri_adc_write_CTRLA_reg(hw, ADC_CTRLA_SWRST);
	}
	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);

	hri_adc_write_CALIB_reg(hw, calib_reg);
	hri_adc_write_CTRLB_reg(hw, _adcs[i].ctrl_b);
    1fd8:	2316      	movs	r3, #22
    1fda:	4a4a      	ldr	r2, [pc, #296]	; (2104 <_adc_init+0x18c>)
    1fdc:	fb03 2301 	mla	r3, r3, r1, r2
    1fe0:	889b      	ldrh	r3, [r3, #4]
	((Adc *)hw)->CTRLB.reg = data;
    1fe2:	80c3      	strh	r3, [r0, #6]
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    1fe4:	6b03      	ldr	r3, [r0, #48]	; 0x30
    1fe6:	f3c3 030b 	ubfx	r3, r3, #0, #12
    1fea:	2b00      	cmp	r3, #0
    1fec:	d1fa      	bne.n	1fe4 <_adc_init+0x6c>
	hri_adc_write_REFCTRL_reg(hw, _adcs[i].ref_ctrl);
    1fee:	2316      	movs	r3, #22
    1ff0:	4a44      	ldr	r2, [pc, #272]	; (2104 <_adc_init+0x18c>)
    1ff2:	fb03 2301 	mla	r3, r3, r1, r2
    1ff6:	799b      	ldrb	r3, [r3, #6]
	((Adc *)hw)->REFCTRL.reg = data;
    1ff8:	7203      	strb	r3, [r0, #8]
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    1ffa:	6b03      	ldr	r3, [r0, #48]	; 0x30
    1ffc:	f3c3 030b 	ubfx	r3, r3, #0, #12
    2000:	2b00      	cmp	r3, #0
    2002:	d1fa      	bne.n	1ffa <_adc_init+0x82>
	hri_adc_write_EVCTRL_reg(hw, _adcs[i].ev_ctrl);
    2004:	2316      	movs	r3, #22
    2006:	4a3f      	ldr	r2, [pc, #252]	; (2104 <_adc_init+0x18c>)
    2008:	fb03 2301 	mla	r3, r3, r1, r2
    200c:	79da      	ldrb	r2, [r3, #7]
	((Adc *)hw)->EVCTRL.reg = data;
    200e:	7082      	strb	r2, [r0, #2]
	hri_adc_write_INPUTCTRL_reg(hw, _adcs[i].input_ctrl);
    2010:	891b      	ldrh	r3, [r3, #8]
	((Adc *)hw)->INPUTCTRL.reg = data;
    2012:	8083      	strh	r3, [r0, #4]
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    2014:	6b03      	ldr	r3, [r0, #48]	; 0x30
    2016:	f3c3 030b 	ubfx	r3, r3, #0, #12
    201a:	2b00      	cmp	r3, #0
    201c:	d1fa      	bne.n	2014 <_adc_init+0x9c>
	hri_adc_write_AVGCTRL_reg(hw, _adcs[i].avg_ctrl);
    201e:	2316      	movs	r3, #22
    2020:	4a38      	ldr	r2, [pc, #224]	; (2104 <_adc_init+0x18c>)
    2022:	fb03 2301 	mla	r3, r3, r1, r2
    2026:	7a9b      	ldrb	r3, [r3, #10]
	((Adc *)hw)->AVGCTRL.reg = data;
    2028:	7283      	strb	r3, [r0, #10]
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    202a:	6b03      	ldr	r3, [r0, #48]	; 0x30
    202c:	f3c3 030b 	ubfx	r3, r3, #0, #12
    2030:	2b00      	cmp	r3, #0
    2032:	d1fa      	bne.n	202a <_adc_init+0xb2>
	hri_adc_write_SAMPCTRL_reg(hw, _adcs[i].samp_ctrl);
    2034:	2316      	movs	r3, #22
    2036:	4a33      	ldr	r2, [pc, #204]	; (2104 <_adc_init+0x18c>)
    2038:	fb03 2301 	mla	r3, r3, r1, r2
    203c:	7adb      	ldrb	r3, [r3, #11]
	((Adc *)hw)->SAMPCTRL.reg = data;
    203e:	72c3      	strb	r3, [r0, #11]
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    2040:	6b03      	ldr	r3, [r0, #48]	; 0x30
    2042:	f3c3 030b 	ubfx	r3, r3, #0, #12
    2046:	2b00      	cmp	r3, #0
    2048:	d1fa      	bne.n	2040 <_adc_init+0xc8>
	hri_adc_write_WINLT_reg(hw, _adcs[i].win_lt);
    204a:	2316      	movs	r3, #22
    204c:	4a2d      	ldr	r2, [pc, #180]	; (2104 <_adc_init+0x18c>)
    204e:	fb03 2301 	mla	r3, r3, r1, r2
    2052:	899b      	ldrh	r3, [r3, #12]
	((Adc *)hw)->WINLT.reg = data;
    2054:	8183      	strh	r3, [r0, #12]
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    2056:	6b03      	ldr	r3, [r0, #48]	; 0x30
    2058:	f013 0f80 	tst.w	r3, #128	; 0x80
    205c:	d1fb      	bne.n	2056 <_adc_init+0xde>
	hri_adc_write_WINUT_reg(hw, _adcs[i].win_ut);
    205e:	2316      	movs	r3, #22
    2060:	4a28      	ldr	r2, [pc, #160]	; (2104 <_adc_init+0x18c>)
    2062:	fb03 2301 	mla	r3, r3, r1, r2
    2066:	89db      	ldrh	r3, [r3, #14]
	((Adc *)hw)->WINUT.reg = data;
    2068:	81c3      	strh	r3, [r0, #14]
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    206a:	6b03      	ldr	r3, [r0, #48]	; 0x30
    206c:	f413 7f80 	tst.w	r3, #256	; 0x100
    2070:	d1fb      	bne.n	206a <_adc_init+0xf2>
	hri_adc_write_GAINCORR_reg(hw, _adcs[i].gain_corr);
    2072:	2316      	movs	r3, #22
    2074:	4a23      	ldr	r2, [pc, #140]	; (2104 <_adc_init+0x18c>)
    2076:	fb03 2301 	mla	r3, r3, r1, r2
    207a:	8a1b      	ldrh	r3, [r3, #16]
	((Adc *)hw)->GAINCORR.reg = data;
    207c:	8203      	strh	r3, [r0, #16]
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    207e:	6b03      	ldr	r3, [r0, #48]	; 0x30
    2080:	f413 7f00 	tst.w	r3, #512	; 0x200
    2084:	d1fb      	bne.n	207e <_adc_init+0x106>
	hri_adc_write_OFFSETCORR_reg(hw, _adcs[i].offset_corr);
    2086:	2316      	movs	r3, #22
    2088:	4a1e      	ldr	r2, [pc, #120]	; (2104 <_adc_init+0x18c>)
    208a:	fb03 2301 	mla	r3, r3, r1, r2
    208e:	8a5b      	ldrh	r3, [r3, #18]
	((Adc *)hw)->OFFSETCORR.reg = data;
    2090:	8243      	strh	r3, [r0, #18]
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    2092:	6b03      	ldr	r3, [r0, #48]	; 0x30
    2094:	f413 6f80 	tst.w	r3, #1024	; 0x400
    2098:	d1fb      	bne.n	2092 <_adc_init+0x11a>
	hri_adc_write_DBGCTRL_reg(hw, _adcs[i].dbg_ctrl);
    209a:	2216      	movs	r2, #22
    209c:	4b19      	ldr	r3, [pc, #100]	; (2104 <_adc_init+0x18c>)
    209e:	fb02 3101 	mla	r1, r2, r1, r3
    20a2:	7d0b      	ldrb	r3, [r1, #20]
	((Adc *)hw)->DBGCTRL.reg = data;
    20a4:	70c3      	strb	r3, [r0, #3]
	hri_adc_write_CTRLA_reg(hw, _adcs[i].ctrl_a);
    20a6:	884b      	ldrh	r3, [r1, #2]
	((Adc *)hw)->CTRLA.reg = data;
    20a8:	8003      	strh	r3, [r0, #0]
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    20aa:	6b03      	ldr	r3, [r0, #48]	; 0x30
    20ac:	f013 0f03 	tst.w	r3, #3
    20b0:	d1fb      	bne.n	20aa <_adc_init+0x132>

	return ERR_NONE;
}
    20b2:	2000      	movs	r0, #0
    20b4:	f85d 4b04 	ldr.w	r4, [sp], #4
    20b8:	4770      	bx	lr
		calib_reg = ADC_CALIB_BIASREFBUF((*(uint32_t *)ADC0_FUSES_BIASREFBUF_ADDR >> ADC0_FUSES_BIASREFBUF_Pos))
    20ba:	f04f 1380 	mov.w	r3, #8388736	; 0x800080
    20be:	681b      	ldr	r3, [r3, #0]
    20c0:	095a      	lsrs	r2, r3, #5
    20c2:	0212      	lsls	r2, r2, #8
    20c4:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
		            | ADC_CALIB_BIASR2R((*(uint32_t *)ADC0_FUSES_BIASR2R_ADDR >> ADC0_FUSES_BIASR2R_Pos))
    20c8:	0a1c      	lsrs	r4, r3, #8
    20ca:	0124      	lsls	r4, r4, #4
    20cc:	f004 0470 	and.w	r4, r4, #112	; 0x70
    20d0:	4322      	orrs	r2, r4
		            | ADC_CALIB_BIASCOMP((*(uint32_t *)ADC0_FUSES_BIASCOMP_ADDR >> ADC0_FUSES_BIASCOMP_Pos));
    20d2:	f3c3 0382 	ubfx	r3, r3, #2, #3
		calib_reg = ADC_CALIB_BIASREFBUF((*(uint32_t *)ADC0_FUSES_BIASREFBUF_ADDR >> ADC0_FUSES_BIASREFBUF_Pos))
    20d6:	431a      	orrs	r2, r3
    20d8:	e758      	b.n	1f8c <_adc_init+0x14>
		calib_reg = ADC_CALIB_BIASREFBUF((*(uint32_t *)ADC1_FUSES_BIASREFBUF_ADDR >> ADC1_FUSES_BIASREFBUF_Pos))
    20da:	f04f 1380 	mov.w	r3, #8388736	; 0x800080
    20de:	681b      	ldr	r3, [r3, #0]
    20e0:	0cda      	lsrs	r2, r3, #19
    20e2:	0212      	lsls	r2, r2, #8
    20e4:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
		            | ADC_CALIB_BIASR2R((*(uint32_t *)ADC1_FUSES_BIASR2R_ADDR >> ADC1_FUSES_BIASR2R_Pos))
    20e8:	0d9c      	lsrs	r4, r3, #22
    20ea:	0124      	lsls	r4, r4, #4
    20ec:	f004 0470 	and.w	r4, r4, #112	; 0x70
    20f0:	4322      	orrs	r2, r4
		            | ADC_CALIB_BIASCOMP((*(uint32_t *)ADC1_FUSES_BIASCOMP_ADDR >> ADC1_FUSES_BIASCOMP_Pos));
    20f2:	f3c3 4302 	ubfx	r3, r3, #16, #3
		calib_reg = ADC_CALIB_BIASREFBUF((*(uint32_t *)ADC1_FUSES_BIASREFBUF_ADDR >> ADC1_FUSES_BIASREFBUF_Pos))
    20f6:	431a      	orrs	r2, r3
    20f8:	e748      	b.n	1f8c <_adc_init+0x14>
    20fa:	bf00      	nop
    20fc:	43001c00 	.word	0x43001c00
    2100:	43002000 	.word	0x43002000
    2104:	00003c2c 	.word	0x00003c2c

00002108 <_adc_interrupt_handler>:
 * \internal ADC interrupt handler
 *
 * \param[in] p The pointer to interrupt parameter
 */
static void _adc_interrupt_handler(struct _adc_async_device *device)
{
    2108:	b508      	push	{r3, lr}
	void *const hw      = device->hw;
    210a:	6942      	ldr	r2, [r0, #20]
	return ((Adc *)hw)->INTFLAG.reg;
    210c:	f892 102e 	ldrb.w	r1, [r2, #46]	; 0x2e
	return ((Adc *)hw)->INTENSET.reg;
    2110:	f892 302d 	ldrb.w	r3, [r2, #45]	; 0x2d
	uint8_t     intflag = hri_adc_read_INTFLAG_reg(hw);
	intflag &= hri_adc_read_INTEN_reg(hw);
    2114:	400b      	ands	r3, r1
	if (intflag & ADC_INTFLAG_RESRDY) {
    2116:	f013 0f01 	tst.w	r3, #1
    211a:	d106      	bne.n	212a <_adc_interrupt_handler+0x22>
		hri_adc_clear_interrupt_RESRDY_bit(hw);
		device->adc_async_ch_cb.convert_done(device, 0, hri_adc_read_RESULT_reg(hw));
	} else if (intflag & ADC_INTFLAG_OVERRUN) {
    211c:	f013 0f02 	tst.w	r3, #2
    2120:	d10d      	bne.n	213e <_adc_interrupt_handler+0x36>
		hri_adc_clear_interrupt_OVERRUN_bit(hw);
		device->adc_async_cb.error_cb(device, 0);
	} else if (intflag & ADC_INTFLAG_WINMON) {
    2122:	f013 0f04 	tst.w	r3, #4
    2126:	d111      	bne.n	214c <_adc_interrupt_handler+0x44>
    2128:	bd08      	pop	{r3, pc}
	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY;
    212a:	2301      	movs	r3, #1
    212c:	f882 302e 	strb.w	r3, [r2, #46]	; 0x2e
		device->adc_async_ch_cb.convert_done(device, 0, hri_adc_read_RESULT_reg(hw));
    2130:	6883      	ldr	r3, [r0, #8]
	return ((Adc *)hw)->RESULT.reg;
    2132:	f8b2 2040 	ldrh.w	r2, [r2, #64]	; 0x40
    2136:	b292      	uxth	r2, r2
    2138:	2100      	movs	r1, #0
    213a:	4798      	blx	r3
    213c:	bd08      	pop	{r3, pc}
	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
    213e:	2302      	movs	r3, #2
    2140:	f882 302e 	strb.w	r3, [r2, #46]	; 0x2e
		device->adc_async_cb.error_cb(device, 0);
    2144:	6843      	ldr	r3, [r0, #4]
    2146:	2100      	movs	r1, #0
    2148:	4798      	blx	r3
    214a:	bd08      	pop	{r3, pc}
	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON;
    214c:	2304      	movs	r3, #4
    214e:	f882 302e 	strb.w	r3, [r2, #46]	; 0x2e
		hri_adc_clear_interrupt_WINMON_bit(hw);
		device->adc_async_cb.window_cb(device, 0);
    2152:	6803      	ldr	r3, [r0, #0]
    2154:	2100      	movs	r1, #0
    2156:	4798      	blx	r3
	}
}
    2158:	e7e6      	b.n	2128 <_adc_interrupt_handler+0x20>
	...

0000215c <_adc_get_regs>:
{
    215c:	b508      	push	{r3, lr}
	uint8_t n = _adc_get_hardware_index((const void *)hw_addr);
    215e:	4b0b      	ldr	r3, [pc, #44]	; (218c <_adc_get_regs+0x30>)
    2160:	4798      	blx	r3
	for (i = 0; i < sizeof(_adcs) / sizeof(struct adc_configuration); i++) {
    2162:	2300      	movs	r3, #0
    2164:	2b01      	cmp	r3, #1
    2166:	d809      	bhi.n	217c <_adc_get_regs+0x20>
		if (_adcs[i].number == n) {
    2168:	2216      	movs	r2, #22
    216a:	fb02 f203 	mul.w	r2, r2, r3
    216e:	4908      	ldr	r1, [pc, #32]	; (2190 <_adc_get_regs+0x34>)
    2170:	5c8a      	ldrb	r2, [r1, r2]
    2172:	4290      	cmp	r0, r2
    2174:	d008      	beq.n	2188 <_adc_get_regs+0x2c>
	for (i = 0; i < sizeof(_adcs) / sizeof(struct adc_configuration); i++) {
    2176:	3301      	adds	r3, #1
    2178:	b2db      	uxtb	r3, r3
    217a:	e7f3      	b.n	2164 <_adc_get_regs+0x8>
	ASSERT(false);
    217c:	228c      	movs	r2, #140	; 0x8c
    217e:	4905      	ldr	r1, [pc, #20]	; (2194 <_adc_get_regs+0x38>)
    2180:	2000      	movs	r0, #0
    2182:	4b05      	ldr	r3, [pc, #20]	; (2198 <_adc_get_regs+0x3c>)
    2184:	4798      	blx	r3
	return 0;
    2186:	2300      	movs	r3, #0
}
    2188:	4618      	mov	r0, r3
    218a:	bd08      	pop	{r3, pc}
    218c:	00001f29 	.word	0x00001f29
    2190:	00003c2c 	.word	0x00003c2c
    2194:	00003c58 	.word	0x00003c58
    2198:	00001e9d 	.word	0x00001e9d

0000219c <_adc_async_init>:
{
    219c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    21a0:	460d      	mov	r5, r1
	ASSERT(device);
    21a2:	4604      	mov	r4, r0
    21a4:	22f1      	movs	r2, #241	; 0xf1
    21a6:	493b      	ldr	r1, [pc, #236]	; (2294 <_adc_async_init+0xf8>)
    21a8:	3000      	adds	r0, #0
    21aa:	bf18      	it	ne
    21ac:	2001      	movne	r0, #1
    21ae:	4b3a      	ldr	r3, [pc, #232]	; (2298 <_adc_async_init+0xfc>)
    21b0:	4798      	blx	r3
	init_status = _adc_init(hw, _adc_get_regs((uint32_t)hw));
    21b2:	4628      	mov	r0, r5
    21b4:	4b39      	ldr	r3, [pc, #228]	; (229c <_adc_async_init+0x100>)
    21b6:	4798      	blx	r3
    21b8:	4601      	mov	r1, r0
    21ba:	4628      	mov	r0, r5
    21bc:	4b38      	ldr	r3, [pc, #224]	; (22a0 <_adc_async_init+0x104>)
    21be:	4798      	blx	r3
	if (init_status) {
    21c0:	4606      	mov	r6, r0
    21c2:	b110      	cbz	r0, 21ca <_adc_async_init+0x2e>
}
    21c4:	4630      	mov	r0, r6
    21c6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	device->hw = hw;
    21ca:	6165      	str	r5, [r4, #20]
	_adc_init_irq_param(hw, device);
    21cc:	4621      	mov	r1, r4
    21ce:	4628      	mov	r0, r5
    21d0:	4b34      	ldr	r3, [pc, #208]	; (22a4 <_adc_async_init+0x108>)
    21d2:	4798      	blx	r3
	NVIC_DisableIRQ(_adc_get_irq_num(device) + 0);
    21d4:	4620      	mov	r0, r4
    21d6:	4f34      	ldr	r7, [pc, #208]	; (22a8 <_adc_async_init+0x10c>)
    21d8:	47b8      	blx	r7
 */
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    21da:	0943      	lsrs	r3, r0, #5
    21dc:	f000 001f 	and.w	r0, r0, #31
    21e0:	2501      	movs	r5, #1
    21e2:	fa05 f000 	lsl.w	r0, r5, r0
    21e6:	f8df 80c4 	ldr.w	r8, [pc, #196]	; 22ac <_adc_async_init+0x110>
    21ea:	3320      	adds	r3, #32
    21ec:	f848 0023 	str.w	r0, [r8, r3, lsl #2]
  __ASM volatile ("dsb 0xF":::"memory");
    21f0:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    21f4:	f3bf 8f6f 	isb	sy
	NVIC_ClearPendingIRQ(_adc_get_irq_num(device) + 0);
    21f8:	4620      	mov	r0, r4
    21fa:	47b8      	blx	r7
 */
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    21fc:	0943      	lsrs	r3, r0, #5
    21fe:	f000 001f 	and.w	r0, r0, #31
    2202:	fa05 f000 	lsl.w	r0, r5, r0
    2206:	3360      	adds	r3, #96	; 0x60
    2208:	f848 0023 	str.w	r0, [r8, r3, lsl #2]
	NVIC_EnableIRQ(_adc_get_irq_num(device) + 0);
    220c:	4620      	mov	r0, r4
    220e:	47b8      	blx	r7
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2210:	0943      	lsrs	r3, r0, #5
    2212:	f000 001f 	and.w	r0, r0, #31
    2216:	4085      	lsls	r5, r0
    2218:	f848 5023 	str.w	r5, [r8, r3, lsl #2]
	NVIC_DisableIRQ(_adc_get_irq_num(device) + 1);
    221c:	4620      	mov	r0, r4
    221e:	47b8      	blx	r7
    2220:	b280      	uxth	r0, r0
    2222:	3001      	adds	r0, #1
    2224:	b280      	uxth	r0, r0
    2226:	b203      	sxth	r3, r0
  if ((int32_t)(IRQn) >= 0)
    2228:	2b00      	cmp	r3, #0
    222a:	db0c      	blt.n	2246 <_adc_async_init+0xaa>
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    222c:	095b      	lsrs	r3, r3, #5
    222e:	f000 001f 	and.w	r0, r0, #31
    2232:	2201      	movs	r2, #1
    2234:	fa02 f000 	lsl.w	r0, r2, r0
    2238:	3320      	adds	r3, #32
    223a:	f848 0023 	str.w	r0, [r8, r3, lsl #2]
  __ASM volatile ("dsb 0xF":::"memory");
    223e:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2242:	f3bf 8f6f 	isb	sy
	NVIC_ClearPendingIRQ(_adc_get_irq_num(device) + 1);
    2246:	4620      	mov	r0, r4
    2248:	4b17      	ldr	r3, [pc, #92]	; (22a8 <_adc_async_init+0x10c>)
    224a:	4798      	blx	r3
    224c:	b280      	uxth	r0, r0
    224e:	3001      	adds	r0, #1
    2250:	b280      	uxth	r0, r0
    2252:	b203      	sxth	r3, r0
  if ((int32_t)(IRQn) >= 0)
    2254:	2b00      	cmp	r3, #0
    2256:	db09      	blt.n	226c <_adc_async_init+0xd0>
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2258:	095b      	lsrs	r3, r3, #5
    225a:	f000 001f 	and.w	r0, r0, #31
    225e:	2201      	movs	r2, #1
    2260:	fa02 f000 	lsl.w	r0, r2, r0
    2264:	3360      	adds	r3, #96	; 0x60
    2266:	4a11      	ldr	r2, [pc, #68]	; (22ac <_adc_async_init+0x110>)
    2268:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
	NVIC_EnableIRQ(_adc_get_irq_num(device) + 1);
    226c:	4620      	mov	r0, r4
    226e:	4b0e      	ldr	r3, [pc, #56]	; (22a8 <_adc_async_init+0x10c>)
    2270:	4798      	blx	r3
    2272:	b280      	uxth	r0, r0
    2274:	3001      	adds	r0, #1
    2276:	b280      	uxth	r0, r0
    2278:	b203      	sxth	r3, r0
  if ((int32_t)(IRQn) >= 0)
    227a:	2b00      	cmp	r3, #0
    227c:	dba2      	blt.n	21c4 <_adc_async_init+0x28>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    227e:	095b      	lsrs	r3, r3, #5
    2280:	f000 001f 	and.w	r0, r0, #31
    2284:	2201      	movs	r2, #1
    2286:	fa02 f000 	lsl.w	r0, r2, r0
    228a:	4a08      	ldr	r2, [pc, #32]	; (22ac <_adc_async_init+0x110>)
    228c:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
    2290:	e798      	b.n	21c4 <_adc_async_init+0x28>
    2292:	bf00      	nop
    2294:	00003c58 	.word	0x00003c58
    2298:	00001e9d 	.word	0x00001e9d
    229c:	0000215d 	.word	0x0000215d
    22a0:	00001f79 	.word	0x00001f79
    22a4:	00001f51 	.word	0x00001f51
    22a8:	00001f39 	.word	0x00001f39
    22ac:	e000e100 	.word	0xe000e100

000022b0 <_adc_async_enable_channel>:
	hri_adc_set_CTRLA_ENABLE_bit(device->hw);
    22b0:	6942      	ldr	r2, [r0, #20]
	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE;
    22b2:	8813      	ldrh	r3, [r2, #0]
    22b4:	b29b      	uxth	r3, r3
    22b6:	f043 0302 	orr.w	r3, r3, #2
    22ba:	8013      	strh	r3, [r2, #0]
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    22bc:	6b13      	ldr	r3, [r2, #48]	; 0x30
    22be:	f013 0f03 	tst.w	r3, #3
    22c2:	d1fb      	bne.n	22bc <_adc_async_enable_channel+0xc>
}
    22c4:	4770      	bx	lr

000022c6 <_adc_async_disable_channel>:
	hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
    22c6:	6942      	ldr	r2, [r0, #20]
	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
    22c8:	8813      	ldrh	r3, [r2, #0]
    22ca:	b29b      	uxth	r3, r3
    22cc:	f023 0302 	bic.w	r3, r3, #2
    22d0:	b29b      	uxth	r3, r3
    22d2:	8013      	strh	r3, [r2, #0]
	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
    22d4:	6b13      	ldr	r3, [r2, #48]	; 0x30
    22d6:	f013 0f03 	tst.w	r3, #3
    22da:	d1fb      	bne.n	22d4 <_adc_async_disable_channel+0xe>
}
    22dc:	4770      	bx	lr

000022de <_adc_async_get_data_size>:
	return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2;
    22de:	6943      	ldr	r3, [r0, #20]
	tmp = ((Adc *)hw)->CTRLB.reg;
    22e0:	88db      	ldrh	r3, [r3, #6]
	tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos;
    22e2:	f3c3 03c1 	ubfx	r3, r3, #3, #2
    22e6:	2b03      	cmp	r3, #3
    22e8:	d001      	beq.n	22ee <_adc_async_get_data_size+0x10>
    22ea:	2002      	movs	r0, #2
}
    22ec:	4770      	bx	lr
	return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2;
    22ee:	2001      	movs	r0, #1
    22f0:	4770      	bx	lr

000022f2 <_adc_async_set_irq_state>:
	void *const hw = device->hw;
    22f2:	6941      	ldr	r1, [r0, #20]
	if (ADC_ASYNC_DEVICE_MONITOR_CB == type) {
    22f4:	2a01      	cmp	r2, #1
    22f6:	d007      	beq.n	2308 <_adc_async_set_irq_state+0x16>
	} else if (ADC_ASYNC_DEVICE_ERROR_CB == type) {
    22f8:	2a02      	cmp	r2, #2
    22fa:	d00e      	beq.n	231a <_adc_async_set_irq_state+0x28>
	} else if (ADC_ASYNC_DEVICE_CONVERT_CB == type) {
    22fc:	b91a      	cbnz	r2, 2306 <_adc_async_set_irq_state+0x14>
	if (value == 0x0) {
    22fe:	b1ab      	cbz	r3, 232c <_adc_async_set_irq_state+0x3a>
		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY;
    2300:	2301      	movs	r3, #1
    2302:	f881 302d 	strb.w	r3, [r1, #45]	; 0x2d
    2306:	4770      	bx	lr
	if (value == 0x0) {
    2308:	b91b      	cbnz	r3, 2312 <_adc_async_set_irq_state+0x20>
		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON;
    230a:	2304      	movs	r3, #4
    230c:	f881 302c 	strb.w	r3, [r1, #44]	; 0x2c
    2310:	4770      	bx	lr
		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON;
    2312:	2304      	movs	r3, #4
    2314:	f881 302d 	strb.w	r3, [r1, #45]	; 0x2d
    2318:	4770      	bx	lr
	if (value == 0x0) {
    231a:	b91b      	cbnz	r3, 2324 <_adc_async_set_irq_state+0x32>
		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN;
    231c:	2302      	movs	r3, #2
    231e:	f881 302c 	strb.w	r3, [r1, #44]	; 0x2c
    2322:	4770      	bx	lr
		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN;
    2324:	2302      	movs	r3, #2
    2326:	f881 302d 	strb.w	r3, [r1, #45]	; 0x2d
    232a:	4770      	bx	lr
		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY;
    232c:	2301      	movs	r3, #1
    232e:	f881 302c 	strb.w	r3, [r1, #44]	; 0x2c
    2332:	4770      	bx	lr

00002334 <ADC0_0_Handler>:

/**
 * \brief DMAC interrupt handler
 */
void ADC0_0_Handler(void)
{
    2334:	b508      	push	{r3, lr}
	_adc_interrupt_handler(_adc0_dev);
    2336:	4b02      	ldr	r3, [pc, #8]	; (2340 <ADC0_0_Handler+0xc>)
    2338:	6818      	ldr	r0, [r3, #0]
    233a:	4b02      	ldr	r3, [pc, #8]	; (2344 <ADC0_0_Handler+0x10>)
    233c:	4798      	blx	r3
    233e:	bd08      	pop	{r3, pc}
    2340:	20000110 	.word	0x20000110
    2344:	00002109 	.word	0x00002109

00002348 <ADC0_1_Handler>:
}
/**
 * \brief DMAC interrupt handler
 */
void ADC0_1_Handler(void)
{
    2348:	b508      	push	{r3, lr}
	_adc_interrupt_handler(_adc0_dev);
    234a:	4b02      	ldr	r3, [pc, #8]	; (2354 <ADC0_1_Handler+0xc>)
    234c:	6818      	ldr	r0, [r3, #0]
    234e:	4b02      	ldr	r3, [pc, #8]	; (2358 <ADC0_1_Handler+0x10>)
    2350:	4798      	blx	r3
    2352:	bd08      	pop	{r3, pc}
    2354:	20000110 	.word	0x20000110
    2358:	00002109 	.word	0x00002109

0000235c <ADC1_0_Handler>:

/**
 * \brief DMAC interrupt handler
 */
void ADC1_0_Handler(void)
{
    235c:	b508      	push	{r3, lr}
	_adc_interrupt_handler(_adc1_dev);
    235e:	4b02      	ldr	r3, [pc, #8]	; (2368 <ADC1_0_Handler+0xc>)
    2360:	6858      	ldr	r0, [r3, #4]
    2362:	4b02      	ldr	r3, [pc, #8]	; (236c <ADC1_0_Handler+0x10>)
    2364:	4798      	blx	r3
    2366:	bd08      	pop	{r3, pc}
    2368:	20000110 	.word	0x20000110
    236c:	00002109 	.word	0x00002109

00002370 <ADC1_1_Handler>:
}
/**
 * \brief DMAC interrupt handler
 */
void ADC1_1_Handler(void)
{
    2370:	b508      	push	{r3, lr}
	_adc_interrupt_handler(_adc1_dev);
    2372:	4b02      	ldr	r3, [pc, #8]	; (237c <ADC1_1_Handler+0xc>)
    2374:	6858      	ldr	r0, [r3, #4]
    2376:	4b02      	ldr	r3, [pc, #8]	; (2380 <ADC1_1_Handler+0x10>)
    2378:	4798      	blx	r3
    237a:	bd08      	pop	{r3, pc}
    237c:	20000110 	.word	0x20000110
    2380:	00002109 	.word	0x00002109

00002384 <_custom_logic_init>:
}

static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data)
{
	CCL_CRITICAL_SECTION_ENTER();
	((Ccl *)hw)->CTRL.reg = data;
    2384:	4a11      	ldr	r2, [pc, #68]	; (23cc <_custom_logic_init+0x48>)
    2386:	2300      	movs	r3, #0
    2388:	7013      	strb	r3, [r2, #0]
    238a:	2101      	movs	r1, #1
    238c:	7011      	strb	r1, [r2, #0]
	uint8_t i;

	hri_ccl_write_CTRL_reg(CCL, 0);
	hri_ccl_write_CTRL_reg(CCL, CCL_CTRL_SWRST);

	for (i = 0; i < REG_SEQCTRL_NUM; i++) {
    238e:	e009      	b.n	23a4 <_custom_logic_init+0x20>
		hri_ccl_write_SEQCTRL_reg(CCL, i, _ccl_reg_cfgs.seqctrl[i]);
    2390:	4a0f      	ldr	r2, [pc, #60]	; (23d0 <_custom_logic_init+0x4c>)
    2392:	441a      	add	r2, r3
    2394:	7c11      	ldrb	r1, [r2, #16]
}

static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data)
{
	CCL_CRITICAL_SECTION_ENTER();
	((Ccl *)hw)->SEQCTRL[index].reg = data;
    2396:	f103 4284 	add.w	r2, r3, #1107296256	; 0x42000000
    239a:	f502 5260 	add.w	r2, r2, #14336	; 0x3800
    239e:	7111      	strb	r1, [r2, #4]
	for (i = 0; i < REG_SEQCTRL_NUM; i++) {
    23a0:	3301      	adds	r3, #1
    23a2:	b2db      	uxtb	r3, r3
    23a4:	2b01      	cmp	r3, #1
    23a6:	d9f3      	bls.n	2390 <_custom_logic_init+0xc>
    23a8:	2300      	movs	r3, #0
    23aa:	e008      	b.n	23be <_custom_logic_init+0x3a>
	}
	for (i = 0; i < REG_LUTCTRL_NUM; i++) {
		hri_ccl_write_LUTCTRL_reg(CCL, i, _ccl_reg_cfgs.lutctrl[i]);
    23ac:	4a08      	ldr	r2, [pc, #32]	; (23d0 <_custom_logic_init+0x4c>)
    23ae:	f852 0023 	ldr.w	r0, [r2, r3, lsl #2]
}

static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
{
	CCL_CRITICAL_SECTION_ENTER();
	((Ccl *)hw)->LUTCTRL[index].reg = data;
    23b2:	1c99      	adds	r1, r3, #2
    23b4:	4a05      	ldr	r2, [pc, #20]	; (23cc <_custom_logic_init+0x48>)
    23b6:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
	for (i = 0; i < REG_LUTCTRL_NUM; i++) {
    23ba:	3301      	adds	r3, #1
    23bc:	b2db      	uxtb	r3, r3
    23be:	2b03      	cmp	r3, #3
    23c0:	d9f4      	bls.n	23ac <_custom_logic_init+0x28>
	((Ccl *)hw)->CTRL.reg = data;
    23c2:	2000      	movs	r0, #0
    23c4:	4b01      	ldr	r3, [pc, #4]	; (23cc <_custom_logic_init+0x48>)
    23c6:	7018      	strb	r0, [r3, #0]
	}

	hri_ccl_write_CTRL_reg(CCL, _ccl_reg_cfgs.ctrl);
	return ERR_NONE;
}
    23c8:	4770      	bx	lr
    23ca:	bf00      	nop
    23cc:	42003800 	.word	0x42003800
    23d0:	00003c70 	.word	0x00003c70

000023d4 <_custom_logic_enable>:
	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE;
    23d4:	4a03      	ldr	r2, [pc, #12]	; (23e4 <_custom_logic_enable+0x10>)
    23d6:	7813      	ldrb	r3, [r2, #0]
    23d8:	f043 0302 	orr.w	r3, r3, #2
    23dc:	7013      	strb	r3, [r2, #0]

int32_t _custom_logic_enable(void)
{
	hri_ccl_set_CTRL_ENABLE_bit(CCL);
	return ERR_NONE;
}
    23de:	2000      	movs	r0, #0
    23e0:	4770      	bx	lr
    23e2:	bf00      	nop
    23e4:	42003800 	.word	0x42003800

000023e8 <_init_chip>:

/**
 * \brief Initialize the hardware abstraction layer
 */
void _init_chip(void)
{
    23e8:	b510      	push	{r4, lr}
}

static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
{
	NVMCTRL_CRITICAL_SECTION_ENTER();
	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask);
    23ea:	4a16      	ldr	r2, [pc, #88]	; (2444 <_init_chip+0x5c>)
    23ec:	8813      	ldrh	r3, [r2, #0]
    23ee:	b29b      	uxth	r3, r3
    23f0:	8013      	strh	r3, [r2, #0]
	hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);

	_osc32kctrl_init_sources();
    23f2:	4b15      	ldr	r3, [pc, #84]	; (2448 <_init_chip+0x60>)
    23f4:	4798      	blx	r3
	_oscctrl_init_sources();
    23f6:	4b15      	ldr	r3, [pc, #84]	; (244c <_init_chip+0x64>)
    23f8:	4798      	blx	r3
	_mclk_init();
    23fa:	4b15      	ldr	r3, [pc, #84]	; (2450 <_init_chip+0x68>)
    23fc:	4798      	blx	r3
#if _GCLK_INIT_1ST
	_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
    23fe:	2006      	movs	r0, #6
    2400:	4c14      	ldr	r4, [pc, #80]	; (2454 <_init_chip+0x6c>)
    2402:	47a0      	blx	r4
#endif
	_oscctrl_init_referenced_generators();
    2404:	4b14      	ldr	r3, [pc, #80]	; (2458 <_init_chip+0x70>)
    2406:	4798      	blx	r3
	_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
    2408:	f640 70f9 	movw	r0, #4089	; 0xff9
    240c:	47a0      	blx	r4
	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC;
    240e:	4a13      	ldr	r2, [pc, #76]	; (245c <_init_chip+0x74>)
    2410:	6913      	ldr	r3, [r2, #16]
    2412:	f443 7300 	orr.w	r3, r3, #512	; 0x200
    2416:	6113      	str	r3, [r2, #16]

#if CONF_DMAC_ENABLE
	hri_mclk_set_AHBMASK_DMAC_bit(MCLK);
	_dma_init();
    2418:	4b11      	ldr	r3, [pc, #68]	; (2460 <_init_chip+0x78>)
    241a:	4798      	blx	r3
	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask;
    241c:	4b11      	ldr	r3, [pc, #68]	; (2464 <_init_chip+0x7c>)
    241e:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    2420:	62da      	str	r2, [r3, #44]	; 0x2c
    2422:	f8d3 20ac 	ldr.w	r2, [r3, #172]	; 0xac
    2426:	f8c3 20ac 	str.w	r2, [r3, #172]	; 0xac
    242a:	f8d3 212c 	ldr.w	r2, [r3, #300]	; 0x12c
    242e:	f042 026a 	orr.w	r2, r2, #106	; 0x6a
    2432:	f8c3 212c 	str.w	r2, [r3, #300]	; 0x12c
    2436:	f8d3 21ac 	ldr.w	r2, [r3, #428]	; 0x1ac
    243a:	f042 02ea 	orr.w	r2, r2, #234	; 0xea
    243e:	f8c3 21ac 	str.w	r2, [r3, #428]	; 0x1ac
    2442:	bd10      	pop	{r4, pc}
    2444:	41004000 	.word	0x41004000
    2448:	00002a51 	.word	0x00002a51
    244c:	00002a65 	.word	0x00002a65
    2450:	00002a45 	.word	0x00002a45
    2454:	000029e9 	.word	0x000029e9
    2458:	00002a69 	.word	0x00002a69
    245c:	40000800 	.word	0x40000800
    2460:	000024e9 	.word	0x000024e9
    2464:	41008000 	.word	0x41008000

00002468 <_dmac_handler>:
}
/**
 * \internal DMAC interrupt handler
 */
static void _dmac_handler(void)
{
    2468:	b508      	push	{r3, lr}
	tmp = ((Dmac *)hw)->INTPEND.reg;
    246a:	4a1d      	ldr	r2, [pc, #116]	; (24e0 <_dmac_handler+0x78>)
    246c:	8c13      	ldrh	r3, [r2, #32]
	uint8_t               channel      = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk);
    246e:	f003 031f 	and.w	r3, r3, #31
	struct _dma_resource *tmp_resource = &_resources[channel];
    2472:	481c      	ldr	r0, [pc, #112]	; (24e4 <_dmac_handler+0x7c>)
    2474:	eb00 1003 	add.w	r0, r0, r3, lsl #4
	tmp = ((Dmac *)hw)->INTPEND.reg;
    2478:	8c12      	ldrh	r2, [r2, #32]

	if (hri_dmac_get_INTPEND_TERR_bit(DMAC)) {
    247a:	f412 7f80 	tst.w	r2, #256	; 0x100
    247e:	d10a      	bne.n	2496 <_dmac_handler+0x2e>
	tmp = ((Dmac *)hw)->INTPEND.reg;
    2480:	4a17      	ldr	r2, [pc, #92]	; (24e0 <_dmac_handler+0x78>)
    2482:	8c12      	ldrh	r2, [r2, #32]
		hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel);
		tmp_resource->dma_cb.error(tmp_resource);
	} else if (hri_dmac_get_INTPEND_TCMPL_bit(DMAC)) {
    2484:	f412 7f00 	tst.w	r2, #512	; 0x200
    2488:	d110      	bne.n	24ac <_dmac_handler+0x44>
	tmp = ((Dmac *)hw)->INTPEND.reg;
    248a:	4a15      	ldr	r2, [pc, #84]	; (24e0 <_dmac_handler+0x78>)
    248c:	8c12      	ldrh	r2, [r2, #32]
		hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC, channel);
		tmp_resource->dma_cb.transfer_done(tmp_resource);
	} else if  (hri_dmac_get_INTPEND_SUSP_bit(DMAC)) {
    248e:	f412 6f80 	tst.w	r2, #1024	; 0x400
    2492:	d117      	bne.n	24c4 <_dmac_handler+0x5c>
    2494:	bd08      	pop	{r3, pc}
	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
}

static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index)
{
	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
    2496:	011b      	lsls	r3, r3, #4
    2498:	f103 4282 	add.w	r2, r3, #1090519040	; 0x41000000
    249c:	f502 4220 	add.w	r2, r2, #40960	; 0xa000
    24a0:	2101      	movs	r1, #1
    24a2:	f882 104e 	strb.w	r1, [r2, #78]	; 0x4e
		tmp_resource->dma_cb.error(tmp_resource);
    24a6:	6843      	ldr	r3, [r0, #4]
    24a8:	4798      	blx	r3
    24aa:	bd08      	pop	{r3, pc}
	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
}

static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index)
{
	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
    24ac:	011b      	lsls	r3, r3, #4
    24ae:	f103 4282 	add.w	r2, r3, #1090519040	; 0x41000000
    24b2:	f502 4220 	add.w	r2, r2, #40960	; 0xa000
    24b6:	2102      	movs	r1, #2
    24b8:	f882 104e 	strb.w	r1, [r2, #78]	; 0x4e
		tmp_resource->dma_cb.transfer_done(tmp_resource);
    24bc:	4a09      	ldr	r2, [pc, #36]	; (24e4 <_dmac_handler+0x7c>)
    24be:	58d3      	ldr	r3, [r2, r3]
    24c0:	4798      	blx	r3
    24c2:	bd08      	pop	{r3, pc}
	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
}

static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index)
{
	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
    24c4:	011b      	lsls	r3, r3, #4
    24c6:	f103 4282 	add.w	r2, r3, #1090519040	; 0x41000000
    24ca:	f502 4220 	add.w	r2, r2, #40960	; 0xa000
    24ce:	2104      	movs	r1, #4
    24d0:	f882 104e 	strb.w	r1, [r2, #78]	; 0x4e
		hri_dmac_clear_CHINTFLAG_SUSP_bit(DMAC, channel);
		tmp_resource->dma_cb.suspend(tmp_resource);
    24d4:	4a03      	ldr	r2, [pc, #12]	; (24e4 <_dmac_handler+0x7c>)
    24d6:	4413      	add	r3, r2
    24d8:	689b      	ldr	r3, [r3, #8]
    24da:	4798      	blx	r3
	}
}
    24dc:	e7da      	b.n	2494 <_dmac_handler+0x2c>
    24de:	bf00      	nop
    24e0:	4100a000 	.word	0x4100a000
    24e4:	20000118 	.word	0x20000118

000024e8 <_dma_init>:
{
    24e8:	b430      	push	{r4, r5}
	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
    24ea:	4a3d      	ldr	r2, [pc, #244]	; (25e0 <_dma_init+0xf8>)
    24ec:	8813      	ldrh	r3, [r2, #0]
    24ee:	b29b      	uxth	r3, r3
    24f0:	f023 0302 	bic.w	r3, r3, #2
    24f4:	b29b      	uxth	r3, r3
    24f6:	8013      	strh	r3, [r2, #0]
	((Dmac *)hw)->CRCCTRL.reg &= ~mask;
    24f8:	8853      	ldrh	r3, [r2, #2]
    24fa:	b29b      	uxth	r3, r3
    24fc:	f423 537c 	bic.w	r3, r3, #16128	; 0x3f00
    2500:	b29b      	uxth	r3, r3
    2502:	8053      	strh	r3, [r2, #2]
	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST;
    2504:	8813      	ldrh	r3, [r2, #0]
    2506:	b29b      	uxth	r3, r3
    2508:	f043 0301 	orr.w	r3, r3, #1
    250c:	8013      	strh	r3, [r2, #0]
	tmp = ((Dmac *)hw)->CTRL.reg;
    250e:	4b34      	ldr	r3, [pc, #208]	; (25e0 <_dma_init+0xf8>)
    2510:	881b      	ldrh	r3, [r3, #0]
	while (hri_dmac_get_CTRL_SWRST_bit(DMAC))
    2512:	f013 0f01 	tst.w	r3, #1
    2516:	d1fa      	bne.n	250e <_dma_init+0x26>
	((Dmac *)hw)->CTRL.reg = data;
    2518:	4b31      	ldr	r3, [pc, #196]	; (25e0 <_dma_init+0xf8>)
    251a:	f44f 7280 	mov.w	r2, #256	; 0x100
    251e:	801a      	strh	r2, [r3, #0]
	tmp = ((Dmac *)hw)->DBGCTRL.reg;
    2520:	7b5a      	ldrb	r2, [r3, #13]
	tmp &= ~DMAC_DBGCTRL_DBGRUN;
    2522:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
	((Dmac *)hw)->DBGCTRL.reg = tmp;
    2526:	735a      	strb	r2, [r3, #13]
	((Dmac *)hw)->PRICTRL0.reg = data;
    2528:	f248 0280 	movw	r2, #32896	; 0x8080
    252c:	615a      	str	r2, [r3, #20]
	hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section);
    252e:	4a2d      	ldr	r2, [pc, #180]	; (25e4 <_dma_init+0xfc>)
	((Dmac *)hw)->BASEADDR.reg = data;
    2530:	635a      	str	r2, [r3, #52]	; 0x34
	hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section);
    2532:	4a2d      	ldr	r2, [pc, #180]	; (25e8 <_dma_init+0x100>)
	((Dmac *)hw)->WRBADDR.reg = data;
    2534:	639a      	str	r2, [r3, #56]	; 0x38
	for (i = 0; i < DMAC_CH_NUM; i++) {
    2536:	2300      	movs	r3, #0
    2538:	e016      	b.n	2568 <_dma_init+0x80>
		hri_dmac_write_CHCTRLA_reg(DMAC, i, _cfgs[i].ctrla);
    253a:	4a2c      	ldr	r2, [pc, #176]	; (25ec <_dma_init+0x104>)
    253c:	f852 5033 	ldr.w	r5, [r2, r3, lsl #3]

static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, uint8_t submodule_index,
                                              hri_dmac_chctrla_reg_t data)
{
	DMAC_CRITICAL_SECTION_ENTER();
	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = data;
    2540:	4c27      	ldr	r4, [pc, #156]	; (25e0 <_dma_init+0xf8>)
    2542:	1d19      	adds	r1, r3, #4
    2544:	0109      	lsls	r1, r1, #4
    2546:	1860      	adds	r0, r4, r1
    2548:	5065      	str	r5, [r4, r1]
		hri_dmac_write_CHPRILVL_reg(DMAC, i, _cfgs[i].prilvl);
    254a:	eb02 02c3 	add.w	r2, r2, r3, lsl #3
    254e:	7911      	ldrb	r1, [r2, #4]

static inline void hri_dmac_write_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
                                               hri_dmac_chprilvl_reg_t data)
{
	DMAC_CRITICAL_SECTION_ENTER();
	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = data;
    2550:	7141      	strb	r1, [r0, #5]
		hri_dmac_write_CHEVCTRL_reg(DMAC, i, _cfgs[i].evctrl);
    2552:	7951      	ldrb	r1, [r2, #5]

static inline void hri_dmac_write_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
                                               hri_dmac_chevctrl_reg_t data)
{
	DMAC_CRITICAL_SECTION_ENTER();
	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = data;
    2554:	7181      	strb	r1, [r0, #6]
		hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl);
    2556:	88d4      	ldrh	r4, [r2, #6]
	((DmacDescriptor *)hw)->BTCTRL.reg = data;
    2558:	4922      	ldr	r1, [pc, #136]	; (25e4 <_dma_init+0xfc>)
    255a:	011a      	lsls	r2, r3, #4
    255c:	1888      	adds	r0, r1, r2
    255e:	528c      	strh	r4, [r1, r2]
	((DmacDescriptor *)hw)->DESCADDR.reg = data;
    2560:	2200      	movs	r2, #0
    2562:	60c2      	str	r2, [r0, #12]
	for (i = 0; i < DMAC_CH_NUM; i++) {
    2564:	3301      	adds	r3, #1
    2566:	b2db      	uxtb	r3, r3
    2568:	2b1f      	cmp	r3, #31
    256a:	d9e6      	bls.n	253a <_dma_init+0x52>
    256c:	2300      	movs	r3, #0
    256e:	e00a      	b.n	2586 <_dma_init+0x9e>
		NVIC_DisableIRQ(DMAC_0_IRQn + i);
    2570:	f103 011f 	add.w	r1, r3, #31
    2574:	b20a      	sxth	r2, r1
  if ((int32_t)(IRQn) >= 0)
    2576:	2a00      	cmp	r2, #0
    2578:	da10      	bge.n	259c <_dma_init+0xb4>
  if ((int32_t)(IRQn) >= 0)
    257a:	2a00      	cmp	r2, #0
    257c:	da1c      	bge.n	25b8 <_dma_init+0xd0>
  if ((int32_t)(IRQn) >= 0)
    257e:	2a00      	cmp	r2, #0
    2580:	da24      	bge.n	25cc <_dma_init+0xe4>
	for (i = 0; i < 5; i++) {
    2582:	3301      	adds	r3, #1
    2584:	b2db      	uxtb	r3, r3
    2586:	2b04      	cmp	r3, #4
    2588:	d9f2      	bls.n	2570 <_dma_init+0x88>
	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE;
    258a:	4a15      	ldr	r2, [pc, #84]	; (25e0 <_dma_init+0xf8>)
    258c:	8813      	ldrh	r3, [r2, #0]
    258e:	b29b      	uxth	r3, r3
    2590:	f043 0302 	orr.w	r3, r3, #2
    2594:	8013      	strh	r3, [r2, #0]
}
    2596:	2000      	movs	r0, #0
    2598:	bc30      	pop	{r4, r5}
    259a:	4770      	bx	lr
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    259c:	0950      	lsrs	r0, r2, #5
    259e:	f001 051f 	and.w	r5, r1, #31
    25a2:	2401      	movs	r4, #1
    25a4:	40ac      	lsls	r4, r5
    25a6:	3020      	adds	r0, #32
    25a8:	4d11      	ldr	r5, [pc, #68]	; (25f0 <_dma_init+0x108>)
    25aa:	f845 4020 	str.w	r4, [r5, r0, lsl #2]
  __ASM volatile ("dsb 0xF":::"memory");
    25ae:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    25b2:	f3bf 8f6f 	isb	sy
    25b6:	e7e0      	b.n	257a <_dma_init+0x92>
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    25b8:	0950      	lsrs	r0, r2, #5
    25ba:	f001 051f 	and.w	r5, r1, #31
    25be:	2401      	movs	r4, #1
    25c0:	40ac      	lsls	r4, r5
    25c2:	3060      	adds	r0, #96	; 0x60
    25c4:	4d0a      	ldr	r5, [pc, #40]	; (25f0 <_dma_init+0x108>)
    25c6:	f845 4020 	str.w	r4, [r5, r0, lsl #2]
    25ca:	e7d8      	b.n	257e <_dma_init+0x96>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    25cc:	0952      	lsrs	r2, r2, #5
    25ce:	f001 011f 	and.w	r1, r1, #31
    25d2:	2001      	movs	r0, #1
    25d4:	fa00 f101 	lsl.w	r1, r0, r1
    25d8:	4805      	ldr	r0, [pc, #20]	; (25f0 <_dma_init+0x108>)
    25da:	f840 1022 	str.w	r1, [r0, r2, lsl #2]
    25de:	e7d0      	b.n	2582 <_dma_init+0x9a>
    25e0:	4100a000 	.word	0x4100a000
    25e4:	200006e0 	.word	0x200006e0
    25e8:	200008e0 	.word	0x200008e0
    25ec:	00003c84 	.word	0x00003c84
    25f0:	e000e100 	.word	0xe000e100

000025f4 <_dma_set_irq_state>:
	if (DMA_TRANSFER_COMPLETE_CB == type) {
    25f4:	b991      	cbnz	r1, 261c <_dma_set_irq_state+0x28>
	if (value == 0x0) {
    25f6:	b942      	cbnz	r2, 260a <_dma_set_irq_state+0x16>
		((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
    25f8:	0100      	lsls	r0, r0, #4
    25fa:	f100 4082 	add.w	r0, r0, #1090519040	; 0x41000000
    25fe:	f500 4020 	add.w	r0, r0, #40960	; 0xa000
    2602:	2302      	movs	r3, #2
    2604:	f880 304c 	strb.w	r3, [r0, #76]	; 0x4c
    2608:	4770      	bx	lr
		((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
    260a:	0100      	lsls	r0, r0, #4
    260c:	f100 4082 	add.w	r0, r0, #1090519040	; 0x41000000
    2610:	f500 4020 	add.w	r0, r0, #40960	; 0xa000
    2614:	2302      	movs	r3, #2
    2616:	f880 304d 	strb.w	r3, [r0, #77]	; 0x4d
    261a:	4770      	bx	lr
	} else if (DMA_TRANSFER_ERROR_CB == type) {
    261c:	2901      	cmp	r1, #1
    261e:	d002      	beq.n	2626 <_dma_set_irq_state+0x32>
	} else if (DMA_TRANSFER_SUSPEND_CB == type) {
    2620:	2902      	cmp	r1, #2
    2622:	d012      	beq.n	264a <_dma_set_irq_state+0x56>
    2624:	4770      	bx	lr
	if (value == 0x0) {
    2626:	b93a      	cbnz	r2, 2638 <_dma_set_irq_state+0x44>
		((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
    2628:	0100      	lsls	r0, r0, #4
    262a:	f100 4082 	add.w	r0, r0, #1090519040	; 0x41000000
    262e:	f500 4020 	add.w	r0, r0, #40960	; 0xa000
    2632:	f880 104c 	strb.w	r1, [r0, #76]	; 0x4c
    2636:	4770      	bx	lr
		((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR;
    2638:	0100      	lsls	r0, r0, #4
    263a:	f100 4082 	add.w	r0, r0, #1090519040	; 0x41000000
    263e:	f500 4020 	add.w	r0, r0, #40960	; 0xa000
    2642:	2301      	movs	r3, #1
    2644:	f880 304d 	strb.w	r3, [r0, #77]	; 0x4d
    2648:	4770      	bx	lr
	if (value == 0x0) {
    264a:	b142      	cbz	r2, 265e <_dma_set_irq_state+0x6a>
		((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
    264c:	0100      	lsls	r0, r0, #4
    264e:	f100 4082 	add.w	r0, r0, #1090519040	; 0x41000000
    2652:	f500 4020 	add.w	r0, r0, #40960	; 0xa000
    2656:	2304      	movs	r3, #4
    2658:	f880 304d 	strb.w	r3, [r0, #77]	; 0x4d
}
    265c:	e7e2      	b.n	2624 <_dma_set_irq_state+0x30>
		((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
    265e:	0100      	lsls	r0, r0, #4
    2660:	f100 4082 	add.w	r0, r0, #1090519040	; 0x41000000
    2664:	f500 4020 	add.w	r0, r0, #40960	; 0xa000
    2668:	2304      	movs	r3, #4
    266a:	f880 304c 	strb.w	r3, [r0, #76]	; 0x4c
    266e:	4770      	bx	lr

00002670 <_dma_set_destination_address>:
	((DmacDescriptor *)hw)->DSTADDR.reg = data;
    2670:	4b02      	ldr	r3, [pc, #8]	; (267c <_dma_set_destination_address+0xc>)
    2672:	eb03 1000 	add.w	r0, r3, r0, lsl #4
    2676:	6081      	str	r1, [r0, #8]
}
    2678:	2000      	movs	r0, #0
    267a:	4770      	bx	lr
    267c:	200006e0 	.word	0x200006e0

00002680 <_dma_set_source_address>:
	((DmacDescriptor *)hw)->SRCADDR.reg = data;
    2680:	4b02      	ldr	r3, [pc, #8]	; (268c <_dma_set_source_address+0xc>)
    2682:	eb03 1000 	add.w	r0, r3, r0, lsl #4
    2686:	6041      	str	r1, [r0, #4]
}
    2688:	2000      	movs	r0, #0
    268a:	4770      	bx	lr
    268c:	200006e0 	.word	0x200006e0

00002690 <_dma_srcinc_enable>:
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    2690:	4a05      	ldr	r2, [pc, #20]	; (26a8 <_dma_srcinc_enable+0x18>)
    2692:	0100      	lsls	r0, r0, #4
    2694:	5a13      	ldrh	r3, [r2, r0]
    2696:	b29b      	uxth	r3, r3
	tmp &= ~DMAC_BTCTRL_SRCINC;
    2698:	f423 6380 	bic.w	r3, r3, #1024	; 0x400
	tmp |= value << DMAC_BTCTRL_SRCINC_Pos;
    269c:	ea43 2181 	orr.w	r1, r3, r1, lsl #10
    26a0:	b289      	uxth	r1, r1
	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
    26a2:	5211      	strh	r1, [r2, r0]
}
    26a4:	2000      	movs	r0, #0
    26a6:	4770      	bx	lr
    26a8:	200006e0 	.word	0x200006e0

000026ac <_dma_set_data_amount>:
{
    26ac:	b430      	push	{r4, r5}
	return ((DmacDescriptor *)hw)->DSTADDR.reg;
    26ae:	4c14      	ldr	r4, [pc, #80]	; (2700 <_dma_set_data_amount+0x54>)
    26b0:	0102      	lsls	r2, r0, #4
    26b2:	18a3      	adds	r3, r4, r2
    26b4:	689d      	ldr	r5, [r3, #8]
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    26b6:	5aa3      	ldrh	r3, [r4, r2]
	uint8_t  beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]);
    26b8:	f3c3 2301 	ubfx	r3, r3, #8, #2
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    26bc:	5aa2      	ldrh	r2, [r4, r2]
	if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) {
    26be:	f412 6f00 	tst.w	r2, #2048	; 0x800
    26c2:	d006      	beq.n	26d2 <_dma_set_data_amount+0x26>
		hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size));
    26c4:	fa01 f403 	lsl.w	r4, r1, r3
    26c8:	442c      	add	r4, r5
	((DmacDescriptor *)hw)->DSTADDR.reg = data;
    26ca:	4a0d      	ldr	r2, [pc, #52]	; (2700 <_dma_set_data_amount+0x54>)
    26cc:	eb02 1200 	add.w	r2, r2, r0, lsl #4
    26d0:	6094      	str	r4, [r2, #8]
	return ((DmacDescriptor *)hw)->SRCADDR.reg;
    26d2:	4c0b      	ldr	r4, [pc, #44]	; (2700 <_dma_set_data_amount+0x54>)
    26d4:	0102      	lsls	r2, r0, #4
    26d6:	18a5      	adds	r5, r4, r2
    26d8:	686d      	ldr	r5, [r5, #4]
	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
    26da:	5aa2      	ldrh	r2, [r4, r2]
	if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) {
    26dc:	f412 6f80 	tst.w	r2, #1024	; 0x400
    26e0:	d005      	beq.n	26ee <_dma_set_data_amount+0x42>
		hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size));
    26e2:	fa01 f303 	lsl.w	r3, r1, r3
    26e6:	442b      	add	r3, r5
	((DmacDescriptor *)hw)->SRCADDR.reg = data;
    26e8:	eb04 1200 	add.w	r2, r4, r0, lsl #4
    26ec:	6053      	str	r3, [r2, #4]
	hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount);
    26ee:	b289      	uxth	r1, r1
	((DmacDescriptor *)hw)->BTCNT.reg = data;
    26f0:	4b03      	ldr	r3, [pc, #12]	; (2700 <_dma_set_data_amount+0x54>)
    26f2:	eb03 1000 	add.w	r0, r3, r0, lsl #4
    26f6:	8041      	strh	r1, [r0, #2]
}
    26f8:	2000      	movs	r0, #0
    26fa:	bc30      	pop	{r4, r5}
    26fc:	4770      	bx	lr
    26fe:	bf00      	nop
    2700:	200006e0 	.word	0x200006e0

00002704 <_dma_enable_transaction>:
{
    2704:	b410      	push	{r4}
	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID;
    2706:	4c0c      	ldr	r4, [pc, #48]	; (2738 <_dma_enable_transaction+0x34>)
    2708:	0102      	lsls	r2, r0, #4
    270a:	5aa3      	ldrh	r3, [r4, r2]
    270c:	b29b      	uxth	r3, r3
    270e:	f043 0301 	orr.w	r3, r3, #1
    2712:	52a3      	strh	r3, [r4, r2]
	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
    2714:	4c09      	ldr	r4, [pc, #36]	; (273c <_dma_enable_transaction+0x38>)
    2716:	1d03      	adds	r3, r0, #4
    2718:	011b      	lsls	r3, r3, #4
    271a:	58e2      	ldr	r2, [r4, r3]
    271c:	f042 0202 	orr.w	r2, r2, #2
    2720:	50e2      	str	r2, [r4, r3]
	if (software_trigger) {
    2722:	b129      	cbz	r1, 2730 <_dma_enable_transaction+0x2c>
		hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel);
    2724:	2301      	movs	r3, #1
    2726:	fa03 f000 	lsl.w	r0, r3, r0
	((Dmac *)hw)->SWTRIGCTRL.reg |= mask;
    272a:	6922      	ldr	r2, [r4, #16]
    272c:	4310      	orrs	r0, r2
    272e:	6120      	str	r0, [r4, #16]
}
    2730:	2000      	movs	r0, #0
    2732:	f85d 4b04 	ldr.w	r4, [sp], #4
    2736:	4770      	bx	lr
    2738:	200006e0 	.word	0x200006e0
    273c:	4100a000 	.word	0x4100a000

00002740 <_dma_set_descriptor>:
{
    2740:	b084      	sub	sp, #16
    2742:	b470      	push	{r4, r5, r6}
    2744:	b085      	sub	sp, #20
    2746:	4606      	mov	r6, r0
    2748:	a809      	add	r0, sp, #36	; 0x24
    274a:	e880 000e 	stmia.w	r0, {r1, r2, r3}
    274e:	c80f      	ldmia	r0, {r0, r1, r2, r3}
    2750:	e88d 000f 	stmia.w	sp, {r0, r1, r2, r3}
	_descriptor_section[channel] = descriptor;
    2754:	4d04      	ldr	r5, [pc, #16]	; (2768 <_dma_set_descriptor+0x28>)
    2756:	eb05 1506 	add.w	r5, r5, r6, lsl #4
    275a:	e885 000f 	stmia.w	r5, {r0, r1, r2, r3}
}
    275e:	2000      	movs	r0, #0
    2760:	b005      	add	sp, #20
    2762:	bc70      	pop	{r4, r5, r6}
    2764:	b004      	add	sp, #16
    2766:	4770      	bx	lr
    2768:	200006e0 	.word	0x200006e0

0000276c <_dma_get_channel_resource>:
	*resource = &_resources[channel];
    276c:	4b02      	ldr	r3, [pc, #8]	; (2778 <_dma_get_channel_resource+0xc>)
    276e:	eb03 1101 	add.w	r1, r3, r1, lsl #4
    2772:	6001      	str	r1, [r0, #0]
}
    2774:	2000      	movs	r0, #0
    2776:	4770      	bx	lr
    2778:	20000118 	.word	0x20000118

0000277c <DMAC_0_Handler>:
/**
 * \brief DMAC interrupt handler
 */
void DMAC_0_Handler(void)
{
    277c:	b508      	push	{r3, lr}
	_dmac_handler();
    277e:	4b01      	ldr	r3, [pc, #4]	; (2784 <DMAC_0_Handler+0x8>)
    2780:	4798      	blx	r3
    2782:	bd08      	pop	{r3, pc}
    2784:	00002469 	.word	0x00002469

00002788 <DMAC_1_Handler>:
}
/**
 * \brief DMAC interrupt handler
 */
void DMAC_1_Handler(void)
{
    2788:	b508      	push	{r3, lr}
	_dmac_handler();
    278a:	4b01      	ldr	r3, [pc, #4]	; (2790 <DMAC_1_Handler+0x8>)
    278c:	4798      	blx	r3
    278e:	bd08      	pop	{r3, pc}
    2790:	00002469 	.word	0x00002469

00002794 <DMAC_2_Handler>:
}
/**
 * \brief DMAC interrupt handler
 */
void DMAC_2_Handler(void)
{
    2794:	b508      	push	{r3, lr}
	_dmac_handler();
    2796:	4b01      	ldr	r3, [pc, #4]	; (279c <DMAC_2_Handler+0x8>)
    2798:	4798      	blx	r3
    279a:	bd08      	pop	{r3, pc}
    279c:	00002469 	.word	0x00002469

000027a0 <DMAC_3_Handler>:
}
/**
 * \brief DMAC interrupt handler
 */
void DMAC_3_Handler(void)
{
    27a0:	b508      	push	{r3, lr}
	_dmac_handler();
    27a2:	4b01      	ldr	r3, [pc, #4]	; (27a8 <DMAC_3_Handler+0x8>)
    27a4:	4798      	blx	r3
    27a6:	bd08      	pop	{r3, pc}
    27a8:	00002469 	.word	0x00002469

000027ac <DMAC_4_Handler>:
}
/**
 * \brief DMAC interrupt handler
 */
void DMAC_4_Handler(void)
{
    27ac:	b508      	push	{r3, lr}
	_dmac_handler();
    27ae:	4b01      	ldr	r3, [pc, #4]	; (27b4 <DMAC_4_Handler+0x8>)
    27b0:	4798      	blx	r3
    27b2:	bd08      	pop	{r3, pc}
    27b4:	00002469 	.word	0x00002469

000027b8 <_ext_irq_handler>:

/**
 * \brief Inter EIC interrupt handler
 */
static void _ext_irq_handler(void)
{
    27b8:	b530      	push	{r4, r5, lr}
    27ba:	b083      	sub	sp, #12
	return tmp;
}

static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw)
{
	return ((Eic *)hw)->INTFLAG.reg;
    27bc:	4b27      	ldr	r3, [pc, #156]	; (285c <_ext_irq_handler+0xa4>)
    27be:	695a      	ldr	r2, [r3, #20]
	volatile uint32_t flags = hri_eic_read_INTFLAG_reg(EIC);
    27c0:	9201      	str	r2, [sp, #4]
	int8_t            pos;
	uint32_t          pin = INVALID_PIN_NUMBER;

	hri_eic_clear_INTFLAG_reg(EIC, flags);
    27c2:	9a01      	ldr	r2, [sp, #4]
}

static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
{
	((Eic *)hw)->INTFLAG.reg = mask;
    27c4:	615a      	str	r2, [r3, #20]

	ASSERT(callback);
    27c6:	4b26      	ldr	r3, [pc, #152]	; (2860 <_ext_irq_handler+0xa8>)
    27c8:	6818      	ldr	r0, [r3, #0]
    27ca:	22e8      	movs	r2, #232	; 0xe8
    27cc:	4925      	ldr	r1, [pc, #148]	; (2864 <_ext_irq_handler+0xac>)
    27ce:	3000      	adds	r0, #0
    27d0:	bf18      	it	ne
    27d2:	2001      	movne	r0, #1
    27d4:	4b24      	ldr	r3, [pc, #144]	; (2868 <_ext_irq_handler+0xb0>)
    27d6:	4798      	blx	r3
	uint32_t          pin = INVALID_PIN_NUMBER;
    27d8:	f04f 35ff 	mov.w	r5, #4294967295

	while (flags) {
    27dc:	e030      	b.n	2840 <_ext_irq_handler+0x88>
					break;
				}
				if (_map[middle].extint < pos) {
					lower = middle + 1;
				} else {
					upper = middle - 1;
    27de:	3b01      	subs	r3, #1
    27e0:	b2d8      	uxtb	r0, r3
			while (upper >= lower) {
    27e2:	4281      	cmp	r1, r0
    27e4:	d80c      	bhi.n	2800 <_ext_irq_handler+0x48>
				middle = (upper + lower) >> 1;
    27e6:	1843      	adds	r3, r0, r1
    27e8:	f3c3 0347 	ubfx	r3, r3, #1, #8
				if (_map[middle].extint == pos) {
    27ec:	4a1f      	ldr	r2, [pc, #124]	; (286c <_ext_irq_handler+0xb4>)
    27ee:	f812 2033 	ldrb.w	r2, [r2, r3, lsl #3]
    27f2:	42a2      	cmp	r2, r4
    27f4:	d003      	beq.n	27fe <_ext_irq_handler+0x46>
				if (_map[middle].extint < pos) {
    27f6:	daf2      	bge.n	27de <_ext_irq_handler+0x26>
					lower = middle + 1;
    27f8:	3301      	adds	r3, #1
    27fa:	b2d9      	uxtb	r1, r3
    27fc:	e7f1      	b.n	27e2 <_ext_irq_handler+0x2a>
					pin = _map[middle].pin;
    27fe:	2525      	movs	r5, #37	; 0x25
				}
			}

			if (INVALID_PIN_NUMBER != pin) {
    2800:	f1b5 3fff 	cmp.w	r5, #4294967295
    2804:	d003      	beq.n	280e <_ext_irq_handler+0x56>
				callback(pin);
    2806:	4b16      	ldr	r3, [pc, #88]	; (2860 <_ext_irq_handler+0xa8>)
    2808:	681b      	ldr	r3, [r3, #0]
    280a:	4628      	mov	r0, r5
    280c:	4798      	blx	r3
			}
			flags &= ~(1ul << pos);
    280e:	2301      	movs	r3, #1
    2810:	40a3      	lsls	r3, r4
    2812:	9c01      	ldr	r4, [sp, #4]
    2814:	ea24 0403 	bic.w	r4, r4, r3
    2818:	9401      	str	r4, [sp, #4]
			pos = ffs(flags) - 1;
    281a:	9b01      	ldr	r3, [sp, #4]
    281c:	fa93 f4a3 	rbit	r4, r3
    2820:	fab4 f484 	clz	r4, r4
    2824:	b90b      	cbnz	r3, 282a <_ext_irq_handler+0x72>
    2826:	f04f 34ff 	mov.w	r4, #4294967295
		while (-1 != pos) {
    282a:	f1b4 3fff 	cmp.w	r4, #4294967295
    282e:	d002      	beq.n	2836 <_ext_irq_handler+0x7e>
    2830:	2001      	movs	r0, #1
    2832:	2100      	movs	r1, #0
    2834:	e7d5      	b.n	27e2 <_ext_irq_handler+0x2a>
	return ((Eic *)hw)->INTFLAG.reg;
    2836:	4b09      	ldr	r3, [pc, #36]	; (285c <_ext_irq_handler+0xa4>)
    2838:	695a      	ldr	r2, [r3, #20]
		}
		flags = hri_eic_read_INTFLAG_reg(EIC);
    283a:	9201      	str	r2, [sp, #4]
		hri_eic_clear_INTFLAG_reg(EIC, flags);
    283c:	9a01      	ldr	r2, [sp, #4]
	((Eic *)hw)->INTFLAG.reg = mask;
    283e:	615a      	str	r2, [r3, #20]
	while (flags) {
    2840:	9b01      	ldr	r3, [sp, #4]
    2842:	b14b      	cbz	r3, 2858 <_ext_irq_handler+0xa0>
		pos = ffs(flags) - 1;
    2844:	9b01      	ldr	r3, [sp, #4]
    2846:	fa93 f4a3 	rbit	r4, r3
    284a:	fab4 f484 	clz	r4, r4
    284e:	2b00      	cmp	r3, #0
    2850:	d1eb      	bne.n	282a <_ext_irq_handler+0x72>
    2852:	f04f 34ff 	mov.w	r4, #4294967295
		while (-1 != pos) {
    2856:	e7e8      	b.n	282a <_ext_irq_handler+0x72>
	}
}
    2858:	b003      	add	sp, #12
    285a:	bd30      	pop	{r4, r5, pc}
    285c:	40002800 	.word	0x40002800
    2860:	20000318 	.word	0x20000318
    2864:	00003d8c 	.word	0x00003d8c
    2868:	00001e9d 	.word	0x00001e9d
    286c:	00003d84 	.word	0x00003d84

00002870 <_ext_irq_init>:
	return ((Eic *)hw)->SYNCBUSY.reg & reg;
    2870:	4b2b      	ldr	r3, [pc, #172]	; (2920 <_ext_irq_init+0xb0>)
    2872:	685b      	ldr	r3, [r3, #4]
	if (!hri_eic_is_syncing(EIC, EIC_SYNCBUSY_SWRST)) {
    2874:	f013 0f01 	tst.w	r3, #1
    2878:	d120      	bne.n	28bc <_ext_irq_init+0x4c>
	while (((Eic *)hw)->SYNCBUSY.reg & reg) {
    287a:	4b29      	ldr	r3, [pc, #164]	; (2920 <_ext_irq_init+0xb0>)
    287c:	685b      	ldr	r3, [r3, #4]
    287e:	f013 0f03 	tst.w	r3, #3
    2882:	d1fa      	bne.n	287a <_ext_irq_init+0xa>

static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
{
	uint8_t tmp;
	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
	tmp = ((Eic *)hw)->CTRLA.reg;
    2884:	4b26      	ldr	r3, [pc, #152]	; (2920 <_ext_irq_init+0xb0>)
    2886:	781b      	ldrb	r3, [r3, #0]
		if (hri_eic_get_CTRLA_reg(EIC, EIC_CTRLA_ENABLE)) {
    2888:	f013 0f02 	tst.w	r3, #2
    288c:	d00e      	beq.n	28ac <_ext_irq_init+0x3c>
	((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE;
    288e:	4a24      	ldr	r2, [pc, #144]	; (2920 <_ext_irq_init+0xb0>)
    2890:	7813      	ldrb	r3, [r2, #0]
    2892:	f003 03fd 	and.w	r3, r3, #253	; 0xfd
    2896:	7013      	strb	r3, [r2, #0]
	while (((Eic *)hw)->SYNCBUSY.reg & reg) {
    2898:	4b21      	ldr	r3, [pc, #132]	; (2920 <_ext_irq_init+0xb0>)
    289a:	685b      	ldr	r3, [r3, #4]
    289c:	f013 0f03 	tst.w	r3, #3
    28a0:	d1fa      	bne.n	2898 <_ext_irq_init+0x28>
    28a2:	4b1f      	ldr	r3, [pc, #124]	; (2920 <_ext_irq_init+0xb0>)
    28a4:	685b      	ldr	r3, [r3, #4]
    28a6:	f013 0f02 	tst.w	r3, #2
    28aa:	d1fa      	bne.n	28a2 <_ext_irq_init+0x32>
}

static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data)
{
	EIC_CRITICAL_SECTION_ENTER();
	((Eic *)hw)->CTRLA.reg = data;
    28ac:	2201      	movs	r2, #1
    28ae:	4b1c      	ldr	r3, [pc, #112]	; (2920 <_ext_irq_init+0xb0>)
    28b0:	701a      	strb	r2, [r3, #0]
	while (((Eic *)hw)->SYNCBUSY.reg & reg) {
    28b2:	4b1b      	ldr	r3, [pc, #108]	; (2920 <_ext_irq_init+0xb0>)
    28b4:	685b      	ldr	r3, [r3, #4]
    28b6:	f013 0f03 	tst.w	r3, #3
    28ba:	d1fa      	bne.n	28b2 <_ext_irq_init+0x42>
    28bc:	4b18      	ldr	r3, [pc, #96]	; (2920 <_ext_irq_init+0xb0>)
    28be:	685b      	ldr	r3, [r3, #4]
    28c0:	f013 0f01 	tst.w	r3, #1
    28c4:	d1fa      	bne.n	28bc <_ext_irq_init+0x4c>
	tmp = ((Eic *)hw)->CTRLA.reg;
    28c6:	4a16      	ldr	r2, [pc, #88]	; (2920 <_ext_irq_init+0xb0>)
    28c8:	7813      	ldrb	r3, [r2, #0]
	tmp &= ~EIC_CTRLA_CKSEL;
    28ca:	f003 03ef 	and.w	r3, r3, #239	; 0xef
	((Eic *)hw)->CTRLA.reg = tmp;
    28ce:	7013      	strb	r3, [r2, #0]
	while (((Eic *)hw)->SYNCBUSY.reg & reg) {
    28d0:	4b13      	ldr	r3, [pc, #76]	; (2920 <_ext_irq_init+0xb0>)
    28d2:	685b      	ldr	r3, [r3, #4]
    28d4:	f013 0f03 	tst.w	r3, #3
    28d8:	d1fa      	bne.n	28d0 <_ext_irq_init+0x60>
}

static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data)
{
	EIC_CRITICAL_SECTION_ENTER();
	((Eic *)hw)->NMICTRL.reg = data;
    28da:	4b11      	ldr	r3, [pc, #68]	; (2920 <_ext_irq_init+0xb0>)
    28dc:	2200      	movs	r2, #0
    28de:	705a      	strb	r2, [r3, #1]
}

static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data)
{
	EIC_CRITICAL_SECTION_ENTER();
	((Eic *)hw)->EVCTRL.reg = data;
    28e0:	609a      	str	r2, [r3, #8]
}

static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data)
{
	EIC_CRITICAL_SECTION_ENTER();
	((Eic *)hw)->ASYNCH.reg = data;
    28e2:	619a      	str	r2, [r3, #24]
}

static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data)
{
	EIC_CRITICAL_SECTION_ENTER();
	((Eic *)hw)->DEBOUNCEN.reg = data;
    28e4:	631a      	str	r2, [r3, #48]	; 0x30
}

static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data)
{
	EIC_CRITICAL_SECTION_ENTER();
	((Eic *)hw)->DPRESCALER.reg = data;
    28e6:	635a      	str	r2, [r3, #52]	; 0x34
	((Eic *)hw)->CONFIG[index].reg = data;
    28e8:	490e      	ldr	r1, [pc, #56]	; (2924 <_ext_irq_init+0xb4>)
    28ea:	61d9      	str	r1, [r3, #28]
    28ec:	621a      	str	r2, [r3, #32]
	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE;
    28ee:	781a      	ldrb	r2, [r3, #0]
    28f0:	f042 0202 	orr.w	r2, r2, #2
    28f4:	701a      	strb	r2, [r3, #0]
	while (((Eic *)hw)->SYNCBUSY.reg & reg) {
    28f6:	4b0a      	ldr	r3, [pc, #40]	; (2920 <_ext_irq_init+0xb0>)
    28f8:	685b      	ldr	r3, [r3, #4]
    28fa:	f013 0f03 	tst.w	r3, #3
    28fe:	d1fa      	bne.n	28f6 <_ext_irq_init+0x86>
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2900:	4b09      	ldr	r3, [pc, #36]	; (2928 <_ext_irq_init+0xb8>)
    2902:	f44f 3200 	mov.w	r2, #131072	; 0x20000
    2906:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
  __ASM volatile ("dsb 0xF":::"memory");
    290a:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    290e:	f3bf 8f6f 	isb	sy
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2912:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2916:	601a      	str	r2, [r3, #0]
	callback = cb;
    2918:	4b04      	ldr	r3, [pc, #16]	; (292c <_ext_irq_init+0xbc>)
    291a:	6018      	str	r0, [r3, #0]
}
    291c:	2000      	movs	r0, #0
    291e:	4770      	bx	lr
    2920:	40002800 	.word	0x40002800
    2924:	00100001 	.word	0x00100001
    2928:	e000e100 	.word	0xe000e100
    292c:	20000318 	.word	0x20000318

00002930 <_ext_irq_enable>:
	uint8_t i      = 0;
    2930:	2300      	movs	r3, #0
	for (; i < ARRAY_SIZE(_map); i++) {
    2932:	b153      	cbz	r3, 294a <_ext_irq_enable+0x1a>
	uint8_t extint = INVALID_EXTINT_NUMBER;
    2934:	22ff      	movs	r2, #255	; 0xff
	if (INVALID_EXTINT_NUMBER == extint) {
    2936:	2aff      	cmp	r2, #255	; 0xff
    2938:	d017      	beq.n	296a <_ext_irq_enable+0x3a>
	if (enable) {
    293a:	b981      	cbnz	r1, 295e <_ext_irq_enable+0x2e>
		hri_eic_clear_INTEN_reg(EIC, 1ul << extint);
    293c:	2301      	movs	r3, #1
    293e:	4093      	lsls	r3, r2
	((Eic *)hw)->INTENCLR.reg = mask;
    2940:	4a0b      	ldr	r2, [pc, #44]	; (2970 <_ext_irq_enable+0x40>)
    2942:	60d3      	str	r3, [r2, #12]
	((Eic *)hw)->INTFLAG.reg = mask;
    2944:	6153      	str	r3, [r2, #20]
	return ERR_NONE;
    2946:	2000      	movs	r0, #0
    2948:	4770      	bx	lr
		if (_map[i].pin == pin) {
    294a:	461a      	mov	r2, r3
    294c:	2825      	cmp	r0, #37	; 0x25
    294e:	d002      	beq.n	2956 <_ext_irq_enable+0x26>
	for (; i < ARRAY_SIZE(_map); i++) {
    2950:	3301      	adds	r3, #1
    2952:	b2db      	uxtb	r3, r3
    2954:	e7ed      	b.n	2932 <_ext_irq_enable+0x2>
			extint = _map[i].extint;
    2956:	4b07      	ldr	r3, [pc, #28]	; (2974 <_ext_irq_enable+0x44>)
    2958:	f813 2032 	ldrb.w	r2, [r3, r2, lsl #3]
			break;
    295c:	e7eb      	b.n	2936 <_ext_irq_enable+0x6>
		hri_eic_set_INTEN_reg(EIC, 1ul << extint);
    295e:	2301      	movs	r3, #1
    2960:	4093      	lsls	r3, r2
	((Eic *)hw)->INTENSET.reg = mask;
    2962:	4a03      	ldr	r2, [pc, #12]	; (2970 <_ext_irq_enable+0x40>)
    2964:	6113      	str	r3, [r2, #16]
	return ERR_NONE;
    2966:	2000      	movs	r0, #0
    2968:	4770      	bx	lr
		return -1;
    296a:	f04f 30ff 	mov.w	r0, #4294967295
}
    296e:	4770      	bx	lr
    2970:	40002800 	.word	0x40002800
    2974:	00003d84 	.word	0x00003d84

00002978 <EIC_5_Handler>:

/**
 * \brief EIC interrupt handler
 */
void EIC_5_Handler(void)
{
    2978:	b508      	push	{r3, lr}
	_ext_irq_handler();
    297a:	4b01      	ldr	r3, [pc, #4]	; (2980 <EIC_5_Handler+0x8>)
    297c:	4798      	blx	r3
    297e:	bd08      	pop	{r3, pc}
    2980:	000027b9 	.word	0x000027b9

00002984 <_event_system_init>:
 */
int32_t _event_system_init(void)
{
	uint8_t i;
	/* configure user multiplexers */
	for (i = 0; i < EVSYS_USERS; i++) {
    2984:	2300      	movs	r3, #0
    2986:	e008      	b.n	299a <_event_system_init+0x16>
		hri_evsys_write_USER_reg(EVSYS, i, user_mux_confs[i]);
    2988:	4a15      	ldr	r2, [pc, #84]	; (29e0 <_event_system_init+0x5c>)
    298a:	5cd0      	ldrb	r0, [r2, r3]
}

static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data)
{
	EVSYS_CRITICAL_SECTION_ENTER();
	((Evsys *)hw)->USER[index].reg = data;
    298c:	f103 0148 	add.w	r1, r3, #72	; 0x48
    2990:	4a14      	ldr	r2, [pc, #80]	; (29e4 <_event_system_init+0x60>)
    2992:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
	for (i = 0; i < EVSYS_USERS; i++) {
    2996:	3301      	adds	r3, #1
    2998:	b2db      	uxtb	r3, r3
    299a:	2b42      	cmp	r3, #66	; 0x42
    299c:	d9f4      	bls.n	2988 <_event_system_init+0x4>
    299e:	2300      	movs	r3, #0
	}

	/* configure channels */
	for (i = 0; i < EVSYS_CHANNELS; i++) {
    29a0:	2b1f      	cmp	r3, #31
    29a2:	d81b      	bhi.n	29dc <_event_system_init+0x58>
{
    29a4:	b410      	push	{r4}
		hri_evsys_write_CHANNEL_reg(EVSYS, i, channel_confs[i]);
    29a6:	4a0e      	ldr	r2, [pc, #56]	; (29e0 <_event_system_init+0x5c>)
    29a8:	eb02 0143 	add.w	r1, r2, r3, lsl #1
    29ac:	f8b1 4044 	ldrh.w	r4, [r1, #68]	; 0x44

static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
                                               hri_evsys_channel_reg_t data)
{
	EVSYS_CRITICAL_SECTION_ENTER();
	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = data;
    29b0:	490c      	ldr	r1, [pc, #48]	; (29e4 <_event_system_init+0x60>)
    29b2:	1d18      	adds	r0, r3, #4
    29b4:	f841 4030 	str.w	r4, [r1, r0, lsl #3]
		hri_evsys_write_CHINTEN_reg(EVSYS, i, interrupt_cfg[i]);
    29b8:	eb02 0283 	add.w	r2, r2, r3, lsl #2
    29bc:	f892 2084 	ldrb.w	r2, [r2, #132]	; 0x84
	((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = data;
    29c0:	eb01 01c0 	add.w	r1, r1, r0, lsl #3
    29c4:	714a      	strb	r2, [r1, #5]
	((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data;
    29c6:	43d2      	mvns	r2, r2
    29c8:	b2d2      	uxtb	r2, r2
    29ca:	710a      	strb	r2, [r1, #4]
	for (i = 0; i < EVSYS_CHANNELS; i++) {
    29cc:	3301      	adds	r3, #1
    29ce:	b2db      	uxtb	r3, r3
    29d0:	2b1f      	cmp	r3, #31
    29d2:	d9e8      	bls.n	29a6 <_event_system_init+0x22>
	}

	return ERR_NONE;
}
    29d4:	2000      	movs	r0, #0
    29d6:	f85d 4b04 	ldr.w	r4, [sp], #4
    29da:	4770      	bx	lr
    29dc:	2000      	movs	r0, #0
    29de:	4770      	bx	lr
    29e0:	00003da4 	.word	0x00003da4
    29e4:	4100e000 	.word	0x4100e000

000029e8 <_gclk_init_generators_by_fref>:

void _gclk_init_generators_by_fref(uint32_t bm)
{

#if CONF_GCLK_GENERATOR_0_CONFIG == 1
	if (bm & (1ul << 0)) {
    29e8:	f010 0f01 	tst.w	r0, #1
    29ec:	d008      	beq.n	2a00 <_gclk_init_generators_by_fref+0x18>
	((Gclk *)hw)->GENCTRL[index].reg = data;
    29ee:	4a11      	ldr	r2, [pc, #68]	; (2a34 <_gclk_init_generators_by_fref+0x4c>)
    29f0:	4b11      	ldr	r3, [pc, #68]	; (2a38 <_gclk_init_generators_by_fref+0x50>)
    29f2:	621a      	str	r2, [r3, #32]
	while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
    29f4:	4b10      	ldr	r3, [pc, #64]	; (2a38 <_gclk_init_generators_by_fref+0x50>)
    29f6:	685a      	ldr	r2, [r3, #4]
    29f8:	f643 73fd 	movw	r3, #16381	; 0x3ffd
    29fc:	421a      	tst	r2, r3
    29fe:	d1f9      	bne.n	29f4 <_gclk_init_generators_by_fref+0xc>
		        | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE);
	}
#endif

#if CONF_GCLK_GENERATOR_1_CONFIG == 1
	if (bm & (1ul << 1)) {
    2a00:	f010 0f02 	tst.w	r0, #2
    2a04:	d008      	beq.n	2a18 <_gclk_init_generators_by_fref+0x30>
	((Gclk *)hw)->GENCTRL[index].reg = data;
    2a06:	4a0d      	ldr	r2, [pc, #52]	; (2a3c <_gclk_init_generators_by_fref+0x54>)
    2a08:	4b0b      	ldr	r3, [pc, #44]	; (2a38 <_gclk_init_generators_by_fref+0x50>)
    2a0a:	625a      	str	r2, [r3, #36]	; 0x24
	while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
    2a0c:	4b0a      	ldr	r3, [pc, #40]	; (2a38 <_gclk_init_generators_by_fref+0x50>)
    2a0e:	685a      	ldr	r2, [r3, #4]
    2a10:	f643 73fd 	movw	r3, #16381	; 0x3ffd
    2a14:	421a      	tst	r2, r3
    2a16:	d1f9      	bne.n	2a0c <_gclk_init_generators_by_fref+0x24>
		        | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE);
	}
#endif

#if CONF_GCLK_GENERATOR_2_CONFIG == 1
	if (bm & (1ul << 2)) {
    2a18:	f010 0f04 	tst.w	r0, #4
    2a1c:	d008      	beq.n	2a30 <_gclk_init_generators_by_fref+0x48>
	((Gclk *)hw)->GENCTRL[index].reg = data;
    2a1e:	4a08      	ldr	r2, [pc, #32]	; (2a40 <_gclk_init_generators_by_fref+0x58>)
    2a20:	4b05      	ldr	r3, [pc, #20]	; (2a38 <_gclk_init_generators_by_fref+0x50>)
    2a22:	629a      	str	r2, [r3, #40]	; 0x28
	while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
    2a24:	4b04      	ldr	r3, [pc, #16]	; (2a38 <_gclk_init_generators_by_fref+0x50>)
    2a26:	685a      	ldr	r2, [r3, #4]
    2a28:	f643 73fd 	movw	r3, #16381	; 0x3ffd
    2a2c:	421a      	tst	r2, r3
    2a2e:	d1f9      	bne.n	2a24 <_gclk_init_generators_by_fref+0x3c>
    2a30:	4770      	bx	lr
    2a32:	bf00      	nop
    2a34:	00010108 	.word	0x00010108
    2a38:	40001c00 	.word	0x40001c00
    2a3c:	00180906 	.word	0x00180906
    2a40:	00010104 	.word	0x00010104

00002a44 <_mclk_init>:
	((Mclk *)hw)->CPUDIV.reg = data;
    2a44:	2201      	movs	r2, #1
    2a46:	4b01      	ldr	r3, [pc, #4]	; (2a4c <_mclk_init+0x8>)
    2a48:	715a      	strb	r2, [r3, #5]
    2a4a:	4770      	bx	lr
    2a4c:	40000800 	.word	0x40000800

00002a50 <_osc32kctrl_init_sources>:
}

static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
{
	uint32_t tmp;
	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
    2a50:	4b03      	ldr	r3, [pc, #12]	; (2a60 <_osc32kctrl_init_sources+0x10>)
    2a52:	69da      	ldr	r2, [r3, #28]
	calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw);
	hri_osc32kctrl_write_OSCULP32K_reg(hw,
#if CONF_OSCULP32K_CALIB_ENABLE == 1
	                                   OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB)
#else
	                                   OSC32KCTRL_OSCULP32K_CALIB(calib)
    2a54:	f402 527c 	and.w	r2, r2, #16128	; 0x3f00
}

static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
{
	OSC32KCTRL_CRITICAL_SECTION_ENTER();
	((Osc32kctrl *)hw)->OSCULP32K.reg = data;
    2a58:	61da      	str	r2, [r3, #28]
	((Osc32kctrl *)hw)->RTCCTRL.reg = data;
    2a5a:	2201      	movs	r2, #1
    2a5c:	741a      	strb	r2, [r3, #16]
    2a5e:	4770      	bx	lr
    2a60:	40001400 	.word	0x40001400

00002a64 <_oscctrl_init_sources>:

/**
 * \brief Initialize clock sources
 */
void _oscctrl_init_sources(void)
{
    2a64:	4770      	bx	lr
	...

00002a68 <_oscctrl_init_referenced_generators>:
	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
    2a68:	4a47      	ldr	r2, [pc, #284]	; (2b88 <_oscctrl_init_referenced_generators+0x120>)
    2a6a:	6a13      	ldr	r3, [r2, #32]
	tmp &= ~GCLK_GENCTRL_SRC_Msk;
    2a6c:	f023 030f 	bic.w	r3, r3, #15
	tmp |= GCLK_GENCTRL_SRC(data);
    2a70:	f043 0304 	orr.w	r3, r3, #4
	((Gclk *)hw)->GENCTRL[index].reg = tmp;
    2a74:	6213      	str	r3, [r2, #32]
	while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
    2a76:	4b44      	ldr	r3, [pc, #272]	; (2b88 <_oscctrl_init_referenced_generators+0x120>)
    2a78:	685a      	ldr	r2, [r3, #4]
    2a7a:	f643 73fd 	movw	r3, #16381	; 0x3ffd
    2a7e:	421a      	tst	r2, r3
    2a80:	d1f9      	bne.n	2a76 <_oscctrl_init_referenced_generators+0xe>
	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos;
    2a82:	4b41      	ldr	r3, [pc, #260]	; (2b88 <_oscctrl_init_referenced_generators+0x120>)
    2a84:	685b      	ldr	r3, [r3, #4]
{
	void *hw = (void *)OSCCTRL;

#if CONF_DFLL_CONFIG == 1
	hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, GCLK_GENCTRL_SRC_OSCULP32K);
	while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK))
    2a86:	f013 0f04 	tst.w	r3, #4
    2a8a:	d1fa      	bne.n	2a82 <_oscctrl_init_referenced_generators+0x1a>
}

static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data)
{
	OSCCTRL_CRITICAL_SECTION_ENTER();
	((Oscctrl *)hw)->DFLLCTRLA.reg = data;
    2a8c:	4b3f      	ldr	r3, [pc, #252]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2a8e:	2200      	movs	r2, #0
    2a90:	771a      	strb	r2, [r3, #28]
}

static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
{
	OSCCTRL_CRITICAL_SECTION_ENTER();
	((Oscctrl *)hw)->DFLLMUL.reg = data;
    2a92:	4a3f      	ldr	r2, [pc, #252]	; (2b90 <_oscctrl_init_referenced_generators+0x128>)
    2a94:	629a      	str	r2, [r3, #40]	; 0x28
}

static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw)
{
	uint8_t tmp;
	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
    2a96:	4b3d      	ldr	r3, [pc, #244]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2a98:	f893 302c 	ldrb.w	r3, [r3, #44]	; 0x2c
#endif

	hri_oscctrl_write_DFLLMUL_reg(hw,
	                              OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP)
	                                  | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL));
	while (hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(hw))
    2a9c:	f013 0f10 	tst.w	r3, #16
    2aa0:	d1f9      	bne.n	2a96 <_oscctrl_init_referenced_generators+0x2e>
	((Oscctrl *)hw)->DFLLCTRLB.reg = data;
    2aa2:	2200      	movs	r2, #0
    2aa4:	4b39      	ldr	r3, [pc, #228]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2aa6:	f883 2020 	strb.w	r2, [r3, #32]
	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
    2aaa:	4b38      	ldr	r3, [pc, #224]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2aac:	f893 302c 	ldrb.w	r3, [r3, #44]	; 0x2c
		;

	hri_oscctrl_write_DFLLCTRLB_reg(hw, 0);
	while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw))
    2ab0:	f013 0f04 	tst.w	r3, #4
    2ab4:	d1f9      	bne.n	2aaa <_oscctrl_init_referenced_generators+0x42>
	((Oscctrl *)hw)->DFLLCTRLA.reg = data;
    2ab6:	2202      	movs	r2, #2
    2ab8:	4b34      	ldr	r3, [pc, #208]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2aba:	771a      	strb	r2, [r3, #28]
	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
    2abc:	4b33      	ldr	r3, [pc, #204]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2abe:	f893 302c 	ldrb.w	r3, [r3, #44]	; 0x2c
		;

	tmp = (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) | OSCCTRL_DFLLCTRLA_ENABLE;
	hri_oscctrl_write_DFLLCTRLA_reg(hw, tmp);
	while (hri_oscctrl_get_DFLLSYNC_ENABLE_bit(hw))
    2ac2:	f013 0f02 	tst.w	r3, #2
    2ac6:	d1f9      	bne.n	2abc <_oscctrl_init_referenced_generators+0x54>
	return ((Oscctrl *)hw)->DFLLVAL.reg;
    2ac8:	4b30      	ldr	r3, [pc, #192]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2aca:	6a5a      	ldr	r2, [r3, #36]	; 0x24
	((Oscctrl *)hw)->DFLLVAL.reg = data;
    2acc:	625a      	str	r2, [r3, #36]	; 0x24
	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
    2ace:	4b2f      	ldr	r3, [pc, #188]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2ad0:	f893 302c 	ldrb.w	r3, [r3, #44]	; 0x2c

#if CONF_DFLL_OVERWRITE_CALIBRATION == 1
	hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE));
#endif
	hri_oscctrl_write_DFLLVAL_reg(hw, hri_oscctrl_read_DFLLVAL_reg(hw));
	while (hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(hw))
    2ad4:	f013 0f08 	tst.w	r3, #8
    2ad8:	d1f9      	bne.n	2ace <_oscctrl_init_referenced_generators+0x66>
	((Oscctrl *)hw)->DFLLCTRLB.reg = data;
    2ada:	2280      	movs	r2, #128	; 0x80
    2adc:	4b2b      	ldr	r3, [pc, #172]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2ade:	f883 2020 	strb.w	r2, [r3, #32]
	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
    2ae2:	4b2a      	ldr	r3, [pc, #168]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2ae4:	f893 302c 	ldrb.w	r3, [r3, #44]	; 0x2c
	tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRLB_BPLCKC_Pos)
	      | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRLB_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRLB_CCDIS_Pos)
	      | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRLB_USBCRM_Pos) | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRLB_LLAW_Pos)
	      | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRLB_STABLE_Pos) | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRLB_MODE_Pos) | 0;
	hri_oscctrl_write_DFLLCTRLB_reg(hw, tmp);
	while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw))
    2ae8:	f013 0f04 	tst.w	r3, #4
    2aec:	d1f9      	bne.n	2ae2 <_oscctrl_init_referenced_generators+0x7a>
	((Gclk *)hw)->PCHCTRL[index].reg = data;
    2aee:	2241      	movs	r2, #65	; 0x41
    2af0:	4b25      	ldr	r3, [pc, #148]	; (2b88 <_oscctrl_init_referenced_generators+0x120>)
    2af2:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data;
    2af6:	2231      	movs	r2, #49	; 0x31
    2af8:	f5a3 6340 	sub.w	r3, r3, #3072	; 0xc00
    2afc:	649a      	str	r2, [r3, #72]	; 0x48
	while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) {
    2afe:	4b23      	ldr	r3, [pc, #140]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2b00:	6d1b      	ldr	r3, [r3, #80]	; 0x50
    2b02:	f013 0f06 	tst.w	r3, #6
    2b06:	d1fa      	bne.n	2afe <_oscctrl_init_referenced_generators+0x96>
	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data;
    2b08:	4b20      	ldr	r3, [pc, #128]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2b0a:	2200      	movs	r2, #0
    2b0c:	64da      	str	r2, [r3, #76]	; 0x4c
	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data;
    2b0e:	2202      	movs	r2, #2
    2b10:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
	while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) {
    2b14:	4b1d      	ldr	r3, [pc, #116]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2b16:	6d1b      	ldr	r3, [r3, #80]	; 0x50
    2b18:	f013 0f02 	tst.w	r3, #2
    2b1c:	d1fa      	bne.n	2b14 <_oscctrl_init_referenced_generators+0xac>
	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
    2b1e:	4b1b      	ldr	r3, [pc, #108]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2b20:	f893 3020 	ldrb.w	r3, [r3, #32]
	                                (CONF_FDPLL1_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
	                                    | (CONF_FDPLL1_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos));
#endif

#if CONF_DFLL_CONFIG == 1
	if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(hw)) {
    2b24:	f013 0f01 	tst.w	r3, #1
    2b28:	d027      	beq.n	2b7a <_oscctrl_init_referenced_generators+0x112>
	tmp = ((Oscctrl *)hw)->STATUS.reg;
    2b2a:	4b18      	ldr	r3, [pc, #96]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2b2c:	691b      	ldr	r3, [r3, #16]
	tmp &= mask;
    2b2e:	f403 6310 	and.w	r3, r3, #2304	; 0x900
		hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC;

		while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask)
    2b32:	f5b3 6f10 	cmp.w	r3, #2304	; 0x900
    2b36:	d1f8      	bne.n	2b2a <_oscctrl_init_referenced_generators+0xc2>
	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK)
    2b38:	4b14      	ldr	r3, [pc, #80]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2b3a:	6d5b      	ldr	r3, [r3, #84]	; 0x54
#endif
#endif

#if CONF_FDPLL1_CONFIG == 1
#if CONF_FDPLL1_ENABLE == 1
	while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 1) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 1)))
    2b3c:	f013 0f01 	tst.w	r3, #1
    2b40:	d104      	bne.n	2b4c <_oscctrl_init_referenced_generators+0xe4>
	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY)
    2b42:	4b12      	ldr	r3, [pc, #72]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2b44:	6d5b      	ldr	r3, [r3, #84]	; 0x54
    2b46:	f013 0f02 	tst.w	r3, #2
    2b4a:	d0f5      	beq.n	2b38 <_oscctrl_init_referenced_generators+0xd0>
	return ((Gclk *)hw)->SYNCBUSY.reg;
    2b4c:	4b0e      	ldr	r3, [pc, #56]	; (2b88 <_oscctrl_init_referenced_generators+0x120>)
    2b4e:	685b      	ldr	r3, [r3, #4]
	hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 1);
#endif
#endif

#if CONF_DFLL_CONFIG == 1
	while (hri_gclk_read_SYNCBUSY_reg(GCLK))
    2b50:	2b00      	cmp	r3, #0
    2b52:	d1fb      	bne.n	2b4c <_oscctrl_init_referenced_generators+0xe4>
	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
    2b54:	4a0c      	ldr	r2, [pc, #48]	; (2b88 <_oscctrl_init_referenced_generators+0x120>)
    2b56:	6a13      	ldr	r3, [r2, #32]
	tmp &= ~GCLK_GENCTRL_SRC_Msk;
    2b58:	f023 030f 	bic.w	r3, r3, #15
	tmp |= GCLK_GENCTRL_SRC(data);
    2b5c:	f043 0308 	orr.w	r3, r3, #8
	((Gclk *)hw)->GENCTRL[index].reg = tmp;
    2b60:	6213      	str	r3, [r2, #32]
	while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
    2b62:	4b09      	ldr	r3, [pc, #36]	; (2b88 <_oscctrl_init_referenced_generators+0x120>)
    2b64:	685a      	ldr	r2, [r3, #4]
    2b66:	f643 73fd 	movw	r3, #16381	; 0x3ffd
    2b6a:	421a      	tst	r2, r3
    2b6c:	d1f9      	bne.n	2b62 <_oscctrl_init_referenced_generators+0xfa>
	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos;
    2b6e:	4b06      	ldr	r3, [pc, #24]	; (2b88 <_oscctrl_init_referenced_generators+0x120>)
    2b70:	685b      	ldr	r3, [r3, #4]
		;
	hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE);
	while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK))
    2b72:	f013 0f04 	tst.w	r3, #4
    2b76:	d1fa      	bne.n	2b6e <_oscctrl_init_referenced_generators+0x106>
		;
#endif
	(void)hw;
}
    2b78:	4770      	bx	lr
	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos;
    2b7a:	4b04      	ldr	r3, [pc, #16]	; (2b8c <_oscctrl_init_referenced_generators+0x124>)
    2b7c:	691b      	ldr	r3, [r3, #16]
		while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw))
    2b7e:	f413 7f80 	tst.w	r3, #256	; 0x100
    2b82:	d0fa      	beq.n	2b7a <_oscctrl_init_referenced_generators+0x112>
    2b84:	e7d8      	b.n	2b38 <_oscctrl_init_referenced_generators+0xd0>
    2b86:	bf00      	nop
    2b88:	40001c00 	.word	0x40001c00
    2b8c:	40001000 	.word	0x40001000
    2b90:	04010000 	.word	0x04010000

00002b94 <_pdec_init>:
 * \param[in] hw The pointer to hardware instance
 *
 * \return Initialization status
 */
static int32_t _pdec_init(void *const hw)
{
    2b94:	b510      	push	{r4, lr}
	ASSERT(hw);
    2b96:	4604      	mov	r4, r0
    2b98:	224f      	movs	r2, #79	; 0x4f
    2b9a:	4923      	ldr	r1, [pc, #140]	; (2c28 <_pdec_init+0x94>)
    2b9c:	3000      	adds	r0, #0
    2b9e:	bf18      	it	ne
    2ba0:	2001      	movne	r0, #1
    2ba2:	4b22      	ldr	r3, [pc, #136]	; (2c2c <_pdec_init+0x98>)
    2ba4:	4798      	blx	r3
	};
}

static inline bool hri_pdec_is_syncing(const void *const hw, hri_pdec_syncbusy_reg_t reg)
{
	return ((Pdec *)hw)->SYNCBUSY.reg & reg;
    2ba6:	6923      	ldr	r3, [r4, #16]

	if (!hri_pdec_is_syncing(hw, PDEC_SYNCBUSY_SWRST)) {
    2ba8:	f013 0f01 	tst.w	r3, #1
    2bac:	d119      	bne.n	2be2 <_pdec_init+0x4e>
	while (((Pdec *)hw)->SYNCBUSY.reg & reg) {
    2bae:	6923      	ldr	r3, [r4, #16]
    2bb0:	f013 0f03 	tst.w	r3, #3
    2bb4:	d1fb      	bne.n	2bae <_pdec_init+0x1a>

static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask)
{
	uint32_t tmp;
	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
	tmp = ((Pdec *)hw)->CTRLA.reg;
    2bb6:	6823      	ldr	r3, [r4, #0]
		if (hri_pdec_get_CTRLA_reg(hw, PDEC_CTRLA_ENABLE)) {
    2bb8:	f013 0f02 	tst.w	r3, #2
    2bbc:	d00b      	beq.n	2bd6 <_pdec_init+0x42>
	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ENABLE;
    2bbe:	6823      	ldr	r3, [r4, #0]
    2bc0:	f023 0302 	bic.w	r3, r3, #2
    2bc4:	6023      	str	r3, [r4, #0]
	while (((Pdec *)hw)->SYNCBUSY.reg & reg) {
    2bc6:	6923      	ldr	r3, [r4, #16]
    2bc8:	f013 0f03 	tst.w	r3, #3
    2bcc:	d1fb      	bne.n	2bc6 <_pdec_init+0x32>
    2bce:	6923      	ldr	r3, [r4, #16]
    2bd0:	f013 0f02 	tst.w	r3, #2
    2bd4:	d1fb      	bne.n	2bce <_pdec_init+0x3a>
}

static inline void hri_pdec_write_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t data)
{
	PDEC_CRITICAL_SECTION_ENTER();
	((Pdec *)hw)->CTRLA.reg = data;
    2bd6:	2301      	movs	r3, #1
    2bd8:	6023      	str	r3, [r4, #0]
	while (((Pdec *)hw)->SYNCBUSY.reg & reg) {
    2bda:	6923      	ldr	r3, [r4, #16]
    2bdc:	f013 0f03 	tst.w	r3, #3
    2be0:	d1fb      	bne.n	2bda <_pdec_init+0x46>
    2be2:	6923      	ldr	r3, [r4, #16]
    2be4:	f013 0f01 	tst.w	r3, #1
    2be8:	d1fb      	bne.n	2be2 <_pdec_init+0x4e>
}

static inline void hri_pdec_write_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t data)
{
	PDEC_CRITICAL_SECTION_ENTER();
	((Pdec *)hw)->FILTER.reg = data;
    2bea:	2300      	movs	r3, #0
    2bec:	7563      	strb	r3, [r4, #21]
	while (((Pdec *)hw)->SYNCBUSY.reg & reg) {
    2bee:	6923      	ldr	r3, [r4, #16]
    2bf0:	f013 0f20 	tst.w	r3, #32
    2bf4:	d1fb      	bne.n	2bee <_pdec_init+0x5a>
	((Pdec *)hw)->DBGCTRL.reg = data;
    2bf6:	2300      	movs	r3, #0
    2bf8:	73e3      	strb	r3, [r4, #15]
	((Pdec *)hw)->PRESC.reg = data;
    2bfa:	7523      	strb	r3, [r4, #20]
	while (((Pdec *)hw)->SYNCBUSY.reg & reg) {
    2bfc:	6923      	ldr	r3, [r4, #16]
    2bfe:	f013 0f10 	tst.w	r3, #16
    2c02:	d1fb      	bne.n	2bfc <_pdec_init+0x68>
	((Pdec *)hw)->EVCTRL.reg = data;
    2c04:	2300      	movs	r3, #0
    2c06:	80e3      	strh	r3, [r4, #6]
}

static inline void hri_pdec_write_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data)
{
	PDEC_CRITICAL_SECTION_ENTER();
	((Pdec *)hw)->CC[index].reg = data;
    2c08:	f64f 73ff 	movw	r3, #65535	; 0xffff
    2c0c:	6223      	str	r3, [r4, #32]
	while (((Pdec *)hw)->SYNCBUSY.reg & reg) {
    2c0e:	6923      	ldr	r3, [r4, #16]
    2c10:	f413 7fc0 	tst.w	r3, #384	; 0x180
    2c14:	d1fb      	bne.n	2c0e <_pdec_init+0x7a>
	((Pdec *)hw)->CTRLA.reg = data;
    2c16:	4b06      	ldr	r3, [pc, #24]	; (2c30 <_pdec_init+0x9c>)
    2c18:	6023      	str	r3, [r4, #0]
	while (((Pdec *)hw)->SYNCBUSY.reg & reg) {
    2c1a:	6923      	ldr	r3, [r4, #16]
    2c1c:	f013 0f03 	tst.w	r3, #3
    2c20:	d1fb      	bne.n	2c1a <_pdec_init+0x86>
	hri_pdec_write_EVCTRL_reg(hw, _pdecs.evctrl);
	hri_pdec_write_CC_reg(hw, 0, 0xffff);
	hri_pdec_write_CTRLA_reg(hw, _pdecs.ctrl_a);

	return ERR_NONE;
}
    2c22:	2000      	movs	r0, #0
    2c24:	bd10      	pop	{r4, pc}
    2c26:	bf00      	nop
    2c28:	00003ea8 	.word	0x00003ea8
    2c2c:	00001e9d 	.word	0x00001e9d
    2c30:	07078400 	.word	0x07078400

00002c34 <_pdec_async_init>:

/**
 * \brief Initialize PDEC
 */
int32_t _pdec_async_init(struct _pdec_async_device *const device, void *const hw)
{
    2c34:	b538      	push	{r3, r4, r5, lr}
    2c36:	460c      	mov	r4, r1
	int32_t init_status;

	ASSERT(device);
    2c38:	4605      	mov	r5, r0
    2c3a:	226b      	movs	r2, #107	; 0x6b
    2c3c:	490d      	ldr	r1, [pc, #52]	; (2c74 <_pdec_async_init+0x40>)
    2c3e:	3000      	adds	r0, #0
    2c40:	bf18      	it	ne
    2c42:	2001      	movne	r0, #1
    2c44:	4b0c      	ldr	r3, [pc, #48]	; (2c78 <_pdec_async_init+0x44>)
    2c46:	4798      	blx	r3

	init_status = _pdec_init(hw);
    2c48:	4620      	mov	r0, r4
    2c4a:	4b0c      	ldr	r3, [pc, #48]	; (2c7c <_pdec_async_init+0x48>)
    2c4c:	4798      	blx	r3
	if (init_status) {
    2c4e:	4601      	mov	r1, r0
    2c50:	b970      	cbnz	r0, 2c70 <_pdec_async_init+0x3c>
		return init_status;
	}
	device->hw = hw;
    2c52:	612c      	str	r4, [r5, #16]
	_pdecs_dev = device;
    2c54:	4b0a      	ldr	r3, [pc, #40]	; (2c80 <_pdec_async_init+0x4c>)
    2c56:	601d      	str	r5, [r3, #0]
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2c58:	4b0a      	ldr	r3, [pc, #40]	; (2c84 <_pdec_async_init+0x50>)
    2c5a:	f44f 2200 	mov.w	r2, #524288	; 0x80000
    2c5e:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
  __ASM volatile ("dsb 0xF":::"memory");
    2c62:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2c66:	f3bf 8f6f 	isb	sy
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2c6a:	f8c3 218c 	str.w	r2, [r3, #396]	; 0x18c
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2c6e:	60da      	str	r2, [r3, #12]
	NVIC_DisableIRQ(PDEC_0_IRQn);
	NVIC_ClearPendingIRQ(PDEC_0_IRQn);
	NVIC_EnableIRQ(PDEC_0_IRQn);

	return ERR_NONE;
}
    2c70:	4608      	mov	r0, r1
    2c72:	bd38      	pop	{r3, r4, r5, pc}
    2c74:	00003ea8 	.word	0x00003ea8
    2c78:	00001e9d 	.word	0x00001e9d
    2c7c:	00002b95 	.word	0x00002b95
    2c80:	2000031c 	.word	0x2000031c
    2c84:	e000e100 	.word	0xe000e100

00002c88 <PDEC_0_Handler>:

/**
 * \internal PDEC interrupt handler
 */
void PDEC_0_Handler(void)
{
    2c88:	b508      	push	{r3, lr}
	void *const hw = _pdecs_dev->hw;
    2c8a:	4b1e      	ldr	r3, [pc, #120]	; (2d04 <PDEC_0_Handler+0x7c>)
    2c8c:	6818      	ldr	r0, [r3, #0]
    2c8e:	6902      	ldr	r2, [r0, #16]
	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos;
    2c90:	7a93      	ldrb	r3, [r2, #10]

	if (hri_pdec_get_interrupt_OVF_bit(hw)) {
    2c92:	f013 0f01 	tst.w	r3, #1
    2c96:	d014      	beq.n	2cc2 <PDEC_0_Handler+0x3a>
	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF;
    2c98:	2301      	movs	r3, #1
    2c9a:	7293      	strb	r3, [r2, #10]
	while (((Pdec *)hw)->SYNCBUSY.reg & reg) {
    2c9c:	6913      	ldr	r3, [r2, #16]
    2c9e:	f3c3 0308 	ubfx	r3, r3, #0, #9
    2ca2:	2b00      	cmp	r3, #0
    2ca4:	d1fa      	bne.n	2c9c <PDEC_0_Handler+0x14>
}

static inline bool hri_pdec_get_STATUS_DIR_bit(const void *const hw)
{
	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_DIR) >> PDEC_STATUS_DIR_Pos;
    2ca6:	8993      	ldrh	r3, [r2, #12]
		hri_pdec_clear_interrupt_OVF_bit(hw);
		if (hri_pdec_get_STATUS_DIR_bit(hw)) {
    2ca8:	f013 0f80 	tst.w	r3, #128	; 0x80
    2cac:	d004      	beq.n	2cb8 <PDEC_0_Handler+0x30>
			_pdecs_dev->pdec_async_cb.irq_handler(_pdecs_dev, PDEC_IRQ_UNDERFLOW, 0);
    2cae:	6843      	ldr	r3, [r0, #4]
    2cb0:	2200      	movs	r2, #0
    2cb2:	2102      	movs	r1, #2
    2cb4:	4798      	blx	r3
    2cb6:	bd08      	pop	{r3, pc}
		} else {
			_pdecs_dev->pdec_async_cb.irq_handler(_pdecs_dev, PDEC_IRQ_OVERFLOW, 0);
    2cb8:	6843      	ldr	r3, [r0, #4]
    2cba:	2200      	movs	r2, #0
    2cbc:	2101      	movs	r1, #1
    2cbe:	4798      	blx	r3
    2cc0:	bd08      	pop	{r3, pc}
	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos;
    2cc2:	7a93      	ldrb	r3, [r2, #10]
		}
	} else if (hri_pdec_get_interrupt_DIR_bit(hw)) {
    2cc4:	f013 0f04 	tst.w	r3, #4
    2cc8:	d108      	bne.n	2cdc <PDEC_0_Handler+0x54>
	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos;
    2cca:	7a93      	ldrb	r3, [r2, #10]
		hri_pdec_clear_interrupt_DIR_bit(hw);
		_pdecs_dev->pdec_async_cb.irq_handler(_pdecs_dev, PDEC_IRQ_DIRECTION, 0);
	} else if (hri_pdec_get_interrupt_VLC_bit(hw)) {
    2ccc:	f013 0f08 	tst.w	r3, #8
    2cd0:	d10b      	bne.n	2cea <PDEC_0_Handler+0x62>
	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos;
    2cd2:	7a93      	ldrb	r3, [r2, #10]
		hri_pdec_clear_interrupt_VLC_bit(hw);
		_pdecs_dev->pdec_async_cb.pos_changed(_pdecs_dev, 0);
	} else if (hri_pdec_get_interrupt_ERR_bit(hw)) {
    2cd4:	f013 0f02 	tst.w	r3, #2
    2cd8:	d10d      	bne.n	2cf6 <PDEC_0_Handler+0x6e>
    2cda:	bd08      	pop	{r3, pc}
	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR;
    2cdc:	2304      	movs	r3, #4
    2cde:	7293      	strb	r3, [r2, #10]
		_pdecs_dev->pdec_async_cb.irq_handler(_pdecs_dev, PDEC_IRQ_DIRECTION, 0);
    2ce0:	6843      	ldr	r3, [r0, #4]
    2ce2:	2200      	movs	r2, #0
    2ce4:	4611      	mov	r1, r2
    2ce6:	4798      	blx	r3
    2ce8:	bd08      	pop	{r3, pc}
	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC;
    2cea:	2308      	movs	r3, #8
    2cec:	7293      	strb	r3, [r2, #10]
		_pdecs_dev->pdec_async_cb.pos_changed(_pdecs_dev, 0);
    2cee:	6803      	ldr	r3, [r0, #0]
    2cf0:	2100      	movs	r1, #0
    2cf2:	4798      	blx	r3
    2cf4:	bd08      	pop	{r3, pc}
	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR;
    2cf6:	2302      	movs	r3, #2
    2cf8:	7293      	strb	r3, [r2, #10]
		hri_pdec_clear_interrupt_ERR_bit(hw);
		_pdecs_dev->pdec_async_cb.irq_handler(_pdecs_dev, PDEC_IRQ_ERROR, 0);
    2cfa:	6843      	ldr	r3, [r0, #4]
    2cfc:	2200      	movs	r2, #0
    2cfe:	2103      	movs	r1, #3
    2d00:	4798      	blx	r3
	}
}
    2d02:	e7ea      	b.n	2cda <PDEC_0_Handler+0x52>
    2d04:	2000031c 	.word	0x2000031c

00002d08 <RAMECC_Handler>:

/**
 * \internal RAMECC interrupt handler
 */
void RAMECC_Handler(void)
{
    2d08:	b500      	push	{lr}
    2d0a:	b083      	sub	sp, #12
	return tmp;
}

static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw)
{
	return ((Ramecc *)hw)->INTFLAG.reg;
    2d0c:	4b0d      	ldr	r3, [pc, #52]	; (2d44 <RAMECC_Handler+0x3c>)
    2d0e:	789b      	ldrb	r3, [r3, #2]
    2d10:	b2db      	uxtb	r3, r3
	struct _ramecc_device *dev      = (struct _ramecc_device *)&device;
	volatile uint32_t      int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC);
    2d12:	9301      	str	r3, [sp, #4]

	if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) {
    2d14:	9b01      	ldr	r3, [sp, #4]
    2d16:	f013 0f02 	tst.w	r3, #2
    2d1a:	d006      	beq.n	2d2a <RAMECC_Handler+0x22>
    2d1c:	4b0a      	ldr	r3, [pc, #40]	; (2d48 <RAMECC_Handler+0x40>)
    2d1e:	681b      	ldr	r3, [r3, #0]
    2d20:	b11b      	cbz	r3, 2d2a <RAMECC_Handler+0x22>
	return tmp;
}

static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw)
{
	return ((Ramecc *)hw)->ERRADDR.reg;
    2d22:	4a08      	ldr	r2, [pc, #32]	; (2d44 <RAMECC_Handler+0x3c>)
    2d24:	6850      	ldr	r0, [r2, #4]
		dev->ramecc_cb.dual_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
    2d26:	4798      	blx	r3
    2d28:	e009      	b.n	2d3e <RAMECC_Handler+0x36>
	} else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) {
    2d2a:	9b01      	ldr	r3, [sp, #4]
    2d2c:	f013 0f01 	tst.w	r3, #1
    2d30:	d005      	beq.n	2d3e <RAMECC_Handler+0x36>
    2d32:	4b05      	ldr	r3, [pc, #20]	; (2d48 <RAMECC_Handler+0x40>)
    2d34:	685b      	ldr	r3, [r3, #4]
    2d36:	b113      	cbz	r3, 2d3e <RAMECC_Handler+0x36>
    2d38:	4a02      	ldr	r2, [pc, #8]	; (2d44 <RAMECC_Handler+0x3c>)
    2d3a:	6850      	ldr	r0, [r2, #4]
		dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
    2d3c:	4798      	blx	r3
	} else {
		return;
	}
}
    2d3e:	b003      	add	sp, #12
    2d40:	f85d fb04 	ldr.w	pc, [sp], #4
    2d44:	41020000 	.word	0x41020000
    2d48:	20000ae0 	.word	0x20000ae0

00002d4c <_sercom_get_hardware_index>:

/**
 * \brief Retrieve ordinal number of the given sercom hardware instance
 */
static uint8_t _sercom_get_hardware_index(const void *const hw)
{
    2d4c:	b470      	push	{r4, r5, r6}
    2d4e:	b089      	sub	sp, #36	; 0x24
    2d50:	4606      	mov	r6, r0
	Sercom *const sercom_modules[] = SERCOM_INSTS;
    2d52:	466c      	mov	r4, sp
    2d54:	4d0c      	ldr	r5, [pc, #48]	; (2d88 <_sercom_get_hardware_index+0x3c>)
    2d56:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
    2d58:	c40f      	stmia	r4!, {r0, r1, r2, r3}
    2d5a:	e895 000f 	ldmia.w	r5, {r0, r1, r2, r3}
    2d5e:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
	/* Find index for SERCOM instance. */
	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
    2d62:	2000      	movs	r0, #0
    2d64:	2807      	cmp	r0, #7
    2d66:	d80a      	bhi.n	2d7e <_sercom_get_hardware_index+0x32>
		if ((uint32_t)hw == (uint32_t)sercom_modules[i]) {
    2d68:	ab08      	add	r3, sp, #32
    2d6a:	eb03 0380 	add.w	r3, r3, r0, lsl #2
    2d6e:	f853 3c20 	ldr.w	r3, [r3, #-32]
    2d72:	42b3      	cmp	r3, r6
    2d74:	d001      	beq.n	2d7a <_sercom_get_hardware_index+0x2e>
	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
    2d76:	3001      	adds	r0, #1
    2d78:	e7f4      	b.n	2d64 <_sercom_get_hardware_index+0x18>
			return i;
    2d7a:	b2c0      	uxtb	r0, r0
    2d7c:	e000      	b.n	2d80 <_sercom_get_hardware_index+0x34>
		}
	}
	return 0;
    2d7e:	2000      	movs	r0, #0
}
    2d80:	b009      	add	sp, #36	; 0x24
    2d82:	bc70      	pop	{r4, r5, r6}
    2d84:	4770      	bx	lr
    2d86:	bf00      	nop
    2d88:	00003ec0 	.word	0x00003ec0

00002d8c <_spi_sync_enable>:
	};
}

static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
{
	return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
    2d8c:	69c3      	ldr	r3, [r0, #28]
 *
 * \return Enabling status
 */
static int32_t _spi_sync_enable(void *const hw)
{
	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
    2d8e:	f013 0f01 	tst.w	r3, #1
    2d92:	d109      	bne.n	2da8 <_spi_sync_enable+0x1c>
}

static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw)
{
	SERCOM_CRITICAL_SECTION_ENTER();
	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
    2d94:	6803      	ldr	r3, [r0, #0]
    2d96:	f043 0302 	orr.w	r3, r3, #2
    2d9a:	6003      	str	r3, [r0, #0]
	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
    2d9c:	69c3      	ldr	r3, [r0, #28]
    2d9e:	f013 0f03 	tst.w	r3, #3
    2da2:	d1fb      	bne.n	2d9c <_spi_sync_enable+0x10>
		return ERR_BUSY;
	}

	hri_sercomspi_set_CTRLA_ENABLE_bit(hw);

	return ERR_NONE;
    2da4:	2000      	movs	r0, #0
    2da6:	4770      	bx	lr
		return ERR_BUSY;
    2da8:	f06f 0003 	mvn.w	r0, #3
}
    2dac:	4770      	bx	lr

00002dae <_spi_sync_rx_enable>:
	return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
    2dae:	69c3      	ldr	r3, [r0, #28]
 *
 * \return Enabling status
 */
static int32_t _spi_sync_rx_enable(void *const hw)
{
	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_CTRLB)) {
    2db0:	f013 0f04 	tst.w	r3, #4
    2db4:	d109      	bne.n	2dca <_spi_sync_rx_enable+0x1c>
}

static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw)
{
	SERCOM_CRITICAL_SECTION_ENTER();
	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN;
    2db6:	6843      	ldr	r3, [r0, #4]
    2db8:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
    2dbc:	6043      	str	r3, [r0, #4]
	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
    2dbe:	69c3      	ldr	r3, [r0, #28]
    2dc0:	f013 0f17 	tst.w	r3, #23
    2dc4:	d1fb      	bne.n	2dbe <_spi_sync_rx_enable+0x10>
		return ERR_BUSY;
	}

	hri_sercomspi_set_CTRLB_RXEN_bit(hw);

	return ERR_NONE;
    2dc6:	2000      	movs	r0, #0
    2dc8:	4770      	bx	lr
		return ERR_BUSY;
    2dca:	f06f 0003 	mvn.w	r0, #3
}
    2dce:	4770      	bx	lr

00002dd0 <_spi_sync_rx_disable>:
	return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
    2dd0:	69c3      	ldr	r3, [r0, #28]
 *
 * \return Disabling status
 */
static int32_t _spi_sync_rx_disable(void *const hw)
{
	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_CTRLB)) {
    2dd2:	f013 0f04 	tst.w	r3, #4
    2dd6:	d109      	bne.n	2dec <_spi_sync_rx_disable+0x1c>
}

static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw)
{
	SERCOM_CRITICAL_SECTION_ENTER();
	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN;
    2dd8:	6843      	ldr	r3, [r0, #4]
    2dda:	f423 3300 	bic.w	r3, r3, #131072	; 0x20000
    2dde:	6043      	str	r3, [r0, #4]
	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
    2de0:	69c3      	ldr	r3, [r0, #28]
    2de2:	f013 0f17 	tst.w	r3, #23
    2de6:	d1fb      	bne.n	2de0 <_spi_sync_rx_disable+0x10>
		return ERR_BUSY;
	}
	hri_sercomspi_clear_CTRLB_RXEN_bit(hw);

	return ERR_NONE;
    2de8:	2000      	movs	r0, #0
    2dea:	4770      	bx	lr
		return ERR_BUSY;
    2dec:	f06f 0003 	mvn.w	r0, #3
}
    2df0:	4770      	bx	lr

00002df2 <_spi_m_get_source_for_dma>:
 *  \return The spi source address
 */
static uint32_t _spi_m_get_source_for_dma(void *const hw)
{
	return (uint32_t) & (((Sercom *)hw)->SPI.DATA);
}
    2df2:	3028      	adds	r0, #40	; 0x28
    2df4:	4770      	bx	lr

00002df6 <_spi_m_get_destination_for_dma>:
 *  \return The spi destination address
 */
static uint32_t _spi_m_get_destination_for_dma(void *const hw)
{
	return (uint32_t) & (((Sercom *)hw)->SPI.DATA);
}
    2df6:	3028      	adds	r0, #40	; 0x28
    2df8:	4770      	bx	lr
	...

00002dfc <_spi_get_tx_dma_channel>:
 *  \param[in] hw_addr The hardware register base address
 *
 *  \return SPI TX DMA channel index.
 */
static uint8_t _spi_get_tx_dma_channel(const void *const hw)
{
    2dfc:	b508      	push	{r3, lr}
	uint8_t index = _sercom_get_hardware_index(hw);
    2dfe:	4b04      	ldr	r3, [pc, #16]	; (2e10 <_spi_get_tx_dma_channel+0x14>)
    2e00:	4798      	blx	r3

	switch (index) {
    2e02:	2805      	cmp	r0, #5
    2e04:	d001      	beq.n	2e0a <_spi_get_tx_dma_channel+0xe>
	case 0:
		return CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL;
    2e06:	2000      	movs	r0, #0
    2e08:	bd08      	pop	{r3, pc}
	case 3:
		return CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL;
	case 4:
		return CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL;
	case 5:
		return CONF_SERCOM_5_SPI_M_DMA_TX_CHANNEL;
    2e0a:	2001      	movs	r0, #1
	case 7:
		return CONF_SERCOM_7_SPI_M_DMA_TX_CHANNEL;
	default:
		return CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL;
	}
}
    2e0c:	bd08      	pop	{r3, pc}
    2e0e:	bf00      	nop
    2e10:	00002d4d 	.word	0x00002d4d

00002e14 <_spi_is_rx_dma_channel_enabled>:
 *  \param[in] hw_addr The hardware register base address
 *
 *  \return one if enabled.
 */
static uint8_t _spi_is_rx_dma_channel_enabled(const void *const hw)
{
    2e14:	b508      	push	{r3, lr}
	uint8_t index = _sercom_get_hardware_index(hw);
    2e16:	4b04      	ldr	r3, [pc, #16]	; (2e28 <_spi_is_rx_dma_channel_enabled+0x14>)
    2e18:	4798      	blx	r3

	switch (index) {
    2e1a:	2805      	cmp	r0, #5
    2e1c:	d001      	beq.n	2e22 <_spi_is_rx_dma_channel_enabled+0xe>
	case 0:
		return CONF_SERCOM_0_SPI_RX_CHANNEL;
    2e1e:	2000      	movs	r0, #0
    2e20:	bd08      	pop	{r3, pc}
	case 3:
		return CONF_SERCOM_3_SPI_RX_CHANNEL;
	case 4:
		return CONF_SERCOM_4_SPI_RX_CHANNEL;
	case 5:
		return CONF_SERCOM_5_SPI_RX_CHANNEL;
    2e22:	2001      	movs	r0, #1
	case 7:
		return CONF_SERCOM_7_SPI_RX_CHANNEL;
	default:
		return false;
	}
}
    2e24:	bd08      	pop	{r3, pc}
    2e26:	bf00      	nop
    2e28:	00002d4d 	.word	0x00002d4d

00002e2c <_spi_get_rx_dma_channel>:
 *  \param[in] hw_addr The hardware register base address
 *
 *  \return SPI RX DMA channel index.
 */
static uint8_t _spi_get_rx_dma_channel(const void *const hw)
{
    2e2c:	b508      	push	{r3, lr}
	uint8_t index = _sercom_get_hardware_index(hw);
    2e2e:	4b07      	ldr	r3, [pc, #28]	; (2e4c <_spi_get_rx_dma_channel+0x20>)
    2e30:	4798      	blx	r3

	switch (index) {
    2e32:	2807      	cmp	r0, #7
    2e34:	d807      	bhi.n	2e46 <_spi_get_rx_dma_channel+0x1a>
    2e36:	e8df f000 	tbb	[pc, r0]
    2e3a:	0404      	.short	0x0404
    2e3c:	06040404 	.word	0x06040404
    2e40:	0404      	.short	0x0404
	case 0:
		return CONF_SERCOM_0_SPI_M_DMA_RX_CHANNEL;
    2e42:	2001      	movs	r0, #1
    2e44:	bd08      	pop	{r3, pc}
	case 3:
		return CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL;
	case 4:
		return CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL;
	case 5:
		return CONF_SERCOM_5_SPI_M_DMA_RX_CHANNEL;
    2e46:	2000      	movs	r0, #0
	case 7:
		return CONF_SERCOM_7_SPI_M_DMA_RX_CHANNEL;
	default:
		return CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL;
	}
}
    2e48:	bd08      	pop	{r3, pc}
    2e4a:	bf00      	nop
    2e4c:	00002d4d 	.word	0x00002d4d

00002e50 <_spi_dma_rx_complete>:
/**
 *  \brief Callback for RX
 *  \param[in, out] dev Pointer to the DMA resource.
 */
static void _spi_dma_rx_complete(struct _dma_resource *resource)
{
    2e50:	b508      	push	{r3, lr}
	struct _spi_m_dma_dev *dev = (struct _spi_m_dma_dev *)resource->back;
    2e52:	68c3      	ldr	r3, [r0, #12]

	if (dev->callbacks.rx) {
    2e54:	689b      	ldr	r3, [r3, #8]
    2e56:	b103      	cbz	r3, 2e5a <_spi_dma_rx_complete+0xa>
		dev->callbacks.rx(resource);
    2e58:	4798      	blx	r3
    2e5a:	bd08      	pop	{r3, pc}

00002e5c <_spi_dma_tx_complete>:
/**
 *  \brief Callback for TX
 *  \param[in, out] dev Pointer to the DMA resource.
 */
static void _spi_dma_tx_complete(struct _dma_resource *resource)
{
    2e5c:	b508      	push	{r3, lr}
	struct _spi_m_dma_dev *dev = (struct _spi_m_dma_dev *)resource->back;
    2e5e:	68c3      	ldr	r3, [r0, #12]

	if (dev->callbacks.tx) {
    2e60:	685b      	ldr	r3, [r3, #4]
    2e62:	b103      	cbz	r3, 2e66 <_spi_dma_tx_complete+0xa>
		dev->callbacks.tx(resource);
    2e64:	4798      	blx	r3
    2e66:	bd08      	pop	{r3, pc}

00002e68 <_spi_dma_tx_suspend>:
/** ADDED
 *  \brief Callback for suspend
 *  \param[in, out] dev Pointer to the DMA resource.
 */
static void _spi_dma_tx_suspend(struct _dma_resource *resource)
{
    2e68:	b508      	push	{r3, lr}
	struct _spi_m_dma_dev *dev = (struct _spi_m_dma_dev *)resource->back;
    2e6a:	68c3      	ldr	r3, [r0, #12]

	if (dev->callbacks.suspend) {
    2e6c:	691b      	ldr	r3, [r3, #16]
    2e6e:	b103      	cbz	r3, 2e72 <_spi_dma_tx_suspend+0xa>
		dev->callbacks.suspend(resource);
    2e70:	4798      	blx	r3
    2e72:	bd08      	pop	{r3, pc}

00002e74 <_spi_dma_error_occured>:
/**
 *  \brief Callback for ERROR
 *  \param[in, out] dev Pointer to the DMA resource.
 */
static void _spi_dma_error_occured(struct _dma_resource *resource)
{
    2e74:	b508      	push	{r3, lr}
	struct _spi_m_dma_dev *dev = (struct _spi_m_dma_dev *)resource->back;
    2e76:	68c3      	ldr	r3, [r0, #12]

	if (dev->callbacks.error) {
    2e78:	68db      	ldr	r3, [r3, #12]
    2e7a:	b103      	cbz	r3, 2e7e <_spi_dma_error_occured+0xa>
		dev->callbacks.error(resource);
    2e7c:	4798      	blx	r3
    2e7e:	bd08      	pop	{r3, pc}

00002e80 <_spi_m_dma_rx_enable>:
{
    2e80:	b510      	push	{r4, lr}
	ASSERT(dev && dev->prvt);
    2e82:	4604      	mov	r4, r0
    2e84:	b168      	cbz	r0, 2ea2 <_spi_m_dma_rx_enable+0x22>
    2e86:	6803      	ldr	r3, [r0, #0]
    2e88:	b14b      	cbz	r3, 2e9e <_spi_m_dma_rx_enable+0x1e>
    2e8a:	2001      	movs	r0, #1
    2e8c:	f640 32fe 	movw	r2, #3070	; 0xbfe
    2e90:	4905      	ldr	r1, [pc, #20]	; (2ea8 <_spi_m_dma_rx_enable+0x28>)
    2e92:	4b06      	ldr	r3, [pc, #24]	; (2eac <_spi_m_dma_rx_enable+0x2c>)
    2e94:	4798      	blx	r3
	return _spi_sync_rx_enable(dev->prvt);
    2e96:	6820      	ldr	r0, [r4, #0]
    2e98:	4b05      	ldr	r3, [pc, #20]	; (2eb0 <_spi_m_dma_rx_enable+0x30>)
    2e9a:	4798      	blx	r3
}
    2e9c:	bd10      	pop	{r4, pc}
	ASSERT(dev && dev->prvt);
    2e9e:	2000      	movs	r0, #0
    2ea0:	e7f4      	b.n	2e8c <_spi_m_dma_rx_enable+0xc>
    2ea2:	2000      	movs	r0, #0
    2ea4:	e7f2      	b.n	2e8c <_spi_m_dma_rx_enable+0xc>
    2ea6:	bf00      	nop
    2ea8:	00003f34 	.word	0x00003f34
    2eac:	00001e9d 	.word	0x00001e9d
    2eb0:	00002daf 	.word	0x00002daf

00002eb4 <_spi_m_dma_rx_disable>:
{
    2eb4:	b510      	push	{r4, lr}
	ASSERT(dev && dev->prvt);
    2eb6:	4604      	mov	r4, r0
    2eb8:	b168      	cbz	r0, 2ed6 <_spi_m_dma_rx_disable+0x22>
    2eba:	6803      	ldr	r3, [r0, #0]
    2ebc:	b14b      	cbz	r3, 2ed2 <_spi_m_dma_rx_disable+0x1e>
    2ebe:	2001      	movs	r0, #1
    2ec0:	f640 4205 	movw	r2, #3077	; 0xc05
    2ec4:	4905      	ldr	r1, [pc, #20]	; (2edc <_spi_m_dma_rx_disable+0x28>)
    2ec6:	4b06      	ldr	r3, [pc, #24]	; (2ee0 <_spi_m_dma_rx_disable+0x2c>)
    2ec8:	4798      	blx	r3
	return _spi_sync_rx_disable(dev->prvt);
    2eca:	6820      	ldr	r0, [r4, #0]
    2ecc:	4b05      	ldr	r3, [pc, #20]	; (2ee4 <_spi_m_dma_rx_disable+0x30>)
    2ece:	4798      	blx	r3
}
    2ed0:	bd10      	pop	{r4, pc}
	ASSERT(dev && dev->prvt);
    2ed2:	2000      	movs	r0, #0
    2ed4:	e7f4      	b.n	2ec0 <_spi_m_dma_rx_disable+0xc>
    2ed6:	2000      	movs	r0, #0
    2ed8:	e7f2      	b.n	2ec0 <_spi_m_dma_rx_disable+0xc>
    2eda:	bf00      	nop
    2edc:	00003f34 	.word	0x00003f34
    2ee0:	00001e9d 	.word	0x00001e9d
    2ee4:	00002dd1 	.word	0x00002dd1

00002ee8 <_spi_m_dma_init>:
	}
}

int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw)
{
    2ee8:	b570      	push	{r4, r5, r6, lr}
    2eea:	4605      	mov	r5, r0
    2eec:	460c      	mov	r4, r1
	uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
    2eee:	4608      	mov	r0, r1
    2ef0:	4b50      	ldr	r3, [pc, #320]	; (3034 <_spi_m_dma_init+0x14c>)
    2ef2:	4798      	blx	r3
	for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) {
    2ef4:	2300      	movs	r3, #0
    2ef6:	2b00      	cmp	r3, #0
    2ef8:	d072      	beq.n	2fe0 <_spi_m_dma_init+0xf8>
	return NULL;
    2efa:	2600      	movs	r6, #0
	const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw);

	ASSERT(dev && hw);
    2efc:	2d00      	cmp	r5, #0
    2efe:	d07b      	beq.n	2ff8 <_spi_m_dma_init+0x110>
    2f00:	2c00      	cmp	r4, #0
    2f02:	d077      	beq.n	2ff4 <_spi_m_dma_init+0x10c>
    2f04:	2001      	movs	r0, #1
    2f06:	f640 42b7 	movw	r2, #3255	; 0xcb7
    2f0a:	494b      	ldr	r1, [pc, #300]	; (3038 <_spi_m_dma_init+0x150>)
    2f0c:	4b4b      	ldr	r3, [pc, #300]	; (303c <_spi_m_dma_init+0x154>)
    2f0e:	4798      	blx	r3

	if (regs == NULL) {
    2f10:	2e00      	cmp	r6, #0
    2f12:	f000 808b 	beq.w	302c <_spi_m_dma_init+0x144>
	return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
    2f16:	69e3      	ldr	r3, [r4, #28]
		return ERR_INVALID_ARG;
	}

	if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
    2f18:	f013 0f01 	tst.w	r3, #1
    2f1c:	d11d      	bne.n	2f5a <_spi_m_dma_init+0x72>
		uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk;
    2f1e:	6833      	ldr	r3, [r6, #0]
    2f20:	f003 021c 	and.w	r2, r3, #28
	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
    2f24:	69e3      	ldr	r3, [r4, #28]
    2f26:	f013 0f03 	tst.w	r3, #3
    2f2a:	d1fb      	bne.n	2f24 <_spi_m_dma_init+0x3c>
	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
    2f2c:	6823      	ldr	r3, [r4, #0]
		if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) {
    2f2e:	f013 0f02 	tst.w	r3, #2
    2f32:	d00b      	beq.n	2f4c <_spi_m_dma_init+0x64>
	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
    2f34:	6823      	ldr	r3, [r4, #0]
    2f36:	f023 0302 	bic.w	r3, r3, #2
    2f3a:	6023      	str	r3, [r4, #0]
	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
    2f3c:	69e3      	ldr	r3, [r4, #28]
    2f3e:	f013 0f03 	tst.w	r3, #3
    2f42:	d1fb      	bne.n	2f3c <_spi_m_dma_init+0x54>
    2f44:	69e3      	ldr	r3, [r4, #28]
    2f46:	f013 0f02 	tst.w	r3, #2
    2f4a:	d1fb      	bne.n	2f44 <_spi_m_dma_init+0x5c>
			hri_sercomspi_clear_CTRLA_ENABLE_bit(hw);
			hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE);
		}
		hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode);
    2f4c:	f042 0201 	orr.w	r2, r2, #1
	((Sercom *)hw)->SPI.CTRLA.reg = data;
    2f50:	6022      	str	r2, [r4, #0]
	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
    2f52:	69e3      	ldr	r3, [r4, #28]
    2f54:	f013 0f03 	tst.w	r3, #3
    2f58:	d1fb      	bne.n	2f52 <_spi_m_dma_init+0x6a>
    2f5a:	69e3      	ldr	r3, [r4, #28]
    2f5c:	f013 0f01 	tst.w	r3, #1
    2f60:	d1fb      	bne.n	2f5a <_spi_m_dma_init+0x72>
	}
	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);

	dev->prvt = hw;
    2f62:	602c      	str	r4, [r5, #0]
	ASSERT(hw && regs);
    2f64:	2c00      	cmp	r4, #0
    2f66:	d04b      	beq.n	3000 <_spi_m_dma_init+0x118>
    2f68:	2e00      	cmp	r6, #0
    2f6a:	d047      	beq.n	2ffc <_spi_m_dma_init+0x114>
    2f6c:	2001      	movs	r0, #1
    2f6e:	f640 120a 	movw	r2, #2314	; 0x90a
    2f72:	4931      	ldr	r1, [pc, #196]	; (3038 <_spi_m_dma_init+0x150>)
    2f74:	4b31      	ldr	r3, [pc, #196]	; (303c <_spi_m_dma_init+0x154>)
    2f76:	4798      	blx	r3
	    hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
    2f78:	6833      	ldr	r3, [r6, #0]
	hri_sercomspi_write_CTRLA_reg(
    2f7a:	f423 7381 	bic.w	r3, r3, #258	; 0x102
    2f7e:	f023 0301 	bic.w	r3, r3, #1
	((Sercom *)hw)->SPI.CTRLA.reg = data;
    2f82:	6023      	str	r3, [r4, #0]
	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
    2f84:	69e3      	ldr	r3, [r4, #28]
    2f86:	f013 0f03 	tst.w	r3, #3
    2f8a:	d1fb      	bne.n	2f84 <_spi_m_dma_init+0x9c>
	    (regs->ctrlb
    2f8c:	6873      	ldr	r3, [r6, #4]
	        | (SERCOM_SPI_CTRLB_RXEN));
    2f8e:	f423 3338 	bic.w	r3, r3, #188416	; 0x2e000
    2f92:	f423 7310 	bic.w	r3, r3, #576	; 0x240
	hri_sercomspi_write_CTRLB_reg(
    2f96:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
}

static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
{
	SERCOM_CRITICAL_SECTION_ENTER();
	((Sercom *)hw)->SPI.CTRLB.reg = data;
    2f9a:	6063      	str	r3, [r4, #4]
	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
    2f9c:	69e3      	ldr	r3, [r4, #28]
    2f9e:	f013 0f17 	tst.w	r3, #23
    2fa2:	d1fb      	bne.n	2f9c <_spi_m_dma_init+0xb4>
	hri_sercomspi_write_BAUD_reg(hw, regs->baud);
    2fa4:	7b33      	ldrb	r3, [r6, #12]
}

static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data)
{
	SERCOM_CRITICAL_SECTION_ENTER();
	((Sercom *)hw)->SPI.BAUD.reg = data;
    2fa6:	7323      	strb	r3, [r4, #12]
	hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
    2fa8:	7b73      	ldrb	r3, [r6, #13]
}

static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data)
{
	SERCOM_CRITICAL_SECTION_ENTER();
	((Sercom *)hw)->SPI.DBGCTRL.reg = data;
    2faa:	f884 3030 	strb.w	r3, [r4, #48]	; 0x30

	_spi_load_regs_master(hw, regs);

	/* If enabled, initialize DMA rx channel */
	if (_spi_is_rx_dma_channel_enabled(hw)) {
    2fae:	4620      	mov	r0, r4
    2fb0:	4b23      	ldr	r3, [pc, #140]	; (3040 <_spi_m_dma_init+0x158>)
    2fb2:	4798      	blx	r3
    2fb4:	bb30      	cbnz	r0, 3004 <_spi_m_dma_init+0x11c>
		dev->resource->dma_cb.transfer_done = _spi_dma_rx_complete;
		dev->resource->dma_cb.error         = _spi_dma_error_occured;
		dev->resource->dma_cb.suspend		= _spi_dma_tx_suspend;		
	}
	/* Initialize DMA tx channel */
	_dma_get_channel_resource(&dev->resource, _spi_get_tx_dma_channel(hw));
    2fb6:	4620      	mov	r0, r4
    2fb8:	4b22      	ldr	r3, [pc, #136]	; (3044 <_spi_m_dma_init+0x15c>)
    2fba:	4798      	blx	r3
    2fbc:	4601      	mov	r1, r0
    2fbe:	f105 001c 	add.w	r0, r5, #28
    2fc2:	4b21      	ldr	r3, [pc, #132]	; (3048 <_spi_m_dma_init+0x160>)
    2fc4:	4798      	blx	r3
	dev->resource->back                 = dev;
    2fc6:	69eb      	ldr	r3, [r5, #28]
    2fc8:	60dd      	str	r5, [r3, #12]
	dev->resource->dma_cb.transfer_done = _spi_dma_tx_complete;
    2fca:	69eb      	ldr	r3, [r5, #28]
    2fcc:	4a1f      	ldr	r2, [pc, #124]	; (304c <_spi_m_dma_init+0x164>)
    2fce:	601a      	str	r2, [r3, #0]
	dev->resource->dma_cb.error         = _spi_dma_error_occured;
    2fd0:	69eb      	ldr	r3, [r5, #28]
    2fd2:	4a1f      	ldr	r2, [pc, #124]	; (3050 <_spi_m_dma_init+0x168>)
    2fd4:	605a      	str	r2, [r3, #4]
	dev->resource->dma_cb.suspend		= _spi_dma_tx_suspend;	
    2fd6:	69eb      	ldr	r3, [r5, #28]
    2fd8:	4a1e      	ldr	r2, [pc, #120]	; (3054 <_spi_m_dma_init+0x16c>)
    2fda:	609a      	str	r2, [r3, #8]

	return ERR_NONE;
    2fdc:	2000      	movs	r0, #0
    2fde:	bd70      	pop	{r4, r5, r6, pc}
		if (sercomspi_regs[i].n == n) {
    2fe0:	2805      	cmp	r0, #5
    2fe2:	d002      	beq.n	2fea <_spi_m_dma_init+0x102>
	for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) {
    2fe4:	3301      	adds	r3, #1
    2fe6:	b2db      	uxtb	r3, r3
    2fe8:	e785      	b.n	2ef6 <_spi_m_dma_init+0xe>
			return &sercomspi_regs[i];
    2fea:	eb03 1603 	add.w	r6, r3, r3, lsl #4
    2fee:	4b1a      	ldr	r3, [pc, #104]	; (3058 <_spi_m_dma_init+0x170>)
    2ff0:	441e      	add	r6, r3
    2ff2:	e783      	b.n	2efc <_spi_m_dma_init+0x14>
	ASSERT(dev && hw);
    2ff4:	2000      	movs	r0, #0
    2ff6:	e786      	b.n	2f06 <_spi_m_dma_init+0x1e>
    2ff8:	2000      	movs	r0, #0
    2ffa:	e784      	b.n	2f06 <_spi_m_dma_init+0x1e>
	ASSERT(hw && regs);
    2ffc:	2000      	movs	r0, #0
    2ffe:	e7b6      	b.n	2f6e <_spi_m_dma_init+0x86>
    3000:	2000      	movs	r0, #0
    3002:	e7b4      	b.n	2f6e <_spi_m_dma_init+0x86>
		_dma_get_channel_resource(&dev->resource, _spi_get_rx_dma_channel(hw));
    3004:	4620      	mov	r0, r4
    3006:	4b15      	ldr	r3, [pc, #84]	; (305c <_spi_m_dma_init+0x174>)
    3008:	4798      	blx	r3
    300a:	4601      	mov	r1, r0
    300c:	f105 001c 	add.w	r0, r5, #28
    3010:	4b0d      	ldr	r3, [pc, #52]	; (3048 <_spi_m_dma_init+0x160>)
    3012:	4798      	blx	r3
		dev->resource->back                 = dev;
    3014:	69eb      	ldr	r3, [r5, #28]
    3016:	60dd      	str	r5, [r3, #12]
		dev->resource->dma_cb.transfer_done = _spi_dma_rx_complete;
    3018:	69eb      	ldr	r3, [r5, #28]
    301a:	4a11      	ldr	r2, [pc, #68]	; (3060 <_spi_m_dma_init+0x178>)
    301c:	601a      	str	r2, [r3, #0]
		dev->resource->dma_cb.error         = _spi_dma_error_occured;
    301e:	69eb      	ldr	r3, [r5, #28]
    3020:	4a0b      	ldr	r2, [pc, #44]	; (3050 <_spi_m_dma_init+0x168>)
    3022:	605a      	str	r2, [r3, #4]
		dev->resource->dma_cb.suspend		= _spi_dma_tx_suspend;		
    3024:	69eb      	ldr	r3, [r5, #28]
    3026:	4a0b      	ldr	r2, [pc, #44]	; (3054 <_spi_m_dma_init+0x16c>)
    3028:	609a      	str	r2, [r3, #8]
    302a:	e7c4      	b.n	2fb6 <_spi_m_dma_init+0xce>
		return ERR_INVALID_ARG;
    302c:	f06f 000c 	mvn.w	r0, #12
}
    3030:	bd70      	pop	{r4, r5, r6, pc}
    3032:	bf00      	nop
    3034:	00002d4d 	.word	0x00002d4d
    3038:	00003f34 	.word	0x00003f34
    303c:	00001e9d 	.word	0x00001e9d
    3040:	00002e15 	.word	0x00002e15
    3044:	00002dfd 	.word	0x00002dfd
    3048:	0000276d 	.word	0x0000276d
    304c:	00002e5d 	.word	0x00002e5d
    3050:	00002e75 	.word	0x00002e75
    3054:	00002e69 	.word	0x00002e69
    3058:	00003f20 	.word	0x00003f20
    305c:	00002e2d 	.word	0x00002e2d
    3060:	00002e51 	.word	0x00002e51

00003064 <_spi_m_dma_enable>:
{
	return _spi_deinit(dev->prvt);
}

int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev)
{
    3064:	b510      	push	{r4, lr}
	ASSERT(dev && dev->prvt);
    3066:	4604      	mov	r4, r0
    3068:	b168      	cbz	r0, 3086 <_spi_m_dma_enable+0x22>
    306a:	6803      	ldr	r3, [r0, #0]
    306c:	b14b      	cbz	r3, 3082 <_spi_m_dma_enable+0x1e>
    306e:	2001      	movs	r0, #1
    3070:	f640 42e4 	movw	r2, #3300	; 0xce4
    3074:	4905      	ldr	r1, [pc, #20]	; (308c <_spi_m_dma_enable+0x28>)
    3076:	4b06      	ldr	r3, [pc, #24]	; (3090 <_spi_m_dma_enable+0x2c>)
    3078:	4798      	blx	r3

	return _spi_sync_enable(dev->prvt);
    307a:	6820      	ldr	r0, [r4, #0]
    307c:	4b05      	ldr	r3, [pc, #20]	; (3094 <_spi_m_dma_enable+0x30>)
    307e:	4798      	blx	r3
}
    3080:	bd10      	pop	{r4, pc}
	ASSERT(dev && dev->prvt);
    3082:	2000      	movs	r0, #0
    3084:	e7f4      	b.n	3070 <_spi_m_dma_enable+0xc>
    3086:	2000      	movs	r0, #0
    3088:	e7f2      	b.n	3070 <_spi_m_dma_enable+0xc>
    308a:	bf00      	nop
    308c:	00003f34 	.word	0x00003f34
    3090:	00001e9d 	.word	0x00001e9d
    3094:	00002d8d 	.word	0x00002d8d

00003098 <_spi_m_dma_register_callback>:

	return size;
}

void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type type, _spi_dma_cb_t func)
{
    3098:	b570      	push	{r4, r5, r6, lr}
    309a:	4605      	mov	r5, r0
    309c:	4614      	mov	r4, r2
	switch (type) {
    309e:	2904      	cmp	r1, #4
    30a0:	d836      	bhi.n	3110 <_spi_m_dma_register_callback+0x78>
    30a2:	e8df f001 	tbb	[pc, r1]
    30a6:	0e03      	.short	0x0e03
    30a8:	3519      	.short	0x3519
    30aa:	2b          	.byte	0x2b
    30ab:	00          	.byte	0x00
	case SPI_DEV_CB_DMA_TX:
		dev->callbacks.tx = func;
    30ac:	606a      	str	r2, [r5, #4]
		_dma_set_irq_state(_spi_get_tx_dma_channel(dev->prvt), DMA_TRANSFER_COMPLETE_CB, func != NULL);
    30ae:	6800      	ldr	r0, [r0, #0]
    30b0:	4b18      	ldr	r3, [pc, #96]	; (3114 <_spi_m_dma_register_callback+0x7c>)
    30b2:	4798      	blx	r3
    30b4:	1c22      	adds	r2, r4, #0
    30b6:	bf18      	it	ne
    30b8:	2201      	movne	r2, #1
    30ba:	2100      	movs	r1, #0
    30bc:	4b16      	ldr	r3, [pc, #88]	; (3118 <_spi_m_dma_register_callback+0x80>)
    30be:	4798      	blx	r3
		break;
    30c0:	bd70      	pop	{r4, r5, r6, pc}
	case SPI_DEV_CB_DMA_RX:
		dev->callbacks.rx = func;
    30c2:	60aa      	str	r2, [r5, #8]
		_dma_set_irq_state(_spi_get_rx_dma_channel(dev->prvt), DMA_TRANSFER_COMPLETE_CB, func != NULL);
    30c4:	6800      	ldr	r0, [r0, #0]
    30c6:	4b15      	ldr	r3, [pc, #84]	; (311c <_spi_m_dma_register_callback+0x84>)
    30c8:	4798      	blx	r3
    30ca:	1c22      	adds	r2, r4, #0
    30cc:	bf18      	it	ne
    30ce:	2201      	movne	r2, #1
    30d0:	2100      	movs	r1, #0
    30d2:	4b11      	ldr	r3, [pc, #68]	; (3118 <_spi_m_dma_register_callback+0x80>)
    30d4:	4798      	blx	r3
		break;
    30d6:	bd70      	pop	{r4, r5, r6, pc}
	case SPI_DEV_CB_DMA_ERROR:
		dev->callbacks.error = func;
    30d8:	60ea      	str	r2, [r5, #12]
		_dma_set_irq_state(_spi_get_rx_dma_channel(dev->prvt), DMA_TRANSFER_ERROR_CB, func != NULL);
    30da:	6800      	ldr	r0, [r0, #0]
    30dc:	4b0f      	ldr	r3, [pc, #60]	; (311c <_spi_m_dma_register_callback+0x84>)
    30de:	4798      	blx	r3
    30e0:	3400      	adds	r4, #0
    30e2:	bf18      	it	ne
    30e4:	2401      	movne	r4, #1
    30e6:	4622      	mov	r2, r4
    30e8:	2101      	movs	r1, #1
    30ea:	4e0b      	ldr	r6, [pc, #44]	; (3118 <_spi_m_dma_register_callback+0x80>)
    30ec:	47b0      	blx	r6
		_dma_set_irq_state(_spi_get_tx_dma_channel(dev->prvt), DMA_TRANSFER_ERROR_CB, func != NULL);
    30ee:	6828      	ldr	r0, [r5, #0]
    30f0:	4b08      	ldr	r3, [pc, #32]	; (3114 <_spi_m_dma_register_callback+0x7c>)
    30f2:	4798      	blx	r3
    30f4:	4622      	mov	r2, r4
    30f6:	2101      	movs	r1, #1
    30f8:	47b0      	blx	r6
		break;
    30fa:	bd70      	pop	{r4, r5, r6, pc}
	case SPI_DEV_CB_DMA_N:
		break;
	case SPI_DEV_CB_DMA_SUSPEND:
		dev->callbacks.suspend = func;
    30fc:	612a      	str	r2, [r5, #16]
		_dma_set_irq_state(_spi_get_rx_dma_channel(dev->prvt), DMA_TRANSFER_SUSPEND_CB, func != NULL);
    30fe:	6800      	ldr	r0, [r0, #0]
    3100:	4b06      	ldr	r3, [pc, #24]	; (311c <_spi_m_dma_register_callback+0x84>)
    3102:	4798      	blx	r3
    3104:	1c22      	adds	r2, r4, #0
    3106:	bf18      	it	ne
    3108:	2201      	movne	r2, #1
    310a:	2102      	movs	r1, #2
    310c:	4b02      	ldr	r3, [pc, #8]	; (3118 <_spi_m_dma_register_callback+0x80>)
    310e:	4798      	blx	r3
    3110:	bd70      	pop	{r4, r5, r6, pc}
    3112:	bf00      	nop
    3114:	00002dfd 	.word	0x00002dfd
    3118:	000025f5 	.word	0x000025f5
    311c:	00002e2d 	.word	0x00002e2d

00003120 <_spi_m_dma_transfer>:
	}
}

int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf,
                            const uint16_t length)
{
    3120:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    3124:	4605      	mov	r5, r0
    3126:	4689      	mov	r9, r1
    3128:	4690      	mov	r8, r2
    312a:	461f      	mov	r7, r3
	const struct sercomspi_regs_cfg *regs  = _spi_get_regs((uint32_t)dev->prvt);
    312c:	6804      	ldr	r4, [r0, #0]
	uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
    312e:	4620      	mov	r0, r4
    3130:	4b33      	ldr	r3, [pc, #204]	; (3200 <_spi_m_dma_transfer+0xe0>)
    3132:	4798      	blx	r3
	for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) {
    3134:	2300      	movs	r3, #0
    3136:	2b00      	cmp	r3, #0
    3138:	d03f      	beq.n	31ba <_spi_m_dma_transfer+0x9a>
	return NULL;
    313a:	f04f 0a00 	mov.w	sl, #0
	uint8_t                          rx_ch = _spi_get_rx_dma_channel(dev->prvt);
    313e:	4620      	mov	r0, r4
    3140:	4b30      	ldr	r3, [pc, #192]	; (3204 <_spi_m_dma_transfer+0xe4>)
    3142:	4798      	blx	r3
    3144:	4606      	mov	r6, r0
	uint8_t                          tx_ch = _spi_get_tx_dma_channel(dev->prvt);
    3146:	4620      	mov	r0, r4
    3148:	4b2f      	ldr	r3, [pc, #188]	; (3208 <_spi_m_dma_transfer+0xe8>)
    314a:	4798      	blx	r3
    314c:	4604      	mov	r4, r0

	if (rxbuf) {
    314e:	f1b8 0f00 	cmp.w	r8, #0
    3152:	d03c      	beq.n	31ce <_spi_m_dma_transfer+0xae>
		/* Enable spi rx */
		_spi_m_dma_rx_enable(dev);
    3154:	4628      	mov	r0, r5
    3156:	4b2d      	ldr	r3, [pc, #180]	; (320c <_spi_m_dma_transfer+0xec>)
    3158:	4798      	blx	r3
		_dma_set_source_address(rx_ch, (void *)_spi_m_get_source_for_dma(dev->prvt));
    315a:	6828      	ldr	r0, [r5, #0]
    315c:	4b2c      	ldr	r3, [pc, #176]	; (3210 <_spi_m_dma_transfer+0xf0>)
    315e:	4798      	blx	r3
    3160:	4601      	mov	r1, r0
    3162:	4630      	mov	r0, r6
    3164:	4b2b      	ldr	r3, [pc, #172]	; (3214 <_spi_m_dma_transfer+0xf4>)
    3166:	4798      	blx	r3
		_dma_set_destination_address(rx_ch, rxbuf);
    3168:	4641      	mov	r1, r8
    316a:	4630      	mov	r0, r6
    316c:	4b2a      	ldr	r3, [pc, #168]	; (3218 <_spi_m_dma_transfer+0xf8>)
    316e:	4798      	blx	r3
		_dma_set_data_amount(rx_ch, length);
    3170:	4639      	mov	r1, r7
    3172:	4630      	mov	r0, r6
    3174:	4b29      	ldr	r3, [pc, #164]	; (321c <_spi_m_dma_transfer+0xfc>)
    3176:	4798      	blx	r3
		_dma_enable_transaction(rx_ch, false);
    3178:	2100      	movs	r1, #0
    317a:	4630      	mov	r0, r6
    317c:	4b28      	ldr	r3, [pc, #160]	; (3220 <_spi_m_dma_transfer+0x100>)
    317e:	4798      	blx	r3
	} else {
		/* Disable spi rx */
		_spi_m_dma_rx_disable(dev);
	}

	if (txbuf) {
    3180:	f1b9 0f00 	cmp.w	r9, #0
    3184:	d027      	beq.n	31d6 <_spi_m_dma_transfer+0xb6>
		/* Enable spi tx */
		_dma_set_source_address(tx_ch, txbuf);
    3186:	4649      	mov	r1, r9
    3188:	4620      	mov	r0, r4
    318a:	4b22      	ldr	r3, [pc, #136]	; (3214 <_spi_m_dma_transfer+0xf4>)
    318c:	4798      	blx	r3
		_dma_set_destination_address(tx_ch, (void *)_spi_m_get_destination_for_dma(dev->prvt));
    318e:	6828      	ldr	r0, [r5, #0]
    3190:	4b24      	ldr	r3, [pc, #144]	; (3224 <_spi_m_dma_transfer+0x104>)
    3192:	4798      	blx	r3
    3194:	4601      	mov	r1, r0
    3196:	4620      	mov	r0, r4
    3198:	4b1f      	ldr	r3, [pc, #124]	; (3218 <_spi_m_dma_transfer+0xf8>)
    319a:	4798      	blx	r3
		_dma_srcinc_enable(tx_ch, true);
    319c:	2101      	movs	r1, #1
    319e:	4620      	mov	r0, r4
    31a0:	4b21      	ldr	r3, [pc, #132]	; (3228 <_spi_m_dma_transfer+0x108>)
    31a2:	4798      	blx	r3
		_dma_set_data_amount(tx_ch, length);
    31a4:	4639      	mov	r1, r7
    31a6:	4620      	mov	r0, r4
    31a8:	4b1c      	ldr	r3, [pc, #112]	; (321c <_spi_m_dma_transfer+0xfc>)
    31aa:	4798      	blx	r3
		_dma_set_source_address(tx_ch, &regs->dummy_byte);
		_dma_set_destination_address(tx_ch, (void *)_spi_m_get_destination_for_dma(dev->prvt));
		_dma_srcinc_enable(tx_ch, false);
		_dma_set_data_amount(tx_ch, length);
	}
	_dma_enable_transaction(tx_ch, false);
    31ac:	2100      	movs	r1, #0
    31ae:	4620      	mov	r0, r4
    31b0:	4b1b      	ldr	r3, [pc, #108]	; (3220 <_spi_m_dma_transfer+0x100>)
    31b2:	4798      	blx	r3

	return ERR_NONE;
}
    31b4:	2000      	movs	r0, #0
    31b6:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		if (sercomspi_regs[i].n == n) {
    31ba:	2805      	cmp	r0, #5
    31bc:	d002      	beq.n	31c4 <_spi_m_dma_transfer+0xa4>
	for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) {
    31be:	3301      	adds	r3, #1
    31c0:	b2db      	uxtb	r3, r3
    31c2:	e7b8      	b.n	3136 <_spi_m_dma_transfer+0x16>
			return &sercomspi_regs[i];
    31c4:	eb03 1a03 	add.w	sl, r3, r3, lsl #4
    31c8:	4b18      	ldr	r3, [pc, #96]	; (322c <_spi_m_dma_transfer+0x10c>)
    31ca:	449a      	add	sl, r3
    31cc:	e7b7      	b.n	313e <_spi_m_dma_transfer+0x1e>
		_spi_m_dma_rx_disable(dev);
    31ce:	4628      	mov	r0, r5
    31d0:	4b17      	ldr	r3, [pc, #92]	; (3230 <_spi_m_dma_transfer+0x110>)
    31d2:	4798      	blx	r3
    31d4:	e7d4      	b.n	3180 <_spi_m_dma_transfer+0x60>
		_dma_set_source_address(tx_ch, &regs->dummy_byte);
    31d6:	f10a 010e 	add.w	r1, sl, #14
    31da:	4620      	mov	r0, r4
    31dc:	4b0d      	ldr	r3, [pc, #52]	; (3214 <_spi_m_dma_transfer+0xf4>)
    31de:	4798      	blx	r3
		_dma_set_destination_address(tx_ch, (void *)_spi_m_get_destination_for_dma(dev->prvt));
    31e0:	6828      	ldr	r0, [r5, #0]
    31e2:	4b10      	ldr	r3, [pc, #64]	; (3224 <_spi_m_dma_transfer+0x104>)
    31e4:	4798      	blx	r3
    31e6:	4601      	mov	r1, r0
    31e8:	4620      	mov	r0, r4
    31ea:	4b0b      	ldr	r3, [pc, #44]	; (3218 <_spi_m_dma_transfer+0xf8>)
    31ec:	4798      	blx	r3
		_dma_srcinc_enable(tx_ch, false);
    31ee:	2100      	movs	r1, #0
    31f0:	4620      	mov	r0, r4
    31f2:	4b0d      	ldr	r3, [pc, #52]	; (3228 <_spi_m_dma_transfer+0x108>)
    31f4:	4798      	blx	r3
		_dma_set_data_amount(tx_ch, length);
    31f6:	4639      	mov	r1, r7
    31f8:	4620      	mov	r0, r4
    31fa:	4b08      	ldr	r3, [pc, #32]	; (321c <_spi_m_dma_transfer+0xfc>)
    31fc:	4798      	blx	r3
    31fe:	e7d5      	b.n	31ac <_spi_m_dma_transfer+0x8c>
    3200:	00002d4d 	.word	0x00002d4d
    3204:	00002e2d 	.word	0x00002e2d
    3208:	00002dfd 	.word	0x00002dfd
    320c:	00002e81 	.word	0x00002e81
    3210:	00002df3 	.word	0x00002df3
    3214:	00002681 	.word	0x00002681
    3218:	00002671 	.word	0x00002671
    321c:	000026ad 	.word	0x000026ad
    3220:	00002705 	.word	0x00002705
    3224:	00002df7 	.word	0x00002df7
    3228:	00002691 	.word	0x00002691
    322c:	00003f20 	.word	0x00003f20
    3230:	00002eb5 	.word	0x00002eb5

00003234 <_tcc_init_irq_param>:
/**
 * \brief Init irq param with the given tcc hardware instance
 */
static void _tcc_init_irq_param(const void *const hw, void *dev)
{
	if (hw == TCC1) {
    3234:	4b03      	ldr	r3, [pc, #12]	; (3244 <_tcc_init_irq_param+0x10>)
    3236:	4298      	cmp	r0, r3
    3238:	d000      	beq.n	323c <_tcc_init_irq_param+0x8>
    323a:	4770      	bx	lr
		_tcc1_dev = (struct _pwm_device *)dev;
    323c:	4b02      	ldr	r3, [pc, #8]	; (3248 <_tcc_init_irq_param+0x14>)
    323e:	6019      	str	r1, [r3, #0]
	}
}
    3240:	e7fb      	b.n	323a <_tcc_init_irq_param+0x6>
    3242:	bf00      	nop
    3244:	41018000 	.word	0x41018000
    3248:	20000320 	.word	0x20000320

0000324c <tcc_pwm_interrupt_handler>:
 * \internal TC interrupt handler for PWM
 *
 * \param[in] instance TC instance number
 */
static void tcc_pwm_interrupt_handler(struct _pwm_device *device)
{
    324c:	b538      	push	{r3, r4, r5, lr}
    324e:	4605      	mov	r5, r0
	void *const hw = device->hw;
    3250:	6904      	ldr	r4, [r0, #16]
	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5;
}

static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw)
{
	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
    3252:	6ae3      	ldr	r3, [r4, #44]	; 0x2c

	if (hri_tcc_get_interrupt_OVF_bit(hw)) {
    3254:	f013 0f01 	tst.w	r3, #1
    3258:	d004      	beq.n	3264 <tcc_pwm_interrupt_handler+0x18>
}

static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw)
{
	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
    325a:	2301      	movs	r3, #1
    325c:	62e3      	str	r3, [r4, #44]	; 0x2c
		hri_tcc_clear_interrupt_OVF_bit(hw);
		if (NULL != device->callback.pwm_period_cb) {
    325e:	6803      	ldr	r3, [r0, #0]
    3260:	b103      	cbz	r3, 3264 <tcc_pwm_interrupt_handler+0x18>
			device->callback.pwm_period_cb(device);
    3262:	4798      	blx	r3
	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
}

static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw)
{
	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos;
    3264:	6aa3      	ldr	r3, [r4, #40]	; 0x28
		}
	}
	if (hri_tcc_get_INTEN_ERR_bit(hw)) {
    3266:	f013 0f08 	tst.w	r3, #8
    326a:	d005      	beq.n	3278 <tcc_pwm_interrupt_handler+0x2c>
	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
    326c:	2308      	movs	r3, #8
    326e:	62e3      	str	r3, [r4, #44]	; 0x2c
		hri_tcc_clear_interrupt_ERR_bit(hw);
		if (NULL != device->callback.pwm_error_cb) {
    3270:	686b      	ldr	r3, [r5, #4]
    3272:	b10b      	cbz	r3, 3278 <tcc_pwm_interrupt_handler+0x2c>
			device->callback.pwm_error_cb(device);
    3274:	4628      	mov	r0, r5
    3276:	4798      	blx	r3
    3278:	bd38      	pop	{r3, r4, r5, pc}
	...

0000327c <_get_tcc_cfg>:

static struct tcc_cfg *_get_tcc_cfg(void *hw)
{
	uint8_t i;

	for (i = 0; i < ARRAY_SIZE(_cfgs); i++) {
    327c:	2300      	movs	r3, #0
    327e:	b13b      	cbz	r3, 3290 <_get_tcc_cfg+0x14>
		if (_cfgs[i].hw == hw) {
			return &(_cfgs[i]);
		}
	}
	return NULL;
    3280:	2000      	movs	r0, #0
    3282:	4770      	bx	lr
			return &(_cfgs[i]);
    3284:	eb03 0443 	add.w	r4, r3, r3, lsl #1
    3288:	0123      	lsls	r3, r4, #4
    328a:	4608      	mov	r0, r1
    328c:	4418      	add	r0, r3
    328e:	e00c      	b.n	32aa <_get_tcc_cfg+0x2e>
{
    3290:	b410      	push	{r4}
		if (_cfgs[i].hw == hw) {
    3292:	eb03 0143 	add.w	r1, r3, r3, lsl #1
    3296:	010a      	lsls	r2, r1, #4
    3298:	4905      	ldr	r1, [pc, #20]	; (32b0 <_get_tcc_cfg+0x34>)
    329a:	588a      	ldr	r2, [r1, r2]
    329c:	4282      	cmp	r2, r0
    329e:	d0f1      	beq.n	3284 <_get_tcc_cfg+0x8>
	for (i = 0; i < ARRAY_SIZE(_cfgs); i++) {
    32a0:	3301      	adds	r3, #1
    32a2:	b2db      	uxtb	r3, r3
    32a4:	2b00      	cmp	r3, #0
    32a6:	d0f4      	beq.n	3292 <_get_tcc_cfg+0x16>
	return NULL;
    32a8:	2000      	movs	r0, #0
}
    32aa:	f85d 4b04 	ldr.w	r4, [sp], #4
    32ae:	4770      	bx	lr
    32b0:	20000078 	.word	0x20000078

000032b4 <_get_tcc_pwm_cfg>:

static struct tcc_pwm_cfg *_get_tcc_pwm_cfg(void *hw)
{
	uint8_t i;

	for (i = 0; i < ARRAY_SIZE(_cfgs_pwm); i++) {
    32b4:	2300      	movs	r3, #0
    32b6:	b123      	cbz	r3, 32c2 <_get_tcc_pwm_cfg+0xe>
		if (_cfgs_pwm[i].hw == hw) {
			return &(_cfgs_pwm[i]);
		}
	}
	return NULL;
    32b8:	2000      	movs	r0, #0
    32ba:	4770      	bx	lr
			return &(_cfgs_pwm[i]);
    32bc:	4809      	ldr	r0, [pc, #36]	; (32e4 <_get_tcc_pwm_cfg+0x30>)
    32be:	4408      	add	r0, r1
    32c0:	e00d      	b.n	32de <_get_tcc_pwm_cfg+0x2a>
{
    32c2:	b410      	push	{r4}
		if (_cfgs_pwm[i].hw == hw) {
    32c4:	eb03 0283 	add.w	r2, r3, r3, lsl #2
    32c8:	0091      	lsls	r1, r2, #2
    32ca:	4a07      	ldr	r2, [pc, #28]	; (32e8 <_get_tcc_pwm_cfg+0x34>)
    32cc:	440a      	add	r2, r1
    32ce:	6b12      	ldr	r2, [r2, #48]	; 0x30
    32d0:	4282      	cmp	r2, r0
    32d2:	d0f3      	beq.n	32bc <_get_tcc_pwm_cfg+0x8>
	for (i = 0; i < ARRAY_SIZE(_cfgs_pwm); i++) {
    32d4:	3301      	adds	r3, #1
    32d6:	b2db      	uxtb	r3, r3
    32d8:	2b00      	cmp	r3, #0
    32da:	d0f3      	beq.n	32c4 <_get_tcc_pwm_cfg+0x10>
	return NULL;
    32dc:	2000      	movs	r0, #0
}
    32de:	f85d 4b04 	ldr.w	r4, [sp], #4
    32e2:	4770      	bx	lr
    32e4:	200000a8 	.word	0x200000a8
    32e8:	20000078 	.word	0x20000078

000032ec <_pwm_init>:
{
    32ec:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    32ee:	4607      	mov	r7, r0
    32f0:	460c      	mov	r4, r1
	struct tcc_cfg *cfg = _get_tcc_cfg(hw);
    32f2:	4608      	mov	r0, r1
    32f4:	4b60      	ldr	r3, [pc, #384]	; (3478 <_pwm_init+0x18c>)
    32f6:	4798      	blx	r3
	if (cfg == NULL) {
    32f8:	2800      	cmp	r0, #0
    32fa:	f000 80b2 	beq.w	3462 <_pwm_init+0x176>
    32fe:	4606      	mov	r6, r0
	struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
    3300:	4620      	mov	r0, r4
    3302:	4b5e      	ldr	r3, [pc, #376]	; (347c <_pwm_init+0x190>)
    3304:	4798      	blx	r3
	if (cfg_pwm == NULL) {
    3306:	4605      	mov	r5, r0
    3308:	2800      	cmp	r0, #0
    330a:	f000 80ad 	beq.w	3468 <_pwm_init+0x17c>
	device->hw = hw;
    330e:	613c      	str	r4, [r7, #16]
	return ((Tcc *)hw)->SYNCBUSY.reg & reg;
    3310:	68a3      	ldr	r3, [r4, #8]
	if (!hri_tcc_is_syncing(hw, TCC_SYNCBUSY_SWRST)) {
    3312:	f013 0f01 	tst.w	r3, #1
    3316:	d119      	bne.n	334c <_pwm_init+0x60>
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    3318:	68a3      	ldr	r3, [r4, #8]
    331a:	f013 0f03 	tst.w	r3, #3
    331e:	d1fb      	bne.n	3318 <_pwm_init+0x2c>

static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
{
	uint32_t tmp;
	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
	tmp = ((Tcc *)hw)->CTRLA.reg;
    3320:	6823      	ldr	r3, [r4, #0]
		if (hri_tcc_get_CTRLA_reg(hw, TCC_CTRLA_ENABLE)) {
    3322:	f013 0f02 	tst.w	r3, #2
    3326:	d00b      	beq.n	3340 <_pwm_init+0x54>
	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE;
    3328:	6823      	ldr	r3, [r4, #0]
    332a:	f023 0302 	bic.w	r3, r3, #2
    332e:	6023      	str	r3, [r4, #0]
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    3330:	68a3      	ldr	r3, [r4, #8]
    3332:	f013 0f03 	tst.w	r3, #3
    3336:	d1fb      	bne.n	3330 <_pwm_init+0x44>
    3338:	68a3      	ldr	r3, [r4, #8]
    333a:	f013 0f02 	tst.w	r3, #2
    333e:	d1fb      	bne.n	3338 <_pwm_init+0x4c>
}

static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data)
{
	TCC_CRITICAL_SECTION_ENTER();
	((Tcc *)hw)->CTRLA.reg = data;
    3340:	2301      	movs	r3, #1
    3342:	6023      	str	r3, [r4, #0]
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    3344:	68a3      	ldr	r3, [r4, #8]
    3346:	f013 0f03 	tst.w	r3, #3
    334a:	d1fb      	bne.n	3344 <_pwm_init+0x58>
    334c:	68a3      	ldr	r3, [r4, #8]
    334e:	f013 0f01 	tst.w	r3, #1
    3352:	d1fb      	bne.n	334c <_pwm_init+0x60>
	hri_tcc_write_CTRLA_reg(hw, cfg->ctrl_a);
    3354:	68b3      	ldr	r3, [r6, #8]
	((Tcc *)hw)->CTRLA.reg = data;
    3356:	6023      	str	r3, [r4, #0]
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    3358:	68a3      	ldr	r3, [r4, #8]
    335a:	f013 0f03 	tst.w	r3, #3
    335e:	d1fb      	bne.n	3358 <_pwm_init+0x6c>
	hri_tcc_set_CTRLB_reg(hw, cfg->ctrl_b);
    3360:	7b33      	ldrb	r3, [r6, #12]
	((Tcc *)hw)->CTRLBSET.reg = mask;
    3362:	7163      	strb	r3, [r4, #5]
	hri_tcc_write_DBGCTRL_reg(hw, cfg->dbg_ctrl);
    3364:	7b73      	ldrb	r3, [r6, #13]
}

static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data)
{
	TCC_CRITICAL_SECTION_ENTER();
	((Tcc *)hw)->DBGCTRL.reg = data;
    3366:	77a3      	strb	r3, [r4, #30]
	hri_tcc_write_EVCTRL_reg(hw, cfg->event_ctrl);
    3368:	6933      	ldr	r3, [r6, #16]
}

static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data)
{
	TCC_CRITICAL_SECTION_ENTER();
	((Tcc *)hw)->EVCTRL.reg = data;
    336a:	6223      	str	r3, [r4, #32]
	hri_tcc_write_WAVE_reg(hw, cfg_pwm->wave);
    336c:	692b      	ldr	r3, [r5, #16]
}

static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data)
{
	TCC_CRITICAL_SECTION_ENTER();
	((Tcc *)hw)->WAVE.reg = data;
    336e:	63e3      	str	r3, [r4, #60]	; 0x3c
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    3370:	68a3      	ldr	r3, [r4, #8]
    3372:	f3c3 030d 	ubfx	r3, r3, #0, #14
    3376:	2b00      	cmp	r3, #0
    3378:	d1fa      	bne.n	3370 <_pwm_init+0x84>
	hri_tcc_write_PER_reg(hw, cfg_pwm->period);
    337a:	68ab      	ldr	r3, [r5, #8]
}

static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data)
{
	TCC_CRITICAL_SECTION_ENTER();
	((Tcc *)hw)->PER.reg = data;
    337c:	6423      	str	r3, [r4, #64]	; 0x40
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    337e:	68a3      	ldr	r3, [r4, #8]
    3380:	f013 0f80 	tst.w	r3, #128	; 0x80
    3384:	d1fb      	bne.n	337e <_pwm_init+0x92>
	cfg->per = cfg_pwm->period;
    3386:	68ab      	ldr	r3, [r5, #8]
    3388:	62f3      	str	r3, [r6, #44]	; 0x2c
	switch (cfg_pwm->sel_ch) {
    338a:	79ab      	ldrb	r3, [r5, #6]
    338c:	2b05      	cmp	r3, #5
    338e:	d86e      	bhi.n	346e <_pwm_init+0x182>
    3390:	e8df f003 	tbb	[pc, r3]
    3394:	4f473f03 	.word	0x4f473f03
    3398:	5f57      	.short	0x5f57
		cfg->cc0 = cfg_pwm->duty_cycle;
    339a:	68eb      	ldr	r3, [r5, #12]
    339c:	6173      	str	r3, [r6, #20]
}

static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
{
	TCC_CRITICAL_SECTION_ENTER();
	((Tcc *)hw)->CC[index].reg = data;
    339e:	6463      	str	r3, [r4, #68]	; 0x44
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    33a0:	68a3      	ldr	r3, [r4, #8]
    33a2:	f413 5f7c 	tst.w	r3, #16128	; 0x3f00
    33a6:	d1fb      	bne.n	33a0 <_pwm_init+0xb4>
	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
    33a8:	2302      	movs	r3, #2
    33aa:	7123      	strb	r3, [r4, #4]
	_tcc_init_irq_param(hw, (void *)device);
    33ac:	4639      	mov	r1, r7
    33ae:	4620      	mov	r0, r4
    33b0:	4b33      	ldr	r3, [pc, #204]	; (3480 <_pwm_init+0x194>)
    33b2:	4798      	blx	r3
	NVIC_DisableIRQ((IRQn_Type)cfg_pwm->irq);
    33b4:	f9b5 3004 	ldrsh.w	r3, [r5, #4]
  if ((int32_t)(IRQn) >= 0)
    33b8:	2b00      	cmp	r3, #0
    33ba:	db0d      	blt.n	33d8 <_pwm_init+0xec>
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    33bc:	095a      	lsrs	r2, r3, #5
    33be:	f003 031f 	and.w	r3, r3, #31
    33c2:	2101      	movs	r1, #1
    33c4:	fa01 f303 	lsl.w	r3, r1, r3
    33c8:	3220      	adds	r2, #32
    33ca:	492e      	ldr	r1, [pc, #184]	; (3484 <_pwm_init+0x198>)
    33cc:	f841 3022 	str.w	r3, [r1, r2, lsl #2]
  __ASM volatile ("dsb 0xF":::"memory");
    33d0:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    33d4:	f3bf 8f6f 	isb	sy
	NVIC_ClearPendingIRQ((IRQn_Type)cfg_pwm->irq);
    33d8:	f9b5 3004 	ldrsh.w	r3, [r5, #4]
  if ((int32_t)(IRQn) >= 0)
    33dc:	2b00      	cmp	r3, #0
    33de:	db09      	blt.n	33f4 <_pwm_init+0x108>
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    33e0:	095a      	lsrs	r2, r3, #5
    33e2:	f003 031f 	and.w	r3, r3, #31
    33e6:	2101      	movs	r1, #1
    33e8:	fa01 f303 	lsl.w	r3, r1, r3
    33ec:	3260      	adds	r2, #96	; 0x60
    33ee:	4925      	ldr	r1, [pc, #148]	; (3484 <_pwm_init+0x198>)
    33f0:	f841 3022 	str.w	r3, [r1, r2, lsl #2]
	NVIC_EnableIRQ((IRQn_Type)cfg_pwm->irq);
    33f4:	f9b5 3004 	ldrsh.w	r3, [r5, #4]
  if ((int32_t)(IRQn) >= 0)
    33f8:	2b00      	cmp	r3, #0
    33fa:	db3b      	blt.n	3474 <_pwm_init+0x188>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    33fc:	0959      	lsrs	r1, r3, #5
    33fe:	f003 031f 	and.w	r3, r3, #31
    3402:	2201      	movs	r2, #1
    3404:	fa02 f303 	lsl.w	r3, r2, r3
    3408:	4a1e      	ldr	r2, [pc, #120]	; (3484 <_pwm_init+0x198>)
    340a:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
	return ERR_NONE;
    340e:	2000      	movs	r0, #0
    3410:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		cfg->cc1 = cfg_pwm->duty_cycle;
    3412:	68eb      	ldr	r3, [r5, #12]
    3414:	61b3      	str	r3, [r6, #24]
	((Tcc *)hw)->CC[index].reg = data;
    3416:	64a3      	str	r3, [r4, #72]	; 0x48
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    3418:	68a3      	ldr	r3, [r4, #8]
    341a:	f413 5f7c 	tst.w	r3, #16128	; 0x3f00
    341e:	d1fb      	bne.n	3418 <_pwm_init+0x12c>
    3420:	e7c2      	b.n	33a8 <_pwm_init+0xbc>
		cfg->cc2 = cfg_pwm->duty_cycle;
    3422:	68eb      	ldr	r3, [r5, #12]
    3424:	61f3      	str	r3, [r6, #28]
	((Tcc *)hw)->CC[index].reg = data;
    3426:	64e3      	str	r3, [r4, #76]	; 0x4c
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    3428:	68a3      	ldr	r3, [r4, #8]
    342a:	f413 5f7c 	tst.w	r3, #16128	; 0x3f00
    342e:	d1fb      	bne.n	3428 <_pwm_init+0x13c>
    3430:	e7ba      	b.n	33a8 <_pwm_init+0xbc>
		cfg->cc3 = cfg_pwm->duty_cycle;
    3432:	68eb      	ldr	r3, [r5, #12]
    3434:	6233      	str	r3, [r6, #32]
	((Tcc *)hw)->CC[index].reg = data;
    3436:	6523      	str	r3, [r4, #80]	; 0x50
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    3438:	68a3      	ldr	r3, [r4, #8]
    343a:	f413 5f7c 	tst.w	r3, #16128	; 0x3f00
    343e:	d1fb      	bne.n	3438 <_pwm_init+0x14c>
    3440:	e7b2      	b.n	33a8 <_pwm_init+0xbc>
		cfg->cc4 = cfg_pwm->duty_cycle;
    3442:	68eb      	ldr	r3, [r5, #12]
    3444:	6273      	str	r3, [r6, #36]	; 0x24
	((Tcc *)hw)->CC[index].reg = data;
    3446:	6563      	str	r3, [r4, #84]	; 0x54
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    3448:	68a3      	ldr	r3, [r4, #8]
    344a:	f413 5f7c 	tst.w	r3, #16128	; 0x3f00
    344e:	d1fb      	bne.n	3448 <_pwm_init+0x15c>
    3450:	e7aa      	b.n	33a8 <_pwm_init+0xbc>
		cfg->cc5 = cfg_pwm->duty_cycle;
    3452:	68eb      	ldr	r3, [r5, #12]
    3454:	62b3      	str	r3, [r6, #40]	; 0x28
	((Tcc *)hw)->CC[index].reg = data;
    3456:	65a3      	str	r3, [r4, #88]	; 0x58
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    3458:	68a3      	ldr	r3, [r4, #8]
    345a:	f413 5f7c 	tst.w	r3, #16128	; 0x3f00
    345e:	d1fb      	bne.n	3458 <_pwm_init+0x16c>
    3460:	e7a2      	b.n	33a8 <_pwm_init+0xbc>
		return ERR_NOT_FOUND;
    3462:	f06f 0009 	mvn.w	r0, #9
    3466:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		return ERR_NOT_FOUND;
    3468:	f06f 0009 	mvn.w	r0, #9
    346c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		return ERR_NO_RESOURCE;
    346e:	f06f 001b 	mvn.w	r0, #27
    3472:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	return ERR_NONE;
    3474:	2000      	movs	r0, #0
}
    3476:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    3478:	0000327d 	.word	0x0000327d
    347c:	000032b5 	.word	0x000032b5
    3480:	00003235 	.word	0x00003235
    3484:	e000e100 	.word	0xe000e100

00003488 <_pwm_enable>:
	hri_tcc_set_CTRLA_ENABLE_bit(device->hw);
    3488:	6902      	ldr	r2, [r0, #16]
	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE;
    348a:	6813      	ldr	r3, [r2, #0]
    348c:	f043 0302 	orr.w	r3, r3, #2
    3490:	6013      	str	r3, [r2, #0]
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    3492:	6893      	ldr	r3, [r2, #8]
    3494:	f013 0f03 	tst.w	r3, #3
    3498:	d1fb      	bne.n	3492 <_pwm_enable+0xa>
}
    349a:	4770      	bx	lr

0000349c <_pwm_is_enabled>:
	return hri_tcc_get_CTRLA_ENABLE_bit(device->hw);
    349c:	6902      	ldr	r2, [r0, #16]
    349e:	6893      	ldr	r3, [r2, #8]
    34a0:	f013 0f03 	tst.w	r3, #3
    34a4:	d1fb      	bne.n	349e <_pwm_is_enabled+0x2>
	tmp = ((Tcc *)hw)->CTRLA.reg;
    34a6:	6810      	ldr	r0, [r2, #0]
	tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos;
    34a8:	f3c0 0040 	ubfx	r0, r0, #1, #1
}
    34ac:	4770      	bx	lr
	...

000034b0 <_pwm_set_irq_state>:
{
    34b0:	b570      	push	{r4, r5, r6, lr}
    34b2:	460c      	mov	r4, r1
    34b4:	4615      	mov	r5, r2
	ASSERT(device);
    34b6:	4606      	mov	r6, r0
    34b8:	f44f 728e 	mov.w	r2, #284	; 0x11c
    34bc:	490c      	ldr	r1, [pc, #48]	; (34f0 <_pwm_set_irq_state+0x40>)
    34be:	3000      	adds	r0, #0
    34c0:	bf18      	it	ne
    34c2:	2001      	movne	r0, #1
    34c4:	4b0b      	ldr	r3, [pc, #44]	; (34f4 <_pwm_set_irq_state+0x44>)
    34c6:	4798      	blx	r3
	if (PWM_DEVICE_PERIOD_CB == type) {
    34c8:	b93c      	cbnz	r4, 34da <_pwm_set_irq_state+0x2a>
		hri_tcc_write_INTEN_OVF_bit(device->hw, disable);
    34ca:	6933      	ldr	r3, [r6, #16]
	if (value == 0x0) {
    34cc:	b915      	cbnz	r5, 34d4 <_pwm_set_irq_state+0x24>
		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
    34ce:	2201      	movs	r2, #1
    34d0:	625a      	str	r2, [r3, #36]	; 0x24
    34d2:	bd70      	pop	{r4, r5, r6, pc}
		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
    34d4:	2201      	movs	r2, #1
    34d6:	629a      	str	r2, [r3, #40]	; 0x28
    34d8:	bd70      	pop	{r4, r5, r6, pc}
	} else if (PWM_DEVICE_ERROR_CB == type) {
    34da:	2c01      	cmp	r4, #1
    34dc:	d000      	beq.n	34e0 <_pwm_set_irq_state+0x30>
    34de:	bd70      	pop	{r4, r5, r6, pc}
		hri_tcc_write_INTEN_ERR_bit(device->hw, disable);
    34e0:	6933      	ldr	r3, [r6, #16]
	if (value == 0x0) {
    34e2:	b115      	cbz	r5, 34ea <_pwm_set_irq_state+0x3a>
		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
    34e4:	2208      	movs	r2, #8
    34e6:	629a      	str	r2, [r3, #40]	; 0x28
}
    34e8:	e7f9      	b.n	34de <_pwm_set_irq_state+0x2e>
		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
    34ea:	2208      	movs	r2, #8
    34ec:	625a      	str	r2, [r3, #36]	; 0x24
    34ee:	bd70      	pop	{r4, r5, r6, pc}
    34f0:	00003f50 	.word	0x00003f50
    34f4:	00001e9d 	.word	0x00001e9d

000034f8 <_tcc_get_pwm>:
}
    34f8:	2000      	movs	r0, #0
    34fa:	4770      	bx	lr

000034fc <TCC1_0_Handler>:
{
    34fc:	b508      	push	{r3, lr}
	tcc_pwm_interrupt_handler(_tcc1_dev);
    34fe:	4b02      	ldr	r3, [pc, #8]	; (3508 <TCC1_0_Handler+0xc>)
    3500:	6818      	ldr	r0, [r3, #0]
    3502:	4b02      	ldr	r3, [pc, #8]	; (350c <TCC1_0_Handler+0x10>)
    3504:	4798      	blx	r3
    3506:	bd08      	pop	{r3, pc}
    3508:	20000320 	.word	0x20000320
    350c:	0000324d 	.word	0x0000324d

00003510 <TC_SPEED_init>:
	return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg;
    3510:	4b24      	ldr	r3, [pc, #144]	; (35a4 <TC_SPEED_init+0x94>)
    3512:	691b      	ldr	r3, [r3, #16]
 * \brief Initialize TC interface
 */
int8_t TC_SPEED_init()
{

	if (!hri_tc_is_syncing(TC0, TC_SYNCBUSY_SWRST)) {
    3514:	f013 0f01 	tst.w	r3, #1
    3518:	d120      	bne.n	355c <TC_SPEED_init+0x4c>
	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
    351a:	4b22      	ldr	r3, [pc, #136]	; (35a4 <TC_SPEED_init+0x94>)
    351c:	691b      	ldr	r3, [r3, #16]
    351e:	f013 0f03 	tst.w	r3, #3
    3522:	d1fa      	bne.n	351a <TC_SPEED_init+0xa>
	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
    3524:	4b1f      	ldr	r3, [pc, #124]	; (35a4 <TC_SPEED_init+0x94>)
    3526:	681b      	ldr	r3, [r3, #0]
		if (hri_tc_get_CTRLA_reg(TC0, TC_CTRLA_ENABLE)) {
    3528:	f013 0f02 	tst.w	r3, #2
    352c:	d00e      	beq.n	354c <TC_SPEED_init+0x3c>
	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
    352e:	4a1d      	ldr	r2, [pc, #116]	; (35a4 <TC_SPEED_init+0x94>)
    3530:	6813      	ldr	r3, [r2, #0]
    3532:	f023 0302 	bic.w	r3, r3, #2
    3536:	6013      	str	r3, [r2, #0]
	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
    3538:	4b1a      	ldr	r3, [pc, #104]	; (35a4 <TC_SPEED_init+0x94>)
    353a:	691b      	ldr	r3, [r3, #16]
    353c:	f013 0f03 	tst.w	r3, #3
    3540:	d1fa      	bne.n	3538 <TC_SPEED_init+0x28>
    3542:	4b18      	ldr	r3, [pc, #96]	; (35a4 <TC_SPEED_init+0x94>)
    3544:	691b      	ldr	r3, [r3, #16]
    3546:	f013 0f02 	tst.w	r3, #2
    354a:	d1fa      	bne.n	3542 <TC_SPEED_init+0x32>
	((Tc *)hw)->COUNT16.CTRLA.reg = data;
    354c:	2201      	movs	r2, #1
    354e:	4b15      	ldr	r3, [pc, #84]	; (35a4 <TC_SPEED_init+0x94>)
    3550:	601a      	str	r2, [r3, #0]
	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
    3552:	4b14      	ldr	r3, [pc, #80]	; (35a4 <TC_SPEED_init+0x94>)
    3554:	691b      	ldr	r3, [r3, #16]
    3556:	f013 0f03 	tst.w	r3, #3
    355a:	d1fa      	bne.n	3552 <TC_SPEED_init+0x42>
    355c:	4b11      	ldr	r3, [pc, #68]	; (35a4 <TC_SPEED_init+0x94>)
    355e:	691b      	ldr	r3, [r3, #16]
    3560:	f013 0f01 	tst.w	r3, #1
    3564:	d1fa      	bne.n	355c <TC_SPEED_init+0x4c>
	((Tc *)hw)->COUNT16.CTRLA.reg = data;
    3566:	4a10      	ldr	r2, [pc, #64]	; (35a8 <TC_SPEED_init+0x98>)
    3568:	4b0e      	ldr	r3, [pc, #56]	; (35a4 <TC_SPEED_init+0x94>)
    356a:	601a      	str	r2, [r3, #0]
	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
    356c:	4b0d      	ldr	r3, [pc, #52]	; (35a4 <TC_SPEED_init+0x94>)
    356e:	691b      	ldr	r3, [r3, #16]
    3570:	f013 0f03 	tst.w	r3, #3
    3574:	d1fa      	bne.n	356c <TC_SPEED_init+0x5c>
	((Tc *)hw)->COUNT16.CTRLBSET.reg = data;
    3576:	4b0b      	ldr	r3, [pc, #44]	; (35a4 <TC_SPEED_init+0x94>)
    3578:	2200      	movs	r2, #0
    357a:	715a      	strb	r2, [r3, #5]
	((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data;
    357c:	22ff      	movs	r2, #255	; 0xff
    357e:	711a      	strb	r2, [r3, #4]
	((Tc *)hw)->COUNT16.EVCTRL.reg = data;
    3580:	f240 1225 	movw	r2, #293	; 0x125
    3584:	80da      	strh	r2, [r3, #6]
	((Tc *)hw)->COUNT16.INTENSET.reg = data;
    3586:	2201      	movs	r2, #1
    3588:	725a      	strb	r2, [r3, #9]
	((Tc *)hw)->COUNT16.INTENCLR.reg = ~data;
    358a:	22fe      	movs	r2, #254	; 0xfe
    358c:	721a      	strb	r2, [r3, #8]
	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
    358e:	681a      	ldr	r2, [r3, #0]
	tmp |= value << TC_CTRLA_ENABLE_Pos;
    3590:	f042 0202 	orr.w	r2, r2, #2
	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
    3594:	601a      	str	r2, [r3, #0]
	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
    3596:	4b03      	ldr	r3, [pc, #12]	; (35a4 <TC_SPEED_init+0x94>)
    3598:	691b      	ldr	r3, [r3, #16]
    359a:	f013 0f03 	tst.w	r3, #3
    359e:	d1fa      	bne.n	3596 <TC_SPEED_init+0x86>
	                           | 1 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: enabled */

	hri_tc_write_CTRLA_ENABLE_bit(TC0, 1 << TC_CTRLA_ENABLE_Pos); /* Enable: enabled */

	return 0;
}
    35a0:	2000      	movs	r0, #0
    35a2:	4770      	bx	lr
    35a4:	40003800 	.word	0x40003800
    35a8:	00030208 	.word	0x00030208

000035ac <TC_ECAT_init>:
	return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg;
    35ac:	4b29      	ldr	r3, [pc, #164]	; (3654 <TC_ECAT_init+0xa8>)
    35ae:	691b      	ldr	r3, [r3, #16]
 * \brief Initialize TC interface
 */
int8_t TC_ECAT_init()
{

	if (!hri_tc_is_syncing(TC7, TC_SYNCBUSY_SWRST)) {
    35b0:	f013 0f01 	tst.w	r3, #1
    35b4:	d120      	bne.n	35f8 <TC_ECAT_init+0x4c>
	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
    35b6:	4b27      	ldr	r3, [pc, #156]	; (3654 <TC_ECAT_init+0xa8>)
    35b8:	691b      	ldr	r3, [r3, #16]
    35ba:	f013 0f03 	tst.w	r3, #3
    35be:	d1fa      	bne.n	35b6 <TC_ECAT_init+0xa>
	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
    35c0:	4b24      	ldr	r3, [pc, #144]	; (3654 <TC_ECAT_init+0xa8>)
    35c2:	681b      	ldr	r3, [r3, #0]
		if (hri_tc_get_CTRLA_reg(TC7, TC_CTRLA_ENABLE)) {
    35c4:	f013 0f02 	tst.w	r3, #2
    35c8:	d00e      	beq.n	35e8 <TC_ECAT_init+0x3c>
	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
    35ca:	4a22      	ldr	r2, [pc, #136]	; (3654 <TC_ECAT_init+0xa8>)
    35cc:	6813      	ldr	r3, [r2, #0]
    35ce:	f023 0302 	bic.w	r3, r3, #2
    35d2:	6013      	str	r3, [r2, #0]
	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
    35d4:	4b1f      	ldr	r3, [pc, #124]	; (3654 <TC_ECAT_init+0xa8>)
    35d6:	691b      	ldr	r3, [r3, #16]
    35d8:	f013 0f03 	tst.w	r3, #3
    35dc:	d1fa      	bne.n	35d4 <TC_ECAT_init+0x28>
    35de:	4b1d      	ldr	r3, [pc, #116]	; (3654 <TC_ECAT_init+0xa8>)
    35e0:	691b      	ldr	r3, [r3, #16]
    35e2:	f013 0f02 	tst.w	r3, #2
    35e6:	d1fa      	bne.n	35de <TC_ECAT_init+0x32>
	((Tc *)hw)->COUNT16.CTRLA.reg = data;
    35e8:	2201      	movs	r2, #1
    35ea:	4b1a      	ldr	r3, [pc, #104]	; (3654 <TC_ECAT_init+0xa8>)
    35ec:	601a      	str	r2, [r3, #0]
	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
    35ee:	4b19      	ldr	r3, [pc, #100]	; (3654 <TC_ECAT_init+0xa8>)
    35f0:	691b      	ldr	r3, [r3, #16]
    35f2:	f013 0f03 	tst.w	r3, #3
    35f6:	d1fa      	bne.n	35ee <TC_ECAT_init+0x42>
    35f8:	4b16      	ldr	r3, [pc, #88]	; (3654 <TC_ECAT_init+0xa8>)
    35fa:	691b      	ldr	r3, [r3, #16]
    35fc:	f013 0f01 	tst.w	r3, #1
    3600:	d1fa      	bne.n	35f8 <TC_ECAT_init+0x4c>
	((Tc *)hw)->COUNT16.CTRLA.reg = data;
    3602:	f44f 7200 	mov.w	r2, #512	; 0x200
    3606:	4b13      	ldr	r3, [pc, #76]	; (3654 <TC_ECAT_init+0xa8>)
    3608:	601a      	str	r2, [r3, #0]
	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
    360a:	4b12      	ldr	r3, [pc, #72]	; (3654 <TC_ECAT_init+0xa8>)
    360c:	691b      	ldr	r3, [r3, #16]
    360e:	f013 0f03 	tst.w	r3, #3
    3612:	d1fa      	bne.n	360a <TC_ECAT_init+0x5e>
	((Tc *)hw)->COUNT16.CTRLBSET.reg = data;
    3614:	4b0f      	ldr	r3, [pc, #60]	; (3654 <TC_ECAT_init+0xa8>)
    3616:	2200      	movs	r2, #0
    3618:	715a      	strb	r2, [r3, #5]
	((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data;
    361a:	22ff      	movs	r2, #255	; 0xff
    361c:	711a      	strb	r2, [r3, #4]
	((Tc *)hw)->COUNT16.WAVE.reg = data;
    361e:	2201      	movs	r2, #1
    3620:	731a      	strb	r2, [r3, #12]
	((Tc *)hw)->COUNT32.CC[index].reg = data;
    3622:	f246 12a8 	movw	r2, #25000	; 0x61a8
    3626:	61da      	str	r2, [r3, #28]
	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
    3628:	4b0a      	ldr	r3, [pc, #40]	; (3654 <TC_ECAT_init+0xa8>)
    362a:	691b      	ldr	r3, [r3, #16]
    362c:	f013 0fc0 	tst.w	r3, #192	; 0xc0
    3630:	d1fa      	bne.n	3628 <TC_ECAT_init+0x7c>
	((Tc *)hw)->COUNT16.INTENSET.reg = data;
    3632:	4b08      	ldr	r3, [pc, #32]	; (3654 <TC_ECAT_init+0xa8>)
    3634:	2201      	movs	r2, #1
    3636:	725a      	strb	r2, [r3, #9]
	((Tc *)hw)->COUNT16.INTENCLR.reg = ~data;
    3638:	22fe      	movs	r2, #254	; 0xfe
    363a:	721a      	strb	r2, [r3, #8]
	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
    363c:	681a      	ldr	r2, [r3, #0]
	tmp |= value << TC_CTRLA_ENABLE_Pos;
    363e:	f042 0202 	orr.w	r2, r2, #2
	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
    3642:	601a      	str	r2, [r3, #0]
	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
    3644:	4b03      	ldr	r3, [pc, #12]	; (3654 <TC_ECAT_init+0xa8>)
    3646:	691b      	ldr	r3, [r3, #16]
    3648:	f013 0f03 	tst.w	r3, #3
    364c:	d1fa      	bne.n	3644 <TC_ECAT_init+0x98>
	                           | 1 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: enabled */

	hri_tc_write_CTRLA_ENABLE_bit(TC7, 1 << TC_CTRLA_ENABLE_Pos); /* Enable: enabled */

	return 0;
}
    364e:	2000      	movs	r0, #0
    3650:	4770      	bx	lr
    3652:	bf00      	nop
    3654:	43001800 	.word	0x43001800

00003658 <adc_cb>:
// ----------------------------------------------------------------------
// 	ADC Callback for Motor Phase Current Measurement.  
// Phase A & B Sampled and converted from LSB to Process Unit PU(Amps)
// ----------------------------------------------------------------------
static void adc_cb(const struct adc_async_descriptor *const descr, const uint8_t channel)
{
    3658:	b410      	push	{r4}
    365a:	b083      	sub	sp, #12
	gpio_set_pin_level(pin, false);
}

inline void tic_port(const uint32_t port)
{
	REG_PORT_OUTSET2 = port;
    365c:	2408      	movs	r4, #8
    365e:	4b23      	ldr	r3, [pc, #140]	; (36ec <adc_cb+0x94>)
    3660:	601c      	str	r4, [r3, #0]
		else(*phase_filtered_pu = (float32_t)(*phase * ADC_LSB_SIZE * ONEON_CURRENT_SENSOR_SENSITIVITY));
		*/
		
		*phase_filtered_pu = (float32_t)(*phase * ADC_LSB_SIZE * ONEON_CURRENT_SENSOR_SENSITIVITY);
	}
	volatile int16_t phase_A_current_raw = hri_adc_read_RESULT_reg(descr->device.hw) - Motor1.Voffset_lsb.A;  //Read ADC 0
    3662:	6943      	ldr	r3, [r0, #20]
	return ((Adc *)hw)->RESULT.reg;
    3664:	f8b3 2040 	ldrh.w	r2, [r3, #64]	; 0x40
    3668:	b292      	uxth	r2, r2
    366a:	4b21      	ldr	r3, [pc, #132]	; (36f0 <adc_cb+0x98>)
    366c:	8d99      	ldrh	r1, [r3, #44]	; 0x2c
    366e:	b289      	uxth	r1, r1
    3670:	1a52      	subs	r2, r2, r1
    3672:	b212      	sxth	r2, r2
    3674:	f8ad 2006 	strh.w	r2, [sp, #6]
	volatile int16_t phase_B_current_raw = (hri_adc_read_RESULT_reg(ADC1) - Motor1.Voffset_lsb.B)*-1;	//Ib is connected backwards //Read ADC 1, synced with ADC0
    3678:	8dda      	ldrh	r2, [r3, #46]	; 0x2e
    367a:	b292      	uxth	r2, r2
    367c:	491d      	ldr	r1, [pc, #116]	; (36f4 <adc_cb+0x9c>)
    367e:	f8b1 1040 	ldrh.w	r1, [r1, #64]	; 0x40
    3682:	b289      	uxth	r1, r1
    3684:	1a52      	subs	r2, r2, r1
    3686:	b212      	sxth	r2, r2
    3688:	f8ad 2004 	strh.w	r2, [sp, #4]
		*phase_filtered_pu = (float32_t)(*phase * ADC_LSB_SIZE * ONEON_CURRENT_SENSOR_SENSITIVITY);
    368c:	f9bd 2006 	ldrsh.w	r2, [sp, #6]
    3690:	ee07 2a10 	vmov	s14, r2
    3694:	eeb8 7ac7 	vcvt.f32.s32	s14, s14
    3698:	ed9f 6a17 	vldr	s12, [pc, #92]	; 36f8 <adc_cb+0xa0>
    369c:	ee27 7a06 	vmul.f32	s14, s14, s12
    36a0:	eef0 6a04 	vmov.f32	s13, #4	; 0x40200000  2.5
    36a4:	ee27 7a26 	vmul.f32	s14, s14, s13
    36a8:	ed83 7a07 	vstr	s14, [r3, #28]
    36ac:	f9bd 2004 	ldrsh.w	r2, [sp, #4]
    36b0:	ee07 2a90 	vmov	s15, r2
    36b4:	eef8 7ae7 	vcvt.f32.s32	s15, s15
    36b8:	ee67 7a86 	vmul.f32	s15, s15, s12
    36bc:	ee67 7aa6 	vmul.f32	s15, s15, s13
    36c0:	edc3 7a08 	vstr	s15, [r3, #32]
	
	// Covert from LSB to PU (A) and filter out small readings
	filter_convert_to_pu(&phase_A_current_raw, &Motor1.Iphase_pu.A); 
	filter_convert_to_pu(&phase_B_current_raw, &Motor1.Iphase_pu.B);
	// i_c = -i_a - i_b because i_a + i_b + i_c = 0
	Motor1.Iphase_pu.C = -Motor1.Iphase_pu.A - Motor1.Iphase_pu.B;
    36c4:	edd3 7a07 	vldr	s15, [r3, #28]
    36c8:	eef1 7a67 	vneg.f32	s15, s15
    36cc:	ed93 7a08 	vldr	s14, [r3, #32]
    36d0:	ee77 7ac7 	vsub.f32	s15, s15, s14
    36d4:	edc3 7a09 	vstr	s15, [r3, #36]	; 0x24
	// Select phase based on Hall State
	//select_active_phase(Motor1.hall_state, &Motor1); 
	// Set Current Loop Flag
	Motor1.timerflags.current_loop_tic = true;
    36d8:	2201      	movs	r2, #1
    36da:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39
}
	
inline void toc_port(const uint32_t port)
{
	REG_PORT_OUTCLR2 = port;
    36de:	4b07      	ldr	r3, [pc, #28]	; (36fc <adc_cb+0xa4>)
    36e0:	601c      	str	r4, [r3, #0]
	//toc(DEBUG_1);
	toc_port(DEBUG_2_PORT);
}
    36e2:	b003      	add	sp, #12
    36e4:	f85d 4b04 	ldr.w	r4, [sp], #4
    36e8:	4770      	bx	lr
    36ea:	bf00      	nop
    36ec:	41008118 	.word	0x41008118
    36f0:	20000328 	.word	0x20000328
    36f4:	43002000 	.word	0x43002000
    36f8:	3a533333 	.word	0x3a533333
    36fc:	41008114 	.word	0x41008114

00003700 <pwm_cb>:
// 	ADC Callback for Motor Phase Current Measurement.
// Phase A & B Sampled and converted from LSB to Process Unit PU(Amps)
// ----------------------------------------------------------------------
static void pwm_cb(const struct pwm_descriptor *const descr)
{
	Motor1.timerflags.pwm_cycle_tic = true;
    3700:	2201      	movs	r2, #1
    3702:	4b02      	ldr	r3, [pc, #8]	; (370c <pwm_cb+0xc>)
    3704:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38
    3708:	4770      	bx	lr
    370a:	bf00      	nop
    370c:	20000328 	.word	0x20000328

00003710 <HW_current_limit_detect_callback>:
}

static void HW_current_limit_detect_callback(void)
{
    3710:	4770      	bx	lr
	...

00003714 <TC7_Handler>:
{
    3714:	b508      	push	{r3, lr}
	if (TC7->COUNT16.INTFLAG.bit.OVF == 0x01) {
    3716:	4b07      	ldr	r3, [pc, #28]	; (3734 <TC7_Handler+0x20>)
    3718:	7a9b      	ldrb	r3, [r3, #10]
    371a:	f013 0f01 	tst.w	r3, #1
    371e:	d100      	bne.n	3722 <TC7_Handler+0xe>
    3720:	bd08      	pop	{r3, pc}
		TC7->COUNT16.INTFLAG.bit.OVF = 0x01;
    3722:	4a04      	ldr	r2, [pc, #16]	; (3734 <TC7_Handler+0x20>)
    3724:	7a93      	ldrb	r3, [r2, #10]
    3726:	f043 0301 	orr.w	r3, r3, #1
    372a:	7293      	strb	r3, [r2, #10]
		One_ms_cycle_callback();
    372c:	4b02      	ldr	r3, [pc, #8]	; (3738 <TC7_Handler+0x24>)
    372e:	4798      	blx	r3
}
    3730:	e7f6      	b.n	3720 <TC7_Handler+0xc>
    3732:	bf00      	nop
    3734:	43001800 	.word	0x43001800
    3738:	000015b1 	.word	0x000015b1

0000373c <TC0_Handler>:
	if (TC0->COUNT32.INTFLAG.bit.MC0 == 0x01) {
    373c:	4b0c      	ldr	r3, [pc, #48]	; (3770 <TC0_Handler+0x34>)
    373e:	7a9b      	ldrb	r3, [r3, #10]
    3740:	f013 0f10 	tst.w	r3, #16
    3744:	d105      	bne.n	3752 <TC0_Handler+0x16>
	if (TC0->COUNT32.INTFLAG.bit.OVF == 0x01) {
    3746:	4b0a      	ldr	r3, [pc, #40]	; (3770 <TC0_Handler+0x34>)
    3748:	7a9b      	ldrb	r3, [r3, #10]
    374a:	f013 0f01 	tst.w	r3, #1
    374e:	d106      	bne.n	375e <TC0_Handler+0x22>
    3750:	4770      	bx	lr
		TC0->COUNT32.INTFLAG.bit.MC0 = 0x01;
    3752:	4a07      	ldr	r2, [pc, #28]	; (3770 <TC0_Handler+0x34>)
    3754:	7a93      	ldrb	r3, [r2, #10]
    3756:	f043 0310 	orr.w	r3, r3, #16
    375a:	7293      	strb	r3, [r2, #10]
    375c:	e7f3      	b.n	3746 <TC0_Handler+0xa>
		TC0->COUNT32.INTFLAG.bit.OVF = 0x01;
    375e:	4a04      	ldr	r2, [pc, #16]	; (3770 <TC0_Handler+0x34>)
    3760:	7a93      	ldrb	r3, [r2, #10]
    3762:	f043 0301 	orr.w	r3, r3, #1
    3766:	7293      	strb	r3, [r2, #10]
		Motor1.calc_rpm = 0;
    3768:	2200      	movs	r2, #0
    376a:	4b02      	ldr	r3, [pc, #8]	; (3774 <TC0_Handler+0x38>)
    376c:	60da      	str	r2, [r3, #12]
}
    376e:	e7ef      	b.n	3750 <TC0_Handler+0x14>
    3770:	40003800 	.word	0x40003800
    3774:	20000328 	.word	0x20000328

00003778 <enable_NVIC_IRQ>:
    3778:	4b08      	ldr	r3, [pc, #32]	; (379c <enable_NVIC_IRQ+0x24>)
    377a:	f44f 2280 	mov.w	r2, #262144	; 0x40000
    377e:	60da      	str	r2, [r3, #12]
    3780:	f44f 6200 	mov.w	r2, #2048	; 0x800
    3784:	60da      	str	r2, [r3, #12]
    3786:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    378a:	601a      	str	r2, [r3, #0]
    378c:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
    3790:	609a      	str	r2, [r3, #8]
    3792:	609a      	str	r2, [r3, #8]
    3794:	f44f 3200 	mov.w	r2, #131072	; 0x20000
    3798:	601a      	str	r2, [r3, #0]
    379a:	4770      	bx	lr
    379c:	e000e100 	.word	0xe000e100

000037a0 <main>:
}



int main(void)
{
    37a0:	b508      	push	{r3, lr}
	/* Initializes MCU, drivers and middleware */
	//__disable_irq();
	atmel_start_init();
    37a2:	4b92      	ldr	r3, [pc, #584]	; (39ec <main+0x24c>)
    37a4:	4798      	blx	r3


	BLDC_init(&Motor1);
    37a6:	4892      	ldr	r0, [pc, #584]	; (39f0 <main+0x250>)
    37a8:	4b92      	ldr	r3, [pc, #584]	; (39f4 <main+0x254>)
    37aa:	4798      	blx	r3
	read_zero_current_offset_value();
    37ac:	4b92      	ldr	r3, [pc, #584]	; (39f8 <main+0x258>)
    37ae:	4798      	blx	r3
	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask);
    37b0:	4a92      	ldr	r2, [pc, #584]	; (39fc <main+0x25c>)
    37b2:	6953      	ldr	r3, [r2, #20]
    37b4:	f043 0302 	orr.w	r3, r3, #2
    37b8:	6153      	str	r3, [r2, #20]
	tmp = ((Tcc *)hw)->CC[index].reg;
    37ba:	6c53      	ldr	r3, [r2, #68]	; 0x44
	tmp &= ~TCC_CC_CC_Msk;
    37bc:	f003 437f 	and.w	r3, r3, #4278190080	; 0xff000000
	tmp |= TCC_CC_CC(data);
    37c0:	f043 0396 	orr.w	r3, r3, #150	; 0x96
	((Tcc *)hw)->CC[index].reg = tmp;
    37c4:	6453      	str	r3, [r2, #68]	; 0x44
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    37c6:	4b8d      	ldr	r3, [pc, #564]	; (39fc <main+0x25c>)
    37c8:	689b      	ldr	r3, [r3, #8]
    37ca:	f413 5f7c 	tst.w	r3, #16128	; 0x3f00
    37ce:	d1fa      	bne.n	37c6 <main+0x26>
	((Tcc *)hw)->PER.reg = data;
    37d0:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    37d4:	4b89      	ldr	r3, [pc, #548]	; (39fc <main+0x25c>)
    37d6:	641a      	str	r2, [r3, #64]	; 0x40
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    37d8:	4b88      	ldr	r3, [pc, #544]	; (39fc <main+0x25c>)
    37da:	689b      	ldr	r3, [r3, #8]
    37dc:	f013 0f80 	tst.w	r3, #128	; 0x80
    37e0:	d1fa      	bne.n	37d8 <main+0x38>
	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0;
    37e2:	4a86      	ldr	r2, [pc, #536]	; (39fc <main+0x25c>)
    37e4:	6bd3      	ldr	r3, [r2, #60]	; 0x3c
    37e6:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
    37ea:	63d3      	str	r3, [r2, #60]	; 0x3c
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    37ec:	4b83      	ldr	r3, [pc, #524]	; (39fc <main+0x25c>)
    37ee:	689b      	ldr	r3, [r3, #8]
    37f0:	f3c3 030d 	ubfx	r3, r3, #0, #14
    37f4:	2b00      	cmp	r3, #0
    37f6:	d1f9      	bne.n	37ec <main+0x4c>
	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1;
    37f8:	4a80      	ldr	r2, [pc, #512]	; (39fc <main+0x25c>)
    37fa:	6bd3      	ldr	r3, [r2, #60]	; 0x3c
    37fc:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
    3800:	63d3      	str	r3, [r2, #60]	; 0x3c
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    3802:	4b7e      	ldr	r3, [pc, #504]	; (39fc <main+0x25c>)
    3804:	689b      	ldr	r3, [r3, #8]
    3806:	f3c3 030d 	ubfx	r3, r3, #0, #14
    380a:	2b00      	cmp	r3, #0
    380c:	d1f9      	bne.n	3802 <main+0x62>
	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2;
    380e:	4a7b      	ldr	r2, [pc, #492]	; (39fc <main+0x25c>)
    3810:	6bd3      	ldr	r3, [r2, #60]	; 0x3c
    3812:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
    3816:	63d3      	str	r3, [r2, #60]	; 0x3c
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    3818:	4b78      	ldr	r3, [pc, #480]	; (39fc <main+0x25c>)
    381a:	689b      	ldr	r3, [r3, #8]
    381c:	f3c3 030d 	ubfx	r3, r3, #0, #14
    3820:	2b00      	cmp	r3, #0
    3822:	d1f9      	bne.n	3818 <main+0x78>
	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3;
    3824:	4a75      	ldr	r2, [pc, #468]	; (39fc <main+0x25c>)
    3826:	6bd3      	ldr	r3, [r2, #60]	; 0x3c
    3828:	f443 2300 	orr.w	r3, r3, #524288	; 0x80000
    382c:	63d3      	str	r3, [r2, #60]	; 0x3c
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    382e:	4b73      	ldr	r3, [pc, #460]	; (39fc <main+0x25c>)
    3830:	689b      	ldr	r3, [r3, #8]
    3832:	f3c3 030d 	ubfx	r3, r3, #0, #14
    3836:	2b00      	cmp	r3, #0
    3838:	d1f9      	bne.n	382e <main+0x8e>
	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL4;
    383a:	4a70      	ldr	r2, [pc, #448]	; (39fc <main+0x25c>)
    383c:	6bd3      	ldr	r3, [r2, #60]	; 0x3c
    383e:	f443 1380 	orr.w	r3, r3, #1048576	; 0x100000
    3842:	63d3      	str	r3, [r2, #60]	; 0x3c
	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
    3844:	4b6d      	ldr	r3, [pc, #436]	; (39fc <main+0x25c>)
    3846:	689b      	ldr	r3, [r3, #8]
    3848:	f3c3 030d 	ubfx	r3, r3, #0, #14
    384c:	2b00      	cmp	r3, #0
    384e:	d1f9      	bne.n	3844 <main+0xa4>
	hri_tcc_set_WAVE_POL1_bit(TCC1);
	hri_tcc_set_WAVE_POL2_bit(TCC1);
	hri_tcc_set_WAVE_POL3_bit(TCC1);
	hri_tcc_set_WAVE_POL4_bit(TCC1);
	
	pwm_register_callback(&TCC_PWM, PWM_PERIOD_CB, pwm_cb);	
    3850:	4c6b      	ldr	r4, [pc, #428]	; (3a00 <main+0x260>)
    3852:	4a6c      	ldr	r2, [pc, #432]	; (3a04 <main+0x264>)
    3854:	2100      	movs	r1, #0
    3856:	4620      	mov	r0, r4
    3858:	4b6b      	ldr	r3, [pc, #428]	; (3a08 <main+0x268>)
    385a:	4798      	blx	r3
	pwm_enable(&TCC_PWM);
    385c:	4620      	mov	r0, r4
    385e:	4b6b      	ldr	r3, [pc, #428]	; (3a0c <main+0x26c>)
    3860:	4798      	blx	r3

}

inline void configure_adc(void)
{
	adc_async_enable_channel(&ADC_0, 0);
    3862:	4c6b      	ldr	r4, [pc, #428]	; (3a10 <main+0x270>)
    3864:	2100      	movs	r1, #0
    3866:	4620      	mov	r0, r4
    3868:	4d6a      	ldr	r5, [pc, #424]	; (3a14 <main+0x274>)
    386a:	47a8      	blx	r5
	adc_async_enable_channel(&ADC_1, 0);
    386c:	2100      	movs	r1, #0
    386e:	486a      	ldr	r0, [pc, #424]	; (3a18 <main+0x278>)
    3870:	47a8      	blx	r5
	
	adc_async_register_callback(&ADC_0, 0, ADC_ASYNC_CONVERT_CB, adc_cb);
    3872:	4b6a      	ldr	r3, [pc, #424]	; (3a1c <main+0x27c>)
    3874:	2200      	movs	r2, #0
    3876:	4611      	mov	r1, r2
    3878:	4620      	mov	r0, r4
    387a:	4c69      	ldr	r4, [pc, #420]	; (3a20 <main+0x280>)
    387c:	47a0      	blx	r4
	configure_tcc_pwm();
	config_pins();
	configure_adc();
	configure_ethercat_dma_descriptors();
    387e:	4b69      	ldr	r3, [pc, #420]	; (3a24 <main+0x284>)
    3880:	4798      	blx	r3
	ethercat_update();
    3882:	4b69      	ldr	r3, [pc, #420]	; (3a28 <main+0x288>)
    3884:	4798      	blx	r3
 *  \brief Enable the custom logic hardware
 *  \return Initialization operation status
 */
static inline int32_t custom_logic_enable(void)
{
	return _custom_logic_enable();
    3886:	4b69      	ldr	r3, [pc, #420]	; (3a2c <main+0x28c>)
    3888:	4798      	blx	r3
	custom_logic_enable();
	configure_TC_CCL_SPEED();
	//ext_irq_register(PIN_PB05, button_on_PB05_pressed);
	ext_irq_register(nDRV_RESET, HW_current_limit_detect_callback);
    388a:	4969      	ldr	r1, [pc, #420]	; (3a30 <main+0x290>)
    388c:	2025      	movs	r0, #37	; 0x25
    388e:	4b69      	ldr	r3, [pc, #420]	; (3a34 <main+0x294>)
    3890:	4798      	blx	r3
	enable_NVIC_IRQ(); // Enable TC_ECAT TC7 Timer
    3892:	4b69      	ldr	r3, [pc, #420]	; (3a38 <main+0x298>)
    3894:	4798      	blx	r3
    3896:	e003      	b.n	38a0 <main+0x100>
			//Motor1.timerflags.pwm_cycle_tic = false;
			//tic(DEBUG_1);
			//exec_commutation();	
			//toc(DEBUG_1);	
		//}
		if(Motor1.timerflags.current_loop_tic) {
    3898:	4b55      	ldr	r3, [pc, #340]	; (39f0 <main+0x250>)
    389a:	f893 3039 	ldrb.w	r3, [r3, #57]	; 0x39
    389e:	b96b      	cbnz	r3, 38bc <main+0x11c>
		if(Motor1.timerflags.motor_telemetry_flag)
    38a0:	4b53      	ldr	r3, [pc, #332]	; (39f0 <main+0x250>)
    38a2:	f893 303b 	ldrb.w	r3, [r3, #59]	; 0x3b
    38a6:	2b00      	cmp	r3, #0
    38a8:	d0f6      	beq.n	3898 <main+0xf8>
			Motor1.timerflags.motor_telemetry_flag = false;
    38aa:	2200      	movs	r2, #0
    38ac:	4b50      	ldr	r3, [pc, #320]	; (39f0 <main+0x250>)
    38ae:	f883 203b 	strb.w	r2, [r3, #59]	; 0x3b
			update_setpoints();
    38b2:	4b62      	ldr	r3, [pc, #392]	; (3a3c <main+0x29c>)
    38b4:	4798      	blx	r3
			update_telemetry();
    38b6:	4b62      	ldr	r3, [pc, #392]	; (3a40 <main+0x2a0>)
    38b8:	4798      	blx	r3
    38ba:	e7ed      	b.n	3898 <main+0xf8>
			Motor1.timerflags.current_loop_tic = false;
    38bc:	2200      	movs	r2, #0
    38be:	4b4c      	ldr	r3, [pc, #304]	; (39f0 <main+0x250>)
    38c0:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39
	REG_PORT_OUTSET2 = port;
    38c4:	2202      	movs	r2, #2
    38c6:	4b5f      	ldr	r3, [pc, #380]	; (3a44 <main+0x2a4>)
    38c8:	601a      	str	r2, [r3, #0]
	if (applicationStatus.fault)
    38ca:	4b5f      	ldr	r3, [pc, #380]	; (3a48 <main+0x2a8>)
    38cc:	789b      	ldrb	r3, [r3, #2]
    38ce:	b123      	cbz	r3, 38da <main+0x13a>
		applicationStatus.previousstate = applicationStatus.currentstate;
    38d0:	4b5d      	ldr	r3, [pc, #372]	; (3a48 <main+0x2a8>)
    38d2:	781a      	ldrb	r2, [r3, #0]
    38d4:	705a      	strb	r2, [r3, #1]
		applicationStatus.currentstate = FAULT;
    38d6:	2209      	movs	r2, #9
    38d8:	701a      	strb	r2, [r3, #0]
	switch(applicationStatus.currentstate)                    							 	/* process current motor state*/
    38da:	4b5b      	ldr	r3, [pc, #364]	; (3a48 <main+0x2a8>)
    38dc:	781b      	ldrb	r3, [r3, #0]
    38de:	2b08      	cmp	r3, #8
    38e0:	d813      	bhi.n	390a <main+0x16a>
    38e2:	e8df f013 	tbh	[pc, r3, lsl #1]
    38e6:	0009      	.short	0x0009
    38e8:	001d0018 	.word	0x001d0018
    38ec:	00220012 	.word	0x00220012
    38f0:	004f0012 	.word	0x004f0012
    38f4:	010500c1 	.word	0x010500c1
	((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
    38f8:	4a54      	ldr	r2, [pc, #336]	; (3a4c <main+0x2ac>)
    38fa:	f04f 6100 	mov.w	r1, #134217728	; 0x8000000
    38fe:	6191      	str	r1, [r2, #24]
	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
    3900:	6151      	str	r1, [r2, #20]
			applicationStatus.previousstate = applicationStatus.currentstate;                                                                                 
    3902:	4a51      	ldr	r2, [pc, #324]	; (3a48 <main+0x2a8>)
    3904:	7053      	strb	r3, [r2, #1]
			applicationStatus.currentstate = SYSTEM_IDLE;
    3906:	2301      	movs	r3, #1
    3908:	7013      	strb	r3, [r2, #0]
	exec_commutation();
    390a:	4b51      	ldr	r3, [pc, #324]	; (3a50 <main+0x2b0>)
    390c:	4798      	blx	r3
	REG_PORT_OUTCLR2 = port;
    390e:	2202      	movs	r2, #2
    3910:	4b50      	ldr	r3, [pc, #320]	; (3a54 <main+0x2b4>)
    3912:	601a      	str	r2, [r3, #0]
    3914:	e7c4      	b.n	38a0 <main+0x100>
				applicationStatus.previousstate = applicationStatus.currentstate;
    3916:	4a4c      	ldr	r2, [pc, #304]	; (3a48 <main+0x2a8>)
    3918:	7053      	strb	r3, [r2, #1]
				applicationStatus.currentstate = MOTOR_IDLE;
    391a:	2302      	movs	r3, #2
    391c:	7013      	strb	r3, [r2, #0]
    391e:	e7f4      	b.n	390a <main+0x16a>
			applicationStatus.previousstate = applicationStatus.currentstate;
    3920:	4a49      	ldr	r2, [pc, #292]	; (3a48 <main+0x2a8>)
    3922:	7053      	strb	r3, [r2, #1]
			applicationStatus.currentstate = MOTOR_PVI_CTRL_STATE;
    3924:	2307      	movs	r3, #7
    3926:	7013      	strb	r3, [r2, #0]
    3928:	e7ef      	b.n	390a <main+0x16a>
			switch (Motor1.regulation_loop_count) {
    392a:	4b31      	ldr	r3, [pc, #196]	; (39f0 <main+0x250>)
    392c:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
    3930:	f003 02ff 	and.w	r2, r3, #255	; 0xff
    3934:	b17b      	cbz	r3, 3956 <main+0x1b6>
    3936:	2a06      	cmp	r2, #6
    3938:	d00d      	beq.n	3956 <main+0x1b6>
					select_active_phase(&Motor1, Motor1.currentHallPattern); 	/* Still measure current */
    393a:	4c2d      	ldr	r4, [pc, #180]	; (39f0 <main+0x250>)
    393c:	7de1      	ldrb	r1, [r4, #23]
    393e:	4620      	mov	r0, r4
    3940:	4b45      	ldr	r3, [pc, #276]	; (3a58 <main+0x2b8>)
    3942:	4798      	blx	r3
			if(Motor1.regulation_loop_count > 23) Motor1.regulation_loop_count = 0;
    3944:	f894 303c 	ldrb.w	r3, [r4, #60]	; 0x3c
    3948:	b2db      	uxtb	r3, r3
    394a:	2b17      	cmp	r3, #23
    394c:	d912      	bls.n	3974 <main+0x1d4>
    394e:	2200      	movs	r2, #0
    3950:	f884 203c 	strb.w	r2, [r4, #60]	; 0x3c
    3954:	e7d9      	b.n	390a <main+0x16a>
					calculate_motor_speed();
    3956:	4b41      	ldr	r3, [pc, #260]	; (3a5c <main+0x2bc>)
    3958:	4798      	blx	r3
					BLDC_runSpeedCntl(&Motor1, Motor1.calc_rpm, Motor1.desired_speed);
    395a:	4825      	ldr	r0, [pc, #148]	; (39f0 <main+0x250>)
    395c:	ed90 0a03 	vldr	s0, [r0, #12]
    3960:	f8b0 30cc 	ldrh.w	r3, [r0, #204]	; 0xcc
    3964:	b21b      	sxth	r3, r3
    3966:	ee00 3a90 	vmov	s1, r3
    396a:	eef8 0ae0 	vcvt.f32.s32	s1, s1
    396e:	4b3c      	ldr	r3, [pc, #240]	; (3a60 <main+0x2c0>)
    3970:	4798      	blx	r3
    3972:	e7e2      	b.n	393a <main+0x19a>
			else Motor1.regulation_loop_count++;
    3974:	4a1e      	ldr	r2, [pc, #120]	; (39f0 <main+0x250>)
    3976:	f892 303c 	ldrb.w	r3, [r2, #60]	; 0x3c
    397a:	3301      	adds	r3, #1
    397c:	b2db      	uxtb	r3, r3
    397e:	f882 303c 	strb.w	r3, [r2, #60]	; 0x3c
    3982:	e7c2      	b.n	390a <main+0x16a>
			switch (Motor1.regulation_loop_count) {
    3984:	4b1a      	ldr	r3, [pc, #104]	; (39f0 <main+0x250>)
    3986:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
    398a:	f003 02ff 	and.w	r2, r3, #255	; 0xff
    398e:	b1b3      	cbz	r3, 39be <main+0x21e>
    3990:	2a06      	cmp	r2, #6
    3992:	d014      	beq.n	39be <main+0x21e>
						select_active_phase(&Motor1, Motor1.currentHallPattern);
    3994:	4c16      	ldr	r4, [pc, #88]	; (39f0 <main+0x250>)
    3996:	7de1      	ldrb	r1, [r4, #23]
    3998:	4620      	mov	r0, r4
    399a:	4b2f      	ldr	r3, [pc, #188]	; (3a58 <main+0x2b8>)
    399c:	4798      	blx	r3
						BLDC_runCurrentCntl(&Motor1, Motor1.Iphase_pu.Bus, Motor1.controllers.Pi_Idc.Ref_pu);
    399e:	ed94 0a0a 	vldr	s0, [r4, #40]	; 0x28
    39a2:	edd4 0a12 	vldr	s1, [r4, #72]	; 0x48
    39a6:	4620      	mov	r0, r4
    39a8:	4b2e      	ldr	r3, [pc, #184]	; (3a64 <main+0x2c4>)
    39aa:	4798      	blx	r3
			if(Motor1.regulation_loop_count > 23) Motor1.regulation_loop_count = 0;
    39ac:	f894 303c 	ldrb.w	r3, [r4, #60]	; 0x3c
    39b0:	b2db      	uxtb	r3, r3
    39b2:	2b17      	cmp	r3, #23
    39b4:	d912      	bls.n	39dc <main+0x23c>
    39b6:	2200      	movs	r2, #0
    39b8:	f884 203c 	strb.w	r2, [r4, #60]	; 0x3c
    39bc:	e7a5      	b.n	390a <main+0x16a>
						calculate_motor_speed();
    39be:	4b27      	ldr	r3, [pc, #156]	; (3a5c <main+0x2bc>)
    39c0:	4798      	blx	r3
						BLDC_runSpeedCntl(&Motor1, Motor1.calc_rpm, Motor1.desired_speed);
    39c2:	480b      	ldr	r0, [pc, #44]	; (39f0 <main+0x250>)
    39c4:	ed90 0a03 	vldr	s0, [r0, #12]
    39c8:	f8b0 30cc 	ldrh.w	r3, [r0, #204]	; 0xcc
    39cc:	b21b      	sxth	r3, r3
    39ce:	ee00 3a90 	vmov	s1, r3
    39d2:	eef8 0ae0 	vcvt.f32.s32	s1, s1
    39d6:	4b22      	ldr	r3, [pc, #136]	; (3a60 <main+0x2c0>)
    39d8:	4798      	blx	r3
    39da:	e7db      	b.n	3994 <main+0x1f4>
			else Motor1.regulation_loop_count++;
    39dc:	4a04      	ldr	r2, [pc, #16]	; (39f0 <main+0x250>)
    39de:	f892 303c 	ldrb.w	r3, [r2, #60]	; 0x3c
    39e2:	3301      	adds	r3, #1
    39e4:	b2db      	uxtb	r3, r3
    39e6:	f882 303c 	strb.w	r3, [r2, #60]	; 0x3c
    39ea:	e78e      	b.n	390a <main+0x16a>
    39ec:	000002d1 	.word	0x000002d1
    39f0:	20000328 	.word	0x20000328
    39f4:	00000315 	.word	0x00000315
    39f8:	00000441 	.word	0x00000441
    39fc:	41018000 	.word	0x41018000
    3a00:	20000404 	.word	0x20000404
    3a04:	00003701 	.word	0x00003701
    3a08:	00001d49 	.word	0x00001d49
    3a0c:	00001d0d 	.word	0x00001d0d
    3a10:	20000438 	.word	0x20000438
    3a14:	00001a19 	.word	0x00001a19
    3a18:	200004c8 	.word	0x200004c8
    3a1c:	00003659 	.word	0x00003659
    3a20:	00001a99 	.word	0x00001a99
    3a24:	00001669 	.word	0x00001669
    3a28:	00001655 	.word	0x00001655
    3a2c:	000023d5 	.word	0x000023d5
    3a30:	00003711 	.word	0x00003711
    3a34:	00001ba1 	.word	0x00001ba1
    3a38:	00003779 	.word	0x00003779
    3a3c:	00001541 	.word	0x00001541
    3a40:	0000148d 	.word	0x0000148d
    3a44:	41008118 	.word	0x41008118
    3a48:	20000324 	.word	0x20000324
    3a4c:	41008000 	.word	0x41008000
    3a50:	00000591 	.word	0x00000591
    3a54:	41008114 	.word	0x41008114
    3a58:	000002dd 	.word	0x000002dd
    3a5c:	00000625 	.word	0x00000625
    3a60:	0000087d 	.word	0x0000087d
    3a64:	000006dd 	.word	0x000006dd
			switch (Motor1.regulation_loop_count) {
    3a68:	4b24      	ldr	r3, [pc, #144]	; (3afc <main+0x35c>)
    3a6a:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
    3a6e:	b2db      	uxtb	r3, r3
    3a70:	2b14      	cmp	r3, #20
    3a72:	d820      	bhi.n	3ab6 <main+0x316>
    3a74:	e8df f003 	tbb	[pc, r3]
    3a78:	1f1f1f0b 	.word	0x1f1f1f0b
    3a7c:	1f1f161f 	.word	0x1f1f161f
    3a80:	1f161f1f 	.word	0x1f161f1f
    3a84:	161f1f1f 	.word	0x161f1f1f
    3a88:	1f1f1f1f 	.word	0x1f1f1f1f
    3a8c:	16          	.byte	0x16
    3a8d:	00          	.byte	0x00
						Motor1.timerflags.motor_telemetry_flag = true; // Update telemetry flag
    3a8e:	481b      	ldr	r0, [pc, #108]	; (3afc <main+0x35c>)
    3a90:	2301      	movs	r3, #1
    3a92:	f880 303b 	strb.w	r3, [r0, #59]	; 0x3b
							BLDC_runPosCntl(&Motor1, Motor1.Num_Steps, Motor1.desired_position);
    3a96:	6901      	ldr	r1, [r0, #16]
    3a98:	f8b0 20ce 	ldrh.w	r2, [r0, #206]	; 0xce
    3a9c:	b212      	sxth	r2, r2
    3a9e:	b209      	sxth	r1, r1
    3aa0:	4b17      	ldr	r3, [pc, #92]	; (3b00 <main+0x360>)
    3aa2:	4798      	blx	r3
								calculate_motor_speed();
    3aa4:	4b17      	ldr	r3, [pc, #92]	; (3b04 <main+0x364>)
    3aa6:	4798      	blx	r3
								BLDC_runSpeedCntl(&Motor1, Motor1.calc_rpm, Motor1.controllers.Pid_Speed.Ref_pu);
    3aa8:	4814      	ldr	r0, [pc, #80]	; (3afc <main+0x35c>)
    3aaa:	ed90 0a03 	vldr	s0, [r0, #12]
    3aae:	edd0 0a1e 	vldr	s1, [r0, #120]	; 0x78
    3ab2:	4b15      	ldr	r3, [pc, #84]	; (3b08 <main+0x368>)
    3ab4:	4798      	blx	r3
								select_active_phase(&Motor1, Motor1.currentHallPattern);
    3ab6:	4c11      	ldr	r4, [pc, #68]	; (3afc <main+0x35c>)
    3ab8:	7de1      	ldrb	r1, [r4, #23]
    3aba:	4620      	mov	r0, r4
    3abc:	4b13      	ldr	r3, [pc, #76]	; (3b0c <main+0x36c>)
    3abe:	4798      	blx	r3
								BLDC_runCurrentCntl(&Motor1, Motor1.Iphase_pu.Bus, Motor1.controllers.Pi_Idc.Ref_pu);
    3ac0:	ed94 0a0a 	vldr	s0, [r4, #40]	; 0x28
    3ac4:	edd4 0a12 	vldr	s1, [r4, #72]	; 0x48
    3ac8:	4620      	mov	r0, r4
    3aca:	4b11      	ldr	r3, [pc, #68]	; (3b10 <main+0x370>)
    3acc:	4798      	blx	r3
			if(Motor1.regulation_loop_count > 23) Motor1.regulation_loop_count = 0;
    3ace:	f894 303c 	ldrb.w	r3, [r4, #60]	; 0x3c
    3ad2:	b2db      	uxtb	r3, r3
    3ad4:	2b17      	cmp	r3, #23
    3ad6:	d903      	bls.n	3ae0 <main+0x340>
    3ad8:	2200      	movs	r2, #0
    3ada:	f884 203c 	strb.w	r2, [r4, #60]	; 0x3c
    3ade:	e714      	b.n	390a <main+0x16a>
			else Motor1.regulation_loop_count++;
    3ae0:	4a06      	ldr	r2, [pc, #24]	; (3afc <main+0x35c>)
    3ae2:	f892 303c 	ldrb.w	r3, [r2, #60]	; 0x3c
    3ae6:	3301      	adds	r3, #1
    3ae8:	b2db      	uxtb	r3, r3
    3aea:	f882 303c 	strb.w	r3, [r2, #60]	; 0x3c
    3aee:	e70c      	b.n	390a <main+0x16a>
			applicationStatus.previousstate = applicationStatus.currentstate;
    3af0:	4a08      	ldr	r2, [pc, #32]	; (3b14 <main+0x374>)
    3af2:	7053      	strb	r3, [r2, #1]
			applicationStatus.currentstate = SYSTEM_IDLE;
    3af4:	2301      	movs	r3, #1
    3af6:	7013      	strb	r3, [r2, #0]
    3af8:	e707      	b.n	390a <main+0x16a>
    3afa:	bf00      	nop
    3afc:	20000328 	.word	0x20000328
    3b00:	00000b15 	.word	0x00000b15
    3b04:	00000625 	.word	0x00000625
    3b08:	0000087d 	.word	0x0000087d
    3b0c:	000002dd 	.word	0x000002dd
    3b10:	000006dd 	.word	0x000006dd
    3b14:	20000324 	.word	0x20000324

00003b18 <__libc_init_array>:
    3b18:	b570      	push	{r4, r5, r6, lr}
    3b1a:	4e0d      	ldr	r6, [pc, #52]	; (3b50 <__libc_init_array+0x38>)
    3b1c:	4c0d      	ldr	r4, [pc, #52]	; (3b54 <__libc_init_array+0x3c>)
    3b1e:	1ba4      	subs	r4, r4, r6
    3b20:	10a4      	asrs	r4, r4, #2
    3b22:	2500      	movs	r5, #0
    3b24:	42a5      	cmp	r5, r4
    3b26:	d109      	bne.n	3b3c <__libc_init_array+0x24>
    3b28:	4e0b      	ldr	r6, [pc, #44]	; (3b58 <__libc_init_array+0x40>)
    3b2a:	4c0c      	ldr	r4, [pc, #48]	; (3b5c <__libc_init_array+0x44>)
    3b2c:	f000 fa1c 	bl	3f68 <_init>
    3b30:	1ba4      	subs	r4, r4, r6
    3b32:	10a4      	asrs	r4, r4, #2
    3b34:	2500      	movs	r5, #0
    3b36:	42a5      	cmp	r5, r4
    3b38:	d105      	bne.n	3b46 <__libc_init_array+0x2e>
    3b3a:	bd70      	pop	{r4, r5, r6, pc}
    3b3c:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
    3b40:	4798      	blx	r3
    3b42:	3501      	adds	r5, #1
    3b44:	e7ee      	b.n	3b24 <__libc_init_array+0xc>
    3b46:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
    3b4a:	4798      	blx	r3
    3b4c:	3501      	adds	r5, #1
    3b4e:	e7f2      	b.n	3b36 <__libc_init_array+0x1e>
    3b50:	00003f74 	.word	0x00003f74
    3b54:	00003f74 	.word	0x00003f74
    3b58:	00003f74 	.word	0x00003f74
    3b5c:	00003f78 	.word	0x00003f78

00003b60 <COMMUTATION_PATTERN>:
    3b60:	30f800fc 60f850f4 507c607c 00fc30f4     ...0.P.`|`|P.0..
    3b70:	30f400fc 607c507c 50f460f8 00fc30f8     ...0|P|`.`.P.0..

00003b80 <MOTOR_COMMUTATION_STEPS>:
    3b80:	02030114 14040605                       ........

00003b88 <dummy_register>:
    3b88:	2000000c                                ... 

00003b8c <abort_fifo_start>:
    3b8c:	20000016                                ... 

00003b90 <wr_pdram_start>:
    3b90:	20000052                                R.. 

00003b94 <cf_pdram_start>:
    3b94:	2000003c                                <.. 

00003b98 <rd_pdram_start>:
    3b98:	2000004f 682f2e2e 732f6c61 682f6372     O.. ../hal/src/h
    3ba8:	615f6c61 615f6364 636e7973 0000632e     al_adc_async.c..
    3bb8:	682f2e2e 732f6c61 682f6372 705f6c61     ../hal/src/hal_p
    3bc8:	5f636564 6e797361 00632e63 682f2e2e     dec_async.c.../h
    3bd8:	732f6c61 682f6372 705f6c61 632e6d77     al/src/hal_pwm.c
    3be8:	00000000 682f2e2e 732f6c61 682f6372     ....../hal/src/h
    3bf8:	735f6c61 6d5f6970 616d645f 0000632e     al_spi_m_dma.c..
    3c08:	682f2e2e 752f6c61 736c6974 6372732f     ../hal/utils/src
    3c18:	6974752f 725f736c 62676e69 65666675     /utils_ringbuffe
    3c28:	00632e72                                r.c.

00003c2c <_adcs>:
    3c2c:	02000000 02030000 00001802 00000000     ................
    3c3c:	00000000 00010000 00000200 18010203     ................
	...
    3c58:	682f2e2e 612f6c70 682f6364 615f6c70     ../hpl/adc/hpl_a
    3c68:	632e6364 00000000                       dc.c....

00003c70 <_ccl_reg_cfgs>:
    3c70:	96444402 00044400 00044400 00044400     .DD..D...D...D..
    3c80:	00000000                                ....

00003c84 <_cfgs>:
    3c84:	00200e00 18028000 00200f00 04028000     .. ....... .....
	...

00003d84 <_map>:
    3d84:	00000005 00000025 682f2e2e 652f6c70     ....%...../hpl/e
    3d94:	682f6369 655f6c70 632e6369 00000000     ic/hpl_eic.c....

00003da4 <user_mux_confs>:
    3da4:	00000200 00000000 00000000 00000000     ................
	...
    3dd0:	00000002 00000000 01000000 00000100     ................
	...

00003de8 <channel_confs>:
    3de8:	02740232 00000000 00000000 00000000     2.t.............
	...

00003e28 <interrupt_cfg>:
	...
    3ea8:	682f2e2e 702f6c70 2f636564 5f6c7068     ../hpl/pdec/hpl_
    3eb8:	63656470 0000632e 40003000 40003400     pdec.c...0.@.4.@
    3ec8:	41012000 41014000 43000000 43000400     . .A.@.A...C...C
    3ed8:	43000800 43000c00                       ...C...C

00003ee0 <_usarts>:
	...

00003ef8 <_i2cms>:
	...

00003f10 <_i2css>:
	...

00003f20 <sercomspi_regs>:
    3f20:	0030000c 00020000 00000000 01ff0007     ..0.............
    3f30:	00000005 682f2e2e 732f6c70 6f637265     ....../hpl/serco
    3f40:	70682f6d 65735f6c 6d6f6372 0000632e     m/hpl_sercom.c..
    3f50:	682f2e2e 742f6c70 682f6363 745f6c70     ../hpl/tcc/hpl_t
    3f60:	632e6363 00000000                       cc.c....

00003f68 <_init>:
    3f68:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3f6a:	bf00      	nop
    3f6c:	bcf8      	pop	{r3, r4, r5, r6, r7}
    3f6e:	bc08      	pop	{r3}
    3f70:	469e      	mov	lr, r3
    3f72:	4770      	bx	lr

00003f74 <__init_array_start>:
    3f74:	00000289 	.word	0x00000289

00003f78 <_fini>:
    3f78:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3f7a:	bf00      	nop
    3f7c:	bcf8      	pop	{r3, r4, r5, r6, r7}
    3f7e:	bc08      	pop	{r3}
    3f80:	469e      	mov	lr, r3
    3f82:	4770      	bx	lr

00003f84 <__fini_array_start>:
    3f84:	00000265 	.word	0x00000265
