format_version: '2'
name: BLDC_E54
versions:
  api: '1.0'
  backend: 1.8.543
  commit: 931b2422bde1a793dea853de68547f48bf245b0f
  content: unknown
  content_pack_name: unknown
  format: '2'
  frontend: 1.8.543
  packs_version_avr8: 1.0.1457
  packs_version_qtouch: unknown
  packs_version_sam: 1.0.1726
  version_backend: 1.8.543
  version_frontend: ''
board:
  identifier: SAME54XplainedPro
  device: SAME54P20A-AU
details: null
application: null
middlewares: {}
drivers:
  ADC_0:
    user_label: ADC_0
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::ADC0::driver_config_definition::ADC::HAL:Driver:ADC.Async
    functionality: ADC
    api: HAL:Driver:ADC_Async
    configuration:
      adc_advanced_settings: true
      adc_arch_adjres: 0
      adc_arch_corren: false
      adc_arch_dbgrun: false
      adc_arch_event_settings: true
      adc_arch_flushei: false
      adc_arch_flushinv: false
      adc_arch_gaincorr: 0
      adc_arch_leftadj: false
      adc_arch_offcomp: false
      adc_arch_offsetcorr: 0
      adc_arch_ondemand: false
      adc_arch_refcomp: false
      adc_arch_resrdyeo: false
      adc_arch_runstdby: false
      adc_arch_samplen: 0
      adc_arch_samplenum: 1 sample
      adc_arch_seqen: 0
      adc_arch_startei: true
      adc_arch_startinv: false
      adc_arch_winlt: 0
      adc_arch_winmode: No window mode
      adc_arch_winmoneo: false
      adc_arch_winut: 0
      adc_differential_mode: false
      adc_freerunning_mode: false
      adc_pinmux_negative: Internal ground
      adc_pinmux_positive: ADC AIN2 pin
      adc_prescaler: Peripheral clock divided by 8
      adc_reference: VDDANA
      adc_resolution: 12-bit
    optional_signals:
    - identifier: ADC_0:AIN/2
      pad: PB08
      mode: Enabled
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::ADC0.AIN.2
      name: ADC0/AIN/2
      label: AIN/2
    variant: null
    clocks:
      domain_group:
        nodes:
        - name: ADC
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        configuration:
          adc_gclk_selection: Generic clock generator 0
  ADC_1:
    user_label: ADC_1
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::ADC1::driver_config_definition::ADC::HAL:Driver:ADC.Async
    functionality: ADC
    api: HAL:Driver:ADC_Async
    configuration:
      adc_advanced_settings: true
      adc_arch_adjres: 0
      adc_arch_corren: false
      adc_arch_dbgrun: false
      adc_arch_event_settings: true
      adc_arch_flushei: false
      adc_arch_flushinv: false
      adc_arch_gaincorr: 0
      adc_arch_leftadj: false
      adc_arch_offcomp: false
      adc_arch_offsetcorr: 0
      adc_arch_ondemand: false
      adc_arch_refcomp: false
      adc_arch_resrdyeo: false
      adc_arch_runstdby: false
      adc_arch_samplen: 0
      adc_arch_samplenum: 1 sample
      adc_arch_seqen: 0
      adc_arch_startei: true
      adc_arch_startinv: false
      adc_arch_winlt: 0
      adc_arch_winmode: No window mode
      adc_arch_winmoneo: false
      adc_arch_winut: 0
      adc_differential_mode: false
      adc_freerunning_mode: false
      adc_pinmux_negative: Internal ground
      adc_pinmux_positive: ADC AIN1 pin
      adc_prescaler: Peripheral clock divided by 8
      adc_reference: VDDANA
      adc_resolution: 12-bit
    optional_signals:
    - identifier: ADC_1:AIN/1
      pad: PB09
      mode: Enabled
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::ADC1.AIN.1
      name: ADC1/AIN/1
      label: AIN/1
    variant: null
    clocks:
      domain_group:
        nodes:
        - name: ADC
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        configuration:
          adc_gclk_selection: Generic clock generator 0
  DIGITAL_GLUE_LOGIC_0:
    user_label: DIGITAL_GLUE_LOGIC_0
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CCL::driver_config_definition::CCL::HAL:Driver:CCL
    functionality: Digital_Glue_Logic
    api: HAL:Driver:CCL
    configuration:
      ccl_arch_advanced_settings: false
      ccl_arch_edgesel_0: false
      ccl_arch_edgesel_1: false
      ccl_arch_edgesel_2: false
      ccl_arch_edgesel_3: false
      ccl_arch_filtsel_0: Disabled
      ccl_arch_filtsel_1: Disabled
      ccl_arch_filtsel_2: Disabled
      ccl_arch_filtsel_3: Disabled
      ccl_arch_insel0_0: IO pin input source
      ccl_arch_insel0_1: IO pin input source
      ccl_arch_insel0_2: IO pin input source
      ccl_arch_insel0_3: IO pin input source
      ccl_arch_insel1_0: IO pin input source
      ccl_arch_insel1_1: IO pin input source
      ccl_arch_insel1_2: IO pin input source
      ccl_arch_insel1_3: IO pin input source
      ccl_arch_insel2_0: IO pin input source
      ccl_arch_insel2_1: IO pin input source
      ccl_arch_insel2_2: IO pin input source
      ccl_arch_insel2_3: IO pin input source
      ccl_arch_invei_0: false
      ccl_arch_invei_1: false
      ccl_arch_invei_2: false
      ccl_arch_invei_3: false
      ccl_arch_lutctrl0: true
      ccl_arch_lutctrl1: false
      ccl_arch_lutctrl2: false
      ccl_arch_lutctrl3: false
      ccl_arch_lutei_0: false
      ccl_arch_lutei_1: false
      ccl_arch_lutei_2: false
      ccl_arch_lutei_3: false
      ccl_arch_luteo_0: true
      ccl_arch_luteo_1: false
      ccl_arch_luteo_2: false
      ccl_arch_luteo_3: false
      ccl_arch_runstdby: false
      ccl_arch_seqsel_0: Sequential logic is disabled
      ccl_arch_seqsel_1: Sequential logic is disabled
      ccl_arch_truth_0: 150
      ccl_arch_truth_1: 0
      ccl_arch_truth_2: 0
      ccl_arch_truth_3: 0
      ccl_e_persistance_0: ''
      ccl_e_persistance_1: ''
      ccl_e_persistance_2: ''
      ccl_e_persistance_3: ''
      ccl_l_persistance_0: ''
      ccl_l_persistance_1: ''
      ccl_l_persistance_2: ''
      ccl_l_persistance_3: ''
    optional_signals:
    - identifier: DIGITAL_GLUE_LOGIC_0:IN/0
      pad: PA04
      mode: Enabled
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::CCL.IN.0
      name: CCL/IN/0
      label: IN/0
    - identifier: DIGITAL_GLUE_LOGIC_0:IN/1
      pad: PA05
      mode: Enabled
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::CCL.IN.1
      name: CCL/IN/1
      label: IN/1
    - identifier: DIGITAL_GLUE_LOGIC_0:IN/2
      pad: PA06
      mode: Enabled
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::CCL.IN.2
      name: CCL/IN/2
      label: IN/2
    variant: null
    clocks:
      domain_group:
        nodes:
        - name: CCL
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        configuration:
          ccl_gclk_selection: Generic clock generator 0
  CMCC:
    user_label: CMCC
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC
    functionality: System
    api: HAL:HPL:CMCC
    configuration:
      cache_size: 4 KB
      cmcc_advanced_configuration: false
      cmcc_clock_gating_disable: false
      cmcc_data_cache_disable: false
      cmcc_enable: false
      cmcc_inst_cache_disable: false
    optional_signals: []
    variant: null
    clocks:
      domain_group: null
  DMAC:
    user_label: DMAC
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
    functionality: System
    api: HAL:HPL:DMAC
    configuration:
      dmac_beatsize_0: 8-bit bus transfer
      dmac_beatsize_1: 8-bit bus transfer
      dmac_beatsize_10: 8-bit bus transfer
      dmac_beatsize_11: 8-bit bus transfer
      dmac_beatsize_12: 8-bit bus transfer
      dmac_beatsize_13: 8-bit bus transfer
      dmac_beatsize_14: 8-bit bus transfer
      dmac_beatsize_15: 8-bit bus transfer
      dmac_beatsize_16: 8-bit bus transfer
      dmac_beatsize_17: 8-bit bus transfer
      dmac_beatsize_18: 8-bit bus transfer
      dmac_beatsize_19: 8-bit bus transfer
      dmac_beatsize_2: 8-bit bus transfer
      dmac_beatsize_20: 8-bit bus transfer
      dmac_beatsize_21: 8-bit bus transfer
      dmac_beatsize_22: 8-bit bus transfer
      dmac_beatsize_23: 8-bit bus transfer
      dmac_beatsize_24: 8-bit bus transfer
      dmac_beatsize_25: 8-bit bus transfer
      dmac_beatsize_26: 8-bit bus transfer
      dmac_beatsize_27: 8-bit bus transfer
      dmac_beatsize_28: 8-bit bus transfer
      dmac_beatsize_29: 8-bit bus transfer
      dmac_beatsize_3: 8-bit bus transfer
      dmac_beatsize_30: 8-bit bus transfer
      dmac_beatsize_31: 8-bit bus transfer
      dmac_beatsize_4: 8-bit bus transfer
      dmac_beatsize_5: 8-bit bus transfer
      dmac_beatsize_6: 8-bit bus transfer
      dmac_beatsize_7: 8-bit bus transfer
      dmac_beatsize_8: 8-bit bus transfer
      dmac_beatsize_9: 8-bit bus transfer
      dmac_blockact_0: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_1: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_10: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_11: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_12: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_13: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_14: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_15: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_16: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_17: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_18: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_19: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_2: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_20: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_21: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_22: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_23: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_24: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_25: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_26: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_27: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_28: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_29: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_3: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_30: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_31: Channel will be disabled if it is the last block transfer
        in the transaction
      dmac_blockact_4: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_5: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_6: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_7: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_8: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_9: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_channel_0_settings: true
      dmac_channel_10_settings: false
      dmac_channel_11_settings: false
      dmac_channel_12_settings: false
      dmac_channel_13_settings: false
      dmac_channel_14_settings: false
      dmac_channel_15_settings: false
      dmac_channel_16_settings: false
      dmac_channel_17_settings: false
      dmac_channel_18_settings: false
      dmac_channel_19_settings: false
      dmac_channel_1_settings: true
      dmac_channel_20_settings: false
      dmac_channel_21_settings: false
      dmac_channel_22_settings: false
      dmac_channel_23_settings: false
      dmac_channel_24_settings: false
      dmac_channel_25_settings: false
      dmac_channel_26_settings: false
      dmac_channel_27_settings: false
      dmac_channel_28_settings: false
      dmac_channel_29_settings: false
      dmac_channel_2_settings: false
      dmac_channel_30_settings: false
      dmac_channel_31_settings: false
      dmac_channel_3_settings: false
      dmac_channel_4_settings: false
      dmac_channel_5_settings: false
      dmac_channel_6_settings: false
      dmac_channel_7_settings: false
      dmac_channel_8_settings: false
      dmac_channel_9_settings: false
      dmac_dbgrun: false
      dmac_dstinc_0: true
      dmac_dstinc_1: false
      dmac_dstinc_10: false
      dmac_dstinc_11: false
      dmac_dstinc_12: false
      dmac_dstinc_13: false
      dmac_dstinc_14: false
      dmac_dstinc_15: false
      dmac_dstinc_16: false
      dmac_dstinc_17: false
      dmac_dstinc_18: false
      dmac_dstinc_19: false
      dmac_dstinc_2: false
      dmac_dstinc_20: false
      dmac_dstinc_21: false
      dmac_dstinc_22: false
      dmac_dstinc_23: false
      dmac_dstinc_24: false
      dmac_dstinc_25: false
      dmac_dstinc_26: false
      dmac_dstinc_27: false
      dmac_dstinc_28: false
      dmac_dstinc_29: false
      dmac_dstinc_3: false
      dmac_dstinc_30: false
      dmac_dstinc_31: false
      dmac_dstinc_4: false
      dmac_dstinc_5: false
      dmac_dstinc_6: false
      dmac_dstinc_7: false
      dmac_dstinc_8: false
      dmac_dstinc_9: false
      dmac_enable: true
      dmac_evact_0: No action
      dmac_evact_1: No action
      dmac_evact_10: No action
      dmac_evact_11: No action
      dmac_evact_12: No action
      dmac_evact_13: No action
      dmac_evact_14: No action
      dmac_evact_15: No action
      dmac_evact_16: No action
      dmac_evact_17: No action
      dmac_evact_18: No action
      dmac_evact_19: No action
      dmac_evact_2: No action
      dmac_evact_20: No action
      dmac_evact_21: No action
      dmac_evact_22: No action
      dmac_evact_23: No action
      dmac_evact_24: No action
      dmac_evact_25: No action
      dmac_evact_26: No action
      dmac_evact_27: No action
      dmac_evact_28: No action
      dmac_evact_29: No action
      dmac_evact_3: No action
      dmac_evact_30: No action
      dmac_evact_31: No action
      dmac_evact_4: No action
      dmac_evact_5: No action
      dmac_evact_6: No action
      dmac_evact_7: No action
      dmac_evact_8: No action
      dmac_evact_9: No action
      dmac_evie_0: false
      dmac_evie_1: false
      dmac_evie_10: false
      dmac_evie_11: false
      dmac_evie_12: false
      dmac_evie_13: false
      dmac_evie_14: false
      dmac_evie_15: false
      dmac_evie_16: false
      dmac_evie_17: false
      dmac_evie_18: false
      dmac_evie_19: false
      dmac_evie_2: false
      dmac_evie_20: false
      dmac_evie_21: false
      dmac_evie_22: false
      dmac_evie_23: false
      dmac_evie_24: false
      dmac_evie_25: false
      dmac_evie_26: false
      dmac_evie_27: false
      dmac_evie_28: false
      dmac_evie_29: false
      dmac_evie_3: false
      dmac_evie_30: false
      dmac_evie_31: false
      dmac_evie_4: false
      dmac_evie_5: false
      dmac_evie_6: false
      dmac_evie_7: false
      dmac_evie_8: false
      dmac_evie_9: false
      dmac_evoe_0: true
      dmac_evoe_1: true
      dmac_evoe_10: false
      dmac_evoe_11: false
      dmac_evoe_12: false
      dmac_evoe_13: false
      dmac_evoe_14: false
      dmac_evoe_15: false
      dmac_evoe_16: false
      dmac_evoe_17: false
      dmac_evoe_18: false
      dmac_evoe_19: false
      dmac_evoe_2: false
      dmac_evoe_20: false
      dmac_evoe_21: false
      dmac_evoe_22: false
      dmac_evoe_23: false
      dmac_evoe_24: false
      dmac_evoe_25: false
      dmac_evoe_26: false
      dmac_evoe_27: false
      dmac_evoe_28: false
      dmac_evoe_29: false
      dmac_evoe_3: false
      dmac_evoe_30: false
      dmac_evoe_31: false
      dmac_evoe_4: false
      dmac_evoe_5: false
      dmac_evoe_6: false
      dmac_evoe_7: false
      dmac_evoe_8: false
      dmac_evoe_9: false
      dmac_evosel_0: Event strobe when block transfer complete
      dmac_evosel_1: Event strobe when block transfer complete
      dmac_evosel_10: Event generation disabled
      dmac_evosel_11: Event generation disabled
      dmac_evosel_12: Event generation disabled
      dmac_evosel_13: Event generation disabled
      dmac_evosel_14: Event generation disabled
      dmac_evosel_15: Event generation disabled
      dmac_evosel_16: Event generation disabled
      dmac_evosel_17: Event generation disabled
      dmac_evosel_18: Event generation disabled
      dmac_evosel_19: Event generation disabled
      dmac_evosel_2: Event generation disabled
      dmac_evosel_20: Event generation disabled
      dmac_evosel_21: Event generation disabled
      dmac_evosel_22: Event generation disabled
      dmac_evosel_23: Event generation disabled
      dmac_evosel_24: Event generation disabled
      dmac_evosel_25: Event generation disabled
      dmac_evosel_26: Event generation disabled
      dmac_evosel_27: Event generation disabled
      dmac_evosel_28: Event generation disabled
      dmac_evosel_29: Event generation disabled
      dmac_evosel_3: Event generation disabled
      dmac_evosel_30: Event generation disabled
      dmac_evosel_31: Event generation disabled
      dmac_evosel_4: Event generation disabled
      dmac_evosel_5: Event generation disabled
      dmac_evosel_6: Event generation disabled
      dmac_evosel_7: Event generation disabled
      dmac_evosel_8: Event generation disabled
      dmac_evosel_9: Event generation disabled
      dmac_lvl_0: Channel priority 0
      dmac_lvl_1: Channel priority 0
      dmac_lvl_10: Channel priority 0
      dmac_lvl_11: Channel priority 0
      dmac_lvl_12: Channel priority 0
      dmac_lvl_13: Channel priority 0
      dmac_lvl_14: Channel priority 0
      dmac_lvl_15: Channel priority 0
      dmac_lvl_16: Channel priority 0
      dmac_lvl_17: Channel priority 0
      dmac_lvl_18: Channel priority 0
      dmac_lvl_19: Channel priority 0
      dmac_lvl_2: Channel priority 0
      dmac_lvl_20: Channel priority 0
      dmac_lvl_21: Channel priority 0
      dmac_lvl_22: Channel priority 0
      dmac_lvl_23: Channel priority 0
      dmac_lvl_24: Channel priority 0
      dmac_lvl_25: Channel priority 0
      dmac_lvl_26: Channel priority 0
      dmac_lvl_27: Channel priority 0
      dmac_lvl_28: Channel priority 0
      dmac_lvl_29: Channel priority 0
      dmac_lvl_3: Channel priority 0
      dmac_lvl_30: Channel priority 0
      dmac_lvl_31: Channel priority 0
      dmac_lvl_4: Channel priority 0
      dmac_lvl_5: Channel priority 0
      dmac_lvl_6: Channel priority 0
      dmac_lvl_7: Channel priority 0
      dmac_lvl_8: Channel priority 0
      dmac_lvl_9: Channel priority 0
      dmac_lvlen0: true
      dmac_lvlen1: false
      dmac_lvlen2: false
      dmac_lvlen3: false
      dmac_lvlpri0: 0
      dmac_lvlpri1: 0
      dmac_lvlpri2: 0
      dmac_lvlpri3: 0
      dmac_rrlvlen0: Round-robin arbitration scheme for channel with priority 0
      dmac_rrlvlen1: Round-robin arbitration scheme for channel with priority 1
      dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
      dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
      dmac_runstdby_0: false
      dmac_runstdby_1: false
      dmac_runstdby_10: false
      dmac_runstdby_11: false
      dmac_runstdby_12: false
      dmac_runstdby_13: false
      dmac_runstdby_14: false
      dmac_runstdby_15: false
      dmac_runstdby_16: false
      dmac_runstdby_17: false
      dmac_runstdby_18: false
      dmac_runstdby_19: false
      dmac_runstdby_2: false
      dmac_runstdby_20: false
      dmac_runstdby_21: false
      dmac_runstdby_22: false
      dmac_runstdby_23: false
      dmac_runstdby_24: false
      dmac_runstdby_25: false
      dmac_runstdby_26: false
      dmac_runstdby_27: false
      dmac_runstdby_28: false
      dmac_runstdby_29: false
      dmac_runstdby_3: false
      dmac_runstdby_30: false
      dmac_runstdby_31: false
      dmac_runstdby_4: false
      dmac_runstdby_5: false
      dmac_runstdby_6: false
      dmac_runstdby_7: false
      dmac_runstdby_8: false
      dmac_runstdby_9: false
      dmac_srcinc_0: false
      dmac_srcinc_1: true
      dmac_srcinc_10: false
      dmac_srcinc_11: false
      dmac_srcinc_12: false
      dmac_srcinc_13: false
      dmac_srcinc_14: false
      dmac_srcinc_15: false
      dmac_srcinc_16: false
      dmac_srcinc_17: false
      dmac_srcinc_18: false
      dmac_srcinc_19: false
      dmac_srcinc_2: false
      dmac_srcinc_20: false
      dmac_srcinc_21: false
      dmac_srcinc_22: false
      dmac_srcinc_23: false
      dmac_srcinc_24: false
      dmac_srcinc_25: false
      dmac_srcinc_26: false
      dmac_srcinc_27: false
      dmac_srcinc_28: false
      dmac_srcinc_29: false
      dmac_srcinc_3: false
      dmac_srcinc_30: false
      dmac_srcinc_31: false
      dmac_srcinc_4: false
      dmac_srcinc_5: false
      dmac_srcinc_6: false
      dmac_srcinc_7: false
      dmac_srcinc_8: false
      dmac_srcinc_9: false
      dmac_stepsel_0: Step size settings apply to the source address
      dmac_stepsel_1: Step size settings apply to the destination address
      dmac_stepsel_10: Step size settings apply to the destination address
      dmac_stepsel_11: Step size settings apply to the destination address
      dmac_stepsel_12: Step size settings apply to the destination address
      dmac_stepsel_13: Step size settings apply to the destination address
      dmac_stepsel_14: Step size settings apply to the destination address
      dmac_stepsel_15: Step size settings apply to the destination address
      dmac_stepsel_16: Step size settings apply to the destination address
      dmac_stepsel_17: Step size settings apply to the destination address
      dmac_stepsel_18: Step size settings apply to the destination address
      dmac_stepsel_19: Step size settings apply to the destination address
      dmac_stepsel_2: Step size settings apply to the destination address
      dmac_stepsel_20: Step size settings apply to the destination address
      dmac_stepsel_21: Step size settings apply to the destination address
      dmac_stepsel_22: Step size settings apply to the destination address
      dmac_stepsel_23: Step size settings apply to the destination address
      dmac_stepsel_24: Step size settings apply to the destination address
      dmac_stepsel_25: Step size settings apply to the destination address
      dmac_stepsel_26: Step size settings apply to the destination address
      dmac_stepsel_27: Step size settings apply to the destination address
      dmac_stepsel_28: Step size settings apply to the destination address
      dmac_stepsel_29: Step size settings apply to the destination address
      dmac_stepsel_3: Step size settings apply to the destination address
      dmac_stepsel_30: Step size settings apply to the destination address
      dmac_stepsel_31: Step size settings apply to the destination address
      dmac_stepsel_4: Step size settings apply to the destination address
      dmac_stepsel_5: Step size settings apply to the destination address
      dmac_stepsel_6: Step size settings apply to the destination address
      dmac_stepsel_7: Step size settings apply to the destination address
      dmac_stepsel_8: Step size settings apply to the destination address
      dmac_stepsel_9: Step size settings apply to the destination address
      dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_trifsrc_0: SERCOM5 RX Trigger
      dmac_trifsrc_1: SERCOM5 TX Trigger
      dmac_trifsrc_10: Only software/event triggers
      dmac_trifsrc_11: Only software/event triggers
      dmac_trifsrc_12: Only software/event triggers
      dmac_trifsrc_13: Only software/event triggers
      dmac_trifsrc_14: Only software/event triggers
      dmac_trifsrc_15: Only software/event triggers
      dmac_trifsrc_16: Only software/event triggers
      dmac_trifsrc_17: Only software/event triggers
      dmac_trifsrc_18: Only software/event triggers
      dmac_trifsrc_19: Only software/event triggers
      dmac_trifsrc_2: Only software/event triggers
      dmac_trifsrc_20: Only software/event triggers
      dmac_trifsrc_21: Only software/event triggers
      dmac_trifsrc_22: Only software/event triggers
      dmac_trifsrc_23: Only software/event triggers
      dmac_trifsrc_24: Only software/event triggers
      dmac_trifsrc_25: Only software/event triggers
      dmac_trifsrc_26: Only software/event triggers
      dmac_trifsrc_27: Only software/event triggers
      dmac_trifsrc_28: Only software/event triggers
      dmac_trifsrc_29: Only software/event triggers
      dmac_trifsrc_3: Only software/event triggers
      dmac_trifsrc_30: Only software/event triggers
      dmac_trifsrc_31: Only software/event triggers
      dmac_trifsrc_4: Only software/event triggers
      dmac_trifsrc_5: Only software/event triggers
      dmac_trifsrc_6: Only software/event triggers
      dmac_trifsrc_7: Only software/event triggers
      dmac_trifsrc_8: Only software/event triggers
      dmac_trifsrc_9: Only software/event triggers
      dmac_trigact_0: One trigger required for each beat transfer
      dmac_trigact_1: One trigger required for each beat transfer
      dmac_trigact_10: One trigger required for each block transfer
      dmac_trigact_11: One trigger required for each block transfer
      dmac_trigact_12: One trigger required for each block transfer
      dmac_trigact_13: One trigger required for each block transfer
      dmac_trigact_14: One trigger required for each block transfer
      dmac_trigact_15: One trigger required for each block transfer
      dmac_trigact_16: One trigger required for each block transfer
      dmac_trigact_17: One trigger required for each block transfer
      dmac_trigact_18: One trigger required for each block transfer
      dmac_trigact_19: One trigger required for each block transfer
      dmac_trigact_2: One trigger required for each block transfer
      dmac_trigact_20: One trigger required for each block transfer
      dmac_trigact_21: One trigger required for each block transfer
      dmac_trigact_22: One trigger required for each block transfer
      dmac_trigact_23: One trigger required for each block transfer
      dmac_trigact_24: One trigger required for each block transfer
      dmac_trigact_25: One trigger required for each block transfer
      dmac_trigact_26: One trigger required for each block transfer
      dmac_trigact_27: One trigger required for each block transfer
      dmac_trigact_28: One trigger required for each block transfer
      dmac_trigact_29: One trigger required for each block transfer
      dmac_trigact_3: One trigger required for each block transfer
      dmac_trigact_30: One trigger required for each block transfer
      dmac_trigact_31: One trigger required for each block transfer
      dmac_trigact_4: One trigger required for each block transfer
      dmac_trigact_5: One trigger required for each block transfer
      dmac_trigact_6: One trigger required for each block transfer
      dmac_trigact_7: One trigger required for each block transfer
      dmac_trigact_8: One trigger required for each block transfer
      dmac_trigact_9: One trigger required for each block transfer
    optional_signals: []
    variant: null
    clocks:
      domain_group: null
  EXTERNAL_IRQ_0:
    user_label: EXTERNAL_IRQ_0
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ
    functionality: External_IRQ
    api: HAL:Driver:Ext_IRQ
    configuration:
      eic_arch_asynch0: false
      eic_arch_asynch1: false
      eic_arch_asynch10: false
      eic_arch_asynch11: false
      eic_arch_asynch12: false
      eic_arch_asynch13: false
      eic_arch_asynch14: false
      eic_arch_asynch15: false
      eic_arch_asynch2: false
      eic_arch_asynch3: false
      eic_arch_asynch4: false
      eic_arch_asynch5: false
      eic_arch_asynch6: false
      eic_arch_asynch7: false
      eic_arch_asynch8: false
      eic_arch_asynch9: false
      eic_arch_cksel: Clocked by GCLK
      eic_arch_debounce_enable0: false
      eic_arch_debounce_enable1: false
      eic_arch_debounce_enable10: false
      eic_arch_debounce_enable11: false
      eic_arch_debounce_enable12: false
      eic_arch_debounce_enable13: false
      eic_arch_debounce_enable14: false
      eic_arch_debounce_enable15: false
      eic_arch_debounce_enable2: false
      eic_arch_debounce_enable3: false
      eic_arch_debounce_enable4: false
      eic_arch_debounce_enable5: false
      eic_arch_debounce_enable6: false
      eic_arch_debounce_enable7: false
      eic_arch_debounce_enable8: false
      eic_arch_debounce_enable9: false
      eic_arch_enable_irq_setting0: false
      eic_arch_enable_irq_setting1: false
      eic_arch_enable_irq_setting10: false
      eic_arch_enable_irq_setting11: false
      eic_arch_enable_irq_setting12: false
      eic_arch_enable_irq_setting13: false
      eic_arch_enable_irq_setting14: false
      eic_arch_enable_irq_setting15: false
      eic_arch_enable_irq_setting2: false
      eic_arch_enable_irq_setting3: false
      eic_arch_enable_irq_setting4: false
      eic_arch_enable_irq_setting5: true
      eic_arch_enable_irq_setting6: false
      eic_arch_enable_irq_setting7: false
      eic_arch_enable_irq_setting8: false
      eic_arch_enable_irq_setting9: false
      eic_arch_extinteo0: false
      eic_arch_extinteo1: false
      eic_arch_extinteo10: false
      eic_arch_extinteo11: false
      eic_arch_extinteo12: false
      eic_arch_extinteo13: false
      eic_arch_extinteo14: false
      eic_arch_extinteo15: false
      eic_arch_extinteo2: false
      eic_arch_extinteo3: false
      eic_arch_extinteo4: false
      eic_arch_extinteo5: false
      eic_arch_extinteo6: false
      eic_arch_extinteo7: false
      eic_arch_extinteo8: false
      eic_arch_extinteo9: false
      eic_arch_filten0: false
      eic_arch_filten1: false
      eic_arch_filten10: false
      eic_arch_filten11: false
      eic_arch_filten12: false
      eic_arch_filten13: false
      eic_arch_filten14: false
      eic_arch_filten15: false
      eic_arch_filten2: false
      eic_arch_filten3: false
      eic_arch_filten4: false
      eic_arch_filten5: false
      eic_arch_filten6: false
      eic_arch_filten7: false
      eic_arch_filten8: false
      eic_arch_filten9: false
      eic_arch_nmi_ctrl: false
      eic_arch_nmiasynch: false
      eic_arch_nmifilten: false
      eic_arch_nmisense: No detection
      eic_arch_prescaler0: Divided by 2
      eic_arch_prescaler1: Divided by 2
      eic_arch_sense0: Rising-edge detection
      eic_arch_sense1: No detection
      eic_arch_sense10: No detection
      eic_arch_sense11: No detection
      eic_arch_sense12: No detection
      eic_arch_sense13: No detection
      eic_arch_sense14: No detection
      eic_arch_sense15: No detection
      eic_arch_sense2: No detection
      eic_arch_sense3: No detection
      eic_arch_sense4: No detection
      eic_arch_sense5: Rising-edge detection
      eic_arch_sense6: No detection
      eic_arch_sense7: No detection
      eic_arch_sense8: No detection
      eic_arch_sense9: No detection
      eic_arch_states0: '3'
      eic_arch_states1: '3'
      eic_arch_tickon: The sampling rate is EIC clock
    optional_signals:
    - identifier: EXTERNAL_IRQ_0:EXTINT/5
      pad: PB05
      mode: Enabled
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::EIC.EXTINT.5
      name: EIC/EXTINT/5
      label: EXTINT/5
    variant: null
    clocks:
      domain_group:
        nodes:
        - name: EIC
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        configuration:
          eic_gclk_selection: Generic clock generator 0
  EVENT_SYSTEM_0:
    user_label: EVENT_SYSTEM_0
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::EVSYS::driver_config_definition::Event.System::HAL:Driver:Event.system
    functionality: Event_System
    api: HAL:Driver:Event_system
    configuration:
      evsys_channel_0: No channel output selected
      evsys_channel_1: Channel 1
      evsys_channel_10: No channel output selected
      evsys_channel_11: No channel output selected
      evsys_channel_12: No channel output selected
      evsys_channel_17: No channel output selected
      evsys_channel_18: No channel output selected
      evsys_channel_19: No channel output selected
      evsys_channel_2: No channel output selected
      evsys_channel_20: No channel output selected
      evsys_channel_21: No channel output selected
      evsys_channel_22: No channel output selected
      evsys_channel_23: No channel output selected
      evsys_channel_24: No channel output selected
      evsys_channel_25: No channel output selected
      evsys_channel_26: No channel output selected
      evsys_channel_27: No channel output selected
      evsys_channel_28: No channel output selected
      evsys_channel_29: No channel output selected
      evsys_channel_3: No channel output selected
      evsys_channel_30: No channel output selected
      evsys_channel_31: No channel output selected
      evsys_channel_32: No channel output selected
      evsys_channel_33: No channel output selected
      evsys_channel_34: No channel output selected
      evsys_channel_35: No channel output selected
      evsys_channel_36: No channel output selected
      evsys_channel_37: No channel output selected
      evsys_channel_38: No channel output selected
      evsys_channel_39: No channel output selected
      evsys_channel_4: No channel output selected
      evsys_channel_40: No channel output selected
      evsys_channel_41: No channel output selected
      evsys_channel_42: No channel output selected
      evsys_channel_43: No channel output selected
      evsys_channel_44: Channel 1
      evsys_channel_45: No channel output selected
      evsys_channel_46: No channel output selected
      evsys_channel_47: No channel output selected
      evsys_channel_48: No channel output selected
      evsys_channel_49: No channel output selected
      evsys_channel_5: No channel output selected
      evsys_channel_50: No channel output selected
      evsys_channel_51: No channel output selected
      evsys_channel_52: No channel output selected
      evsys_channel_53: No channel output selected
      evsys_channel_54: No channel output selected
      evsys_channel_55: Channel 0
      evsys_channel_56: No channel output selected
      evsys_channel_57: Channel 0
      evsys_channel_58: No channel output selected
      evsys_channel_59: No channel output selected
      evsys_channel_6: No channel output selected
      evsys_channel_60: No channel output selected
      evsys_channel_61: No channel output selected
      evsys_channel_62: No channel output selected
      evsys_channel_63: No channel output selected
      evsys_channel_64: No channel output selected
      evsys_channel_65: No channel output selected
      evsys_channel_66: No channel output selected
      evsys_channel_7: No channel output selected
      evsys_channel_8: No channel output selected
      evsys_channel_9: No channel output selected
      evsys_channel_setting_0: true
      evsys_channel_setting_1: true
      evsys_channel_setting_10: false
      evsys_channel_setting_11: false
      evsys_channel_setting_12: false
      evsys_channel_setting_13: false
      evsys_channel_setting_14: false
      evsys_channel_setting_15: false
      evsys_channel_setting_16: false
      evsys_channel_setting_17: false
      evsys_channel_setting_18: false
      evsys_channel_setting_19: false
      evsys_channel_setting_2: false
      evsys_channel_setting_20: false
      evsys_channel_setting_21: false
      evsys_channel_setting_22: false
      evsys_channel_setting_23: false
      evsys_channel_setting_24: false
      evsys_channel_setting_25: false
      evsys_channel_setting_26: false
      evsys_channel_setting_27: false
      evsys_channel_setting_28: false
      evsys_channel_setting_29: false
      evsys_channel_setting_3: false
      evsys_channel_setting_30: false
      evsys_channel_setting_31: false
      evsys_channel_setting_4: false
      evsys_channel_setting_5: false
      evsys_channel_setting_6: false
      evsys_channel_setting_7: false
      evsys_channel_setting_8: false
      evsys_channel_setting_9: false
      evsys_edgsel_0: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_1: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_10: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_11: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_12: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_13: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_14: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_15: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_16: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_17: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_18: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_19: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_2: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_20: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_21: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_22: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_23: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_24: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_25: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_26: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_27: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_28: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_29: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_3: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_30: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_31: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_4: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_5: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_6: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_7: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_8: No event output when using the resynchronized or synchronous
        path
      evsys_edgsel_9: No event output when using the resynchronized or synchronous
        path
      evsys_evd_0: false
      evsys_evd_1: false
      evsys_evd_10: false
      evsys_evd_11: false
      evsys_evd_12: false
      evsys_evd_13: false
      evsys_evd_14: false
      evsys_evd_15: false
      evsys_evd_16: false
      evsys_evd_17: false
      evsys_evd_18: false
      evsys_evd_19: false
      evsys_evd_2: false
      evsys_evd_20: false
      evsys_evd_21: false
      evsys_evd_22: false
      evsys_evd_23: false
      evsys_evd_24: false
      evsys_evd_25: false
      evsys_evd_26: false
      evsys_evd_27: false
      evsys_evd_28: false
      evsys_evd_29: false
      evsys_evd_3: false
      evsys_evd_30: false
      evsys_evd_31: false
      evsys_evd_4: false
      evsys_evd_5: false
      evsys_evd_6: false
      evsys_evd_7: false
      evsys_evd_8: false
      evsys_evd_9: false
      evsys_evgen_0: TCC1 overflow
      evsys_evgen_1: CCL LUT output 0
      evsys_evgen_10: No event generator
      evsys_evgen_11: No event generator
      evsys_evgen_12: No event generator
      evsys_evgen_13: No event generator
      evsys_evgen_14: No event generator
      evsys_evgen_15: No event generator
      evsys_evgen_16: No event generator
      evsys_evgen_17: No event generator
      evsys_evgen_18: No event generator
      evsys_evgen_19: No event generator
      evsys_evgen_2: No event generator
      evsys_evgen_20: No event generator
      evsys_evgen_21: No event generator
      evsys_evgen_22: No event generator
      evsys_evgen_23: No event generator
      evsys_evgen_24: No event generator
      evsys_evgen_25: No event generator
      evsys_evgen_26: No event generator
      evsys_evgen_27: No event generator
      evsys_evgen_28: No event generator
      evsys_evgen_29: No event generator
      evsys_evgen_3: No event generator
      evsys_evgen_30: No event generator
      evsys_evgen_31: No event generator
      evsys_evgen_4: No event generator
      evsys_evgen_5: No event generator
      evsys_evgen_6: No event generator
      evsys_evgen_7: No event generator
      evsys_evgen_8: No event generator
      evsys_evgen_9: No event generator
      evsys_ondemand_0: false
      evsys_ondemand_1: false
      evsys_ondemand_10: false
      evsys_ondemand_11: false
      evsys_ondemand_12: false
      evsys_ondemand_13: false
      evsys_ondemand_14: false
      evsys_ondemand_15: false
      evsys_ondemand_16: false
      evsys_ondemand_17: false
      evsys_ondemand_18: false
      evsys_ondemand_19: false
      evsys_ondemand_2: false
      evsys_ondemand_20: false
      evsys_ondemand_21: false
      evsys_ondemand_22: false
      evsys_ondemand_23: false
      evsys_ondemand_24: false
      evsys_ondemand_25: false
      evsys_ondemand_26: false
      evsys_ondemand_27: false
      evsys_ondemand_28: false
      evsys_ondemand_29: false
      evsys_ondemand_3: false
      evsys_ondemand_30: false
      evsys_ondemand_31: false
      evsys_ondemand_4: false
      evsys_ondemand_5: false
      evsys_ondemand_6: false
      evsys_ondemand_7: false
      evsys_ondemand_8: false
      evsys_ondemand_9: false
      evsys_ovr_0: false
      evsys_ovr_1: false
      evsys_ovr_10: false
      evsys_ovr_11: false
      evsys_ovr_12: false
      evsys_ovr_13: false
      evsys_ovr_14: false
      evsys_ovr_15: false
      evsys_ovr_16: false
      evsys_ovr_17: false
      evsys_ovr_18: false
      evsys_ovr_19: false
      evsys_ovr_2: false
      evsys_ovr_20: false
      evsys_ovr_21: false
      evsys_ovr_22: false
      evsys_ovr_23: false
      evsys_ovr_24: false
      evsys_ovr_25: false
      evsys_ovr_26: false
      evsys_ovr_27: false
      evsys_ovr_28: false
      evsys_ovr_29: false
      evsys_ovr_3: false
      evsys_ovr_30: false
      evsys_ovr_31: false
      evsys_ovr_4: false
      evsys_ovr_5: false
      evsys_ovr_6: false
      evsys_ovr_7: false
      evsys_ovr_8: false
      evsys_ovr_9: false
      evsys_path_0: Asynchronous path
      evsys_path_1: Asynchronous path
      evsys_path_10: Synchronous path
      evsys_path_11: Synchronous path
      evsys_path_12: Synchronous path
      evsys_path_13: Synchronous path
      evsys_path_14: Synchronous path
      evsys_path_15: Synchronous path
      evsys_path_16: Synchronous path
      evsys_path_17: Synchronous path
      evsys_path_18: Synchronous path
      evsys_path_19: Synchronous path
      evsys_path_2: Synchronous path
      evsys_path_20: Synchronous path
      evsys_path_21: Synchronous path
      evsys_path_22: Synchronous path
      evsys_path_23: Synchronous path
      evsys_path_24: Synchronous path
      evsys_path_25: Synchronous path
      evsys_path_26: Synchronous path
      evsys_path_27: Synchronous path
      evsys_path_28: Synchronous path
      evsys_path_29: Synchronous path
      evsys_path_3: Synchronous path
      evsys_path_30: Synchronous path
      evsys_path_31: Synchronous path
      evsys_path_4: Synchronous path
      evsys_path_5: Synchronous path
      evsys_path_6: Synchronous path
      evsys_path_7: Synchronous path
      evsys_path_8: Synchronous path
      evsys_path_9: Synchronous path
      evsys_runstdby_0: false
      evsys_runstdby_1: false
      evsys_runstdby_10: false
      evsys_runstdby_11: false
      evsys_runstdby_12: false
      evsys_runstdby_13: false
      evsys_runstdby_14: false
      evsys_runstdby_15: false
      evsys_runstdby_16: false
      evsys_runstdby_17: false
      evsys_runstdby_18: false
      evsys_runstdby_19: false
      evsys_runstdby_2: false
      evsys_runstdby_20: false
      evsys_runstdby_21: false
      evsys_runstdby_22: false
      evsys_runstdby_23: false
      evsys_runstdby_24: false
      evsys_runstdby_25: false
      evsys_runstdby_26: false
      evsys_runstdby_27: false
      evsys_runstdby_28: false
      evsys_runstdby_29: false
      evsys_runstdby_3: false
      evsys_runstdby_30: false
      evsys_runstdby_31: false
      evsys_runstdby_4: false
      evsys_runstdby_5: false
      evsys_runstdby_6: false
      evsys_runstdby_7: false
      evsys_runstdby_8: false
      evsys_runstdby_9: false
    optional_signals: []
    variant: null
    clocks:
      domain_group:
        nodes:
        - name: Channel 0
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        - name: Channel 1
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        - name: Channel 2
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        - name: Channel 3
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        - name: Channel 4
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        - name: Channel 5
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        - name: Channel 6
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        - name: Channel 7
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        - name: Channel 8
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        - name: Channel 9
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        - name: Channel 10
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        - name: Channel 11
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        configuration:
          evsys_clk_selection_0: Generic clock generator 0
          evsys_clk_selection_1: Generic clock generator 0
          evsys_clk_selection_10: Generic clock generator 0
          evsys_clk_selection_11: Generic clock generator 0
          evsys_clk_selection_2: Generic clock generator 0
          evsys_clk_selection_3: Generic clock generator 0
          evsys_clk_selection_4: Generic clock generator 0
          evsys_clk_selection_5: Generic clock generator 0
          evsys_clk_selection_6: Generic clock generator 0
          evsys_clk_selection_7: Generic clock generator 0
          evsys_clk_selection_8: Generic clock generator 0
          evsys_clk_selection_9: Generic clock generator 0
  GCLK:
    user_label: GCLK
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
    functionality: System
    api: HAL:HPL:GCLK
    configuration:
      $input: 12000000
      $input_id: External Crystal Oscillator 8-48MHz (XOSC1)
      RESERVED_InputFreq: 12000000
      RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1)
      _$freq_output_Generic clock generator 0: 100000000
      _$freq_output_Generic clock generator 1: 2000000
      _$freq_output_Generic clock generator 10: 12000000
      _$freq_output_Generic clock generator 11: 12000000
      _$freq_output_Generic clock generator 2: 32768
      _$freq_output_Generic clock generator 3: 32768
      _$freq_output_Generic clock generator 4: 12000000
      _$freq_output_Generic clock generator 5: 12000000
      _$freq_output_Generic clock generator 6: 12000000
      _$freq_output_Generic clock generator 7: 12000000
      _$freq_output_Generic clock generator 8: 12000000
      _$freq_output_Generic clock generator 9: 12000000
      enable_gclk_gen_0: true
      enable_gclk_gen_0__externalclock: 1000000
      enable_gclk_gen_1: true
      enable_gclk_gen_10: false
      enable_gclk_gen_10__externalclock: 1000000
      enable_gclk_gen_11: false
      enable_gclk_gen_11__externalclock: 1000000
      enable_gclk_gen_1__externalclock: 1000000
      enable_gclk_gen_2: true
      enable_gclk_gen_2__externalclock: 1000000
      enable_gclk_gen_3: false
      enable_gclk_gen_3__externalclock: 1000000
      enable_gclk_gen_4: false
      enable_gclk_gen_4__externalclock: 1000000
      enable_gclk_gen_5: false
      enable_gclk_gen_5__externalclock: 1000000
      enable_gclk_gen_6: false
      enable_gclk_gen_6__externalclock: 1000000
      enable_gclk_gen_7: false
      enable_gclk_gen_7__externalclock: 1000000
      enable_gclk_gen_8: false
      enable_gclk_gen_8__externalclock: 1000000
      enable_gclk_gen_9: false
      enable_gclk_gen_9__externalclock: 1000000
      gclk_arch_gen_0_enable: true
      gclk_arch_gen_0_idc: false
      gclk_arch_gen_0_oe: false
      gclk_arch_gen_0_oov: false
      gclk_arch_gen_0_runstdby: false
      gclk_arch_gen_10_enable: false
      gclk_arch_gen_10_idc: false
      gclk_arch_gen_10_oe: false
      gclk_arch_gen_10_oov: false
      gclk_arch_gen_10_runstdby: false
      gclk_arch_gen_11_enable: false
      gclk_arch_gen_11_idc: false
      gclk_arch_gen_11_oe: false
      gclk_arch_gen_11_oov: false
      gclk_arch_gen_11_runstdby: false
      gclk_arch_gen_1_enable: true
      gclk_arch_gen_1_idc: false
      gclk_arch_gen_1_oe: true
      gclk_arch_gen_1_oov: false
      gclk_arch_gen_1_runstdby: false
      gclk_arch_gen_2_enable: true
      gclk_arch_gen_2_idc: false
      gclk_arch_gen_2_oe: false
      gclk_arch_gen_2_oov: false
      gclk_arch_gen_2_runstdby: false
      gclk_arch_gen_3_enable: false
      gclk_arch_gen_3_idc: false
      gclk_arch_gen_3_oe: false
      gclk_arch_gen_3_oov: false
      gclk_arch_gen_3_runstdby: false
      gclk_arch_gen_4_enable: false
      gclk_arch_gen_4_idc: false
      gclk_arch_gen_4_oe: false
      gclk_arch_gen_4_oov: false
      gclk_arch_gen_4_runstdby: false
      gclk_arch_gen_5_enable: false
      gclk_arch_gen_5_idc: false
      gclk_arch_gen_5_oe: false
      gclk_arch_gen_5_oov: false
      gclk_arch_gen_5_runstdby: false
      gclk_arch_gen_6_enable: false
      gclk_arch_gen_6_idc: false
      gclk_arch_gen_6_oe: false
      gclk_arch_gen_6_oov: false
      gclk_arch_gen_6_runstdby: false
      gclk_arch_gen_7_enable: false
      gclk_arch_gen_7_idc: false
      gclk_arch_gen_7_oe: false
      gclk_arch_gen_7_oov: false
      gclk_arch_gen_7_runstdby: false
      gclk_arch_gen_8_enable: false
      gclk_arch_gen_8_idc: false
      gclk_arch_gen_8_oe: false
      gclk_arch_gen_8_oov: false
      gclk_arch_gen_8_runstdby: false
      gclk_arch_gen_9_enable: false
      gclk_arch_gen_9_idc: false
      gclk_arch_gen_9_oe: false
      gclk_arch_gen_9_oov: false
      gclk_arch_gen_9_runstdby: false
      gclk_gen_0_div: 1
      gclk_gen_0_div_sel: false
      gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL1)
      gclk_gen_10_div: 1
      gclk_gen_10_div_sel: false
      gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
      gclk_gen_11_div: 1
      gclk_gen_11_div_sel: false
      gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
      gclk_gen_1_div: 24
      gclk_gen_1_div_sel: false
      gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M)
      gclk_gen_2_div: 1
      gclk_gen_2_div_sel: false
      gclk_gen_2_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
      gclk_gen_3_div: 1
      gclk_gen_3_div_sel: false
      gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
      gclk_gen_4_div: 1
      gclk_gen_4_div_sel: false
      gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
      gclk_gen_5_div: 1
      gclk_gen_5_div_sel: false
      gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
      gclk_gen_6_div: 1
      gclk_gen_6_div_sel: false
      gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
      gclk_gen_7_div: 1
      gclk_gen_7_div_sel: false
      gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
      gclk_gen_8_div: 1
      gclk_gen_8_div_sel: false
      gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
      gclk_gen_9_div: 1
      gclk_gen_9_div_sel: false
      gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
    optional_signals: []
    variant: null
    clocks:
      domain_group: null
  MCLK:
    user_label: MCLK
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK
    functionality: System
    api: HAL:HPL:MCLK
    configuration:
      $input: 100000000
      $input_id: Generic clock generator 0
      RESERVED_InputFreq: 100000000
      RESERVED_InputFreq_id: Generic clock generator 0
      _$freq_output_CPU: 100000000
      cpu_clock_source: Generic clock generator 0
      cpu_div: '1'
      enable_cpu_clock: true
      mclk_arch_bupdiv: Divide by 8
      mclk_arch_hsdiv: Divide by 1
      mclk_arch_lpdiv: Divide by 4
      nvm_wait_states: '0'
    optional_signals: []
    variant: null
    clocks:
      domain_group:
        nodes:
        - name: CPU
          input: CPU
          external: false
          external_frequency: 0
        configuration: {}
  OSC32KCTRL:
    user_label: OSC32KCTRL
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL
    functionality: System
    api: HAL:HPL:OSC32KCTRL
    configuration:
      $input: 32768
      $input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
      RESERVED_InputFreq: 32768
      RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
      _$freq_output_RTC source: 32768
      enable_osculp32k: true
      enable_rtc_source: false
      enable_xosc32k: false
      osculp32k_calib: 0
      osculp32k_calib_enable: false
      rtc_1khz_selection: false
      rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
      xosc32k_arch_cfden: false
      xosc32k_arch_cfdeo: false
      xosc32k_arch_cgm: Standard mode
      xosc32k_arch_en1k: false
      xosc32k_arch_en32k: false
      xosc32k_arch_enable: false
      xosc32k_arch_ondemand: true
      xosc32k_arch_runstdby: false
      xosc32k_arch_startup: 62592us
      xosc32k_arch_swben: false
      xosc32k_arch_xtalen: true
    optional_signals: []
    variant: null
    clocks:
      domain_group: null
  OSCCTRL:
    user_label: OSCCTRL
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL
    functionality: System
    api: HAL:HPL:OSCCTRL
    configuration:
      $input: 2000000
      $input_id: Generic clock generator 1
      RESERVED_InputFreq: 2000000
      RESERVED_InputFreq_id: Generic clock generator 1
      _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
      _$freq_output_Digital Phase Locked Loop (DPLL0): 47985664
      _$freq_output_Digital Phase Locked Loop (DPLL1): 100000000
      _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000
      _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000
      dfll_arch_bplckc: false
      dfll_arch_calibration: false
      dfll_arch_ccdis: false
      dfll_arch_coarse: 31
      dfll_arch_cstep: 1
      dfll_arch_enable: true
      dfll_arch_fine: 128
      dfll_arch_fstep: 1
      dfll_arch_llaw: false
      dfll_arch_ondemand: false
      dfll_arch_qldis: false
      dfll_arch_runstdby: false
      dfll_arch_stable: false
      dfll_arch_usbcrm: false
      dfll_arch_waitlock: true
      dfll_mode: Open Loop Mode
      dfll_mul: 0
      dfll_ref_clock: Generic clock generator 2
      enable_dfll: true
      enable_fdpll0: false
      enable_fdpll1: true
      enable_xosc0: false
      enable_xosc1: false
      fdpll0_arch_dcoen: false
      fdpll0_arch_enable: false
      fdpll0_arch_filter: 0
      fdpll0_arch_lbypass: false
      fdpll0_arch_ltime: No time-out, automatic lock
      fdpll0_arch_ondemand: false
      fdpll0_arch_refclk: XOSC32K clock reference
      fdpll0_arch_runstdby: false
      fdpll0_arch_wuf: false
      fdpll0_clock_dcofilter: 0
      fdpll0_clock_div: 0
      fdpll0_ldr: 1463
      fdpll0_ldrfrac: 13
      fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)
      fdpll1_arch_dcoen: false
      fdpll1_arch_enable: true
      fdpll1_arch_filter: 0
      fdpll1_arch_lbypass: false
      fdpll1_arch_ltime: No time-out, automatic lock
      fdpll1_arch_ondemand: false
      fdpll1_arch_refclk: GCLK clock reference
      fdpll1_arch_runstdby: false
      fdpll1_arch_wuf: false
      fdpll1_clock_dcofilter: 0
      fdpll1_clock_div: 0
      fdpll1_ldr: 49
      fdpll1_ldrfrac: 0
      fdpll1_ref_clock: Generic clock generator 1
      xosc0_arch_cfden: false
      xosc0_arch_enable: false
      xosc0_arch_enalc: false
      xosc0_arch_lowbufgain: false
      xosc0_arch_ondemand: false
      xosc0_arch_runstdby: false
      xosc0_arch_startup: 31us
      xosc0_arch_swben: false
      xosc0_arch_xtalen: false
      xosc0_frequency: 12000000
      xosc1_arch_cfden: false
      xosc1_arch_enable: false
      xosc1_arch_enalc: false
      xosc1_arch_lowbufgain: false
      xosc1_arch_ondemand: false
      xosc1_arch_runstdby: false
      xosc1_arch_startup: 31us
      xosc1_arch_swben: false
      xosc1_arch_xtalen: true
      xosc1_frequency: 12000000
    optional_signals: []
    variant: null
    clocks:
      domain_group: null
  POSITION_DECODER_0:
    user_label: POSITION_DECODER_0
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::PDEC::driver_config_definition::Position.Decoder::HAL:Driver:PDEC.Async
    functionality: Position_Decoder
    api: HAL:Driver:PDEC_Async
    configuration:
      pdec_config: Auto correction mode (AUTOC)
      pdec_dbgrun: false
      pdec_direo: false
      pdec_erroreo: false
      pdec_event_settings: false
      pdec_filter_settings: false
      pdec_fliter: 0
      pdec_index_invert: false
      pdec_int_dir: false
      pdec_int_error: false
      pdec_int_overflow: false
      pdec_int_vel: true
      pdec_min_duration: 0
      pdec_overflow: false
      pdec_pha_matcheo: false
      pdec_phase_swap: false
      pdec_phasea_invert: false
      pdec_phaseb_invert: false
      pdec_phb_matcheo: false
      pdec_prescaler: No division
      pdec_runstdby: false
      pdec_velocityeo: false
    optional_signals: []
    variant: null
    clocks:
      domain_group:
        nodes:
        - name: PDEC
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        configuration:
          pdec_gclk_selection: Generic clock generator 0
  PORT:
    user_label: PORT
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT
    functionality: System
    api: HAL:HPL:PORT
    configuration:
      enable_port_input_event_0: true
      enable_port_input_event_1: false
      enable_port_input_event_2: false
      enable_port_input_event_3: false
      porta_event_action_0: Output register of pin will be set to level of event
      porta_event_action_1: Output register of pin will be set to level of event
      porta_event_action_2: Output register of pin will be set to level of event
      porta_event_action_3: Output register of pin will be set to level of event
      porta_event_pin_identifier_0: 0
      porta_event_pin_identifier_1: 0
      porta_event_pin_identifier_2: 0
      porta_event_pin_identifier_3: 0
      porta_input_event_enable_0: false
      porta_input_event_enable_1: false
      porta_input_event_enable_2: false
      porta_input_event_enable_3: false
      portb_event_action_0: Output register of pin will be set to level of event
      portb_event_action_1: Output register of pin will be set to level of event
      portb_event_action_2: Output register of pin will be set to level of event
      portb_event_action_3: Output register of pin will be set to level of event
      portb_event_pin_identifier_0: 0
      portb_event_pin_identifier_1: 0
      portb_event_pin_identifier_2: 0
      portb_event_pin_identifier_3: 0
      portb_input_event_enable_0: false
      portb_input_event_enable_1: false
      portb_input_event_enable_2: false
      portb_input_event_enable_3: false
      portc_event_action_0: Toggle output register of pin on event
      portc_event_action_1: Output register of pin will be set to level of event
      portc_event_action_2: Output register of pin will be set to level of event
      portc_event_action_3: Output register of pin will be set to level of event
      portc_event_pin_identifier_0: 10
      portc_event_pin_identifier_1: 0
      portc_event_pin_identifier_2: 0
      portc_event_pin_identifier_3: 0
      portc_input_event_enable_0: false
      portc_input_event_enable_1: false
      portc_input_event_enable_2: false
      portc_input_event_enable_3: false
      portd_event_action_0: Toggle output register of pin on event
      portd_event_action_1: Output register of pin will be set to level of event
      portd_event_action_2: Output register of pin will be set to level of event
      portd_event_action_3: Output register of pin will be set to level of event
      portd_event_pin_identifier_0: 10
      portd_event_pin_identifier_1: 0
      portd_event_pin_identifier_2: 0
      portd_event_pin_identifier_3: 0
      portd_input_event_enable_0: true
      portd_input_event_enable_1: false
      portd_input_event_enable_2: false
      portd_input_event_enable_3: false
    optional_signals: []
    variant: null
    clocks:
      domain_group: null
  RAMECC:
    user_label: RAMECC
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC
    functionality: System
    api: HAL:HPL:RAMECC
    configuration: {}
    optional_signals: []
    variant: null
    clocks:
      domain_group: null
  SPI_0:
    user_label: SPI_0
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM5::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.DMA
    functionality: SPI
    api: HAL:Driver:SPI_Master_DMA
    configuration:
      spi_master_advanced: true
      spi_master_arch_cpha: Sample input on leading edge
      spi_master_arch_cpol: SCK is low when idle
      spi_master_arch_dbgstop: Keep running
      spi_master_arch_dord: MSB first
      spi_master_arch_ibon: In data stream
      spi_master_arch_runstdby: false
      spi_master_baud_rate: 6000000
      spi_master_character_size: 8 bits
      spi_master_dma_rx_channel: 0
      spi_master_dma_tx_channel: 1
      spi_master_dummybyte: 511
      spi_master_rx_channel: true
      spi_master_rx_enable: true
    optional_signals: []
    variant:
      specification: TXPO=0, RXPO=3
      required_signals:
      - name: SERCOM5/PAD/0
        pad: PB16
        label: MOSI
      - name: SERCOM5/PAD/1
        pad: PB17
        label: SCK
      - name: SERCOM5/PAD/3
        pad: PB01
        label: MISO
    clocks:
      domain_group:
        nodes:
        - name: Core
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        - name: Slow
          input: Generic clock generator 3
          external: false
          external_frequency: 0
        configuration:
          core_gclk_selection: Generic clock generator 0
          slow_gclk_selection: Generic clock generator 3
  TC_SPEED:
    user_label: TC_SPEED
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC0::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer
    functionality: Timer
    api: Lite:TC:Timer
    configuration:
      cc_cc0: 0
      cc_cc1: 0
      cc_control: false
      count_control: false
      count_count: 0
      ctrla_alock: false
      ctrla_capten0: true
      ctrla_capten1: true
      ctrla_captmode0: DEFAULT
      ctrla_captmode1: DEFAULT
      ctrla_control: true
      ctrla_copen0: false
      ctrla_copen1: false
      ctrla_enable: true
      ctrla_mode: 2
      ctrla_ondemand: false
      ctrla_prescaler: DIV4
      ctrla_prescsync: GCLK
      ctrla_runstdby: false
      ctrlbset_cmd: NONE
      ctrlbset_control: false
      ctrlbset_dir: false
      ctrlbset_lupd: false
      ctrlbset_oneshot: false
      ctrlc_inven0: false
      ctrlc_inven1: false
      dbgctrl_control: false
      dbgctrl_dbgrun: false
      drvctrl_control: false
      evctrl_control: true
      evctrl_evact: PPW
      evctrl_mceo0: false
      evctrl_mceo1: false
      evctrl_ovfeo: true
      evctrl_tcei: true
      evctrl_tcinv: false
      intenset_control: true
      intenset_err: false
      intenset_mc0: false
      intenset_mc1: false
      intenset_ovf: true
      wave_control: true
      wave_wavegen: NFRQ
    optional_signals: []
    variant: null
    clocks:
      domain_group:
        nodes:
        - name: TC
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        configuration:
          tc_gclk_selection: Generic clock generator 0
  TC_ECAT:
    user_label: TC_ECAT
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC7::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer
    functionality: Timer
    api: Lite:TC:Timer
    configuration:
      cc_cc0: 25000
      cc_cc1: 0
      cc_control: true
      count_control: false
      count_count: 0
      ctrla_alock: false
      ctrla_capten0: false
      ctrla_capten1: false
      ctrla_captmode0: DEFAULT
      ctrla_captmode1: DEFAULT
      ctrla_control: true
      ctrla_copen0: false
      ctrla_copen1: false
      ctrla_enable: true
      ctrla_mode: 0
      ctrla_ondemand: false
      ctrla_prescaler: DIV4
      ctrla_prescsync: GCLK
      ctrla_runstdby: false
      ctrlbset_cmd: NONE
      ctrlbset_control: false
      ctrlbset_dir: false
      ctrlbset_lupd: false
      ctrlbset_oneshot: false
      ctrlc_inven0: false
      ctrlc_inven1: false
      dbgctrl_control: false
      dbgctrl_dbgrun: false
      drvctrl_control: false
      evctrl_control: false
      evctrl_evact: 'OFF'
      evctrl_mceo0: false
      evctrl_mceo1: false
      evctrl_ovfeo: false
      evctrl_tcei: false
      evctrl_tcinv: false
      intenset_control: true
      intenset_err: false
      intenset_mc0: false
      intenset_mc1: false
      intenset_ovf: true
      wave_control: true
      wave_wavegen: MFRQ
    optional_signals: []
    variant: null
    clocks:
      domain_group:
        nodes:
        - name: TC
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        configuration:
          tc_gclk_selection: Generic clock generator 0
  TCC_PWM2:
    user_label: TCC_PWM2
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TCC0::driver_config_definition::PWM.Mode::Lite:TCC:PWM
    functionality: PWM
    api: Lite:TCC:PWM
    configuration:
      cc_cc0: 0
      cc_cc1: 0
      cc_cc2: 0
      cc_cc3: 0
      cc_cc4: 0
      cc_cc5: 0
      cc_control: true
      ctrla_alock: false
      ctrla_control: true
      ctrla_enable: true
      ctrla_prescaler: DIV2
      ctrla_prescsync: GCLK
      ctrla_runstdby: false
      ctrlbset_cmd: NONE
      ctrlbset_control: false
      ctrlbset_dir: false
      ctrlbset_idxcmd: DISABLE
      ctrlbset_lupd: false
      ctrlbset_oneshot: false
      dbgctrl_control: false
      dbgctrl_dbgrun: false
      dbgctrl_fddbd: false
      drvctrl_control: false
      drvctrl_filterval0: 0
      drvctrl_filterval1: 0
      drvctrl_inven0: false
      drvctrl_inven1: false
      drvctrl_inven2: false
      drvctrl_inven3: false
      drvctrl_inven4: false
      drvctrl_inven5: false
      drvctrl_inven6: false
      drvctrl_inven7: false
      drvctrl_nre0: false
      drvctrl_nre1: false
      drvctrl_nre2: false
      drvctrl_nre3: false
      drvctrl_nre4: false
      drvctrl_nre5: false
      drvctrl_nre6: false
      drvctrl_nre7: false
      drvctrl_nrv0: false
      drvctrl_nrv1: false
      drvctrl_nrv2: false
      drvctrl_nrv3: false
      drvctrl_nrv4: false
      drvctrl_nrv5: false
      drvctrl_nrv6: false
      drvctrl_nrv7: false
      evctrl_cnteo: false
      evctrl_cntsel: START
      evctrl_control: true
      evctrl_evact0: 'OFF'
      evctrl_evact1: 'OFF'
      evctrl_mcei0: false
      evctrl_mcei1: false
      evctrl_mcei2: false
      evctrl_mcei3: false
      evctrl_mcei4: false
      evctrl_mcei5: false
      evctrl_mceo0: false
      evctrl_mceo1: false
      evctrl_mceo2: false
      evctrl_mceo3: false
      evctrl_mceo4: false
      evctrl_mceo5: false
      evctrl_ovfeo: true
      evctrl_tcei0: false
      evctrl_tcei1: false
      evctrl_tcinv0: false
      evctrl_tcinv1: false
      evctrl_trgeo: false
      fctrla_blank: NONE
      fctrla_blankpresc: false
      fctrla_blankval: 0
      fctrla_chsel: CC0
      fctrla_control: false
      fctrla_filterval: 0
      fctrla_halt: DISABLE
      fctrla_keep: false
      fctrla_qual: false
      fctrla_restart: false
      fctrla_src: DISABLE
      fctrlb_blank: NONE
      fctrlb_blankpresc: false
      fctrlb_blankval: 0
      fctrlb_chsel: CC0
      fctrlb_control: false
      fctrlb_filterval: 0
      fctrlb_halt: DISABLE
      fctrlb_keep: false
      fctrlb_qual: false
      fctrlb_restart: false
      fctrlb_src: DISABLE
      intenset_cnt: false
      intenset_control: false
      intenset_dfs: false
      intenset_err: false
      intenset_fault0: false
      intenset_fault1: false
      intenset_faulta: false
      intenset_faultb: false
      intenset_mc0: false
      intenset_mc1: false
      intenset_mc2: false
      intenset_mc3: false
      intenset_mc4: false
      intenset_mc5: false
      intenset_ovf: false
      intenset_trg: false
      patt_control: false
      patt_pge0: false
      patt_pge1: false
      patt_pge2: false
      patt_pge3: false
      patt_pgv0: false
      patt_pgv1: false
      patt_pgv2: false
      patt_pgv3: false
      per_control: true
      per_per: 1000
      wave_ciccen0: false
      wave_ciccen1: false
      wave_ciccen2: false
      wave_ciccen3: false
      wave_ciperen: false
      wave_control: true
      wave_pol0: true
      wave_pol1: true
      wave_pol2: true
      wave_pol3: true
      wave_pol4: true
      wave_pol5: true
      wave_ramp: RAMP1
      wave_swap0: false
      wave_swap1: false
      wave_swap2: false
      wave_swap3: false
      wave_wavegen: DSBOTTOM
      wexctrl_control: true
      wexctrl_dths: 0
      wexctrl_dtien0: false
      wexctrl_dtien1: false
      wexctrl_dtien2: false
      wexctrl_dtien3: false
      wexctrl_dtls: 0
      wexctrl_otmx: 0
    optional_signals:
    - identifier: TCC_PWM2:WO/0
      pad: PC04
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC0.WO.0
      name: TCC0/WO/0
      label: WO/0
    - identifier: TCC_PWM2:WO/1
      pad: PD08
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC0.WO.1
      name: TCC0/WO/1
      label: WO/1
    - identifier: TCC_PWM2:WO/2
      pad: PD09
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC0.WO.2
      name: TCC0/WO/2
      label: WO/2
    - identifier: TCC_PWM2:WO/3
      pad: PD10
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC0.WO.3
      name: TCC0/WO/3
      label: WO/3
    - identifier: TCC_PWM2:WO/4
      pad: PA16
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC0.WO.4
      name: TCC0/WO/4
      label: WO/4
    - identifier: TCC_PWM2:WO/5
      pad: PA17
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC0.WO.5
      name: TCC0/WO/5
      label: WO/5
    - identifier: TCC_PWM2:WO/6
      pad: PC22
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC0.WO.6
      name: TCC0/WO/6
      label: WO/6
    - identifier: TCC_PWM2:WO/7
      pad: PC23
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC0.WO.7
      name: TCC0/WO/7
      label: WO/7
    variant: null
    clocks:
      domain_group:
        nodes:
        - name: TCC
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        configuration:
          tcc_gclk_selection: Generic clock generator 0
  TCC_PWM:
    user_label: TCC_PWM
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TCC1::driver_config_definition::PWM.Mode::Lite:TCC:PWM
    functionality: PWM
    api: Lite:TCC:PWM
    configuration:
      cc_cc0: 0
      cc_cc1: 0
      cc_cc2: 0
      cc_cc3: 0
      cc_cc4: 0
      cc_cc5: 0
      cc_control: false
      ctrla_alock: false
      ctrla_control: true
      ctrla_enable: true
      ctrla_prescaler: DIV2
      ctrla_prescsync: GCLK
      ctrla_runstdby: false
      ctrlbset_cmd: NONE
      ctrlbset_control: false
      ctrlbset_dir: false
      ctrlbset_idxcmd: DISABLE
      ctrlbset_lupd: false
      ctrlbset_oneshot: false
      dbgctrl_control: false
      dbgctrl_dbgrun: false
      dbgctrl_fddbd: false
      drvctrl_control: false
      drvctrl_filterval0: 0
      drvctrl_filterval1: 0
      drvctrl_inven0: false
      drvctrl_inven1: false
      drvctrl_inven2: false
      drvctrl_inven3: false
      drvctrl_inven4: false
      drvctrl_inven5: false
      drvctrl_inven6: false
      drvctrl_inven7: false
      drvctrl_nre0: false
      drvctrl_nre1: false
      drvctrl_nre2: false
      drvctrl_nre3: false
      drvctrl_nre4: false
      drvctrl_nre5: false
      drvctrl_nre6: false
      drvctrl_nre7: false
      drvctrl_nrv0: false
      drvctrl_nrv1: false
      drvctrl_nrv2: false
      drvctrl_nrv3: false
      drvctrl_nrv4: false
      drvctrl_nrv5: false
      drvctrl_nrv6: false
      drvctrl_nrv7: false
      evctrl_cnteo: false
      evctrl_cntsel: START
      evctrl_control: true
      evctrl_evact0: 'OFF'
      evctrl_evact1: 'OFF'
      evctrl_mcei0: false
      evctrl_mcei1: false
      evctrl_mcei2: false
      evctrl_mcei3: false
      evctrl_mcei4: false
      evctrl_mcei5: false
      evctrl_mceo0: false
      evctrl_mceo1: false
      evctrl_mceo2: false
      evctrl_mceo3: false
      evctrl_mceo4: false
      evctrl_mceo5: false
      evctrl_ovfeo: true
      evctrl_tcei0: false
      evctrl_tcei1: false
      evctrl_tcinv0: false
      evctrl_tcinv1: false
      evctrl_trgeo: false
      fctrla_blank: NONE
      fctrla_blankpresc: false
      fctrla_blankval: 0
      fctrla_chsel: CC0
      fctrla_control: false
      fctrla_filterval: 0
      fctrla_halt: DISABLE
      fctrla_keep: false
      fctrla_qual: false
      fctrla_restart: false
      fctrla_src: DISABLE
      fctrlb_blank: NONE
      fctrlb_blankpresc: false
      fctrlb_blankval: 0
      fctrlb_chsel: CC0
      fctrlb_control: false
      fctrlb_filterval: 0
      fctrlb_halt: DISABLE
      fctrlb_keep: false
      fctrlb_qual: false
      fctrlb_restart: false
      fctrlb_src: DISABLE
      intenset_cnt: false
      intenset_control: false
      intenset_dfs: false
      intenset_err: false
      intenset_fault0: false
      intenset_fault1: false
      intenset_faulta: false
      intenset_faultb: false
      intenset_mc0: false
      intenset_mc1: false
      intenset_mc2: false
      intenset_mc3: false
      intenset_mc4: false
      intenset_mc5: false
      intenset_ovf: false
      intenset_trg: false
      patt_control: false
      patt_pge0: false
      patt_pge1: false
      patt_pge2: false
      patt_pge3: false
      patt_pgv0: false
      patt_pgv1: false
      patt_pgv2: false
      patt_pgv3: false
      per_control: true
      per_per: 1000
      wave_ciccen0: false
      wave_ciccen1: false
      wave_ciccen2: false
      wave_ciccen3: false
      wave_ciperen: false
      wave_control: true
      wave_pol0: true
      wave_pol1: true
      wave_pol2: true
      wave_pol3: true
      wave_pol4: false
      wave_pol5: false
      wave_ramp: RAMP1
      wave_swap0: false
      wave_swap1: false
      wave_swap2: false
      wave_swap3: false
      wave_wavegen: DSBOTTOM
      wexctrl_control: true
      wexctrl_dths: 0
      wexctrl_dtien0: false
      wexctrl_dtien1: false
      wexctrl_dtien2: false
      wexctrl_dtien3: false
      wexctrl_dtls: 0
      wexctrl_otmx: 3
    optional_signals:
    - identifier: TCC_PWM:WO/0
      pad: PC14
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC1.WO.0
      name: TCC1/WO/0
      label: WO/0
    - identifier: TCC_PWM:WO/2
      pad: PB26
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC1.WO.2
      name: TCC1/WO/2
      label: WO/2
    - identifier: TCC_PWM:WO/3
      pad: PB27
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC1.WO.3
      name: TCC1/WO/3
      label: WO/3
    - identifier: TCC_PWM:WO/4
      pad: PB28
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC1.WO.4
      name: TCC1/WO/4
      label: WO/4
    - identifier: TCC_PWM:WO/5
      pad: PB29
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC1.WO.5
      name: TCC1/WO/5
      label: WO/5
    - identifier: TCC_PWM:WO/6
      pad: PA22
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC1.WO.6
      name: TCC1/WO/6
      label: WO/6
    - identifier: TCC_PWM:WO/7
      pad: PA23
      mode: PWM output
      configuration: null
      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::TCC1.WO.7
      name: TCC1/WO/7
      label: WO/7
    variant: null
    clocks:
      domain_group:
        nodes:
        - name: TCC
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        configuration:
          tcc_gclk_selection: Generic clock generator 0
pads:
  DEBUG_1:
    name: PC01
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC01
    mode: Digital output
    user_label: DEBUG_1
    configuration: null
  DEBUG_3:
    name: PC02
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC02
    mode: Digital output
    user_label: DEBUG_3
    configuration: null
  DEBUG_2:
    name: PC03
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC03
    mode: Digital output
    user_label: DEBUG_2
    configuration: null
  nDRV_RESET:
    name: PB05
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB05
    mode: Digital input
    user_label: nDRV_RESET
    configuration: null
  PB08:
    name: PB08
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB08
    mode: Analog
    user_label: PB08
    configuration: null
  PB09:
    name: PB09
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB09
    mode: Analog
    user_label: PB09
    configuration: null
  HALL_C:
    name: PA04
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA04
    mode: Peripheral IO
    user_label: HALL_C
    configuration: null
  HALL_B:
    name: PA05
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA05
    mode: Peripheral IO
    user_label: HALL_B
    configuration: null
  HALL_A:
    name: PA06
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA06
    mode: Peripheral IO
    user_label: HALL_A
    configuration: null
  M2_0:
    name: PC04
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC04
    mode: Peripheral IO
    user_label: M2_0
    configuration: null
  M3_4:
    name: PB14
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB14
    mode: Digital output
    user_label: M3_4
    configuration: null
  M3_5:
    name: PB15
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB15
    mode: Digital output
    user_label: M3_5
    configuration: null
  M2_1:
    name: PD08
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PD08
    mode: Peripheral IO
    user_label: M2_1
    configuration: null
  M2_2:
    name: PD09
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PD09
    mode: Peripheral IO
    user_label: M2_2
    configuration: null
  M2_3:
    name: PD10
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PD10
    mode: Peripheral IO
    user_label: M2_3
    configuration: null
  M3_2:
    name: PC14
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC14
    mode: Peripheral IO
    user_label: M3_2
    configuration: null
  M2_4:
    name: PA16
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA16
    mode: Peripheral IO
    user_label: M2_4
    configuration: null
  M2_5:
    name: PA17
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA17
    mode: Peripheral IO
    user_label: M2_5
    configuration: null
  M3_3:
    name: PA18
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA18
    mode: Digital output
    user_label: M3_3
    configuration: null
  LED0:
    name: PC18
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC18
    mode: Digital output
    user_label: LED0
    configuration:
      pad_initial_level: Low
  M3_0:
    name: PC22
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC22
    mode: Peripheral IO
    user_label: M3_0
    configuration: null
  M3_1:
    name: PC23
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC23
    mode: Peripheral IO
    user_label: M3_1
    configuration: null
  PB16:
    name: PB16
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB16
    mode: Digital output
    user_label: PB16
    configuration: null
  PB17:
    name: PB17
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB17
    mode: Digital output
    user_label: PB17
    configuration: null
  DRV_ENA:
    name: PA22
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA22
    mode: Peripheral IO
    user_label: DRV_ENA
    configuration: null
  DRV_INA:
    name: PA23
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA23
    mode: Peripheral IO
    user_label: DRV_INA
    configuration: null
  DRV_INC:
    name: PB26
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB26
    mode: Peripheral IO
    user_label: DRV_INC
    configuration: null
  DRV_INB:
    name: PB27
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB27
    mode: Peripheral IO
    user_label: DRV_INB
    configuration: null
  DRV_ENB:
    name: PB28
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB28
    mode: Peripheral IO
    user_label: DRV_ENB
    configuration: null
  DRV_ENC:
    name: PB29
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB29
    mode: Peripheral IO
    user_label: DRV_ENC
    configuration: null
  DRV_RESET:
    name: PA27
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA27
    mode: Digital output
    user_label: DRV_RESET
    configuration: null
  SW0:
    name: PB31
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB31
    mode: Digital input
    user_label: SW0
    configuration:
      pad_pull_config: Pull-up
  DEBUG_4:
    name: PC30
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC30
    mode: Digital output
    user_label: DEBUG_4
    configuration: null
  ECAT_SPI_CS_PIN:
    name: PB00
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB00
    mode: Digital output
    user_label: ECAT_SPI_CS_PIN
    configuration:
      pad_initial_level: High
  PB01:
    name: PB01
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB01
    mode: Digital input
    user_label: PB01
    configuration: null
toolchain_options: []
