diff --git a/BLDC_E54/.vs/BLDC_E54/v14/.atsuo b/BLDC_E54/.vs/BLDC_E54/v14/.atsuo
index e660b8b..5d8f3cc 100644
Binary files a/BLDC_E54/.vs/BLDC_E54/v14/.atsuo and b/BLDC_E54/.vs/BLDC_E54/v14/.atsuo differ
diff --git a/BLDC_E54/BLDC_E54/.atmelstart/AtmelStart.gpdsc b/BLDC_E54/BLDC_E54/.atmelstart/AtmelStart.gpdsc
index be063c4..c30cc14 100644
--- a/BLDC_E54/BLDC_E54/.atmelstart/AtmelStart.gpdsc
+++ b/BLDC_E54/BLDC_E54/.atmelstart/AtmelStart.gpdsc
@@ -42,11 +42,12 @@
       <description>Atmel Start Framework</description>
       <RTE_Components_h>#define ATMEL_START</RTE_Components_h>
       <files>
-        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/adc_async.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/adc_sync.rst"/>
         <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/custom_logic.rst"/>
         <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/evsys.rst"/>
         <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/ext_irq.rst"/>
         <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/pdec_async.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/pwm.rst"/>
         <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_dma.rst"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
@@ -101,14 +102,11 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
-        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_ringbuffer.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
-        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_ringbuffer.c"/>
         <file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
         <file category="doc" condition="ARMCC, GCC, IAR" name="hpl/doc_lite/tc.rst"/>
-        <file category="doc" condition="ARMCC, GCC, IAR" name="hpl/doc_lite/tcc.rst"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_e54.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_e54.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_e54.h"/>
@@ -154,20 +152,24 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
-        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_pwm.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_async.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_pwm.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_dma.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_timer.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
-        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_adc_async.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_adc_sync.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_ext_irq.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_pwm.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_dma.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc.c"/>
@@ -193,8 +195,8 @@
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.h"/>
-        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/tcc/tcc_lite.c"/>
-        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/tcc/tcc_lite.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_adc_config.h"/>
@@ -210,6 +212,7 @@
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_pdec_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tcc_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
         <file category="include" condition="ARMCC, GCC, IAR" name=""/>
         <file category="include" condition="ARMCC, GCC, IAR" name="config"/>
diff --git a/BLDC_E54/BLDC_E54/.atmelstart/atmel_start_config.atstart b/BLDC_E54/BLDC_E54/.atmelstart/atmel_start_config.atstart
index ba6c85c..5f6d02e 100644
--- a/BLDC_E54/BLDC_E54/.atmelstart/atmel_start_config.atstart
+++ b/BLDC_E54/BLDC_E54/.atmelstart/atmel_start_config.atstart
@@ -22,9 +22,9 @@ middlewares: {}
 drivers:
   ADC_0:
     user_label: ADC_0
-    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::ADC0::driver_config_definition::ADC::HAL:Driver:ADC.Async
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::ADC0::driver_config_definition::ADC::HAL:Driver:ADC.Sync
     functionality: ADC
-    api: HAL:Driver:ADC_Async
+    api: HAL:Driver:ADC_Sync
     configuration:
       adc_advanced_settings: true
       adc_arch_adjres: 0
@@ -39,12 +39,12 @@ drivers:
       adc_arch_offsetcorr: 0
       adc_arch_ondemand: false
       adc_arch_refcomp: false
-      adc_arch_resrdyeo: false
+      adc_arch_resrdyeo: true
       adc_arch_runstdby: false
-      adc_arch_samplen: 0
+      adc_arch_samplen: 3
       adc_arch_samplenum: 1 sample
       adc_arch_seqen: 0
-      adc_arch_startei: true
+      adc_arch_startei: false
       adc_arch_startinv: false
       adc_arch_winlt: 0
       adc_arch_winmode: No window mode
@@ -65,61 +65,13 @@ drivers:
       definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::ADC0.AIN.2
       name: ADC0/AIN/2
       label: AIN/2
-    variant: null
-    clocks:
-      domain_group:
-        nodes:
-        - name: ADC
-          input: Generic clock generator 0
-          external: false
-          external_frequency: 0
-        configuration:
-          adc_gclk_selection: Generic clock generator 0
-  ADC_1:
-    user_label: ADC_1
-    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::ADC1::driver_config_definition::ADC::HAL:Driver:ADC.Async
-    functionality: ADC
-    api: HAL:Driver:ADC_Async
-    configuration:
-      adc_advanced_settings: true
-      adc_arch_adjres: 0
-      adc_arch_corren: false
-      adc_arch_dbgrun: false
-      adc_arch_event_settings: true
-      adc_arch_flushei: false
-      adc_arch_flushinv: false
-      adc_arch_gaincorr: 0
-      adc_arch_leftadj: false
-      adc_arch_offcomp: false
-      adc_arch_offsetcorr: 0
-      adc_arch_ondemand: false
-      adc_arch_refcomp: false
-      adc_arch_resrdyeo: false
-      adc_arch_runstdby: false
-      adc_arch_samplen: 0
-      adc_arch_samplenum: 1 sample
-      adc_arch_seqen: 0
-      adc_arch_startei: true
-      adc_arch_startinv: false
-      adc_arch_winlt: 0
-      adc_arch_winmode: No window mode
-      adc_arch_winmoneo: false
-      adc_arch_winut: 0
-      adc_differential_mode: false
-      adc_freerunning_mode: false
-      adc_pinmux_negative: Internal ground
-      adc_pinmux_positive: ADC AIN1 pin
-      adc_prescaler: Peripheral clock divided by 8
-      adc_reference: VDDANA
-      adc_resolution: 12-bit
-    optional_signals:
-    - identifier: ADC_1:AIN/1
+    - identifier: ADC_0:AIN/3
       pad: PB09
       mode: Enabled
       configuration: null
-      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::ADC1.AIN.1
-      name: ADC1/AIN/1
-      label: AIN/1
+      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::ADC0.AIN.3
+      name: ADC0/AIN/3
+      label: AIN/3
     variant: null
     clocks:
       domain_group:
@@ -254,7 +206,7 @@ drivers:
       dmac_beatsize_17: 8-bit bus transfer
       dmac_beatsize_18: 8-bit bus transfer
       dmac_beatsize_19: 8-bit bus transfer
-      dmac_beatsize_2: 8-bit bus transfer
+      dmac_beatsize_2: 32-bit bus transfer
       dmac_beatsize_20: 8-bit bus transfer
       dmac_beatsize_21: 8-bit bus transfer
       dmac_beatsize_22: 8-bit bus transfer
@@ -265,7 +217,7 @@ drivers:
       dmac_beatsize_27: 8-bit bus transfer
       dmac_beatsize_28: 8-bit bus transfer
       dmac_beatsize_29: 8-bit bus transfer
-      dmac_beatsize_3: 8-bit bus transfer
+      dmac_beatsize_3: 16-bit bus transfer
       dmac_beatsize_30: 8-bit bus transfer
       dmac_beatsize_31: 8-bit bus transfer
       dmac_beatsize_4: 8-bit bus transfer
@@ -298,8 +250,7 @@ drivers:
         in the transaction
       dmac_blockact_19: Channel will be disabled if it is the last block transfer
         in the transaction
-      dmac_blockact_2: Channel will be disabled if it is the last block transfer in
-        the transaction
+      dmac_blockact_2: Channel suspend operation is complete
       dmac_blockact_20: Channel will be disabled if it is the last block transfer
         in the transaction
       dmac_blockact_21: Channel will be disabled if it is the last block transfer
@@ -321,7 +272,7 @@ drivers:
       dmac_blockact_29: Channel will be disabled if it is the last block transfer
         in the transaction
       dmac_blockact_3: Channel will be disabled if it is the last block transfer in
-        the transaction
+        the transaction and block interrupt
       dmac_blockact_30: Channel will be disabled if it is the last block transfer
         in the transaction
       dmac_blockact_31: Channel will be disabled if it is the last block transfer
@@ -360,17 +311,17 @@ drivers:
       dmac_channel_27_settings: false
       dmac_channel_28_settings: false
       dmac_channel_29_settings: false
-      dmac_channel_2_settings: false
+      dmac_channel_2_settings: true
       dmac_channel_30_settings: false
       dmac_channel_31_settings: false
-      dmac_channel_3_settings: false
+      dmac_channel_3_settings: true
       dmac_channel_4_settings: false
       dmac_channel_5_settings: false
       dmac_channel_6_settings: false
       dmac_channel_7_settings: false
       dmac_channel_8_settings: false
       dmac_channel_9_settings: false
-      dmac_dbgrun: false
+      dmac_dbgrun: true
       dmac_dstinc_0: true
       dmac_dstinc_1: false
       dmac_dstinc_10: false
@@ -394,7 +345,7 @@ drivers:
       dmac_dstinc_27: false
       dmac_dstinc_28: false
       dmac_dstinc_29: false
-      dmac_dstinc_3: false
+      dmac_dstinc_3: true
       dmac_dstinc_30: false
       dmac_dstinc_31: false
       dmac_dstinc_4: false
@@ -416,7 +367,7 @@ drivers:
       dmac_evact_17: No action
       dmac_evact_18: No action
       dmac_evact_19: No action
-      dmac_evact_2: No action
+      dmac_evact_2: Channel resume operation
       dmac_evact_20: No action
       dmac_evact_21: No action
       dmac_evact_22: No action
@@ -448,7 +399,7 @@ drivers:
       dmac_evie_17: false
       dmac_evie_18: false
       dmac_evie_19: false
-      dmac_evie_2: false
+      dmac_evie_2: true
       dmac_evie_20: false
       dmac_evie_21: false
       dmac_evie_22: false
@@ -532,8 +483,8 @@ drivers:
       dmac_evosel_7: Event generation disabled
       dmac_evosel_8: Event generation disabled
       dmac_evosel_9: Event generation disabled
-      dmac_lvl_0: Channel priority 0
-      dmac_lvl_1: Channel priority 0
+      dmac_lvl_0: Channel priority 1
+      dmac_lvl_1: Channel priority 1
       dmac_lvl_10: Channel priority 0
       dmac_lvl_11: Channel priority 0
       dmac_lvl_12: Channel priority 0
@@ -565,17 +516,17 @@ drivers:
       dmac_lvl_8: Channel priority 0
       dmac_lvl_9: Channel priority 0
       dmac_lvlen0: true
-      dmac_lvlen1: false
-      dmac_lvlen2: false
-      dmac_lvlen3: false
+      dmac_lvlen1: true
+      dmac_lvlen2: true
+      dmac_lvlen3: true
       dmac_lvlpri0: 0
       dmac_lvlpri1: 0
       dmac_lvlpri2: 0
       dmac_lvlpri3: 0
       dmac_rrlvlen0: Round-robin arbitration scheme for channel with priority 0
       dmac_rrlvlen1: Round-robin arbitration scheme for channel with priority 1
-      dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
-      dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
+      dmac_rrlvlen2: Round-robin arbitration scheme for channel with priority 2
+      dmac_rrlvlen3: Round-robin arbitration scheme for channel with priority 3
       dmac_runstdby_0: false
       dmac_runstdby_1: false
       dmac_runstdby_10: false
@@ -588,7 +539,7 @@ drivers:
       dmac_runstdby_17: false
       dmac_runstdby_18: false
       dmac_runstdby_19: false
-      dmac_runstdby_2: false
+      dmac_runstdby_2: true
       dmac_runstdby_20: false
       dmac_runstdby_21: false
       dmac_runstdby_22: false
@@ -599,7 +550,7 @@ drivers:
       dmac_runstdby_27: false
       dmac_runstdby_28: false
       dmac_runstdby_29: false
-      dmac_runstdby_3: false
+      dmac_runstdby_3: true
       dmac_runstdby_30: false
       dmac_runstdby_31: false
       dmac_runstdby_4: false
@@ -620,7 +571,7 @@ drivers:
       dmac_srcinc_17: false
       dmac_srcinc_18: false
       dmac_srcinc_19: false
-      dmac_srcinc_2: false
+      dmac_srcinc_2: true
       dmac_srcinc_20: false
       dmac_srcinc_21: false
       dmac_srcinc_22: false
@@ -652,7 +603,7 @@ drivers:
       dmac_stepsel_17: Step size settings apply to the destination address
       dmac_stepsel_18: Step size settings apply to the destination address
       dmac_stepsel_19: Step size settings apply to the destination address
-      dmac_stepsel_2: Step size settings apply to the destination address
+      dmac_stepsel_2: Step size settings apply to the source address
       dmac_stepsel_20: Step size settings apply to the destination address
       dmac_stepsel_21: Step size settings apply to the destination address
       dmac_stepsel_22: Step size settings apply to the destination address
@@ -716,7 +667,7 @@ drivers:
       dmac_trifsrc_17: Only software/event triggers
       dmac_trifsrc_18: Only software/event triggers
       dmac_trifsrc_19: Only software/event triggers
-      dmac_trifsrc_2: Only software/event triggers
+      dmac_trifsrc_2: ADC0 Sequencing Trigger
       dmac_trifsrc_20: Only software/event triggers
       dmac_trifsrc_21: Only software/event triggers
       dmac_trifsrc_22: Only software/event triggers
@@ -727,7 +678,7 @@ drivers:
       dmac_trifsrc_27: Only software/event triggers
       dmac_trifsrc_28: Only software/event triggers
       dmac_trifsrc_29: Only software/event triggers
-      dmac_trifsrc_3: Only software/event triggers
+      dmac_trifsrc_3: ADC0 Result Ready Trigger
       dmac_trifsrc_30: Only software/event triggers
       dmac_trifsrc_31: Only software/event triggers
       dmac_trifsrc_4: Only software/event triggers
@@ -748,7 +699,7 @@ drivers:
       dmac_trigact_17: One trigger required for each block transfer
       dmac_trigact_18: One trigger required for each block transfer
       dmac_trigact_19: One trigger required for each block transfer
-      dmac_trigact_2: One trigger required for each block transfer
+      dmac_trigact_2: One trigger required for each beat transfer
       dmac_trigact_20: One trigger required for each block transfer
       dmac_trigact_21: One trigger required for each block transfer
       dmac_trigact_22: One trigger required for each block transfer
@@ -759,7 +710,7 @@ drivers:
       dmac_trigact_27: One trigger required for each block transfer
       dmac_trigact_28: One trigger required for each block transfer
       dmac_trigact_29: One trigger required for each block transfer
-      dmac_trigact_3: One trigger required for each block transfer
+      dmac_trigact_3: One trigger required for each beat transfer
       dmac_trigact_30: One trigger required for each block transfer
       dmac_trigact_31: One trigger required for each block transfer
       dmac_trigact_4: One trigger required for each block transfer
@@ -909,7 +860,7 @@ drivers:
     api: HAL:Driver:Event_system
     configuration:
       evsys_channel_0: No channel output selected
-      evsys_channel_1: Channel 1
+      evsys_channel_1: No channel output selected
       evsys_channel_10: No channel output selected
       evsys_channel_11: No channel output selected
       evsys_channel_12: No channel output selected
@@ -943,7 +894,7 @@ drivers:
       evsys_channel_41: No channel output selected
       evsys_channel_42: No channel output selected
       evsys_channel_43: No channel output selected
-      evsys_channel_44: Channel 1
+      evsys_channel_44: No channel output selected
       evsys_channel_45: No channel output selected
       evsys_channel_46: No channel output selected
       evsys_channel_47: No channel output selected
@@ -955,9 +906,9 @@ drivers:
       evsys_channel_52: No channel output selected
       evsys_channel_53: No channel output selected
       evsys_channel_54: No channel output selected
-      evsys_channel_55: Channel 0
+      evsys_channel_55: No channel output selected
       evsys_channel_56: No channel output selected
-      evsys_channel_57: Channel 0
+      evsys_channel_57: No channel output selected
       evsys_channel_58: No channel output selected
       evsys_channel_59: No channel output selected
       evsys_channel_6: No channel output selected
@@ -968,11 +919,11 @@ drivers:
       evsys_channel_64: No channel output selected
       evsys_channel_65: No channel output selected
       evsys_channel_66: No channel output selected
-      evsys_channel_7: No channel output selected
+      evsys_channel_7: Channel 0
       evsys_channel_8: No channel output selected
       evsys_channel_9: No channel output selected
       evsys_channel_setting_0: true
-      evsys_channel_setting_1: true
+      evsys_channel_setting_1: false
       evsys_channel_setting_10: false
       evsys_channel_setting_11: false
       evsys_channel_setting_12: false
@@ -1100,7 +1051,7 @@ drivers:
       evsys_evd_8: false
       evsys_evd_9: false
       evsys_evgen_0: TCC1 overflow
-      evsys_evgen_1: CCL LUT output 0
+      evsys_evgen_1: No event generator
       evsys_evgen_10: No event generator
       evsys_evgen_11: No event generator
       evsys_evgen_12: No event generator
@@ -1196,7 +1147,7 @@ drivers:
       evsys_ovr_8: false
       evsys_ovr_9: false
       evsys_path_0: Asynchronous path
-      evsys_path_1: Asynchronous path
+      evsys_path_1: Synchronous path
       evsys_path_10: Synchronous path
       evsys_path_11: Synchronous path
       evsys_path_12: Synchronous path
@@ -1902,157 +1853,58 @@ drivers:
           tc_gclk_selection: Generic clock generator 0
   TCC_PWM2:
     user_label: TCC_PWM2
-    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TCC0::driver_config_definition::PWM.Mode::Lite:TCC:PWM
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TCC0::driver_config_definition::PWM::HAL:Driver:PWM
     functionality: PWM
-    api: Lite:TCC:PWM
+    api: HAL:Driver:PWM
     configuration:
-      cc_cc0: 0
-      cc_cc1: 0
-      cc_cc2: 0
-      cc_cc3: 0
-      cc_cc4: 0
-      cc_cc5: 0
-      cc_control: true
-      ctrla_alock: false
-      ctrla_control: true
-      ctrla_enable: true
-      ctrla_prescaler: DIV2
-      ctrla_prescsync: GCLK
-      ctrla_runstdby: false
-      ctrlbset_cmd: NONE
-      ctrlbset_control: false
-      ctrlbset_dir: false
-      ctrlbset_idxcmd: DISABLE
-      ctrlbset_lupd: false
-      ctrlbset_oneshot: false
-      dbgctrl_control: false
-      dbgctrl_dbgrun: false
-      dbgctrl_fddbd: false
-      drvctrl_control: false
-      drvctrl_filterval0: 0
-      drvctrl_filterval1: 0
-      drvctrl_inven0: false
-      drvctrl_inven1: false
-      drvctrl_inven2: false
-      drvctrl_inven3: false
-      drvctrl_inven4: false
-      drvctrl_inven5: false
-      drvctrl_inven6: false
-      drvctrl_inven7: false
-      drvctrl_nre0: false
-      drvctrl_nre1: false
-      drvctrl_nre2: false
-      drvctrl_nre3: false
-      drvctrl_nre4: false
-      drvctrl_nre5: false
-      drvctrl_nre6: false
-      drvctrl_nre7: false
-      drvctrl_nrv0: false
-      drvctrl_nrv1: false
-      drvctrl_nrv2: false
-      drvctrl_nrv3: false
-      drvctrl_nrv4: false
-      drvctrl_nrv5: false
-      drvctrl_nrv6: false
-      drvctrl_nrv7: false
-      evctrl_cnteo: false
-      evctrl_cntsel: START
-      evctrl_control: true
-      evctrl_evact0: 'OFF'
-      evctrl_evact1: 'OFF'
-      evctrl_mcei0: false
-      evctrl_mcei1: false
-      evctrl_mcei2: false
-      evctrl_mcei3: false
-      evctrl_mcei4: false
-      evctrl_mcei5: false
-      evctrl_mceo0: false
-      evctrl_mceo1: false
-      evctrl_mceo2: false
-      evctrl_mceo3: false
-      evctrl_mceo4: false
-      evctrl_mceo5: false
-      evctrl_ovfeo: true
-      evctrl_tcei0: false
-      evctrl_tcei1: false
-      evctrl_tcinv0: false
-      evctrl_tcinv1: false
-      evctrl_trgeo: false
-      fctrla_blank: NONE
-      fctrla_blankpresc: false
-      fctrla_blankval: 0
-      fctrla_chsel: CC0
-      fctrla_control: false
-      fctrla_filterval: 0
-      fctrla_halt: DISABLE
-      fctrla_keep: false
-      fctrla_qual: false
-      fctrla_restart: false
-      fctrla_src: DISABLE
-      fctrlb_blank: NONE
-      fctrlb_blankpresc: false
-      fctrlb_blankval: 0
-      fctrlb_chsel: CC0
-      fctrlb_control: false
-      fctrlb_filterval: 0
-      fctrlb_halt: DISABLE
-      fctrlb_keep: false
-      fctrlb_qual: false
-      fctrlb_restart: false
-      fctrlb_src: DISABLE
-      intenset_cnt: false
-      intenset_control: false
-      intenset_dfs: false
-      intenset_err: false
-      intenset_fault0: false
-      intenset_fault1: false
-      intenset_faulta: false
-      intenset_faultb: false
-      intenset_mc0: false
-      intenset_mc1: false
-      intenset_mc2: false
-      intenset_mc3: false
-      intenset_mc4: false
-      intenset_mc5: false
-      intenset_ovf: false
-      intenset_trg: false
-      patt_control: false
-      patt_pge0: false
-      patt_pge1: false
-      patt_pge2: false
-      patt_pge3: false
-      patt_pgv0: false
-      patt_pgv1: false
-      patt_pgv2: false
-      patt_pgv3: false
-      per_control: true
-      per_per: 1000
-      wave_ciccen0: false
-      wave_ciccen1: false
-      wave_ciccen2: false
-      wave_ciccen3: false
-      wave_ciperen: false
-      wave_control: true
-      wave_pol0: true
-      wave_pol1: true
-      wave_pol2: true
-      wave_pol3: true
-      wave_pol4: true
-      wave_pol5: true
-      wave_ramp: RAMP1
-      wave_swap0: false
-      wave_swap1: false
-      wave_swap2: false
-      wave_swap3: false
-      wave_wavegen: DSBOTTOM
-      wexctrl_control: true
-      wexctrl_dths: 0
-      wexctrl_dtien0: false
-      wexctrl_dtien1: false
-      wexctrl_dtien2: false
-      wexctrl_dtien3: false
-      wexctrl_dtls: 0
-      wexctrl_otmx: 0
+      tcc_arch_alock: false
+      tcc_arch_cc0: 0
+      tcc_arch_cc1: 0
+      tcc_arch_cc2: 0
+      tcc_arch_cc3: 0
+      tcc_arch_cc4: 0
+      tcc_arch_cc5: 0
+      tcc_arch_cnteo: false
+      tcc_arch_cntsel: An interrupt/event is generated when a new counter cycle starts
+      tcc_arch_cpten0: false
+      tcc_arch_cpten1: false
+      tcc_arch_cpten2: false
+      tcc_arch_cpten3: false
+      tcc_arch_cpten4: false
+      tcc_arch_cpten5: false
+      tcc_arch_cpten6: false
+      tcc_arch_cpten7: false
+      tcc_arch_dbgrun: false
+      tcc_arch_evact0: Event action disabled
+      tcc_arch_evact1: Event action disabled
+      tcc_arch_lupd: false
+      tcc_arch_mcei0: false
+      tcc_arch_mcei1: false
+      tcc_arch_mcei2: false
+      tcc_arch_mcei3: false
+      tcc_arch_mcei4: false
+      tcc_arch_mcei5: false
+      tcc_arch_mceo0: false
+      tcc_arch_mceo1: false
+      tcc_arch_mceo2: false
+      tcc_arch_mceo3: false
+      tcc_arch_mceo4: false
+      tcc_arch_mceo5: false
+      tcc_arch_ovfeo: true
+      tcc_arch_prescsync: Reload or reset counter on next GCLK
+      tcc_arch_runstdby: false
+      tcc_arch_sel_ch: 0
+      tcc_arch_tcei0: false
+      tcc_arch_tcei1: false
+      tcc_arch_tceinv0: false
+      tcc_arch_tceinv1: false
+      tcc_arch_trgeo: false
+      tcc_arch_wave_duty_val: 500
+      tcc_arch_wave_per_val: 40
+      tcc_arch_wavegen: Dual-slope, interrupt/event at ZERO (DSBOTTOM)
+      tcc_per: 10000
+      tcc_prescaler: Divide by 2
+      timer_event_control: true
     optional_signals:
     - identifier: TCC_PWM2:WO/0
       pad: PC04
@@ -2122,157 +1974,52 @@ drivers:
           tcc_gclk_selection: Generic clock generator 0
   TCC_PWM:
     user_label: TCC_PWM
-    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TCC1::driver_config_definition::PWM.Mode::Lite:TCC:PWM
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TCC1::driver_config_definition::PWM::HAL:Driver:PWM
     functionality: PWM
-    api: Lite:TCC:PWM
+    api: HAL:Driver:PWM
     configuration:
-      cc_cc0: 0
-      cc_cc1: 0
-      cc_cc2: 0
-      cc_cc3: 0
-      cc_cc4: 0
-      cc_cc5: 0
-      cc_control: false
-      ctrla_alock: false
-      ctrla_control: true
-      ctrla_enable: true
-      ctrla_prescaler: DIV2
-      ctrla_prescsync: GCLK
-      ctrla_runstdby: false
-      ctrlbset_cmd: NONE
-      ctrlbset_control: false
-      ctrlbset_dir: false
-      ctrlbset_idxcmd: DISABLE
-      ctrlbset_lupd: false
-      ctrlbset_oneshot: false
-      dbgctrl_control: false
-      dbgctrl_dbgrun: false
-      dbgctrl_fddbd: false
-      drvctrl_control: false
-      drvctrl_filterval0: 0
-      drvctrl_filterval1: 0
-      drvctrl_inven0: false
-      drvctrl_inven1: false
-      drvctrl_inven2: false
-      drvctrl_inven3: false
-      drvctrl_inven4: false
-      drvctrl_inven5: false
-      drvctrl_inven6: false
-      drvctrl_inven7: false
-      drvctrl_nre0: false
-      drvctrl_nre1: false
-      drvctrl_nre2: false
-      drvctrl_nre3: false
-      drvctrl_nre4: false
-      drvctrl_nre5: false
-      drvctrl_nre6: false
-      drvctrl_nre7: false
-      drvctrl_nrv0: false
-      drvctrl_nrv1: false
-      drvctrl_nrv2: false
-      drvctrl_nrv3: false
-      drvctrl_nrv4: false
-      drvctrl_nrv5: false
-      drvctrl_nrv6: false
-      drvctrl_nrv7: false
-      evctrl_cnteo: false
-      evctrl_cntsel: START
-      evctrl_control: true
-      evctrl_evact0: 'OFF'
-      evctrl_evact1: 'OFF'
-      evctrl_mcei0: false
-      evctrl_mcei1: false
-      evctrl_mcei2: false
-      evctrl_mcei3: false
-      evctrl_mcei4: false
-      evctrl_mcei5: false
-      evctrl_mceo0: false
-      evctrl_mceo1: false
-      evctrl_mceo2: false
-      evctrl_mceo3: false
-      evctrl_mceo4: false
-      evctrl_mceo5: false
-      evctrl_ovfeo: true
-      evctrl_tcei0: false
-      evctrl_tcei1: false
-      evctrl_tcinv0: false
-      evctrl_tcinv1: false
-      evctrl_trgeo: false
-      fctrla_blank: NONE
-      fctrla_blankpresc: false
-      fctrla_blankval: 0
-      fctrla_chsel: CC0
-      fctrla_control: false
-      fctrla_filterval: 0
-      fctrla_halt: DISABLE
-      fctrla_keep: false
-      fctrla_qual: false
-      fctrla_restart: false
-      fctrla_src: DISABLE
-      fctrlb_blank: NONE
-      fctrlb_blankpresc: false
-      fctrlb_blankval: 0
-      fctrlb_chsel: CC0
-      fctrlb_control: false
-      fctrlb_filterval: 0
-      fctrlb_halt: DISABLE
-      fctrlb_keep: false
-      fctrlb_qual: false
-      fctrlb_restart: false
-      fctrlb_src: DISABLE
-      intenset_cnt: false
-      intenset_control: false
-      intenset_dfs: false
-      intenset_err: false
-      intenset_fault0: false
-      intenset_fault1: false
-      intenset_faulta: false
-      intenset_faultb: false
-      intenset_mc0: false
-      intenset_mc1: false
-      intenset_mc2: false
-      intenset_mc3: false
-      intenset_mc4: false
-      intenset_mc5: false
-      intenset_ovf: false
-      intenset_trg: false
-      patt_control: false
-      patt_pge0: false
-      patt_pge1: false
-      patt_pge2: false
-      patt_pge3: false
-      patt_pgv0: false
-      patt_pgv1: false
-      patt_pgv2: false
-      patt_pgv3: false
-      per_control: true
-      per_per: 1000
-      wave_ciccen0: false
-      wave_ciccen1: false
-      wave_ciccen2: false
-      wave_ciccen3: false
-      wave_ciperen: false
-      wave_control: true
-      wave_pol0: true
-      wave_pol1: true
-      wave_pol2: true
-      wave_pol3: true
-      wave_pol4: false
-      wave_pol5: false
-      wave_ramp: RAMP1
-      wave_swap0: false
-      wave_swap1: false
-      wave_swap2: false
-      wave_swap3: false
-      wave_wavegen: DSBOTTOM
-      wexctrl_control: true
-      wexctrl_dths: 0
-      wexctrl_dtien0: false
-      wexctrl_dtien1: false
-      wexctrl_dtien2: false
-      wexctrl_dtien3: false
-      wexctrl_dtls: 0
-      wexctrl_otmx: 3
+      tcc_arch_alock: false
+      tcc_arch_cc0: 0
+      tcc_arch_cc1: 0
+      tcc_arch_cc2: 0
+      tcc_arch_cc3: 0
+      tcc_arch_cnteo: false
+      tcc_arch_cntsel: An interrupt/event is generated when a new counter cycle starts
+      tcc_arch_cpten0: false
+      tcc_arch_cpten1: false
+      tcc_arch_cpten2: false
+      tcc_arch_cpten3: false
+      tcc_arch_cpten4: false
+      tcc_arch_cpten5: false
+      tcc_arch_cpten6: false
+      tcc_arch_cpten7: false
+      tcc_arch_dbgrun: false
+      tcc_arch_evact0: Event action disabled
+      tcc_arch_evact1: Event action disabled
+      tcc_arch_lupd: false
+      tcc_arch_mcei0: false
+      tcc_arch_mcei1: false
+      tcc_arch_mcei2: false
+      tcc_arch_mcei3: false
+      tcc_arch_mceo0: false
+      tcc_arch_mceo1: false
+      tcc_arch_mceo2: false
+      tcc_arch_mceo3: false
+      tcc_arch_ovfeo: true
+      tcc_arch_prescsync: Reload or reset counter on next GCLK
+      tcc_arch_runstdby: false
+      tcc_arch_sel_ch: 3
+      tcc_arch_tcei0: false
+      tcc_arch_tcei1: false
+      tcc_arch_tceinv0: false
+      tcc_arch_tceinv1: false
+      tcc_arch_trgeo: false
+      tcc_arch_wave_duty_val: 500
+      tcc_arch_wave_per_val: 40
+      tcc_arch_wavegen: Dual-slope, interrupt/event at ZERO (DSBOTTOM)
+      tcc_per: 10000
+      tcc_prescaler: Divide by 2
+      timer_event_control: true
     optional_signals:
     - identifier: TCC_PWM:WO/0
       pad: PC14
diff --git a/BLDC_E54/BLDC_E54/BLDC_E54.cproj b/BLDC_E54/BLDC_E54/BLDC_E54.cproj
index 4d2da00..1d7b923 100644
--- a/BLDC_E54/BLDC_E54/BLDC_E54.cproj
+++ b/BLDC_E54/BLDC_E54/BLDC_E54.cproj
@@ -104,11 +104,9 @@
           <AcmeProjectActionInfo Action="File" Source="hal/utils/include/utils_increment_macro.h" IsConfig="false" Hash="yV2DDykoVCXX+XgiNyG+Sw" />
           <AcmeProjectActionInfo Action="File" Source="hal/utils/include/utils_list.h" IsConfig="false" Hash="60r34J7DkHyqgr2iqa6aXg" />
           <AcmeProjectActionInfo Action="File" Source="hal/utils/include/utils_repeat_macro.h" IsConfig="false" Hash="yidXppbw9HriaIIl6gVfEQ" />
-          <AcmeProjectActionInfo Action="File" Source="hal/utils/include/utils_ringbuffer.h" IsConfig="false" Hash="H/Lfgr8Y95zCUmEfoJAavQ" />
           <AcmeProjectActionInfo Action="File" Source="hal/utils/src/utils_assert.c" IsConfig="false" Hash="858+H2i44SFMGhFZ4+PSPw" />
           <AcmeProjectActionInfo Action="File" Source="hal/utils/src/utils_event.c" IsConfig="false" Hash="sR2eRthblYjlO/jHulP6aw" />
           <AcmeProjectActionInfo Action="File" Source="hal/utils/src/utils_list.c" IsConfig="false" Hash="rW6uwWgOnnMWzJjuYzxzZw" />
-          <AcmeProjectActionInfo Action="File" Source="hal/utils/src/utils_ringbuffer.c" IsConfig="false" Hash="MBhQOsuapWaZGq/1E6lcTw" />
           <AcmeProjectActionInfo Action="File" Source="hal/utils/src/utils_syscalls.c" IsConfig="false" Hash="NaBnZufa6Sau3+tzlyR7Kw" />
           <AcmeProjectActionInfo Action="File" Source="hri/hri_ac_e54.h" IsConfig="false" Hash="y6Jvvj/Cob45BC3nHprWHw" />
           <AcmeProjectActionInfo Action="File" Source="hri/hri_adc_e54.h" IsConfig="false" Hash="NqwOa13FZwkE2Qmc67WaCA" />
@@ -150,28 +148,32 @@
           <AcmeProjectActionInfo Action="File" Source="hri/hri_usb_e54.h" IsConfig="false" Hash="I+Mpxa40hh4o1NE68Zi5Gg" />
           <AcmeProjectActionInfo Action="File" Source="hri/hri_wdt_e54.h" IsConfig="false" Hash="CfZas1TGXPKWyHJU+xHJ7A" />
           <AcmeProjectActionInfo Action="File" Source="main.c" IsConfig="false" Hash="k0AH7j+BrmdFhBPzCCMptA" />
-          <AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="p82/RGyeISp9230+9OgEVA" />
-          <AcmeProjectActionInfo Action="File" Source="driver_init.h" IsConfig="false" Hash="G3BXbqpqnC/oNeodOZOakw" />
+          <AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="mceoTydnA8kDgec50q1/vA" />
+          <AcmeProjectActionInfo Action="File" Source="driver_init.h" IsConfig="false" Hash="kvX4HyQhlWgUubWSbqV0nw" />
           <AcmeProjectActionInfo Action="File" Source="atmel_start_pins.h" IsConfig="false" Hash="HgMCzaF/v9sYxwI7oBvlfw" />
-          <AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="jO30bFUAW0QLeY3/iT6N7A" />
-          <AcmeProjectActionInfo Action="File" Source="examples/driver_examples.c" IsConfig="false" Hash="L/uQJr5cqjsjEMQe8K4q0g" />
-          <AcmeProjectActionInfo Action="File" Source="hal/include/hal_adc_async.h" IsConfig="false" Hash="kQUwcVcp1XAP9GQn0S34sw" />
+          <AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="TkkzzVyvo+cx7KsAp9l52Q" />
+          <AcmeProjectActionInfo Action="File" Source="examples/driver_examples.c" IsConfig="false" Hash="YYAdWL1s+Q+NEcezd0cOGw" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hal_adc_sync.h" IsConfig="false" Hash="ez1X5T9kpYwT+1+5x4Pxqg" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hal_pwm.h" IsConfig="false" Hash="RXcBZcci/7vXKRJKNIq/Kw" />
           <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_adc_async.h" IsConfig="false" Hash="kKbVmqgGDUkuWZYErBwgVA" />
           <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_adc_sync.h" IsConfig="false" Hash="dCWrizZn0RtcCM73jZ/k6A" />
           <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_missing_features.h" IsConfig="false" Hash="XsAvpgfutzkw0Y5SydYFaw" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_pwm.h" IsConfig="false" Hash="1wL9C0Z542rKOnnyJpZ7Yg" />
           <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_reset.h" IsConfig="false" Hash="WwLFRlBtuZ/qnD1JuDKnRQ" />
           <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_spi_m_async.h" IsConfig="false" Hash="JyMw9jeJO0jGqfT03txHXQ" />
           <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_spi_m_dma.h" IsConfig="false" Hash="OoU5yflSLAc5VbWSzixnvg" />
           <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_spi_m_sync.h" IsConfig="false" Hash="s1GhyLjhjIsfqixooG3LFA" />
           <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_spi_s_async.h" IsConfig="false" Hash="ptPiaJ1lVqH5794NmOHDFQ" />
           <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_spi_s_sync.h" IsConfig="false" Hash="gEGr6GqKbsOQvxQYz2fotA" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_timer.h" IsConfig="false" Hash="s/0PW0pyF4MQIYZJ6S0wyA" />
           <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_usart_async.h" IsConfig="false" Hash="tBfmk3BN3Q1WbYVoWDbsJw" />
           <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_usart_sync.h" IsConfig="false" Hash="Yj+PoPxG2CqDOy5XoIWkwg" />
-          <AcmeProjectActionInfo Action="File" Source="hal/src/hal_adc_async.c" IsConfig="false" Hash="v3JpZEnczYxSmx7a+K50SA" />
+          <AcmeProjectActionInfo Action="File" Source="hal/src/hal_adc_sync.c" IsConfig="false" Hash="g0MT/8E9mrmMV9tMAyu/aQ" />
           <AcmeProjectActionInfo Action="File" Source="hal/src/hal_ext_irq.c" IsConfig="false" Hash="xrASRVTJh+j6G3mFcEOt+A" />
+          <AcmeProjectActionInfo Action="File" Source="hal/src/hal_pwm.c" IsConfig="false" Hash="ZFJmg7/0rhQ6JMKyxuk9kw" />
           <AcmeProjectActionInfo Action="File" Source="hal/src/hal_spi_m_dma.c" IsConfig="false" Hash="KMrinO/3xx7qWxy2PsJB7g" />
           <AcmeProjectActionInfo Action="File" Source="hal/utils/include/parts.h" IsConfig="false" Hash="THMC0T2wU10PzPgIVGK93g" />
-          <AcmeProjectActionInfo Action="File" Source="hpl/adc/hpl_adc.c" IsConfig="false" Hash="lHQXcLLzUGEXRE8/MqemkA" />
+          <AcmeProjectActionInfo Action="File" Source="hpl/adc/hpl_adc.c" IsConfig="false" Hash="zpNRk8aViOSavv+cy054MA" />
           <AcmeProjectActionInfo Action="File" Source="hpl/adc/hpl_adc_base.h" IsConfig="false" Hash="19A6ERNtsVVhqvnpGbR3Lg" />
           <AcmeProjectActionInfo Action="File" Source="hpl/ccl/hpl_ccl.c" IsConfig="false" Hash="tXTxcKR6ZW9n3smV6Dp+DA" />
           <AcmeProjectActionInfo Action="File" Source="hpl/cmcc/hpl_cmcc.c" IsConfig="false" Hash="xrdKSj3ppVwQWgZ3zrlaRg" />
@@ -194,16 +196,16 @@
           <AcmeProjectActionInfo Action="File" Source="hpl/sercom/hpl_sercom.c" IsConfig="false" Hash="hcMq5dgdlyb9xXr1YOQnMQ" />
           <AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.c" IsConfig="false" Hash="uY4XeQhtAqGMZvw6U6EEVA" />
           <AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.h" IsConfig="false" Hash="MH8wpmGdaXsDgVxVA/8iWw" />
-          <AcmeProjectActionInfo Action="File" Source="hpl/tcc/tcc_lite.c" IsConfig="false" Hash="9TFYH+GTJJBWSu1bZtuG5Q" />
-          <AcmeProjectActionInfo Action="File" Source="hpl/tcc/tcc_lite.h" IsConfig="false" Hash="Ve+zuL+YeyPrAWKXGeSoJQ" />
+          <AcmeProjectActionInfo Action="File" Source="hpl/tcc/hpl_tcc.c" IsConfig="false" Hash="DC3UZSTUv1CDjekNxClhVg" />
+          <AcmeProjectActionInfo Action="File" Source="hpl/tcc/hpl_tcc.h" IsConfig="false" Hash="rdWkAK12qkOYV59tWwzy6A" />
           <AcmeProjectActionInfo Action="File" Source="atmel_start.h" IsConfig="false" Hash="9RBG5E2ViQiSP2Gn4/FGpA" />
           <AcmeProjectActionInfo Action="File" Source="atmel_start.c" IsConfig="false" Hash="1RHIE7zTtYK4DURNPUqF9w" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="1eDjif7f+y5ngynXRphsfw" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="5zoRW/YUsZApmDgQt0R2iQ" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_ccl_config.h" IsConfig="true" Hash="d2ozzqBRrRzP7EQeYn4m3w" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="XIdge/a/TjUqBqjAi3RqHg" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="Fgy1mDm2BRBY3IBfwL3mfg" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="6xqR/FfKqve2wjz45CZHjA" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="yVNVuUNdJBgKTrTaGQKklA" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="V00MuwusNA40W3fKunzS/A" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="XcRDNsb7d6ZuAa9h2WTYEw" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_mclk_config.h" IsConfig="true" Hash="pxBzoQXTG66x4dbzVzxteg" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_osc32kctrl_config.h" IsConfig="true" Hash="HgvzEqDUH4jq/syjj/+G+Q" />
@@ -211,7 +213,8 @@
           <AcmeProjectActionInfo Action="File" Source="config/hpl_pdec_config.h" IsConfig="true" Hash="TQEBQwc7hx8I+kxqBkjXSg" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="lz3FE+9jWhub2Z5CsHWovQ" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="WUXQgarVBcGAlxKxYn1jjA" />
-          <AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="gpOB7aTCI49UNQrS4QOmPw" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_tcc_config.h" IsConfig="true" Hash="wNzdbwRT/WSrvrPDOGRR1Q" />
+          <AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="2uHUNbHBWWR974H4mXVMgQ" />
         </AcmeActionInfos>
         <NonsecureFilesInfo />
       </AcmeProjectConfig>
@@ -535,6 +538,9 @@
     <Compile Include="Config\hpl_sercom_config.h">
       <SubType>compile</SubType>
     </Compile>
+    <Compile Include="Config\hpl_tcc_config.h">
+      <SubType>compile</SubType>
+    </Compile>
     <Compile Include="Config\peripheral_clk_config.h">
       <SubType>compile</SubType>
     </Compile>
@@ -568,7 +574,7 @@
     <Compile Include="examples\driver_examples.h">
       <SubType>compile</SubType>
     </Compile>
-    <Compile Include="hal\include\hal_adc_async.h">
+    <Compile Include="hal\include\hal_adc_sync.h">
       <SubType>compile</SubType>
     </Compile>
     <Compile Include="hal\include\hal_atomic.h">
@@ -601,6 +607,9 @@
     <Compile Include="hal\include\hal_pdec_async.h">
       <SubType>compile</SubType>
     </Compile>
+    <Compile Include="hal\include\hal_pwm.h">
+      <SubType>compile</SubType>
+    </Compile>
     <Compile Include="hal\include\hal_sleep.h">
       <SubType>compile</SubType>
     </Compile>
@@ -664,6 +673,9 @@
     <Compile Include="hal\include\hpl_pdec_async.h">
       <SubType>compile</SubType>
     </Compile>
+    <Compile Include="hal\include\hpl_pwm.h">
+      <SubType>compile</SubType>
+    </Compile>
     <Compile Include="hal\include\hpl_ramecc.h">
       <SubType>compile</SubType>
     </Compile>
@@ -700,6 +712,9 @@
     <Compile Include="hal\include\hpl_spi_s_sync.h">
       <SubType>compile</SubType>
     </Compile>
+    <Compile Include="hal\include\hpl_timer.h">
+      <SubType>compile</SubType>
+    </Compile>
     <Compile Include="hal\include\hpl_usart.h">
       <SubType>compile</SubType>
     </Compile>
@@ -709,7 +724,7 @@
     <Compile Include="hal\include\hpl_usart_sync.h">
       <SubType>compile</SubType>
     </Compile>
-    <Compile Include="hal\src\hal_adc_async.c">
+    <Compile Include="hal\src\hal_adc_sync.c">
       <SubType>compile</SubType>
     </Compile>
     <Compile Include="hal\src\hal_atomic.c">
@@ -739,6 +754,9 @@
     <Compile Include="hal\src\hal_pdec_async.c">
       <SubType>compile</SubType>
     </Compile>
+    <Compile Include="hal\src\hal_pwm.c">
+      <SubType>compile</SubType>
+    </Compile>
     <Compile Include="hal\src\hal_sleep.c">
       <SubType>compile</SubType>
     </Compile>
@@ -775,9 +793,6 @@
     <Compile Include="hal\utils\include\utils_repeat_macro.h">
       <SubType>compile</SubType>
     </Compile>
-    <Compile Include="hal\utils\include\utils_ringbuffer.h">
-      <SubType>compile</SubType>
-    </Compile>
     <Compile Include="hal\utils\src\utils_assert.c">
       <SubType>compile</SubType>
     </Compile>
@@ -787,9 +802,6 @@
     <Compile Include="hal\utils\src\utils_list.c">
       <SubType>compile</SubType>
     </Compile>
-    <Compile Include="hal\utils\src\utils_ringbuffer.c">
-      <SubType>compile</SubType>
-    </Compile>
     <Compile Include="hal\utils\src\utils_syscalls.c">
       <SubType>compile</SubType>
     </Compile>
@@ -856,10 +868,10 @@
     <Compile Include="hpl\sercom\hpl_sercom.c">
       <SubType>compile</SubType>
     </Compile>
-    <Compile Include="hpl\tcc\tcc_lite.c">
+    <Compile Include="hpl\tcc\hpl_tcc.c">
       <SubType>compile</SubType>
     </Compile>
-    <Compile Include="hpl\tcc\tcc_lite.h">
+    <Compile Include="hpl\tcc\hpl_tcc.h">
       <SubType>compile</SubType>
     </Compile>
     <Compile Include="hpl\tc\tc_lite.c">
@@ -1048,7 +1060,7 @@
     <None Include="Device_Startup\same54p20a_sram.ld">
       <SubType>compile</SubType>
     </None>
-    <None Include="hal\documentation\adc_async.rst">
+    <None Include="hal\documentation\adc_sync.rst">
       <SubType>compile</SubType>
     </None>
     <None Include="hal\documentation\custom_logic.rst">
@@ -1063,15 +1075,15 @@
     <None Include="hal\documentation\pdec_async.rst">
       <SubType>compile</SubType>
     </None>
+    <None Include="hal\documentation\pwm.rst">
+      <SubType>compile</SubType>
+    </None>
     <None Include="hal\documentation\spi_master_dma.rst">
       <SubType>compile</SubType>
     </None>
     <None Include="hpl\doc_lite\tc.rst">
       <SubType>compile</SubType>
     </None>
-    <None Include="hpl\doc_lite\tcc.rst">
-      <SubType>compile</SubType>
-    </None>
   </ItemGroup>
   <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
 </Project>
\ No newline at end of file
diff --git a/BLDC_E54/BLDC_E54/Config/hpl_adc_config.h b/BLDC_E54/BLDC_E54/Config/hpl_adc_config.h
index 5496bcb..9964e0a 100644
--- a/BLDC_E54/BLDC_E54/Config/hpl_adc_config.h
+++ b/BLDC_E54/BLDC_E54/Config/hpl_adc_config.h
@@ -209,7 +209,7 @@
 // <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
 // <id> adc_arch_samplen
 #ifndef CONF_ADC_0_SAMPLEN
-#define CONF_ADC_0_SAMPLEN 0
+#define CONF_ADC_0_SAMPLEN 3
 #endif
 
 // <o> Window Monitor Mode
@@ -264,7 +264,7 @@
 // <i> Enables event output on result ready event (RESRDEO)
 // <id> adc_arch_resrdyeo
 #ifndef CONF_ADC_0_RESRDYEO
-#define CONF_ADC_0_RESRDYEO 0
+#define CONF_ADC_0_RESRDYEO 1
 #endif
 
 // <q> Invert flush Event Signal
@@ -292,300 +292,7 @@
 // <i> Trigger a conversion on event. (STARTEI)
 // <id> adc_arch_startei
 #ifndef CONF_ADC_0_STARTEI
-#define CONF_ADC_0_STARTEI 1
-#endif
-
-// </e>
-
-#ifndef CONF_ADC_1_ENABLE
-#define CONF_ADC_1_ENABLE 1
-#endif
-
-// <h> Basic Configuration
-
-// <o> Conversion Result Resolution
-// <0x0=>12-bit
-// <0x1=>16-bit (averaging must be enabled)
-// <0x2=>10-bit
-// <0x3=>8-bit
-// <i>  Defines the bit resolution for the ADC sample values (RESSEL)
-// <id> adc_resolution
-#ifndef CONF_ADC_1_RESSEL
-#define CONF_ADC_1_RESSEL 0x0
-#endif
-
-// <o> Reference Selection
-// <0x0=>Internal bandgap reference
-// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
-// <0x3=>VDDANA
-// <0x4=>External reference A
-// <0x5=>External reference B
-// <0x6=>External reference C
-// <i> Select the reference for the ADC (REFSEL)
-// <id> adc_reference
-#ifndef CONF_ADC_1_REFSEL
-#define CONF_ADC_1_REFSEL 0x3
-#endif
-
-// <o> Prescaler configuration
-// <0x0=>Peripheral clock divided by 2
-// <0x1=>Peripheral clock divided by 4
-// <0x2=>Peripheral clock divided by 8
-// <0x3=>Peripheral clock divided by 16
-// <0x4=>Peripheral clock divided by 32
-// <0x5=>Peripheral clock divided by 64
-// <0x6=>Peripheral clock divided by 128
-// <0x7=>Peripheral clock divided by 256
-// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
-// <id> adc_prescaler
-#ifndef CONF_ADC_1_PRESCALER
-#define CONF_ADC_1_PRESCALER 0x2
-#endif
-
-// <q> Free Running Mode
-// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
-// <id> adc_freerunning_mode
-#ifndef CONF_ADC_1_FREERUN
-#define CONF_ADC_1_FREERUN 0
-#endif
-
-// <q> Differential Mode
-// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
-// <id> adc_differential_mode
-#ifndef CONF_ADC_1_DIFFMODE
-#define CONF_ADC_1_DIFFMODE 0
-#endif
-
-// <o> Positive Mux Input Selection
-// <0x00=>ADC AIN0 pin
-// <0x01=>ADC AIN1 pin
-// <0x02=>ADC AIN2 pin
-// <0x03=>ADC AIN3 pin
-// <0x04=>ADC AIN4 pin
-// <0x05=>ADC AIN5 pin
-// <0x06=>ADC AIN6 pin
-// <0x07=>ADC AIN7 pin
-// <0x08=>ADC AIN8 pin
-// <0x09=>ADC AIN9 pin
-// <0x0A=>ADC AIN10 pin
-// <0x0B=>ADC AIN11 pin
-// <0x0C=>ADC AIN12 pin
-// <0x0D=>ADC AIN13 pin
-// <0x0E=>ADC AIN14 pin
-// <0x0F=>ADC AIN15 pin
-// <0x18=>1/4 scaled core supply
-// <0x19=>1/4 Scaled VBAT Supply
-// <0x1A=>1/4 scaled I/O supply
-// <0x1B=>Bandgap voltage
-// <0x1C=>Temperature reference (PTAT)
-// <0x1D=>Temperature reference (CTAT)
-// <0x1E=>DAC Output
-// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
-// <id> adc_pinmux_positive
-#ifndef CONF_ADC_1_MUXPOS
-#define CONF_ADC_1_MUXPOS 0x1
-#endif
-
-// <o> Negative Mux Input Selection
-// <0x00=>ADC AIN0 pin
-// <0x01=>ADC AIN1 pin
-// <0x02=>ADC AIN2 pin
-// <0x03=>ADC AIN3 pin
-// <0x04=>ADC AIN4 pin
-// <0x05=>ADC AIN5 pin
-// <0x06=>ADC AIN6 pin
-// <0x07=>ADC AIN7 pin
-// <0x18=>Internal ground
-// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
-// <id> adc_pinmux_negative
-#ifndef CONF_ADC_1_MUXNEG
-#define CONF_ADC_1_MUXNEG 0x18
-#endif
-
-// </h>
-
-// <e> Advanced Configuration
-// <id> adc_advanced_settings
-#ifndef CONF_ADC_1_ADVANCED
-#define CONF_ADC_1_ADVANCED 1
-#endif
-
-// <q> Run in standby
-// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
-// <id> adc_arch_runstdby
-#ifndef CONF_ADC_1_RUNSTDBY
-#define CONF_ADC_1_RUNSTDBY 0
-#endif
-
-// <q>Debug Run
-// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
-// <id> adc_arch_dbgrun
-#ifndef CONF_ADC_1_DBGRUN
-#define CONF_ADC_1_DBGRUN 0
-#endif
-
-// <q> On Demand Control
-// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
-// <id> adc_arch_ondemand
-#ifndef CONF_ADC_1_ONDEMAND
-#define CONF_ADC_1_ONDEMAND 0
-#endif
-
-// <q> Left-Adjusted Result
-// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
-// <id> adc_arch_leftadj
-#ifndef CONF_ADC_1_LEFTADJ
-#define CONF_ADC_1_LEFTADJ 0
-#endif
-
-// <q> Reference Buffer Offset Compensation Enable
-// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
-// <id> adc_arch_refcomp
-#ifndef CONF_ADC_1_REFCOMP
-#define CONF_ADC_1_REFCOMP 0
-#endif
-
-// <q>Comparator Offset Compensation Enable
-// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
-// <id> adc_arch_offcomp
-#ifndef CONF_ADC_1_OFFCOMP
-#define CONF_ADC_1_OFFCOMP 0
-#endif
-
-// <q> Digital Correction Logic Enabled
-// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
-// <id> adc_arch_corren
-#ifndef CONF_ADC_1_CORREN
-#define CONF_ADC_1_CORREN 0
-#endif
-
-// <o> Offset Correction Value <0-4095>
-// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
-// <id> adc_arch_offsetcorr
-#ifndef CONF_ADC_1_OFFSETCORR
-#define CONF_ADC_1_OFFSETCORR 0
-#endif
-
-// <o> Gain Correction Value <0-4095>
-// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
-// <id> adc_arch_gaincorr
-#ifndef CONF_ADC_1_GAINCORR
-#define CONF_ADC_1_GAINCORR 0
-#endif
-
-// <o> Adjusting Result / Division Coefficient <0-7>
-// <i> These bits define the division coefficient in 2n steps. (ADJRES)
-// <id> adc_arch_adjres
-#ifndef CONF_ADC_1_ADJRES
-#define CONF_ADC_1_ADJRES 0x0
-#endif
-
-// <o.0..10> Number of Samples to be Collected
-// <0x0=>1 sample
-// <0x1=>2 samples
-// <0x2=>4 samples
-// <0x3=>8 samples
-// <0x4=>16 samples
-// <0x5=>32 samples
-// <0x6=>64 samples
-// <0x7=>128 samples
-// <0x8=>256 samples
-// <0x9=>512 samples
-// <0xA=>1024 samples
-// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
-// <id> adc_arch_samplenum
-#ifndef CONF_ADC_1_SAMPLENUM
-#define CONF_ADC_1_SAMPLENUM 0x0
-#endif
-
-// <o> Sampling Time Length <0-63>
-// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
-// <id> adc_arch_samplen
-#ifndef CONF_ADC_1_SAMPLEN
-#define CONF_ADC_1_SAMPLEN 0
-#endif
-
-// <o> Window Monitor Mode
-// <0x0=>No window mode
-// <0x1=>Mode 1: RESULT above lower threshold
-// <0x2=>Mode 2: RESULT beneath upper threshold
-// <0x3=>Mode 3: RESULT inside lower and upper threshold
-// <0x4=>Mode 4: RESULT outside lower and upper threshold
-// <i> These bits enable and define the window monitor mode. (WINMODE)
-// <id> adc_arch_winmode
-#ifndef CONF_ADC_1_WINMODE
-#define CONF_ADC_1_WINMODE 0x0
-#endif
-
-// <o> Window Monitor Lower Threshold <0-65535>
-// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
-// <id> adc_arch_winlt
-#ifndef CONF_ADC_1_WINLT
-#define CONF_ADC_1_WINLT 0
-#endif
-
-// <o> Window Monitor Upper Threshold <0-65535>
-// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
-// <id> adc_arch_winut
-#ifndef CONF_ADC_1_WINUT
-#define CONF_ADC_1_WINUT 0
-#endif
-
-// <o> Bitmask for positive input sequence <0-4294967295>
-// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
-// <id> adc_arch_seqen
-#ifndef CONF_ADC_1_SEQEN
-#define CONF_ADC_1_SEQEN 0x0
-#endif
-
-// </e>
-
-// <e> Event Control
-// <id> adc_arch_event_settings
-#ifndef CONF_ADC_1_EVENT_CONTROL
-#define CONF_ADC_1_EVENT_CONTROL 1
-#endif
-
-// <q> Window Monitor Event Out
-// <i> Enables event output on window event (WINMONEO)
-// <id> adc_arch_winmoneo
-#ifndef CONF_ADC_1_WINMONEO
-#define CONF_ADC_1_WINMONEO 0
-#endif
-
-// <q> Result Ready Event Out
-// <i> Enables event output on result ready event (RESRDEO)
-// <id> adc_arch_resrdyeo
-#ifndef CONF_ADC_1_RESRDYEO
-#define CONF_ADC_1_RESRDYEO 0
-#endif
-
-// <q> Invert flush Event Signal
-// <i> Invert the flush event input signal (FLUSHINV)
-// <id> adc_arch_flushinv
-#ifndef CONF_ADC_1_FLUSHINV
-#define CONF_ADC_1_FLUSHINV 0
-#endif
-
-// <q> Trigger Flush On Event
-// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
-// <id> adc_arch_flushei
-#ifndef CONF_ADC_1_FLUSHEI
-#define CONF_ADC_1_FLUSHEI 0
-#endif
-
-// <q> Invert Start Conversion Event Signal
-// <i> Invert the start conversion event input signal (STARTINV)
-// <id> adc_arch_startinv
-#ifndef CONF_ADC_1_STARTINV
-#define CONF_ADC_1_STARTINV 0
-#endif
-
-// <q> Trigger Conversion On Event
-// <i> Trigger a conversion on event. (STARTEI)
-// <id> adc_arch_startei
-#ifndef CONF_ADC_1_STARTEI
-#define CONF_ADC_1_STARTEI 1
+#define CONF_ADC_0_STARTEI 0
 #endif
 
 // </e>
diff --git a/BLDC_E54/BLDC_E54/Config/hpl_dmac_config.h b/BLDC_E54/BLDC_E54/Config/hpl_dmac_config.h
index 45f58f7..0c66b0e 100644
--- a/BLDC_E54/BLDC_E54/Config/hpl_dmac_config.h
+++ b/BLDC_E54/BLDC_E54/Config/hpl_dmac_config.h
@@ -36,7 +36,7 @@
 // <i> Indicates whether Priority Level 1 is enabled or not
 // <id> dmac_lvlen1
 #ifndef CONF_DMAC_LVLEN1
-#define CONF_DMAC_LVLEN1 0
+#define CONF_DMAC_LVLEN1 1
 #endif
 
 // <o> Level 1 Round-Robin Arbitration
@@ -57,7 +57,7 @@
 // <i> Indicates whether Priority Level 2 is enabled or not
 // <id> dmac_lvlen2
 #ifndef CONF_DMAC_LVLEN2
-#define CONF_DMAC_LVLEN2 0
+#define CONF_DMAC_LVLEN2 1
 #endif
 
 // <o> Level 2 Round-Robin Arbitration
@@ -66,7 +66,7 @@
 // <i> Defines Level 2 Arbitration for DMA channels
 // <id> dmac_rrlvlen2
 #ifndef CONF_DMAC_RRLVLEN2
-#define CONF_DMAC_RRLVLEN2 0
+#define CONF_DMAC_RRLVLEN2 1
 #endif
 
 // <o> Level 2 Channel Priority Number <0x00-0xFF>
@@ -78,7 +78,7 @@
 // <i> Indicates whether Priority Level 3 is enabled or not
 // <id> dmac_lvlen3
 #ifndef CONF_DMAC_LVLEN3
-#define CONF_DMAC_LVLEN3 0
+#define CONF_DMAC_LVLEN3 1
 #endif
 
 // <o> Level 3 Round-Robin Arbitration
@@ -87,7 +87,7 @@
 // <i> Defines Level 3 Arbitration for DMA channels
 // <id> dmac_rrlvlen3
 #ifndef CONF_DMAC_RRLVLEN3
-#define CONF_DMAC_RRLVLEN3 0
+#define CONF_DMAC_RRLVLEN3 1
 #endif
 
 // <o> Level 3 Channel Priority Number <0x00-0xFF>
@@ -99,7 +99,7 @@
 // <i> Indicates whether Debug Run is enabled or not
 // <id> dmac_dbgrun
 #ifndef CONF_DMAC_DBGRUN
-#define CONF_DMAC_DBGRUN 0
+#define CONF_DMAC_DBGRUN 1
 #endif
 
 // <e> Channel 0 settings
@@ -225,7 +225,7 @@
 // <i> Defines the arbitration level for this channel
 // <id> dmac_lvl_0
 #ifndef CONF_DMAC_LVL_0
-#define CONF_DMAC_LVL_0 0
+#define CONF_DMAC_LVL_0 1
 #endif
 
 // <q> Channel Event Output
@@ -449,7 +449,7 @@
 // <i> Defines the arbitration level for this channel
 // <id> dmac_lvl_1
 #ifndef CONF_DMAC_LVL_1
-#define CONF_DMAC_LVL_1 0
+#define CONF_DMAC_LVL_1 1
 #endif
 
 // <q> Channel Event Output
@@ -553,14 +553,14 @@
 // <e> Channel 2 settings
 // <id> dmac_channel_2_settings
 #ifndef CONF_DMAC_CHANNEL_2_SETTINGS
-#define CONF_DMAC_CHANNEL_2_SETTINGS 0
+#define CONF_DMAC_CHANNEL_2_SETTINGS 1
 #endif
 
 // <q> Channel Run in Standby
 // <i> Indicates whether channel 2 is running in standby mode or not
 // <id> dmac_runstdby_2
 #ifndef CONF_DMAC_RUNSTDBY_2
-#define CONF_DMAC_RUNSTDBY_2 0
+#define CONF_DMAC_RUNSTDBY_2 1
 #endif
 
 // <o> Trigger action
@@ -570,7 +570,7 @@
 // <i> Defines the trigger action used for a transfer
 // <id> dmac_trigact_2
 #ifndef CONF_DMAC_TRIGACT_2
-#define CONF_DMAC_TRIGACT_2 0
+#define CONF_DMAC_TRIGACT_2 2
 #endif
 
 // <o> Trigger source
@@ -662,7 +662,7 @@
 // <i> Defines the peripheral trigger which is source of the transfer
 // <id> dmac_trifsrc_2
 #ifndef CONF_DMAC_TRIGSRC_2
-#define CONF_DMAC_TRIGSRC_2 0
+#define CONF_DMAC_TRIGSRC_2 69
 #endif
 
 // <o> Channel Arbitration Level
@@ -687,7 +687,7 @@
 // <i> Indicates whether channel event reception is enabled or not
 // <id> dmac_evie_2
 #ifndef CONF_DMAC_EVIE_2
-#define CONF_DMAC_EVIE_2 0
+#define CONF_DMAC_EVIE_2 1
 #endif
 
 // <o> Event Input Action
@@ -701,7 +701,7 @@
 // <i> Defines the event input action
 // <id> dmac_evact_2
 #ifndef CONF_DMAC_EVACT_2
-#define CONF_DMAC_EVACT_2 0
+#define CONF_DMAC_EVACT_2 5
 #endif
 
 // <o> Address Increment Step Size
@@ -725,14 +725,14 @@
 // <i> Defines whether source or destination addresses are using the step size settings
 // <id> dmac_stepsel_2
 #ifndef CONF_DMAC_STEPSEL_2
-#define CONF_DMAC_STEPSEL_2 0
+#define CONF_DMAC_STEPSEL_2 1
 #endif
 
 // <q> Source Address Increment
 // <i> Indicates whether the source address incrementation is enabled or not
 // <id> dmac_srcinc_2
 #ifndef CONF_DMAC_SRCINC_2
-#define CONF_DMAC_SRCINC_2 0
+#define CONF_DMAC_SRCINC_2 1
 #endif
 
 // <q> Destination Address Increment
@@ -749,7 +749,7 @@
 // <i> Defines the size of one beat
 // <id> dmac_beatsize_2
 #ifndef CONF_DMAC_BEATSIZE_2
-#define CONF_DMAC_BEATSIZE_2 0
+#define CONF_DMAC_BEATSIZE_2 2
 #endif
 
 // <o> Block Action
@@ -760,7 +760,7 @@
 // <i> Defines the the DMAC should take after a block transfer has completed
 // <id> dmac_blockact_2
 #ifndef CONF_DMAC_BLOCKACT_2
-#define CONF_DMAC_BLOCKACT_2 0
+#define CONF_DMAC_BLOCKACT_2 2
 #endif
 
 // <o> Event Output Selection
@@ -777,14 +777,14 @@
 // <e> Channel 3 settings
 // <id> dmac_channel_3_settings
 #ifndef CONF_DMAC_CHANNEL_3_SETTINGS
-#define CONF_DMAC_CHANNEL_3_SETTINGS 0
+#define CONF_DMAC_CHANNEL_3_SETTINGS 1
 #endif
 
 // <q> Channel Run in Standby
 // <i> Indicates whether channel 3 is running in standby mode or not
 // <id> dmac_runstdby_3
 #ifndef CONF_DMAC_RUNSTDBY_3
-#define CONF_DMAC_RUNSTDBY_3 0
+#define CONF_DMAC_RUNSTDBY_3 1
 #endif
 
 // <o> Trigger action
@@ -794,7 +794,7 @@
 // <i> Defines the trigger action used for a transfer
 // <id> dmac_trigact_3
 #ifndef CONF_DMAC_TRIGACT_3
-#define CONF_DMAC_TRIGACT_3 0
+#define CONF_DMAC_TRIGACT_3 2
 #endif
 
 // <o> Trigger source
@@ -886,7 +886,7 @@
 // <i> Defines the peripheral trigger which is source of the transfer
 // <id> dmac_trifsrc_3
 #ifndef CONF_DMAC_TRIGSRC_3
-#define CONF_DMAC_TRIGSRC_3 0
+#define CONF_DMAC_TRIGSRC_3 68
 #endif
 
 // <o> Channel Arbitration Level
@@ -963,7 +963,7 @@
 // <i> Indicates whether the destination address incrementation is enabled or not
 // <id> dmac_dstinc_3
 #ifndef CONF_DMAC_DSTINC_3
-#define CONF_DMAC_DSTINC_3 0
+#define CONF_DMAC_DSTINC_3 1
 #endif
 
 // <o> Beat Size
@@ -973,7 +973,7 @@
 // <i> Defines the size of one beat
 // <id> dmac_beatsize_3
 #ifndef CONF_DMAC_BEATSIZE_3
-#define CONF_DMAC_BEATSIZE_3 0
+#define CONF_DMAC_BEATSIZE_3 1
 #endif
 
 // <o> Block Action
@@ -984,7 +984,7 @@
 // <i> Defines the the DMAC should take after a block transfer has completed
 // <id> dmac_blockact_3
 #ifndef CONF_DMAC_BLOCKACT_3
-#define CONF_DMAC_BLOCKACT_3 0
+#define CONF_DMAC_BLOCKACT_3 1
 #endif
 
 // <o> Event Output Selection
diff --git a/BLDC_E54/BLDC_E54/Config/hpl_evsys_config.h b/BLDC_E54/BLDC_E54/Config/hpl_evsys_config.h
index de2427b..36955a2 100644
--- a/BLDC_E54/BLDC_E54/Config/hpl_evsys_config.h
+++ b/BLDC_E54/BLDC_E54/Config/hpl_evsys_config.h
@@ -188,7 +188,7 @@
 // <e> Channel 1 settings
 // <id> evsys_channel_setting_1
 #ifndef CONF_EVSYS_CHANNEL_SETTINGS_1
-#define CONF_EVSYS_CHANNEL_SETTINGS_1 1
+#define CONF_EVSYS_CHANNEL_SETTINGS_1 0
 #endif
 
 // <y> Edge detection
@@ -209,7 +209,7 @@
 // <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
 // <id> evsys_path_1
 #ifndef CONF_PATH_1
-#define CONF_PATH_1 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
+#define CONF_PATH_1 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
 #endif
 
 // <o> Event generator
@@ -333,7 +333,7 @@
 // <0x77=>CCL LUT output 3
 // <id> evsys_evgen_1
 #ifndef CONF_EVGEN_1
-#define CONF_EVGEN_1 116
+#define CONF_EVGEN_1 0
 #endif
 
 // <q> Overrun channel interrupt
@@ -5880,7 +5880,7 @@
 // <id> evsys_channel_1
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_1
-#define CONF_CHANNEL_1 2
+#define CONF_CHANNEL_1 0
 #endif
 
 // <o> Channel selection for PORT event 1
@@ -6122,7 +6122,7 @@
 // <id> evsys_channel_7
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_7
-#define CONF_CHANNEL_7 0
+#define CONF_CHANNEL_7 1
 #endif
 
 // <o> Channel selection for DMAC channel 3
@@ -7464,7 +7464,7 @@
 // <id> evsys_channel_44
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_44
-#define CONF_CHANNEL_44 2
+#define CONF_CHANNEL_44 0
 #endif
 
 // <o> Channel selection for TC1 event
@@ -7908,7 +7908,7 @@
 // <id> evsys_channel_55
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_55
-#define CONF_CHANNEL_55 1
+#define CONF_CHANNEL_55 0
 #endif
 
 // <o> Channel selection for ADC0 flush event
@@ -7988,7 +7988,7 @@
 // <id> evsys_channel_57
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_57
-#define CONF_CHANNEL_57 1
+#define CONF_CHANNEL_57 0
 #endif
 
 // <o> Channel selection for ADC1 flush event
diff --git a/BLDC_E54/BLDC_E54/Config/peripheral_clk_config.h b/BLDC_E54/BLDC_E54/Config/peripheral_clk_config.h
index 76001ee..366d8bd 100644
--- a/BLDC_E54/BLDC_E54/Config/peripheral_clk_config.h
+++ b/BLDC_E54/BLDC_E54/Config/peripheral_clk_config.h
@@ -44,46 +44,6 @@
 #define CONF_GCLK_ADC0_FREQUENCY 100000000
 #endif
 
-// <y> ADC Clock Source
-// <id> adc_gclk_selection
-
-// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
-
-// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
-
-// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
-
-// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
-
-// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
-
-// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
-
-// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
-
-// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
-
-// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
-
-// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
-
-// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
-
-// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
-
-// <i> Select the clock source for ADC.
-#ifndef CONF_GCLK_ADC1_SRC
-#define CONF_GCLK_ADC1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#endif
-
-/**
- * \def CONF_GCLK_ADC1_FREQUENCY
- * \brief ADC1's Clock frequency
- */
-#ifndef CONF_GCLK_ADC1_FREQUENCY
-#define CONF_GCLK_ADC1_FREQUENCY 100000000
-#endif
-
 // <y> CCL Clock Source
 // <id> ccl_gclk_selection
 
diff --git a/BLDC_E54/BLDC_E54/Debug/atmel_start.d b/BLDC_E54/BLDC_E54/Debug/atmel_start.d
index 3f84573..a5c9ebb 100644
--- a/BLDC_E54/BLDC_E54/Debug/atmel_start.d
+++ b/BLDC_E54/BLDC_E54/Debug/atmel_start.d
@@ -140,10 +140,7 @@ atmel_start.d atmel_start.o: .././atmel_start.c ../atmel_start.h \
  ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
  ../hal/include/hal_init.h ../hal/include/hpl_init.h \
  ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
- ../hal/include/hal_adc_async.h ../hal/include/hpl_adc_async.h \
- ../hal/include/hpl_adc_sync.h ../hal/include/hpl_irq.h \
- ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \
- ../hal/utils/include/utils_assert.h \
+ ../hal/include/hal_adc_sync.h ../hal/include/hpl_adc_sync.h \
  ../hal/include/hpl_missing_features.h ../hal/include/hal_custom_logic.h \
  ../hal/include/hpl_custom_logic.h ../hal/include/hal_ext_irq.h \
  ../hal/include/hpl_ext_irq.h ../hal/include/hal_evsys.h \
@@ -151,7 +148,9 @@ atmel_start.d atmel_start.o: .././atmel_start.c ../atmel_start.h \
  ../hal/utils/include/utils.h ../hal/include/hpl_pdec_async.h \
  ../hal/include/hal_spi_m_dma.h ../hal/include/hpl_spi_m_dma.h \
  ../hal/include/hpl_spi.h ../hal/include/hpl_spi_dma.h \
- ../hal/include/hpl_dma.h ../hpl/tc/tc_lite.h ../hpl/tcc/tcc_lite.h
+ ../hal/include/hpl_dma.h ../hpl/tc/tc_lite.h ../hal/include/hal_pwm.h \
+ ../hal/include/hpl_pwm.h ../hal/include/hpl_irq.h ../hpl/tcc/hpl_tcc.h \
+ ../hal/include/hpl_timer.h
 
 ../atmel_start.h:
 
@@ -505,20 +504,10 @@ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include
 
 ../hal/include/hal_sleep.h:
 
-../hal/include/hal_adc_async.h:
-
-../hal/include/hpl_adc_async.h:
+../hal/include/hal_adc_sync.h:
 
 ../hal/include/hpl_adc_sync.h:
 
-../hal/include/hpl_irq.h:
-
-../hal/utils/include/utils_ringbuffer.h:
-
-../hal/utils/include/compiler.h:
-
-../hal/utils/include/utils_assert.h:
-
 ../hal/include/hpl_missing_features.h:
 
 ../hal/include/hal_custom_logic.h:
@@ -551,4 +540,12 @@ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include
 
 ../hpl/tc/tc_lite.h:
 
-../hpl/tcc/tcc_lite.h:
+../hal/include/hal_pwm.h:
+
+../hal/include/hpl_pwm.h:
+
+../hal/include/hpl_irq.h:
+
+../hpl/tcc/hpl_tcc.h:
+
+../hal/include/hpl_timer.h:
diff --git a/BLDC_E54/BLDC_E54/Debug/atmel_start.o b/BLDC_E54/BLDC_E54/Debug/atmel_start.o
index cfca5ae..4b0a545 100644
Binary files a/BLDC_E54/BLDC_E54/Debug/atmel_start.o and b/BLDC_E54/BLDC_E54/Debug/atmel_start.o differ
diff --git a/BLDC_E54/BLDC_E54/Debug/bldc.d b/BLDC_E54/BLDC_E54/Debug/bldc.d
index 0397013..b174854 100644
--- a/BLDC_E54/BLDC_E54/Debug/bldc.d
+++ b/BLDC_E54/BLDC_E54/Debug/bldc.d
@@ -155,10 +155,7 @@ bldc.d bldc.o: .././bldc.c .././bldc.h .././arm_math.h \
  ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
  ../hal/include/hal_init.h ../hal/include/hpl_init.h \
  ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
- ../hal/include/hal_adc_async.h ../hal/include/hpl_adc_async.h \
- ../hal/include/hpl_adc_sync.h ../hal/include/hpl_irq.h \
- ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \
- ../hal/utils/include/utils_assert.h \
+ ../hal/include/hal_adc_sync.h ../hal/include/hpl_adc_sync.h \
  ../hal/include/hpl_missing_features.h ../hal/include/hal_custom_logic.h \
  ../hal/include/hpl_custom_logic.h ../hal/include/hal_ext_irq.h \
  ../hal/include/hpl_ext_irq.h ../hal/include/hal_evsys.h \
@@ -166,8 +163,10 @@ bldc.d bldc.o: .././bldc.c .././bldc.h .././arm_math.h \
  ../hal/utils/include/utils.h ../hal/include/hpl_pdec_async.h \
  ../hal/include/hal_spi_m_dma.h ../hal/include/hpl_spi_m_dma.h \
  ../hal/include/hpl_spi.h ../hal/include/hpl_spi_dma.h \
- ../hal/include/hpl_dma.h ../hpl/tc/tc_lite.h ../hpl/tcc/tcc_lite.h \
- .././control.h .././utilities.h .././motor_params.h .././statemachine.h
+ ../hal/include/hpl_dma.h ../hpl/tc/tc_lite.h ../hal/include/hal_pwm.h \
+ ../hal/include/hpl_pwm.h ../hal/include/hpl_irq.h ../hpl/tcc/hpl_tcc.h \
+ ../hal/include/hpl_timer.h .././control.h .././utilities.h \
+ .././motor_params.h .././statemachine.h
 
 .././bldc.h:
 
@@ -553,20 +552,10 @@ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include
 
 ../hal/include/hal_sleep.h:
 
-../hal/include/hal_adc_async.h:
-
-../hal/include/hpl_adc_async.h:
+../hal/include/hal_adc_sync.h:
 
 ../hal/include/hpl_adc_sync.h:
 
-../hal/include/hpl_irq.h:
-
-../hal/utils/include/utils_ringbuffer.h:
-
-../hal/utils/include/compiler.h:
-
-../hal/utils/include/utils_assert.h:
-
 ../hal/include/hpl_missing_features.h:
 
 ../hal/include/hal_custom_logic.h:
@@ -599,7 +588,15 @@ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include
 
 ../hpl/tc/tc_lite.h:
 
-../hpl/tcc/tcc_lite.h:
+../hal/include/hal_pwm.h:
+
+../hal/include/hpl_pwm.h:
+
+../hal/include/hpl_irq.h:
+
+../hpl/tcc/hpl_tcc.h:
+
+../hal/include/hpl_timer.h:
 
 .././control.h:
 
diff --git a/BLDC_E54/BLDC_E54/Debug/bldc.o b/BLDC_E54/BLDC_E54/Debug/bldc.o
index 658fff2..5960b2e 100644
Binary files a/BLDC_E54/BLDC_E54/Debug/bldc.o and b/BLDC_E54/BLDC_E54/Debug/bldc.o differ
diff --git a/BLDC_E54/BLDC_E54/Debug/driver_init.d b/BLDC_E54/BLDC_E54/Debug/driver_init.d
index 042ab8a..03da81a 100644
--- a/BLDC_E54/BLDC_E54/Debug/driver_init.d
+++ b/BLDC_E54/BLDC_E54/Debug/driver_init.d
@@ -140,10 +140,7 @@ driver_init.d driver_init.o: .././driver_init.c .././driver_init.h \
  ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
  ../hal/include/hal_init.h ../hal/include/hpl_init.h \
  ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
- ../hal/include/hal_adc_async.h ../hal/include/hpl_adc_async.h \
- ../hal/include/hpl_adc_sync.h ../hal/include/hpl_irq.h \
- ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \
- ../hal/utils/include/utils_assert.h \
+ ../hal/include/hal_adc_sync.h ../hal/include/hpl_adc_sync.h \
  ../hal/include/hpl_missing_features.h ../hal/include/hal_custom_logic.h \
  ../hal/include/hpl_custom_logic.h ../hal/include/hal_ext_irq.h \
  ../hal/include/hpl_ext_irq.h ../hal/include/hal_evsys.h \
@@ -151,8 +148,10 @@ driver_init.d driver_init.o: .././driver_init.c .././driver_init.h \
  ../hal/utils/include/utils.h ../hal/include/hpl_pdec_async.h \
  ../hal/include/hal_spi_m_dma.h ../hal/include/hpl_spi_m_dma.h \
  ../hal/include/hpl_spi.h ../hal/include/hpl_spi_dma.h \
- ../hal/include/hpl_dma.h ../hpl/tc/tc_lite.h ../hpl/tcc/tcc_lite.h \
- ../Config/peripheral_clk_config.h ../hpl/adc/hpl_adc_base.h \
+ ../hal/include/hpl_dma.h ../hpl/tc/tc_lite.h ../hal/include/hal_pwm.h \
+ ../hal/include/hpl_pwm.h ../hal/include/hpl_irq.h ../hpl/tcc/hpl_tcc.h \
+ ../hal/include/hpl_timer.h ../Config/peripheral_clk_config.h \
+ ../hpl/adc/hpl_adc_base.h ../hal/include/hpl_adc_async.h \
  ../hal/include/hpl_adc_sync.h
 
 .././driver_init.h:
@@ -505,20 +504,10 @@ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include
 
 ../hal/include/hal_sleep.h:
 
-../hal/include/hal_adc_async.h:
-
-../hal/include/hpl_adc_async.h:
+../hal/include/hal_adc_sync.h:
 
 ../hal/include/hpl_adc_sync.h:
 
-../hal/include/hpl_irq.h:
-
-../hal/utils/include/utils_ringbuffer.h:
-
-../hal/utils/include/compiler.h:
-
-../hal/utils/include/utils_assert.h:
-
 ../hal/include/hpl_missing_features.h:
 
 ../hal/include/hal_custom_logic.h:
@@ -551,10 +540,20 @@ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include
 
 ../hpl/tc/tc_lite.h:
 
-../hpl/tcc/tcc_lite.h:
+../hal/include/hal_pwm.h:
+
+../hal/include/hpl_pwm.h:
+
+../hal/include/hpl_irq.h:
+
+../hpl/tcc/hpl_tcc.h:
+
+../hal/include/hpl_timer.h:
 
 ../Config/peripheral_clk_config.h:
 
 ../hpl/adc/hpl_adc_base.h:
 
+../hal/include/hpl_adc_async.h:
+
 ../hal/include/hpl_adc_sync.h:
diff --git a/BLDC_E54/BLDC_E54/Debug/driver_init.o b/BLDC_E54/BLDC_E54/Debug/driver_init.o
index 2182c15..793b47b 100644
Binary files a/BLDC_E54/BLDC_E54/Debug/driver_init.o and b/BLDC_E54/BLDC_E54/Debug/driver_init.o differ
diff --git a/BLDC_E54/BLDC_E54/Debug/ethercat/ethercat_e54.d b/BLDC_E54/BLDC_E54/Debug/ethercat/ethercat_e54.d
index 2705988..28feb14 100644
--- a/BLDC_E54/BLDC_E54/Debug/ethercat/ethercat_e54.d
+++ b/BLDC_E54/BLDC_E54/Debug/ethercat/ethercat_e54.d
@@ -141,10 +141,7 @@ ethercat/ethercat_e54.d ethercat/ethercat_e54.o: \
  ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
  ../hal/include/hal_init.h ../hal/include/hpl_init.h \
  ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
- ../hal/include/hal_adc_async.h ../hal/include/hpl_adc_async.h \
- ../hal/include/hpl_adc_sync.h ../hal/include/hpl_irq.h \
- ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \
- ../hal/utils/include/utils_assert.h \
+ ../hal/include/hal_adc_sync.h ../hal/include/hpl_adc_sync.h \
  ../hal/include/hpl_missing_features.h ../hal/include/hal_custom_logic.h \
  ../hal/include/hpl_custom_logic.h ../hal/include/hal_ext_irq.h \
  ../hal/include/hpl_ext_irq.h ../hal/include/hal_evsys.h \
@@ -152,9 +149,11 @@ ethercat/ethercat_e54.d ethercat/ethercat_e54.o: \
  ../hal/utils/include/utils.h ../hal/include/hpl_pdec_async.h \
  ../hal/include/hal_spi_m_dma.h ../hal/include/hpl_spi_m_dma.h \
  ../hal/include/hpl_spi.h ../hal/include/hpl_spi_dma.h \
- ../hal/include/hpl_dma.h ../hpl/tc/tc_lite.h ../hpl/tcc/tcc_lite.h \
- ../pins.h ../driver_init.h ../ethercat/ethercat_e54.h \
- ../ethercat/ethercat_slave_def.h ../bldc.h ../arm_math.h \
+ ../hal/include/hpl_dma.h ../hpl/tc/tc_lite.h ../hal/include/hal_pwm.h \
+ ../hal/include/hpl_pwm.h ../hal/include/hpl_irq.h ../hpl/tcc/hpl_tcc.h \
+ ../hal/include/hpl_timer.h ../pins.h ../driver_init.h \
+ ../ethercat/ethercat_e54.h ../ethercat/ethercat_slave_def.h ../bldc.h \
+ ../arm_math.h \
  c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
  c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
  c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
@@ -524,20 +523,10 @@ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include
 
 ../hal/include/hal_sleep.h:
 
-../hal/include/hal_adc_async.h:
-
-../hal/include/hpl_adc_async.h:
+../hal/include/hal_adc_sync.h:
 
 ../hal/include/hpl_adc_sync.h:
 
-../hal/include/hpl_irq.h:
-
-../hal/utils/include/utils_ringbuffer.h:
-
-../hal/utils/include/compiler.h:
-
-../hal/utils/include/utils_assert.h:
-
 ../hal/include/hpl_missing_features.h:
 
 ../hal/include/hal_custom_logic.h:
@@ -570,7 +559,15 @@ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include
 
 ../hpl/tc/tc_lite.h:
 
-../hpl/tcc/tcc_lite.h:
+../hal/include/hal_pwm.h:
+
+../hal/include/hpl_pwm.h:
+
+../hal/include/hpl_irq.h:
+
+../hpl/tcc/hpl_tcc.h:
+
+../hal/include/hpl_timer.h:
 
 ../pins.h:
 
diff --git a/BLDC_E54/BLDC_E54/Debug/ethercat/ethercat_e54.o b/BLDC_E54/BLDC_E54/Debug/ethercat/ethercat_e54.o
index 68500e9..08ff890 100644
Binary files a/BLDC_E54/BLDC_E54/Debug/ethercat/ethercat_e54.o and b/BLDC_E54/BLDC_E54/Debug/ethercat/ethercat_e54.o differ
diff --git a/BLDC_E54/BLDC_E54/Debug/examples/driver_examples.d b/BLDC_E54/BLDC_E54/Debug/examples/driver_examples.d
index c6add7d..8262932 100644
--- a/BLDC_E54/BLDC_E54/Debug/examples/driver_examples.d
+++ b/BLDC_E54/BLDC_E54/Debug/examples/driver_examples.d
@@ -141,10 +141,7 @@ examples/driver_examples.d examples/driver_examples.o: \
  ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
  ../hal/include/hal_init.h ../hal/include/hpl_init.h \
  ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
- ../hal/include/hal_adc_async.h ../hal/include/hpl_adc_async.h \
- ../hal/include/hpl_adc_sync.h ../hal/include/hpl_irq.h \
- ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \
- ../hal/utils/include/utils_assert.h \
+ ../hal/include/hal_adc_sync.h ../hal/include/hpl_adc_sync.h \
  ../hal/include/hpl_missing_features.h ../hal/include/hal_custom_logic.h \
  ../hal/include/hpl_custom_logic.h ../hal/include/hal_ext_irq.h \
  ../hal/include/hpl_ext_irq.h ../hal/include/hal_evsys.h \
@@ -152,7 +149,9 @@ examples/driver_examples.d examples/driver_examples.o: \
  ../hal/utils/include/utils.h ../hal/include/hpl_pdec_async.h \
  ../hal/include/hal_spi_m_dma.h ../hal/include/hpl_spi_m_dma.h \
  ../hal/include/hpl_spi.h ../hal/include/hpl_spi_dma.h \
- ../hal/include/hpl_dma.h ../hpl/tc/tc_lite.h ../hpl/tcc/tcc_lite.h
+ ../hal/include/hpl_dma.h ../hpl/tc/tc_lite.h ../hal/include/hal_pwm.h \
+ ../hal/include/hpl_pwm.h ../hal/include/hpl_irq.h ../hpl/tcc/hpl_tcc.h \
+ ../hal/include/hpl_timer.h
 
 ../examples/driver_examples.h:
 
@@ -506,20 +505,10 @@ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include
 
 ../hal/include/hal_sleep.h:
 
-../hal/include/hal_adc_async.h:
-
-../hal/include/hpl_adc_async.h:
+../hal/include/hal_adc_sync.h:
 
 ../hal/include/hpl_adc_sync.h:
 
-../hal/include/hpl_irq.h:
-
-../hal/utils/include/utils_ringbuffer.h:
-
-../hal/utils/include/compiler.h:
-
-../hal/utils/include/utils_assert.h:
-
 ../hal/include/hpl_missing_features.h:
 
 ../hal/include/hal_custom_logic.h:
@@ -552,4 +541,12 @@ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include
 
 ../hpl/tc/tc_lite.h:
 
-../hpl/tcc/tcc_lite.h:
+../hal/include/hal_pwm.h:
+
+../hal/include/hpl_pwm.h:
+
+../hal/include/hpl_irq.h:
+
+../hpl/tcc/hpl_tcc.h:
+
+../hal/include/hpl_timer.h:
diff --git a/BLDC_E54/BLDC_E54/Debug/examples/driver_examples.o b/BLDC_E54/BLDC_E54/Debug/examples/driver_examples.o
index b9f6c23..f6c52ba 100644
Binary files a/BLDC_E54/BLDC_E54/Debug/examples/driver_examples.o and b/BLDC_E54/BLDC_E54/Debug/examples/driver_examples.o differ
diff --git a/BLDC_E54/BLDC_E54/Debug/hal/src/hal_adc_async.d b/BLDC_E54/BLDC_E54/Debug/hal/src/hal_adc_async.d
deleted file mode 100644
index 968d46f..0000000
--- a/BLDC_E54/BLDC_E54/Debug/hal/src/hal_adc_async.d
+++ /dev/null
@@ -1,482 +0,0 @@
-hal/src/hal_adc_async.d hal/src/hal_adc_async.o: \
- ../hal/src/hal_adc_async.c ../hal/include/hal_adc_async.h \
- ../hal/include/hpl_adc_async.h ../hal/include/hpl_adc_sync.h \
- ../hal/utils/include/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../hal/utils/include/parts.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/same54.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/same54p20a.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm4.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/system_same54.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/ac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/adc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/aes.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/can.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/ccl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/cmcc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/dac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/dmac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/dsu.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/eic.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/evsys.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/freqm.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/gclk.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/gmac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/hmatrixb.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/icm.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/i2s.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/mclk.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/nvmctrl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/oscctrl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/osc32kctrl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pcc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pdec.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pm.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/port.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/qspi.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/ramecc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/rstc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/rtc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/sdhc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/sercom.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/supc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/tc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/tcc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/trng.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/usb.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/wdt.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/ac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/adc0.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/adc1.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/aes.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/can0.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/can1.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/ccl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/cmcc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/dac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/dmac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/dsu.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/eic.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/evsys.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/freqm.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/gclk.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/gmac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/hmatrix.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/icm.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/i2s.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/mclk.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/nvmctrl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/oscctrl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/osc32kctrl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pcc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pdec.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pm.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/port.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pukcc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/qspi.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/ramecc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/rstc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/rtc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sdhc0.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sdhc1.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom0.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom1.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom2.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom3.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom4.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom5.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom6.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom7.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/supc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc0.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc1.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc2.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc3.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc4.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc5.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc6.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc7.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc0.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc1.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc2.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc3.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc4.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/trng.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/usb.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/wdt.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/pio/same54p20a.h \
- ../hri/hri_e54.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/sam.h \
- ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
- ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
- ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
- ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
- ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
- ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
- ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
- ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
- ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
- ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
- ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
- ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
- ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
- ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
- ../hal/utils/include/err_codes.h ../hal/include/hpl_irq.h \
- ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \
- ../hal/utils/include/utils_assert.h \
- ../hal/include/hpl_missing_features.h \
- ../hal/utils/include/utils_assert.h ../hal/utils/include/utils.h
-
-../hal/include/hal_adc_async.h:
-
-../hal/include/hpl_adc_async.h:
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-../hal/include/hpl_adc_sync.h:
-
-../hal/utils/include/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../hal/utils/include/parts.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/same54.h:
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-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm4.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/system_same54.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/ac.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/adc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/aes.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/can.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/ccl.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/cmcc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/dac.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/dmac.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/dsu.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/eic.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/evsys.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/freqm.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/gclk.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/gmac.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/hmatrixb.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/icm.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/i2s.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/mclk.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/nvmctrl.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/oscctrl.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/osc32kctrl.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pac.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pcc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pdec.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pm.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/port.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/qspi.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/ramecc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/rstc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/rtc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/sdhc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/sercom.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/supc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/tc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/tcc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/trng.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/usb.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/wdt.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/ac.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/adc0.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/adc1.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/aes.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/can0.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/can1.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/ccl.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/cmcc.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/dac.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/dmac.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/dsu.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/eic.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/evsys.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/freqm.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/gclk.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/gmac.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/hmatrix.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/icm.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/i2s.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/mclk.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/nvmctrl.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/oscctrl.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/osc32kctrl.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pac.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pcc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pdec.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pm.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/port.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pukcc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/qspi.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/ramecc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/rstc.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/rtc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sdhc0.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sdhc1.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom0.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom1.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom2.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom3.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom4.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom5.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom6.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom7.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/supc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc0.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc1.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc2.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc3.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc4.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc5.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc6.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc7.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc0.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc1.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc2.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc3.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc4.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/trng.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/usb.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/wdt.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/pio/same54p20a.h:
-
-../hri/hri_e54.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/sam.h:
-
-../hri/hri_ac_e54.h:
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-../hal/include/hal_atomic.h:
-
-../hri/hri_adc_e54.h:
-
-../hri/hri_aes_e54.h:
-
-../hri/hri_can_e54.h:
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-../hri/hri_ccl_e54.h:
-
-../hri/hri_cmcc_e54.h:
-
-../hri/hri_dac_e54.h:
-
-../hri/hri_dmac_e54.h:
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-../hri/hri_dsu_e54.h:
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-../hri/hri_eic_e54.h:
-
-../hri/hri_evsys_e54.h:
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-../hri/hri_freqm_e54.h:
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-../hri/hri_gclk_e54.h:
-
-../hri/hri_gmac_e54.h:
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-../hri/hri_hmatrixb_e54.h:
-
-../hri/hri_i2s_e54.h:
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-../hri/hri_icm_e54.h:
-
-../hri/hri_mclk_e54.h:
-
-../hri/hri_nvmctrl_e54.h:
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-../hri/hri_osc32kctrl_e54.h:
-
-../hri/hri_oscctrl_e54.h:
-
-../hri/hri_pac_e54.h:
-
-../hri/hri_pcc_e54.h:
-
-../hri/hri_pdec_e54.h:
-
-../hri/hri_pm_e54.h:
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-../hri/hri_port_e54.h:
-
-../hri/hri_qspi_e54.h:
-
-../hri/hri_ramecc_e54.h:
-
-../hri/hri_rstc_e54.h:
-
-../hri/hri_rtc_e54.h:
-
-../hri/hri_sdhc_e54.h:
-
-../hri/hri_sercom_e54.h:
-
-../hri/hri_supc_e54.h:
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-../hri/hri_tc_e54.h:
-
-../hri/hri_tcc_e54.h:
-
-../hri/hri_trng_e54.h:
-
-../hri/hri_usb_e54.h:
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-../hri/hri_wdt_e54.h:
-
-../hal/utils/include/err_codes.h:
-
-../hal/include/hpl_irq.h:
-
-../hal/utils/include/utils_ringbuffer.h:
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-../hal/utils/include/compiler.h:
-
-../hal/utils/include/utils_assert.h:
-
-../hal/include/hpl_missing_features.h:
-
-../hal/utils/include/utils_assert.h:
-
-../hal/utils/include/utils.h:
diff --git a/BLDC_E54/BLDC_E54/Debug/hal/src/hal_adc_async.o b/BLDC_E54/BLDC_E54/Debug/hal/src/hal_adc_async.o
deleted file mode 100644
index e945917..0000000
Binary files a/BLDC_E54/BLDC_E54/Debug/hal/src/hal_adc_async.o and /dev/null differ
diff --git a/BLDC_E54/BLDC_E54/Debug/hal/src/hal_spi_m_dma.o b/BLDC_E54/BLDC_E54/Debug/hal/src/hal_spi_m_dma.o
index 6d79714..c3f7b51 100644
Binary files a/BLDC_E54/BLDC_E54/Debug/hal/src/hal_spi_m_dma.o and b/BLDC_E54/BLDC_E54/Debug/hal/src/hal_spi_m_dma.o differ
diff --git a/BLDC_E54/BLDC_E54/Debug/hal/utils/src/utils_ringbuffer.d b/BLDC_E54/BLDC_E54/Debug/hal/utils/src/utils_ringbuffer.d
deleted file mode 100644
index 6dac0d5..0000000
--- a/BLDC_E54/BLDC_E54/Debug/hal/utils/src/utils_ringbuffer.d
+++ /dev/null
@@ -1,464 +0,0 @@
-hal/utils/src/utils_ringbuffer.d hal/utils/src/utils_ringbuffer.o: \
- ../hal/utils/src/utils_ringbuffer.c \
- ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../hal/utils/include/parts.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/same54.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/same54p20a.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm4.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/system_same54.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/ac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/adc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/aes.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/can.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/ccl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/cmcc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/dac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/dmac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/dsu.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/eic.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/evsys.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/freqm.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/gclk.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/gmac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/hmatrixb.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/icm.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/i2s.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/mclk.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/nvmctrl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/oscctrl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/osc32kctrl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pcc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pdec.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pm.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/port.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/qspi.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/ramecc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/rstc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/rtc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/sdhc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/sercom.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/supc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/tc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/tcc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/trng.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/usb.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/wdt.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/ac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/adc0.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/adc1.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/aes.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/can0.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/can1.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/ccl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/cmcc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/dac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/dmac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/dsu.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/eic.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/evsys.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/freqm.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/gclk.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/gmac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/hmatrix.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/icm.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/i2s.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/mclk.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/nvmctrl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/oscctrl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/osc32kctrl.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pac.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pcc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pdec.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pm.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/port.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pukcc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/qspi.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/ramecc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/rstc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/rtc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sdhc0.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sdhc1.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom0.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom1.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom2.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom3.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom4.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom5.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom6.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom7.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/supc.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc0.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc1.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc2.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc3.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc4.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc5.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc6.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc7.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc0.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc1.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc2.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc3.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc4.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/trng.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/usb.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/wdt.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/pio/same54p20a.h \
- ../hri/hri_e54.h \
- C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/sam.h \
- ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h \
- ../hal/utils/include/compiler.h ../hri/hri_adc_e54.h \
- ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
- ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
- ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
- ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
- ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
- ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
- ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
- ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
- ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
- ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
- ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
- ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
- ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
- ../hal/utils/include/err_codes.h ../hal/utils/include/utils_assert.h
-
-../hal/utils/include/utils_ringbuffer.h:
-
-../hal/utils/include/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../hal/utils/include/parts.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/same54.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/same54p20a.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm4.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/system_same54.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/ac.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/adc.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/aes.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/can.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/ccl.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/cmcc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/dac.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/dmac.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/dsu.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/eic.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/evsys.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/freqm.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/gclk.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/gmac.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/hmatrixb.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/icm.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/i2s.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/mclk.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/nvmctrl.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/oscctrl.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/osc32kctrl.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pac.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pcc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pdec.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/pm.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/port.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/qspi.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/ramecc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/rstc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/rtc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/sdhc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/sercom.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/supc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/tc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/tcc.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/trng.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/usb.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/component/wdt.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/ac.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/adc0.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/adc1.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/aes.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/can0.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/can1.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/ccl.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/cmcc.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/dac.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/dmac.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/dsu.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/eic.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/evsys.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/freqm.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/gclk.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/gmac.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/hmatrix.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/icm.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/i2s.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/mclk.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/nvmctrl.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/oscctrl.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/osc32kctrl.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pac.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pcc.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pdec.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pm.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/port.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/pukcc.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/qspi.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/ramecc.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/rstc.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/rtc.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sdhc0.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sdhc1.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom0.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom3.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom4.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom5.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom6.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/sercom7.h:
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-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/supc.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc0.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc1.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc2.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc3.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc4.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc5.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc6.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tc7.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc0.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc1.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc2.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc3.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/tcc4.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/trng.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/usb.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/instance/wdt.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/pio/same54p20a.h:
-
-../hri/hri_e54.h:
-
-C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include/sam.h:
-
-../hri/hri_ac_e54.h:
-
-../hal/include/hal_atomic.h:
-
-../hal/utils/include/compiler.h:
-
-../hri/hri_adc_e54.h:
-
-../hri/hri_aes_e54.h:
-
-../hri/hri_can_e54.h:
-
-../hri/hri_ccl_e54.h:
-
-../hri/hri_cmcc_e54.h:
-
-../hri/hri_dac_e54.h:
-
-../hri/hri_dmac_e54.h:
-
-../hri/hri_dsu_e54.h:
-
-../hri/hri_eic_e54.h:
-
-../hri/hri_evsys_e54.h:
-
-../hri/hri_freqm_e54.h:
-
-../hri/hri_gclk_e54.h:
-
-../hri/hri_gmac_e54.h:
-
-../hri/hri_hmatrixb_e54.h:
-
-../hri/hri_i2s_e54.h:
-
-../hri/hri_icm_e54.h:
-
-../hri/hri_mclk_e54.h:
-
-../hri/hri_nvmctrl_e54.h:
-
-../hri/hri_osc32kctrl_e54.h:
-
-../hri/hri_oscctrl_e54.h:
-
-../hri/hri_pac_e54.h:
-
-../hri/hri_pcc_e54.h:
-
-../hri/hri_pdec_e54.h:
-
-../hri/hri_pm_e54.h:
-
-../hri/hri_port_e54.h:
-
-../hri/hri_qspi_e54.h:
-
-../hri/hri_ramecc_e54.h:
-
-../hri/hri_rstc_e54.h:
-
-../hri/hri_rtc_e54.h:
-
-../hri/hri_sdhc_e54.h:
-
-../hri/hri_sercom_e54.h:
-
-../hri/hri_supc_e54.h:
-
-../hri/hri_tc_e54.h:
-
-../hri/hri_tcc_e54.h:
-
-../hri/hri_trng_e54.h:
-
-../hri/hri_usb_e54.h:
-
-../hri/hri_wdt_e54.h:
-
-../hal/utils/include/err_codes.h:
-
-../hal/utils/include/utils_assert.h:
diff --git a/BLDC_E54/BLDC_E54/Debug/hal/utils/src/utils_ringbuffer.o b/BLDC_E54/BLDC_E54/Debug/hal/utils/src/utils_ringbuffer.o
deleted file mode 100644
index 6c97db8..0000000
Binary files a/BLDC_E54/BLDC_E54/Debug/hal/utils/src/utils_ringbuffer.o and /dev/null differ
diff --git a/BLDC_E54/BLDC_E54/Debug/hpl/adc/hpl_adc.o b/BLDC_E54/BLDC_E54/Debug/hpl/adc/hpl_adc.o
index fc6eafc..e9f69dc 100644
Binary files a/BLDC_E54/BLDC_E54/Debug/hpl/adc/hpl_adc.o and b/BLDC_E54/BLDC_E54/Debug/hpl/adc/hpl_adc.o differ
diff --git a/BLDC_E54/BLDC_E54/Debug/hpl/core/hpl_core_m4.o b/BLDC_E54/BLDC_E54/Debug/hpl/core/hpl_core_m4.o
index ba8b599..818b6eb 100644
Binary files a/BLDC_E54/BLDC_E54/Debug/hpl/core/hpl_core_m4.o and b/BLDC_E54/BLDC_E54/Debug/hpl/core/hpl_core_m4.o differ
diff --git a/BLDC_E54/BLDC_E54/Debug/hpl/core/hpl_init.o b/BLDC_E54/BLDC_E54/Debug/hpl/core/hpl_init.o
index 93c2135..c14eacf 100644
Binary files a/BLDC_E54/BLDC_E54/Debug/hpl/core/hpl_init.o and b/BLDC_E54/BLDC_E54/Debug/hpl/core/hpl_init.o differ
diff --git a/BLDC_E54/BLDC_E54/Debug/hpl/dmac/hpl_dmac.o b/BLDC_E54/BLDC_E54/Debug/hpl/dmac/hpl_dmac.o
index d275ca2..a73eb57 100644
Binary files a/BLDC_E54/BLDC_E54/Debug/hpl/dmac/hpl_dmac.o and b/BLDC_E54/BLDC_E54/Debug/hpl/dmac/hpl_dmac.o differ
diff --git a/BLDC_E54/BLDC_E54/Debug/hpl/evsys/hpl_evsys.o b/BLDC_E54/BLDC_E54/Debug/hpl/evsys/hpl_evsys.o
index 2f3fb2f..77ef915 100644
Binary files a/BLDC_E54/BLDC_E54/Debug/hpl/evsys/hpl_evsys.o and b/BLDC_E54/BLDC_E54/Debug/hpl/evsys/hpl_evsys.o differ
diff --git a/BLDC_E54/BLDC_E54/Debug/hpl/mclk/hpl_mclk.o b/BLDC_E54/BLDC_E54/Debug/hpl/mclk/hpl_mclk.o
index 01d2682..f551846 100644
Binary files a/BLDC_E54/BLDC_E54/Debug/hpl/mclk/hpl_mclk.o and b/BLDC_E54/BLDC_E54/Debug/hpl/mclk/hpl_mclk.o differ
diff --git a/BLDC_E54/BLDC_E54/Debug/hpl/sercom/hpl_sercom.o b/BLDC_E54/BLDC_E54/Debug/hpl/sercom/hpl_sercom.o
index 0b2cfd6..a27541a 100644
Binary files a/BLDC_E54/BLDC_E54/Debug/hpl/sercom/hpl_sercom.o and b/BLDC_E54/BLDC_E54/Debug/hpl/sercom/hpl_sercom.o differ
diff --git a/BLDC_E54/BLDC_E54/Debug/main.d b/BLDC_E54/BLDC_E54/Debug/main.d
index 54cc284..cc2ea38 100644
--- a/BLDC_E54/BLDC_E54/Debug/main.d
+++ b/BLDC_E54/BLDC_E54/Debug/main.d
@@ -140,10 +140,7 @@ main.d main.o: .././main.c ../atmel_start.h ../driver_init.h \
  ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
  ../hal/include/hal_init.h ../hal/include/hpl_init.h \
  ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
- ../hal/include/hal_adc_async.h ../hal/include/hpl_adc_async.h \
- ../hal/include/hpl_adc_sync.h ../hal/include/hpl_irq.h \
- ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \
- ../hal/utils/include/utils_assert.h \
+ ../hal/include/hal_adc_sync.h ../hal/include/hpl_adc_sync.h \
  ../hal/include/hpl_missing_features.h ../hal/include/hal_custom_logic.h \
  ../hal/include/hpl_custom_logic.h ../hal/include/hal_ext_irq.h \
  ../hal/include/hpl_ext_irq.h ../hal/include/hal_evsys.h \
@@ -151,8 +148,9 @@ main.d main.o: .././main.c ../atmel_start.h ../driver_init.h \
  ../hal/utils/include/utils.h ../hal/include/hpl_pdec_async.h \
  ../hal/include/hal_spi_m_dma.h ../hal/include/hpl_spi_m_dma.h \
  ../hal/include/hpl_spi.h ../hal/include/hpl_spi_dma.h \
- ../hal/include/hpl_dma.h ../hpl/tc/tc_lite.h ../hpl/tcc/tcc_lite.h \
- ../arm_math.h \
+ ../hal/include/hpl_dma.h ../hpl/tc/tc_lite.h ../hal/include/hal_pwm.h \
+ ../hal/include/hpl_pwm.h ../hal/include/hpl_irq.h ../hpl/tcc/hpl_tcc.h \
+ ../hal/include/hpl_timer.h ../arm_math.h \
  c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
  c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
  c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
@@ -524,20 +522,10 @@ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include
 
 ../hal/include/hal_sleep.h:
 
-../hal/include/hal_adc_async.h:
-
-../hal/include/hpl_adc_async.h:
+../hal/include/hal_adc_sync.h:
 
 ../hal/include/hpl_adc_sync.h:
 
-../hal/include/hpl_irq.h:
-
-../hal/utils/include/utils_ringbuffer.h:
-
-../hal/utils/include/compiler.h:
-
-../hal/utils/include/utils_assert.h:
-
 ../hal/include/hpl_missing_features.h:
 
 ../hal/include/hal_custom_logic.h:
@@ -570,7 +558,15 @@ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include
 
 ../hpl/tc/tc_lite.h:
 
-../hpl/tcc/tcc_lite.h:
+../hal/include/hal_pwm.h:
+
+../hal/include/hpl_pwm.h:
+
+../hal/include/hpl_irq.h:
+
+../hpl/tcc/hpl_tcc.h:
+
+../hal/include/hpl_timer.h:
 
 ../arm_math.h:
 
diff --git a/BLDC_E54/BLDC_E54/Debug/main.o b/BLDC_E54/BLDC_E54/Debug/main.o
index 507d3a5..638bca8 100644
Binary files a/BLDC_E54/BLDC_E54/Debug/main.o and b/BLDC_E54/BLDC_E54/Debug/main.o differ
diff --git a/BLDC_E54/BLDC_E54/Debug/makedep.mk b/BLDC_E54/BLDC_E54/Debug/makedep.mk
index e168937..e134b19 100644
--- a/BLDC_E54/BLDC_E54/Debug/makedep.mk
+++ b/BLDC_E54/BLDC_E54/Debug/makedep.mk
@@ -16,7 +16,7 @@ ethercat\ethercat_e54.c
 
 examples\driver_examples.c
 
-hal\src\hal_adc_async.c
+hal\src\hal_adc_sync.c
 
 hal\src\hal_atomic.c
 
@@ -36,6 +36,8 @@ hal\src\hal_io.c
 
 hal\src\hal_pdec_async.c
 
+hal\src\hal_pwm.c
+
 hal\src\hal_sleep.c
 
 hal\src\hal_spi_m_dma.c
@@ -46,8 +48,6 @@ hal\utils\src\utils_event.c
 
 hal\utils\src\utils_list.c
 
-hal\utils\src\utils_ringbuffer.c
-
 hal\utils\src\utils_syscalls.c
 
 hpl\adc\hpl_adc.c
@@ -82,7 +82,7 @@ hpl\ramecc\hpl_ramecc.c
 
 hpl\sercom\hpl_sercom.c
 
-hpl\tcc\tcc_lite.c
+hpl\tcc\hpl_tcc.c
 
 hpl\tc\tc_lite.c
 
diff --git a/BLDC_E54/BLDC_E54/bldc.c b/BLDC_E54/BLDC_E54/bldc.c
index 2c2f71c..e74110f 100644
--- a/BLDC_E54/BLDC_E54/bldc.c
+++ b/BLDC_E54/BLDC_E54/bldc.c
@@ -80,6 +80,7 @@ void BldcInitStruct(BLDCMotor_t *motor)
 	motor->VoneByDcBus_pu = 1.0f/DEVICE_DC_VOLTAGE_V;
 	motor->motor_commutation_Pattern = COMMUTATION_PATTERN_M1;
 	
+	
 	motor->motor_setpoints.desired_torque	= 0.0;
 	motor->motor_setpoints.desired_speed	= 0;
 	motor->motor_setpoints.desired_position = 0;
@@ -146,6 +147,8 @@ void BldcInitFunctions()
 	Motor1.SetDutyCycle = SetM1DutyCycle;
 	Motor2.SetDutyCycle = SetM2DutyCycle;
 	Motor3.SetDutyCycle = SetM3DutyCycle;
+	
+
 }
 
 // ----------------------------------------------------------------------
@@ -153,16 +156,20 @@ void BldcInitFunctions()
 // This voltage is subtracted from all reading for Bi-Directional Current
 // Measurement
 // ----------------------------------------------------------------------
-void read_zero_current_offset_value(void)
+void read_zero_current_offset_value(BLDCMotor_t *motor)
 {
 	uint32_t phase_A_zero_current_offset_temp = 0;
 	uint32_t phase_B_zero_current_offset_temp = 0;
+	volatile uint16_t zero_current_offset_temp[2] = {0,0};
 	uint8_t samples = 16;
-	int16_t i;
+	uint8_t i;
 	
-	adc_async_enable_channel(&ADC_0, 0);
-	adc_async_enable_channel(&ADC_1, 0);
+	adc_sync_enable_channel(&ADC_0, 0);
+	//adc_sync_enable_channel(&ADC_1, 0);
 	
+	ADC0->INPUTCTRL.reg = 0x1802; 
+	while (ADC0->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */	
+			
 	for (i=0; i<samples; i++)
 	{
 		volatile uint16_t zero_current_offset_temp[2] = {0,0};
@@ -172,22 +179,31 @@ void read_zero_current_offset_value(void)
 		while (ADC0->INTFLAG.bit.RESRDY == 0);			/* Wait for the result ready flag to be set. */
 		ADC0->INTFLAG.reg = ADC_INTFLAG_RESRDY;			/* Clear the flag. */
 		zero_current_offset_temp[0]	= ADC0->RESULT.reg; /* Read the value. */
-		
-		while (ADC1->STATUS.bit.ADCBUSY) {};			/* Wait for bus synchronization. */
-		ADC1->SWTRIG.bit.START = true;					/* Start the ADC using a software trigger. */
-		while (ADC1->INTFLAG.bit.RESRDY == 0);			/* Wait for the result ready flag to be set. */
-		ADC1->INTFLAG.reg = ADC_INTFLAG_RESRDY;			/* Clear the flag. */
-		zero_current_offset_temp[1]	= ADC1->RESULT.reg; /* Read the value. */
 			
 		phase_A_zero_current_offset_temp += zero_current_offset_temp[0];
-		phase_B_zero_current_offset_temp += zero_current_offset_temp[1];
-		samples--;
 	}
-	//Motor1.Iphase_pu
-	Motor1.Voffset_lsb.A = phase_A_zero_current_offset_temp/samples;
-	Motor1.Voffset_lsb.B = phase_B_zero_current_offset_temp/samples;
-	adc_async_disable_channel(&ADC_0, 0);
-	adc_async_disable_channel(&ADC_1, 0);
+		
+	/* Set Motor Variables */
+	motor->Voffset_lsb.A = phase_A_zero_current_offset_temp/samples;
+	
+	ADC0->INPUTCTRL.reg = 0x1803; 
+	while (ADC0->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
+	
+	for (i=0; i<samples; i++)
+	{		
+		while (ADC0->STATUS.bit.ADCBUSY) {};			/* Wait for bus synchronization. */
+		ADC0->SWTRIG.bit.START = true;					/* Start the ADC using a software trigger. */
+		while (ADC0->INTFLAG.bit.RESRDY == 0);			/* Wait for the result ready flag to be set. */
+		ADC0->INTFLAG.reg = ADC_INTFLAG_RESRDY;			/* Clear the flag. */
+		zero_current_offset_temp[1]	= ADC0->RESULT.reg; /* Read the value. */
+			
+		phase_B_zero_current_offset_temp += zero_current_offset_temp[1];
+	}
+	
+	/* Set Motor Variables */
+	motor->Voffset_lsb.B = phase_B_zero_current_offset_temp/samples;
+	adc_sync_disable_channel(&ADC_0, 0);
+	//adc_sync_disable_channel(&ADC_1, 0);
 }
 
 //uint8_t get_dir_hall_code(void)
diff --git a/BLDC_E54/BLDC_E54/bldc.h b/BLDC_E54/BLDC_E54/bldc.h
index 02341b8..1ad1291 100644
--- a/BLDC_E54/BLDC_E54/bldc.h
+++ b/BLDC_E54/BLDC_E54/bldc.h
@@ -119,6 +119,7 @@ volatile typedef struct BLDCmotor
 	/* Hardware */
 	const Tcc *hw;
 	const uint16_t *motor_commutation_Pattern;
+	uint32_t current_sensor_channels[2];
 	/* Status */
 	MOTOR_Status motor_status;
 	/* Measured Values */
@@ -151,6 +152,15 @@ volatile BLDCMotor_t Motor1;
 volatile BLDCMotor_t Motor2;
 volatile BLDCMotor_t Motor3;
 
+
+static uint8_t currentSensorCount	= 4;
+static uint32_t adc_seq_regs[4]		= {0x1802, 0x1803, 0x1802, 0x1803};
+static volatile uint16_t adc_res[4] = {0};
+static volatile bool adc_dma_done	= 0;
+
+struct _dma_resource *adc_sram_dma_resource;
+struct _dma_resource *adc_dmac_sequence_resource;
+
 // ----------------------------------------------------------------------
 // 	functions
 // ----------------------------------------------------------------------
@@ -160,9 +170,9 @@ void BldcInitFunctions(void);
 
 
 void select_active_phase(BLDCMotor_t *Motor, uint8_t hall_state);
-void read_zero_current_offset_value(void);
-int32_t adc_sync_read_channel(struct adc_async_descriptor *const descr, const uint8_t channel, uint8_t *const buffer, const uint16_t length);
-static uint16_t adc_read(struct adc_async_descriptor *const descr, const uint8_t channel);
+void read_zero_current_offset_value(BLDCMotor_t *Motor);
+//int32_t adc_sync_read_channel(struct adc_async_descriptor *const descr, const uint8_t channel, uint8_t *const buffer, const uint16_t length);
+//static uint16_t adc_read(struct adc_async_descriptor *const descr, const uint8_t channel);
 void exec_commutation(void);
 uint8_t get_dir_hall_code(void);
 uint8_t get_hall_state(void);
diff --git a/BLDC_E54/BLDC_E54/configuration.h b/BLDC_E54/BLDC_E54/configuration.h
index f9bdf6d..6690b29 100644
--- a/BLDC_E54/BLDC_E54/configuration.h
+++ b/BLDC_E54/BLDC_E54/configuration.h
@@ -16,11 +16,58 @@
 #include "pins.h"
 #include "bldc.h"
 
+#define DMAC_CHANNEL_ADC_SEQ 2U
+#define DMAC_CHANNEL_ADC_SRAM 3U
+
+
+void dummy2 (void){
+	while(1);
+}
+
+void dummy3 (void){
+	while(1);
+}
+
+void dummy4 (void){
+	while(1);
+}
+void dummy5 (void){
+	while(1);
+}
+
+void dummy6 (void){
+	while(1);
+}
 
 inline void configure_tcc_pwm(void)
 {
-	hri_tcc_set_WEXCTRL_OTMX_bf(TCC1, 2);
- 	hri_tcc_write_CC_CC_bf(TCC1, 0, 150);
+	
+	/* TCC0 */
+	hri_tcc_set_WEXCTRL_OTMX_bf(TCC0, 0);
+	hri_tcc_write_PER_reg(TCC0,1000);
+	
+	hri_tcc_set_WAVE_POL0_bit(TCC0);
+	hri_tcc_set_WAVE_POL1_bit(TCC0);
+	hri_tcc_set_WAVE_POL2_bit(TCC0);
+	hri_tcc_set_WAVE_POL3_bit(TCC0);
+	hri_tcc_set_WAVE_POL4_bit(TCC0);
+	hri_tcc_set_WAVE_POL5_bit(TCC0);
+	hri_tcc_write_CC_CC_bf(TCC0, 0, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 1, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 2, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 3, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 4, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 5, 0);
+	
+	hri_tcc_write_CTRLA_ENABLE_bit(TCC0, 1 << TCC_CTRLA_ENABLE_Pos);
+	
+	
+	/* TCC1 */
+	hri_tcc_set_WEXCTRL_OTMX_bf(TCC1, 3);
+ 	hri_tcc_write_CC_CC_bf(TCC1, 0, 0);
+	hri_tcc_write_CC_CC_bf(TCC1, 1, 0);
+	hri_tcc_write_CC_CC_bf(TCC1, 2, 0);
+	hri_tcc_write_CC_CC_bf(TCC1, 3, 0);
 	//hri_tcc_write_CC_CC_bf(TCC1, 0, 0);
 	hri_tcc_write_PER_reg(TCC1,1000);
 	//pwm_set_parameters(&TCC_PWM, 1000, 250);
@@ -30,22 +77,23 @@ inline void configure_tcc_pwm(void)
 	hri_tcc_set_WAVE_POL2_bit(TCC1);
 	hri_tcc_set_WAVE_POL3_bit(TCC1);
 	hri_tcc_set_WAVE_POL4_bit(TCC1);
+	hri_tcc_set_WAVE_POL5_bit(TCC1);
 	
 	hri_tcc_clear_CTRLA_ENABLE_bit(TCC1);
 	hri_tcc_write_CTRLA_MSYNC_bit(TCC1, true);
-	hri_tcc_write_CTRLA_ENABLE_bit(TCC1, 1 << TCC_CTRLA_ENABLE_Pos); /* Enable: enabled */
+	//hri_tcc_write_CTRLA_ENABLE_bit(TCC1, 1 << TCC_CTRLA_ENABLE_Pos); /* Enable: enabled */
 	
-	//pwm_register_callback(&TCC_PWM, PWM_PERIOD_CB, pwm_cb);	
-	//pwm_enable(&TCC_PWM);
+	pwm_register_callback(&TCC_PWM, PWM_PERIOD_CB, pwm_cb);	
+	pwm_enable(&TCC_PWM);
 
 }
 
 inline void configure_adc(void)
 {
-	adc_async_enable_channel(&ADC_0, 0);
-	adc_async_enable_channel(&ADC_1, 0);
+	adc_sync_enable_channel(&ADC_0, 0);
+	//adc_sync_enable_channel(&ADC_1, 0);
 	
-	adc_async_register_callback(&ADC_0, 0, ADC_ASYNC_CONVERT_CB, adc_cb);
+	//adc_async_register_callback(&ADC_0, 0, ADC_ASYNC_CONVERT_CB, adc_cb);
 	//adc_async_register_callback(&ADC_1, 0, ADC_ASYNC_CONVERT_CB, convert_cb_ADC_1);
 	//adc_async_start_conversion(&ADC_0);
 	//adc_async_start_conversion(&ADC_1);
@@ -67,6 +115,48 @@ inline void configure_TC_CCL_SPEED(void)
 	
 }
 
+inline void adc_init_dma(void)
+{
+	adc_sram_dmac_init();
+	adc_dmac_sequence_init();
+	hri_adc_set_DSEQCTRL_INPUTCTRL_bit(ADC0);
+	hri_adc_set_DSEQCTRL_AUTOSTART_bit(ADC0);
+}
+
+inline void adc_dmac_sequence_init()
+{
+	/* Configure the DMAC source address, destination address,
+	 * next descriptor address, data count and Enable the DMAC Channel */
+	_dma_set_source_address(DMAC_CHANNEL_ADC_SEQ, (const void *)adc_seq_regs);
+	_dma_set_destination_address(DMAC_CHANNEL_ADC_SEQ, (const void *)&ADC0->DSEQDATA.reg);
+	_dma_set_data_amount(DMAC_CHANNEL_ADC_SEQ, 4);
+	_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SEQ, DMAC_CHANNEL_ADC_SEQ);
+	_dma_enable_transaction(DMAC_CHANNEL_ADC_SEQ, false);
+	_dma_get_channel_resource(&adc_dmac_sequence_resource, DMAC_CHANNEL_ADC_SEQ);
+	adc_dmac_sequence_resource[0].dma_cb.error = dummy2;
+	adc_dmac_sequence_resource[0].dma_cb.suspend = dummy3;
+	adc_dmac_sequence_resource[0].dma_cb.transfer_done = dummy4;
+	
+
+	hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[2], 0x01);	//Suspend
+}
+
+inline void adc_sram_dmac_init()
+{
+	/* Configure the DMAC source address, destination address,
+	 * next descriptor address, data count and Enable the DMAC Channel */
+	_dma_set_source_address(DMAC_CHANNEL_ADC_SRAM, (const void *)&ADC0->RESULT.reg);
+	_dma_set_destination_address(DMAC_CHANNEL_ADC_SRAM, (const void *)adc_res);
+	_dma_set_data_amount(DMAC_CHANNEL_ADC_SRAM, 4);
+	_dma_set_irq_state(DMAC_CHANNEL_ADC_SRAM, DMA_TRANSFER_COMPLETE_CB, true);
+	_dma_get_channel_resource(&adc_sram_dma_resource, DMAC_CHANNEL_ADC_SRAM);
+	adc_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback;
+	adc_sram_dma_resource[0].dma_cb.error = dummy6;
+	adc_sram_dma_resource[0].dma_cb.suspend = dummy5;
+	
+	_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SRAM, DMAC_CHANNEL_ADC_SRAM);
+	_dma_enable_transaction(DMAC_CHANNEL_ADC_SRAM, false);
+}
 
 
 
diff --git a/BLDC_E54/BLDC_E54/driver_init.c b/BLDC_E54/BLDC_E54/driver_init.c
index d7fecf8..9cef5b4 100644
--- a/BLDC_E54/BLDC_E54/driver_init.c
+++ b/BLDC_E54/BLDC_E54/driver_init.c
@@ -11,75 +11,43 @@
 #include <utils.h>
 #include <hal_init.h>
 
-#include <hpl_adc_base.h>
 #include <hpl_adc_base.h>
 
-/* The channel amount for ADC */
-#define ADC_0_CH_AMOUNT 1
-
-/* The buffer size for ADC */
-#define ADC_0_BUFFER_SIZE 16
-
-/* The maximal channel number of enabled channels */
-#define ADC_0_CH_MAX 0
-
-/* The channel amount for ADC */
-#define ADC_1_CH_AMOUNT 1
-
-/* The buffer size for ADC */
-#define ADC_1_BUFFER_SIZE 16
-
-/* The maximal channel number of enabled channels */
-#define ADC_1_CH_MAX 0
-
-struct adc_async_descriptor         ADC_0;
-struct adc_async_channel_descriptor ADC_0_ch[ADC_0_CH_AMOUNT];
-struct adc_async_descriptor         ADC_1;
-struct adc_async_channel_descriptor ADC_1_ch[ADC_1_CH_AMOUNT];
-
-static uint8_t ADC_0_buffer[ADC_0_BUFFER_SIZE];
-static uint8_t ADC_0_map[ADC_0_CH_MAX + 1];
-static uint8_t ADC_1_buffer[ADC_1_BUFFER_SIZE];
-static uint8_t ADC_1_map[ADC_1_CH_MAX + 1];
+struct adc_sync_descriptor ADC_0;
 
 struct pdec_async_descriptor POSITION_DECODER_0;
 
 struct spi_m_dma_descriptor SPI_0;
 
-/**
- * \brief ADC initialization function
- *
- * Enables ADC peripheral, clocks and initializes ADC driver
- */
-void ADC_0_init(void)
+struct pwm_descriptor TCC_PWM2;
+
+struct pwm_descriptor TCC_PWM;
+
+void ADC_0_PORT_init(void)
 {
-	hri_mclk_set_APBDMASK_ADC0_bit(MCLK);
-	hri_gclk_write_PCHCTRL_reg(GCLK, ADC0_GCLK_ID, CONF_GCLK_ADC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
-	adc_async_init(&ADC_0, ADC0, ADC_0_map, ADC_0_CH_MAX, ADC_0_CH_AMOUNT, &ADC_0_ch[0], (void *)NULL);
-	adc_async_register_channel_buffer(&ADC_0, 0, ADC_0_buffer, ADC_0_BUFFER_SIZE);
 
 	// Disable digital pin circuitry
 	gpio_set_pin_direction(PB08, GPIO_DIRECTION_OFF);
 
 	gpio_set_pin_function(PB08, PINMUX_PB08B_ADC0_AIN2);
-}
-
-/**
- * \brief ADC initialization function
- *
- * Enables ADC peripheral, clocks and initializes ADC driver
- */
-void ADC_1_init(void)
-{
-	hri_mclk_set_APBDMASK_ADC1_bit(MCLK);
-	hri_gclk_write_PCHCTRL_reg(GCLK, ADC1_GCLK_ID, CONF_GCLK_ADC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
-	adc_async_init(&ADC_1, ADC1, ADC_1_map, ADC_1_CH_MAX, ADC_1_CH_AMOUNT, &ADC_1_ch[0], (void *)NULL);
-	adc_async_register_channel_buffer(&ADC_1, 0, ADC_1_buffer, ADC_1_BUFFER_SIZE);
 
 	// Disable digital pin circuitry
 	gpio_set_pin_direction(PB09, GPIO_DIRECTION_OFF);
 
-	gpio_set_pin_function(PB09, PINMUX_PB09B_ADC1_AIN1);
+	gpio_set_pin_function(PB09, PINMUX_PB09B_ADC0_AIN3);
+}
+
+void ADC_0_CLOCK_init(void)
+{
+	hri_mclk_set_APBDMASK_ADC0_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, ADC0_GCLK_ID, CONF_GCLK_ADC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void ADC_0_init(void)
+{
+	ADC_0_CLOCK_init();
+	ADC_0_PORT_init();
+	adc_sync_init(&ADC_0, ADC0, (void *)NULL);
 }
 
 void DIGITAL_GLUE_LOGIC_0_PORT_init(void)
@@ -129,7 +97,6 @@ void EXTERNAL_IRQ_0_init(void)
 void EVENT_SYSTEM_0_init(void)
 {
 	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_0, CONF_GCLK_EVSYS_CHANNEL_0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
-	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_1, CONF_GCLK_EVSYS_CHANNEL_1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
 
 	hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);
 
@@ -246,10 +213,18 @@ void TCC_PWM2_PORT_init(void)
 
 void TCC_PWM2_CLOCK_init(void)
 {
+
 	hri_mclk_set_APBBMASK_TCC0_bit(MCLK);
 	hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, CONF_GCLK_TCC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
 }
 
+void TCC_PWM2_init(void)
+{
+	TCC_PWM2_CLOCK_init();
+	TCC_PWM2_PORT_init();
+	pwm_init(&TCC_PWM2, TCC0, _tcc_get_pwm());
+}
+
 void TCC_PWM_PORT_init(void)
 {
 
@@ -270,10 +245,18 @@ void TCC_PWM_PORT_init(void)
 
 void TCC_PWM_CLOCK_init(void)
 {
+
 	hri_mclk_set_APBBMASK_TCC1_bit(MCLK);
 	hri_gclk_write_PCHCTRL_reg(GCLK, TCC1_GCLK_ID, CONF_GCLK_TCC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
 }
 
+void TCC_PWM_init(void)
+{
+	TCC_PWM_CLOCK_init();
+	TCC_PWM_PORT_init();
+	pwm_init(&TCC_PWM, TCC1, _tcc_get_pwm());
+}
+
 void system_init(void)
 {
 	init_mcu();
@@ -434,7 +417,6 @@ void system_init(void)
 	gpio_set_pin_function(DEBUG_4, GPIO_PIN_FUNCTION_OFF);
 
 	ADC_0_init();
-	ADC_1_init();
 
 	DIGITAL_GLUE_LOGIC_0_init();
 
@@ -454,15 +436,7 @@ void system_init(void)
 
 	TC_ECAT_init();
 
-	TCC_PWM2_CLOCK_init();
-
-	TCC_PWM2_PORT_init();
-
 	TCC_PWM2_init();
 
-	TCC_PWM_CLOCK_init();
-
-	TCC_PWM_PORT_init();
-
 	TCC_PWM_init();
 }
diff --git a/BLDC_E54/BLDC_E54/driver_init.h b/BLDC_E54/BLDC_E54/driver_init.h
index 46de5a2..400b201 100644
--- a/BLDC_E54/BLDC_E54/driver_init.h
+++ b/BLDC_E54/BLDC_E54/driver_init.h
@@ -21,8 +21,7 @@ extern "C" {
 #include <hal_io.h>
 #include <hal_sleep.h>
 
-#include <hal_adc_async.h>
-#include <hal_adc_async.h>
+#include <hal_adc_sync.h>
 
 #include <hal_custom_logic.h>
 
@@ -35,19 +34,26 @@ extern "C" {
 #include <hal_spi_m_dma.h>
 #include <tc_lite.h>
 #include <tc_lite.h>
-#include <tcc_lite.h>
-#include <tcc_lite.h>
 
-extern struct adc_async_descriptor ADC_0;
-extern struct adc_async_descriptor ADC_1;
+#include <hal_pwm.h>
+#include <hpl_tcc.h>
+
+#include <hal_pwm.h>
+#include <hpl_tcc.h>
+
+extern struct adc_sync_descriptor ADC_0;
 
 extern struct pdec_async_descriptor POSITION_DECODER_0;
 
 extern struct spi_m_dma_descriptor SPI_0;
 
-void ADC_0_init(void);
+extern struct pwm_descriptor TCC_PWM2;
 
-void ADC_1_init(void);
+extern struct pwm_descriptor TCC_PWM;
+
+void ADC_0_PORT_init(void);
+void ADC_0_CLOCK_init(void);
+void ADC_0_init(void);
 
 void DIGITAL_GLUE_LOGIC_0_PORT_init(void);
 void DIGITAL_GLUE_LOGIC_0_CLOCK_init(void);
@@ -69,17 +75,13 @@ void TC_ECAT_CLOCK_init(void);
 
 int8_t TC_ECAT_init(void);
 
-void TCC_PWM2_CLOCK_init(void);
-
 void TCC_PWM2_PORT_init(void);
-
-int8_t TCC_PWM2_init(void);
-
-void TCC_PWM_CLOCK_init(void);
+void TCC_PWM2_CLOCK_init(void);
+void TCC_PWM2_init(void);
 
 void TCC_PWM_PORT_init(void);
-
-int8_t TCC_PWM_init(void);
+void TCC_PWM_CLOCK_init(void);
+void TCC_PWM_init(void);
 
 /**
  * \brief Perform system initialization, initialize pins and clocks for
diff --git a/BLDC_E54/BLDC_E54/ethercat/ethercat_e54.c b/BLDC_E54/BLDC_E54/ethercat/ethercat_e54.c
index 6821d9b..b822f00 100644
--- a/BLDC_E54/BLDC_E54/ethercat/ethercat_e54.c
+++ b/BLDC_E54/BLDC_E54/ethercat/ethercat_e54.c
@@ -77,23 +77,9 @@ void update_setpoints(void)
 	//Motor1.Spare4							= 0;	 
 }
 
-
 
 extern void One_ms_cycle_callback(void)
 {
-	tic_port(DEBUG_3_PORT);
-	//tic(DEBUG_2);
-	//gpio_toggle_pin_level(DBG_PIN1);
-	
-	//update Motor telemetry
-	//tic(DEBUG_2);
-	//update_setpoints();
-	//toc(DEBUG_2);
-	//tic(DEBUG_3);
-	//update_telemetry();
-	//toc(DEBUG_3);
-	
-	//tic(DEBUG_3);
 	tx_ethercat = true;
 	if(tx_ethercat_done){
 		volatile int i=0;
@@ -110,14 +96,11 @@ extern void One_ms_cycle_callback(void)
 		gpio_set_pin_level(ECAT_SPI_CS_PIN, false);  // SPI_Slave Select LOW
 		DMAC->Channel[0].CHCTRLB.reg = 0x2; // Resume		
 		//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
-		/*hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[0], DMAC_CHCTRLB_CMD_RESUME_Val)*/;	//TX Channel	
		
		DMAC->Channel[1].CHCTRLB.reg = 0x2; // Resume
		tx_ethercat_done = false;
	}
	else {
		gpio_set_pin_level(ECAT_SPI_CS_PIN, true);			// SPI_Slave Select HIGH
+		/*hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[0], DMAC_CHCTRLB_CMD_RESUME_Val)*/;	//TX Channel	
		
		DMAC->Channel[1].CHCTRLB.reg = 0x2; // Resume
		tx_ethercat_done = false;
	}
	else {
		
		gpio_set_pin_level(ECAT_SPI_CS_PIN, true);			// SPI_Slave Select HIGH
 		tx_ethercat_done = false;
		
		//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_rx.channel_id);
 		//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
 		//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_tx.channel_id);
		//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[1], DMAC_CHCTRLB_CMD_RESUME_Val);	//RX Channel
		gpio_set_pin_level(ECAT_SPI_CS_PIN, false); // SPI_Slave Select LOW
		_dma_enable_transaction(0,false);
		//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
 		//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[0], DMAC_CHCTRLB_CMD_RESUME_Val);	//TX Channel
		_dma_enable_transaction(1,false);
		tx_ethercat_done = false;
	}
-	//toc(DEBUG_3);
-	//toc(DEBUG_2);
-	toc_port(DEBUG_3_PORT);
 }
 
 // ----------------------------------------------------------------------
diff --git a/BLDC_E54/BLDC_E54/examples/driver_examples.c b/BLDC_E54/BLDC_E54/examples/driver_examples.c
index 090df04..a0dd9e6 100644
--- a/BLDC_E54/BLDC_E54/examples/driver_examples.c
+++ b/BLDC_E54/BLDC_E54/examples/driver_examples.c
@@ -10,32 +10,18 @@
 #include "driver_init.h"
 #include "utils.h"
 
-static void convert_cb_ADC_0(const struct adc_async_descriptor *const descr, const uint8_t channel)
-{
-}
-
 /**
  * Example of using ADC_0 to generate waveform.
  */
 void ADC_0_example(void)
 {
-	adc_async_enable_channel(&ADC_0, 0);
-	adc_async_register_callback(&ADC_0, 0, ADC_ASYNC_CONVERT_CB, convert_cb_ADC_0);
-	adc_async_start_conversion(&ADC_0);
-}
+	uint8_t buffer[2];
 
-static void convert_cb_ADC_1(const struct adc_async_descriptor *const descr, const uint8_t channel)
-{
-}
+	adc_sync_enable_channel(&ADC_0, 0);
 
-/**
- * Example of using ADC_1 to generate waveform.
- */
-void ADC_1_example(void)
-{
-	adc_async_enable_channel(&ADC_1, 0);
-	adc_async_register_callback(&ADC_1, 0, ADC_ASYNC_CONVERT_CB, convert_cb_ADC_1);
-	adc_async_start_conversion(&ADC_1);
+	while (1) {
+		adc_sync_read_channel(&ADC_0, 0, buffer, 2);
+	}
 }
 
 /**
@@ -107,3 +93,21 @@ void SPI_0_example(void)
 	spi_m_dma_enable(&SPI_0);
 	io_write(io, example_SPI_0, 12);
 }
+
+/**
+ * Example of using TCC_PWM2.
+ */
+void TCC_PWM2_example(void)
+{
+	pwm_set_parameters(&TCC_PWM2, 10000, 5000);
+	pwm_enable(&TCC_PWM2);
+}
+
+/**
+ * Example of using TCC_PWM.
+ */
+void TCC_PWM_example(void)
+{
+	pwm_set_parameters(&TCC_PWM, 10000, 5000);
+	pwm_enable(&TCC_PWM);
+}
diff --git a/BLDC_E54/BLDC_E54/examples/driver_examples.h b/BLDC_E54/BLDC_E54/examples/driver_examples.h
index cf73a2d..5700d41 100644
--- a/BLDC_E54/BLDC_E54/examples/driver_examples.h
+++ b/BLDC_E54/BLDC_E54/examples/driver_examples.h
@@ -14,8 +14,6 @@ extern "C" {
 
 void ADC_0_example(void);
 
-void ADC_1_example(void);
-
 void DIGITAL_GLUE_LOGIC_0_example(void);
 
 void EXTERNAL_IRQ_0_example(void);
@@ -24,6 +22,10 @@ void POSITION_DECODER_0_example(void);
 
 void SPI_0_example(void);
 
+void TCC_PWM2_example(void);
+
+void TCC_PWM_example(void);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/BLDC_E54/BLDC_E54/hal/documentation/adc_async.rst b/BLDC_E54/BLDC_E54/hal/documentation/adc_async.rst
deleted file mode 100644
index ac525cd..0000000
--- a/BLDC_E54/BLDC_E54/hal/documentation/adc_async.rst
+++ /dev/null
@@ -1,101 +0,0 @@
-=======================
-ADC Asynchronous driver
-=======================
-
-An ADC (Analog-to-Digital Converter) converts analog signals to digital values.
-A reference signal with a known voltage level is quantified into equally
-sized chunks, each representing a digital value from 0 to the highest number
-possible with the bit resolution supported by the ADC. The input voltage
-measured by the ADC is compared against these chunks and the chunk with the
-closest voltage level defines the digital value that can be used to represent
-the analog input voltage level.
-
-Usually an ADC can operate in either differential or single-ended mode.
-In differential mode two signals (V+ and V-) are compared against each other
-and the resulting digital value represents the relative voltage level between
-V+ and V-. This means that if the input voltage level on V+ is lower than on
-V- the digital value is negative, which also means that in differential
-mode one bit is lost to the sign. In single-ended mode only V+ is compared
-against the reference voltage, and the resulting digital value only can be
-positive, but the full bit-range of the ADC can be used.
-
-Usually multiple resolutions are supported by the ADC, lower resolution can
-reduce the conversion time, but lose accuracy.
-
-Some ADCs has a gain stage on the input lines which can be used to increase the
-dynamic range. The default gain value is usually x1, which means that the
-conversion range is from 0V to the reference voltage.
-Applications can change the gain stage, to increase or reduce the conversion
-range.
-
-The window mode allows the conversion result to be compared to a set of
-predefined threshold values. Applications can use callback function to monitor
-if the conversion result exceeds predefined threshold value.
-
-Usually multiple reference voltages are supported by the ADC, both internal and
-external with difference voltage levels. The reference voltage have an impact
-on the accuracy, and should be selected to cover the full range of the analog
-input signal and never less than the expected maximum input voltage.
-
-There are two conversion modes supported by ADC, single shot and free running.
-In single shot mode the ADC only make one conversion when triggered by the
-application, in free running mode it continues to make conversion from it
-is triggered until it is stopped by the application. When window monitoring,
-the ADC should be set to free running mode.
-
-The ADC async driver use a channel map buffer to map the relation between the 
-enabled channels number and the index of register channel descriptor. The index 
-of channel map buffer is channel number, and the value of channel map buffer is
-the index of register channel descriptor. For example, when register channel_1, 
-channel_5, and channel_9 in sequence, the value of channel_map[1] is 0, the value 
-of channel_map[5] is 1, the value of channel_map[9] is 2.
-
-The ADC async driver use a ring buffer to store ADC sample data. When the ADC
-raise the sample complete interrupt, a copy of the ADC sample register is stored
-in the ring buffer at the next free location. This will happen regardless of if
-the ADC is in one shot mode or in free running mode. When the ring buffer is
-full, the next sample will overwrite the oldest sample in the ring buffer. The
-size of the ring buffer is set by a macro in atmel_start.h called ADC_BUFFER_SIZE.
-
-To read the samples from the ring buffer, the function adc_async_read is used.
-This function reads the number of bytes asked for from the ring buffer, starting
-from the oldest byte. If the number of bytes asked for are more than currently
-available in the ring buffer, the number of available bytes are read. The
-adc_async_read function will return the actual number of bytes read from the buffer
-back to the caller. If the number of bytes asked for is less than the available
-bytes in the ring buffer, the remaining bytes will be kept until a new call to
-adc_async_read or it's overwritten because the ring buffer is full.
-
-Note that the adc_async_read_channel function will always read bytes from the ring buffer,
-and for samples > 8-bit the read length has to be power of two number.
-
-Features
---------
-* Initialization and de-initialization
-* Single shot or free running conversion modes
-* Start ADC conversion
-* Callback on conversion done, error and monitor events
-* Ring buffer
-
-Applications
-------------
-* Measurement of internal sensor. E.g., MCU internal temperature sensor value.
-* Measurement of external sensor. E.g., Temperature, humidity sensor value.
-* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave.
-
-Dependencies
-------------
-* ADC hardware with result ready/conversion done, error and monitor interrupt.
-
-Concurrency
------------
-N/A
-
-Limitations
------------
-N/A
-
-Knows issues and workarounds
-----------------------------
-N/A
-
diff --git a/BLDC_E54/BLDC_E54/hal/include/hal_adc_async.h b/BLDC_E54/BLDC_E54/hal/include/hal_adc_async.h
deleted file mode 100644
index 971f20b..0000000
--- a/BLDC_E54/BLDC_E54/hal/include/hal_adc_async.h
+++ /dev/null
@@ -1,399 +0,0 @@
-/**
- * \file
- *
- * \brief ADC functionality declaration.
- *
- * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef HAL_ADC_ASYNC_H_INCLUDED
-#define HAL_ADC_ASYNC_H_INCLUDED
-
-#include <hpl_adc_async.h>
-#include <utils_ringbuffer.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \addtogroup doc_driver_hal_adc_async
- *
- * @{
- */
-
-/**
- * \brief ADC descriptor
- *
- * The ADC descriptor forward declaration.
- */
-struct adc_async_descriptor;
-
-/**
- * \brief ADC callback type
- */
-typedef void (*adc_async_cb_t)(const struct adc_async_descriptor *const descr, const uint8_t channel);
-
-/**
- * \brief ADC callback types
- */
-enum adc_async_callback_type {
-	/** ADC convert done callback */
-	ADC_ASYNC_CONVERT_CB,
-	/** ADC monitor callback */
-	ADC_ASYNC_MONITOR_CB,
-	/** ADC error callback */
-	ADC_ASYNC_ERROR_CB
-};
-
-/**
- * \brief ADC callbacks
- */
-struct adc_async_callbacks {
-	/** Monitor callback  */
-	adc_async_cb_t monitor;
-	/** Error callback  */
-	adc_async_cb_t error;
-};
-
-/**
- * \brief ADC channel callbacks
- */
-struct adc_async_ch_callbacks {
-	/** Convert done callback  */
-	adc_async_cb_t convert_done;
-};
-
-/**
- * \brief ADC channel buffer descriptor
- */
-struct adc_async_channel_descriptor {
-	/** ADC channel callbacks type */
-	struct adc_async_ch_callbacks adc_async_ch_cb;
-	/** Convert buffer  */
-	struct ringbuffer convert;
-	/** Bytes in buffer  */
-	uint16_t bytes_in_buffer;
-};
-
-/**
- * \brief ADC descriptor
- */
-struct adc_async_descriptor {
-	/** ADC device */
-	struct _adc_async_device device;
-	/** ADC callbacks type */
-	struct adc_async_callbacks adc_async_cb;
-	/** Enabled channel map */
-	uint8_t *channel_map;
-	/** Enabled maximum channel number */
-	uint8_t channel_max;
-	/** Enabled channel amount */
-	uint8_t channel_amount;
-	/** ADC channel descriptor */
-	struct adc_async_channel_descriptor *descr_ch;
-};
-
-/**
- * \brief Initialize ADC
- *
- * This function initializes the given ADC descriptor.
- * It checks if the given hardware is not initialized and if the given hardware
- * is permitted to be initialized.
- *
- * \param[out] descr         An ADC descriptor to initialize
- * \param[in] hw             The pointer to hardware instance
- * \param[in] channel_map    The pointer to ADC channel mapping
- * \param[in] channel_max    ADC enabled maximum channel number
- * \param[in] channel_amount ADC enabled channel amount
- * \param[in] descr_ch       A buffer to keep all channel descriptor
- * \param[in] func           The pointer to as set of functions pointers
- *
- * \return Initialization status.
- * \retval -1 Passed parameters were invalid or an ADC is already initialized
- * \retval 0 The initialization is completed successfully
- */
-int32_t adc_async_init(struct adc_async_descriptor *const descr, void *const hw, uint8_t *channel_map,
-                       uint8_t channel_max, uint8_t channel_amount, struct adc_async_channel_descriptor *const descr_ch,
-                       void *const func);
-
-/**
- * \brief Deinitialize ADC
- *
- * This function deinitializes the given ADC descriptor.
- * It checks if the given hardware is initialized and if the given hardware is
- * permitted to be deinitialized.
- *
- * \param[in] descr An ADC descriptor to deinitialize
- *
- * \return De-initialization status.
- */
-int32_t adc_async_deinit(struct adc_async_descriptor *const descr);
-
-/**
- * \brief Register ADC channel buffer
- *
- * This function initializes the given ADC channel buffer descriptor.
- *
- * \param[in] descr          An ADC descriptor to initialize
- * \param[in] channel        Channel number
- * \param[in] convert_buffer A buffer to keep converted values
- * \param[in] convert_buffer_length The length of the buffer above
- *
- * \return Initialization status.
- * \retval -1 Passed parameters were invalid or an ADC is already initialized
- * \retval 0 The initialization is completed successfully
- */
-int32_t adc_async_register_channel_buffer(struct adc_async_descriptor *const descr, const uint8_t channel,
-                                          uint8_t *const convert_buffer, const uint16_t convert_buffer_length);
-
-/**
- * \brief Enable channel of ADC
- *
- * Use this function to set the ADC peripheral to enabled state.
- *
- * \param[in] descr    Pointer to the ADC descriptor
- * \param[in] channel  Channel number
- *
- * \return Operation status.
- *
- */
-int32_t adc_async_enable_channel(struct adc_async_descriptor *const descr, const uint8_t channel);
-
-/**
- * \brief Disable channel of ADC
- *
- * Use this function to set the ADC peripheral to disabled state.
- *
- * \param[in] descr   Pointer to the ADC descriptor
- * \param[in] channel  Channel number
- *
- * \return Operation status.
- *
- */
-int32_t adc_async_disable_channel(struct adc_async_descriptor *const descr, const uint8_t channel);
-
-/**
- * \brief Register ADC callback
- *
- * \param[in] io_descr  An adc descriptor
- * \param[in] channel   Channel number
- * \param[in] type      Callback type
- * \param[in] cb        A callback function, passing NULL de-registers callback
- *
- * \return The status of callback assignment.
- * \retval -1 Passed parameters were invalid or the ADC is not initialized
- * \retval 0 A callback is registered successfully
- */
-int32_t adc_async_register_callback(struct adc_async_descriptor *const descr, const uint8_t channel,
-                                    const enum adc_async_callback_type type, adc_async_cb_t cb);
-
-/**
- * \brief Read data from the ADC
- *
- * \param[in] descr     The pointer to the ADC descriptor
- * \param[in] channel   Channel number
- * \param[in] buf       A buffer to read data to
- * \param[in] length    The size of a buffer
- *
- * \return The number of bytes read.
- */
-int32_t adc_async_read_channel(struct adc_async_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
-                               const uint16_t length);
-
-/**
- * \brief Start conversion
- *
- * This function starts single conversion if no automatic (free-run) mode is
- * enabled.
- *
- * \param[in] descr The pointer to the ADC descriptor
- *
- * \return Start conversion status.
- */
-int32_t adc_async_start_conversion(struct adc_async_descriptor *const descr);
-
-/**
- * \brief Set ADC reference source
- *
- * This function sets ADC reference source.
- *
- * \param[in] descr     The pointer to the ADC descriptor
- * \param[in] reference A reference source to set
- *
- * \return Status of the ADC reference source setting.
- */
-int32_t adc_async_set_reference(struct adc_async_descriptor *const descr, const adc_reference_t reference);
-
-/**
- * \brief Set ADC resolution
- *
- * This function sets ADC resolution.
- *
- * \param[in] descr      The pointer to the ADC descriptor
- * \param[in] resolution A resolution to set
- *
- * \return Status of the ADC resolution setting.
- */
-int32_t adc_async_set_resolution(struct adc_async_descriptor *const descr, const adc_resolution_t resolution);
-
-/**
- * \brief Set ADC input source of a channel
- *
- * This function sets the ADC positive and negative input sources.
- *
- * \param[in] descr     The pointer to the ADC descriptor
- * \param[in] pos_input A positive input source to set
- * \param[in] neg_input A negative input source to set
- * \param[in] channel   Channel number
- *
- * \return Status of the ADC channels setting.
- */
-int32_t adc_async_set_inputs(struct adc_async_descriptor *const descr, const adc_pos_input_t pos_input,
-                             const adc_neg_input_t neg_input, const uint8_t channel);
-
-/**
- * \brief Set ADC conversion mode
- *
- * This function sets ADC conversion mode.
- *
- * \param[in] descr The pointer to the ADC descriptor
- * \param[in] mode  A conversion mode to set
- *
- * \return Status of the ADC conversion mode setting.
- */
-int32_t adc_async_set_conversion_mode(struct adc_async_descriptor *const descr, const enum adc_conversion_mode mode);
-
-/**
- * \brief Set ADC differential mode
- *
- * This function sets ADC differential mode.
- *
- * \param[in] descr   The pointer to the ADC descriptor
- * \param[in] channel Channel number
- * \param[in] mode    A differential mode to set
- *
- * \return Status of the ADC differential mode setting.
- */
-int32_t adc_async_set_channel_differential_mode(struct adc_async_descriptor *const descr, const uint8_t channel,
-                                                const enum adc_differential_mode mode);
-
-/**
- * \brief Set ADC channel gain
- *
- * This function sets ADC channel gain.
- *
- * \param[in] descr   The pointer to the ADC descriptor
- * \param[in] channel Channel number
- * \param[in] gain    A gain to set
- *
- * \return Status of the ADC gain setting.
- */
-int32_t adc_async_set_channel_gain(struct adc_async_descriptor *const descr, const uint8_t channel,
-                                   const adc_gain_t gain);
-
-/**
- * \brief Set ADC window mode
- *
- * This function sets ADC window mode.
- *
- * \param[in] descr The pointer to the ADC descriptor
- * \param[in] mode  A window mode to set
- *
- * \return Status of the ADC window mode setting.
- */
-int32_t adc_async_set_window_mode(struct adc_async_descriptor *const descr, const adc_window_mode_t mode);
-
-/**
- * \brief Set ADC thresholds
- *
- * This function sets the ADC positive and negative thresholds.
- *
- * \param[in] descr         The pointer to the ADC descriptor
- * \param[in] low_threshold A lower thresholds to set
- * \param[in] up_threshold  An upper thresholds to set
- *
- * \return Status of the ADC thresholds setting.
- */
-int32_t adc_async_set_thresholds(struct adc_async_descriptor *const descr, const adc_threshold_t low_threshold,
-                                 const adc_threshold_t up_threshold);
-
-/**
- * \brief Retrieve threshold state
- *
- * This function retrieves ADC threshold state.
- *
- * \param[in] descr  The pointer to the ADC descriptor
- * \param[out] state The threshold state
- *
- * \return The state of ADC thresholds state retrieving.
- */
-int32_t adc_async_get_threshold_state(const struct adc_async_descriptor *const descr,
-                                      adc_threshold_status_t *const            state);
-
-/**
- * \brief Check if conversion is complete
- *
- * This function checks if the ADC has finished the conversion.
- *
- * \param[in] descr   The pointer to the ADC descriptor
- * \param[in] channel Channel number
- *
- * \return The status of the ADC conversion completion checking.
- * \retval 1 The conversion is complete
- * \retval 0 The conversion is not complete
- */
-int32_t adc_async_is_channel_conversion_complete(const struct adc_async_descriptor *const descr, const uint8_t channel);
-
-/**
- * \brief Flush ADC ringbuf
- *
- * This function flush ADC RX ringbuf.
- *
- * \param[in] descr    The pointer to the ADC descriptor
- * \param[in] channel  Channel number
- *
- * \return ERR_NONE
- */
-int32_t adc_async_flush_rx_buffer(struct adc_async_descriptor *const descr, const uint8_t channel);
-
-/**
- * \brief Retrieve the current driver version
- *
- * \return Current driver version.
- */
-uint32_t adc_async_get_version(void);
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#include <hpl_missing_features.h>
-
-#endif /* HAL_ADC_ASYNC_H_INCLUDED */
diff --git a/BLDC_E54/BLDC_E54/hal/include/hpl_dma.h b/BLDC_E54/BLDC_E54/hal/include/hpl_dma.h
index 078b6b4..410f95d 100644
--- a/BLDC_E54/BLDC_E54/hal/include/hpl_dma.h
+++ b/BLDC_E54/BLDC_E54/hal/include/hpl_dma.h
@@ -55,7 +55,8 @@ struct _dma_resource;
 /**
  * \brief DMA callback types
  */
-enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB, DMA_TRANSFER_SUSPEND_CB  };
+
+enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB, DMA_SUSPEND_CB };
 
 /**
  * \brief DMA interrupt callbacks
diff --git a/BLDC_E54/BLDC_E54/hal/src/hal_adc_async.c b/BLDC_E54/BLDC_E54/hal/src/hal_adc_async.c
deleted file mode 100644
index 933335c..0000000
--- a/BLDC_E54/BLDC_E54/hal/src/hal_adc_async.c
+++ /dev/null
@@ -1,393 +0,0 @@
-/**
- * \file
- *
- * \brief ADC functionality implementation.
- *
- * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-/**
- * \brief Indicates HAL being compiled. Must be defined before including.
- */
-#define _COMPILING_HAL
-
-#include "hal_adc_async.h"
-#include <utils_assert.h>
-#include <utils.h>
-#include <hal_atomic.h>
-
-/**
- * \brief Driver version
- */
-#define DRIVER_VERSION 0x00000001u
-
-static void adc_async_channel_conversion_done(struct _adc_async_device *device, const uint8_t channel,
-                                              const uint16_t data);
-static void adc_async_window_threshold_reached(struct _adc_async_device *device, const uint8_t channel);
-static void adc_async_error_occured(struct _adc_async_device *device, const uint8_t channel);
-
-/**
- * \brief Initialize ADC
- */
-int32_t adc_async_init(struct adc_async_descriptor *const descr, void *const hw, uint8_t *channel_map,
-                       uint8_t channel_max, uint8_t channel_amount, struct adc_async_channel_descriptor *const descr_ch,
-                       void *const func)
-{
-	int32_t                   init_status;
-	struct _adc_async_device *device;
-	ASSERT(descr && hw && channel_map && channel_amount && descr_ch);
-	ASSERT(channel_amount <= (channel_max + 1));
-
-	device = &descr->device;
-	for (uint8_t i = 0; i <= channel_max; i++) {
-		channel_map[i] = 0xFF;
-	}
-	descr->channel_map    = channel_map;
-	descr->channel_max    = channel_max;
-	descr->channel_amount = channel_amount;
-	descr->descr_ch       = descr_ch;
-	init_status           = _adc_async_init(device, hw);
-	if (init_status) {
-		return init_status;
-	}
-
-	device->adc_async_ch_cb.convert_done = adc_async_channel_conversion_done;
-	device->adc_async_cb.window_cb       = adc_async_window_threshold_reached;
-	device->adc_async_cb.error_cb        = adc_async_error_occured;
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Deinitialize ADC
- */
-int32_t adc_async_deinit(struct adc_async_descriptor *const descr)
-{
-	ASSERT(descr);
-	_adc_async_deinit(&descr->device);
-
-	return ERR_NONE;
-}
-
-int32_t adc_async_register_channel_buffer(struct adc_async_descriptor *const descr, const uint8_t channel,
-                                          uint8_t *const convert_buffer, const uint16_t convert_buffer_length)
-{
-	uint8_t i, index = 0;
-
-	ASSERT(descr && convert_buffer && convert_buffer_length);
-	ASSERT(descr->channel_max >= channel);
-
-	if (descr->channel_map[channel] != 0xFF) {
-		return ERR_INVALID_ARG;
-	}
-	for (i = 0; i <= descr->channel_max; i++) {
-		if (descr->channel_map[i] != 0xFF) {
-			index++;
-		}
-	}
-
-	if (index > descr->channel_amount) {
-		return ERR_NO_RESOURCE;
-	}
-	if (ERR_NONE != ringbuffer_init(&descr->descr_ch[index].convert, convert_buffer, convert_buffer_length)) {
-		return ERR_INVALID_ARG;
-	}
-	descr->channel_map[channel]            = index;
-	descr->descr_ch[index].bytes_in_buffer = 0;
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Enable ADC
- */
-int32_t adc_async_enable_channel(struct adc_async_descriptor *const descr, const uint8_t channel)
-{
-	ASSERT(descr);
-	ASSERT(descr->channel_max >= channel);
-	_adc_async_enable_channel(&descr->device, channel);
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Disable ADC
- */
-int32_t adc_async_disable_channel(struct adc_async_descriptor *const descr, const uint8_t channel)
-{
-	ASSERT(descr);
-	ASSERT(descr->channel_max >= channel);
-	_adc_async_disable_channel(&descr->device, channel);
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Register ADC callback
- */
-int32_t adc_async_register_callback(struct adc_async_descriptor *const descr, const uint8_t channel,
-                                    const enum adc_async_callback_type type, adc_async_cb_t cb)
-{
-	ASSERT(descr);
-	ASSERT(descr->channel_max >= channel);
-
-	uint8_t index = descr->channel_map[channel];
-	switch (type) {
-	case ADC_ASYNC_CONVERT_CB:
-		descr->descr_ch[index].adc_async_ch_cb.convert_done = cb;
-		break;
-	case ADC_ASYNC_MONITOR_CB:
-		descr->adc_async_cb.monitor = cb;
-		break;
-	case ADC_ASYNC_ERROR_CB:
-		descr->adc_async_cb.error = cb;
-		break;
-	default:
-		return ERR_INVALID_ARG;
-	}
-	_adc_async_set_irq_state(&descr->device, channel, (enum _adc_async_callback_type)type, cb != NULL);
-
-	return ERR_NONE;
-}
-
-/*
- * \brief Read data from ADC
- */
-int32_t adc_async_read_channel(struct adc_async_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
-                               const uint16_t length)
-{
-	uint8_t  data_size, index;
-	uint32_t num;
-	uint16_t was_read = 0;
-
-	ASSERT(descr && buffer && length);
-	ASSERT(descr->channel_max >= channel);
-	data_size = _adc_async_get_data_size(&descr->device);
-	ASSERT(!(length % data_size));
-	(void)data_size;
-
-	index                                         = descr->channel_map[channel];
-	struct adc_async_channel_descriptor *descr_ch = &descr->descr_ch[index];
-
-	CRITICAL_SECTION_ENTER()
-	num = ringbuffer_num(&descr_ch->convert);
-	CRITICAL_SECTION_LEAVE()
-
-	while ((was_read < num) && (was_read < length)) {
-		ringbuffer_get(&descr_ch->convert, &buffer[was_read++]);
-	}
-	descr_ch->bytes_in_buffer -= was_read;
-
-	return was_read;
-}
-
-/**
- * \brief Start conversion
- */
-int32_t adc_async_start_conversion(struct adc_async_descriptor *const descr)
-{
-	ASSERT(descr);
-	_adc_async_convert(&descr->device);
-	return ERR_NONE;
-}
-
-/**
- * \brief Set ADC reference source
- */
-int32_t adc_async_set_reference(struct adc_async_descriptor *const descr, const adc_reference_t reference)
-{
-	ASSERT(descr);
-	_adc_async_set_reference_source(&descr->device, reference);
-	return ERR_NONE;
-}
-
-/**
- * \brief Set ADC resolution
- */
-int32_t adc_async_set_resolution(struct adc_async_descriptor *const descr, const adc_resolution_t resolution)
-{
-	ASSERT(descr);
-	_adc_async_set_resolution(&descr->device, resolution);
-	return ERR_NONE;
-}
-
-/**
- * \brief Set ADC input source for a channel
- */
-int32_t adc_async_set_inputs(struct adc_async_descriptor *const descr, const adc_pos_input_t pos_input,
-                             const adc_neg_input_t neg_input, const uint8_t channel)
-{
-	ASSERT(descr);
-	ASSERT(descr->channel_max >= channel);
-	_adc_async_set_inputs(&descr->device, pos_input, neg_input, channel);
-	return ERR_NONE;
-}
-
-/**
- * \brief Set ADC thresholds
- */
-int32_t adc_async_set_thresholds(struct adc_async_descriptor *const descr, const adc_threshold_t low_threshold,
-                                 const adc_threshold_t up_threshold)
-{
-	ASSERT(descr);
-	_adc_async_set_thresholds(&descr->device, low_threshold, up_threshold);
-	return ERR_NONE;
-}
-
-/**
- * \brief Set ADC gain
- */
-int32_t adc_async_set_channel_gain(struct adc_async_descriptor *const descr, const uint8_t channel,
-                                   const adc_gain_t gain)
-{
-	ASSERT(descr);
-	ASSERT(descr->channel_max >= channel);
-	_adc_async_set_channel_gain(&descr->device, channel, gain);
-	return ERR_NONE;
-}
-
-/**
- * \brief Set ADC conversion mode
- */
-int32_t adc_async_set_conversion_mode(struct adc_async_descriptor *const descr, const enum adc_conversion_mode mode)
-{
-	ASSERT(descr);
-	_adc_async_set_conversion_mode(&descr->device, mode);
-	return ERR_NONE;
-}
-
-/**
- * \brief Set ADC differential mode
- */
-int32_t adc_async_set_channel_differential_mode(struct adc_async_descriptor *const descr, const uint8_t channel,
-                                                const enum adc_differential_mode mode)
-{
-	ASSERT(descr);
-	ASSERT(descr->channel_max >= channel);
-	_adc_async_set_channel_differential_mode(&descr->device, channel, mode);
-	return ERR_NONE;
-}
-
-/**
- * \brief Set ADC window mode
- */
-int32_t adc_async_set_window_mode(struct adc_async_descriptor *const descr, const adc_window_mode_t mode)
-{
-	ASSERT(descr);
-	_adc_async_set_window_mode(&descr->device, mode);
-	return ERR_NONE;
-}
-
-/**
- * \brief Retrieve threshold state
- */
-int32_t adc_async_get_threshold_state(const struct adc_async_descriptor *const descr,
-                                      adc_threshold_status_t *const            state)
-{
-	ASSERT(descr && state);
-	_adc_async_get_threshold_state(&descr->device, state);
-	return ERR_NONE;
-}
-
-/**
- * \brief Check if conversion is complete
- */
-int32_t adc_async_is_channel_conversion_complete(const struct adc_async_descriptor *const descr, const uint8_t channel)
-{
-	ASSERT(descr);
-	ASSERT(descr->channel_max >= channel);
-	return _adc_async_is_channel_conversion_done(&descr->device, channel);
-}
-
-/**
- * \brief flush adc ringbuf
- */
-int32_t adc_async_flush_rx_buffer(struct adc_async_descriptor *const descr, const uint8_t channel)
-{
-	ASSERT(descr);
-	ASSERT(descr->channel_max >= channel);
-
-	uint8_t                              index    = descr->channel_map[channel];
-	struct adc_async_channel_descriptor *descr_ch = &descr->descr_ch[index];
-
-	return ringbuffer_flush(&descr_ch->convert);
-}
-
-/**
- * \brief Retrieve the current driver version
- */
-uint32_t adc_async_get_version(void)
-{
-	return DRIVER_VERSION;
-}
-
-/**
- * \internal Process conversion completion
- *
- * \param[in] device The pointer to ADC device structure
- * \param[in] data Converted data
- */
-static void adc_async_channel_conversion_done(struct _adc_async_device *device, const uint8_t channel,
-                                              const uint16_t data)
-{
-	struct adc_async_descriptor *const descr = CONTAINER_OF(device, struct adc_async_descriptor, device);
-
-	uint8_t                              index    = descr->channel_map[channel];
-	struct adc_async_channel_descriptor *descr_ch = &descr->descr_ch[index];
-
-	ringbuffer_put(&descr_ch->convert, data);
-	if (1 < _adc_async_get_data_size(&descr->device)) {
-		ringbuffer_put(&descr_ch->convert, data >> 8);
-		++descr_ch->bytes_in_buffer;
-	}
-	++descr_ch->bytes_in_buffer;
-
-	if (descr_ch->adc_async_ch_cb.convert_done) {
-		descr_ch->adc_async_ch_cb.convert_done(descr, channel);
-	}
-}
-
-static void adc_async_window_threshold_reached(struct _adc_async_device *device, const uint8_t channel)
-{
-	struct adc_async_descriptor *const descr = CONTAINER_OF(device, struct adc_async_descriptor, device);
-
-	if (descr->adc_async_cb.monitor) {
-		descr->adc_async_cb.monitor(descr, channel);
-	}
-}
-
-static void adc_async_error_occured(struct _adc_async_device *device, const uint8_t channel)
-{
-	struct adc_async_descriptor *const descr = CONTAINER_OF(device, struct adc_async_descriptor, device);
-
-	if (descr->adc_async_cb.error) {
-		descr->adc_async_cb.error(descr, channel);
-	}
-}
-
-//@}
diff --git a/BLDC_E54/BLDC_E54/hal/utils/include/utils_ringbuffer.h b/BLDC_E54/BLDC_E54/hal/utils/include/utils_ringbuffer.h
deleted file mode 100644
index 401d557..0000000
--- a/BLDC_E54/BLDC_E54/hal/utils/include/utils_ringbuffer.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/**
- * \file
- *
- * \brief Ringbuffer declaration.
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-#ifndef _UTILS_RINGBUFFER_H_INCLUDED
-#define _UTILS_RINGBUFFER_H_INCLUDED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \addtogroup doc_driver_hal_utils_ringbuffer
- *
- * @{
- */
-
-#include "compiler.h"
-#include "utils_assert.h"
-
-/**
- * \brief Ring buffer element type
- */
-struct ringbuffer {
-	uint8_t *buf;         /** Buffer base address */
-	uint32_t size;        /** Buffer size */
-	uint32_t read_index;  /** Buffer read index */
-	uint32_t write_index; /** Buffer write index */
-};
-
-/**
- * \brief Ring buffer init
- *
- * \param[in] rb The pointer to a ring buffer structure instance
- * \param[in] buf Space to store the data
- * \param[in] size The buffer length, must be aligned with power of 2
- *
- * \return ERR_NONE on success, or an error code on failure.
- */
-int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size);
-
-/**
- * \brief Get one byte from ring buffer, the user needs to handle the concurrent
- * access on buffer via put/get/flush
- *
- * \param[in] rb The pointer to a ring buffer structure instance
- * \param[in] data One byte space to store the read data
- *
- * \return ERR_NONE on success, or an error code on failure.
- */
-int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data);
-
-/**
- * \brief Put one byte to ring buffer, the user needs to handle the concurrent access
- * on buffer via put/get/flush
- *
- * \param[in] rb The pointer to a ring buffer structure instance
- * \param[in] data One byte data to be put into ring buffer
- *
- * \return ERR_NONE on success, or an error code on failure.
- */
-int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data);
-
-/**
- * \brief Return the element number of ring buffer
- *
- * \param[in] rb The pointer to a ring buffer structure instance
- *
- * \return The number of elements in ring buffer [0, rb->size]
- */
-uint32_t ringbuffer_num(const struct ringbuffer *const rb);
-
-/**
- * \brief Flush ring buffer, the user needs to handle the concurrent access on buffer
- * via put/get/flush
- *
- * \param[in] rb The pointer to a ring buffer structure instance
- *
- * \return ERR_NONE on success, or an error code on failure.
- */
-uint32_t ringbuffer_flush(struct ringbuffer *const rb);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _UTILS_RINGBUFFER_H_INCLUDED */
diff --git a/BLDC_E54/BLDC_E54/hal/utils/src/utils_ringbuffer.c b/BLDC_E54/BLDC_E54/hal/utils/src/utils_ringbuffer.c
deleted file mode 100644
index 45cac83..0000000
--- a/BLDC_E54/BLDC_E54/hal/utils/src/utils_ringbuffer.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/**
- * \file
- *
- * \brief Ringbuffer functionality implementation.
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-#include "utils_ringbuffer.h"
-
-/**
- * \brief Ringbuffer init
- */
-int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size)
-{
-	ASSERT(rb && buf && size);
-
-	/*
-	 * buf size must be aligned to power of 2
-	 */
-	if ((size & (size - 1)) != 0) {
-		return ERR_INVALID_ARG;
-	}
-
-	/* size - 1 is faster in calculation */
-	rb->size        = size - 1;
-	rb->read_index  = 0;
-	rb->write_index = rb->read_index;
-	rb->buf         = (uint8_t *)buf;
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Get one byte from ringbuffer
- *
- */
-int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data)
-{
-	ASSERT(rb && data);
-
-	if (rb->write_index != rb->read_index) {
-		*data = rb->buf[rb->read_index & rb->size];
-		rb->read_index++;
-		return ERR_NONE;
-	}
-
-	return ERR_NOT_FOUND;
-}
-
-/**
- * \brief Put one byte to ringbuffer
- *
- */
-int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data)
-{
-	ASSERT(rb);
-
-	rb->buf[rb->write_index & rb->size] = data;
-
-	/*
-	 * buffer full strategy: new data will overwrite the oldest data in
-	 * the buffer
-	 */
-	if ((rb->write_index - rb->read_index) > rb->size) {
-		rb->read_index = rb->write_index - rb->size;
-	}
-
-	rb->write_index++;
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Return the element number of ringbuffer
- */
-uint32_t ringbuffer_num(const struct ringbuffer *const rb)
-{
-	ASSERT(rb);
-
-	return rb->write_index - rb->read_index;
-}
-
-/**
- * \brief Flush ringbuffer
- */
-uint32_t ringbuffer_flush(struct ringbuffer *const rb)
-{
-	ASSERT(rb);
-
-	rb->read_index = rb->write_index;
-
-	return ERR_NONE;
-}
diff --git a/BLDC_E54/BLDC_E54/hpl/adc/hpl_adc.c b/BLDC_E54/BLDC_E54/hpl/adc/hpl_adc.c
index f3db401..29f7da5 100644
--- a/BLDC_E54/BLDC_E54/hpl/adc/hpl_adc.c
+++ b/BLDC_E54/BLDC_E54/hpl/adc/hpl_adc.c
@@ -108,10 +108,6 @@ static const struct adc_configuration _adcs[] = {
 #endif
 };
 
-static struct _adc_async_device *_adc0_dev = NULL;
-
-static struct _adc_async_device *_adc1_dev = NULL;
-
 static void _adc_set_reference_source(void *const hw, const adc_reference_t reference);
 
 /**
@@ -155,12 +151,6 @@ static uint8_t _adc_get_irq_num(const struct _adc_async_device *const device)
  */
 static void _adc_init_irq_param(const void *const hw, struct _adc_async_device *dev)
 {
-	if (hw == ADC0) {
-		_adc0_dev = dev;
-	}
-	if (hw == ADC1) {
-		_adc1_dev = dev;
-	}
 }
 
 /**
@@ -744,58 +734,6 @@ void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint
 	}
 }
 
-/**
- * \internal ADC interrupt handler
- *
- * \param[in] p The pointer to interrupt parameter
- */
-static void _adc_interrupt_handler(struct _adc_async_device *device)
-{
-	void *const hw      = device->hw;
-	uint8_t     intflag = hri_adc_read_INTFLAG_reg(hw);
-	intflag &= hri_adc_read_INTEN_reg(hw);
-	if (intflag & ADC_INTFLAG_RESRDY) {
-		hri_adc_clear_interrupt_RESRDY_bit(hw);
-		device->adc_async_ch_cb.convert_done(device, 0, hri_adc_read_RESULT_reg(hw));
-	} else if (intflag & ADC_INTFLAG_OVERRUN) {
-		hri_adc_clear_interrupt_OVERRUN_bit(hw);
-		device->adc_async_cb.error_cb(device, 0);
-	} else if (intflag & ADC_INTFLAG_WINMON) {
-		hri_adc_clear_interrupt_WINMON_bit(hw);
-		device->adc_async_cb.window_cb(device, 0);
-	}
-}
-
-/**
- * \brief DMAC interrupt handler
- */
-void ADC0_0_Handler(void)
-{
-	_adc_interrupt_handler(_adc0_dev);
-}
-/**
- * \brief DMAC interrupt handler
- */
-void ADC0_1_Handler(void)
-{
-	_adc_interrupt_handler(_adc0_dev);
-}
-
-/**
- * \brief DMAC interrupt handler
- */
-void ADC1_0_Handler(void)
-{
-	_adc_interrupt_handler(_adc1_dev);
-}
-/**
- * \brief DMAC interrupt handler
- */
-void ADC1_1_Handler(void)
-{
-	_adc_interrupt_handler(_adc1_dev);
-}
-
 /**
  * \brief Retrieve ADC sync helper functions
  */
diff --git a/BLDC_E54/BLDC_E54/hpl/dmac/hpl_dmac.c b/BLDC_E54/BLDC_E54/hpl/dmac/hpl_dmac.c
index 8313c71..fc3b059 100644
--- a/BLDC_E54/BLDC_E54/hpl/dmac/hpl_dmac.c
+++ b/BLDC_E54/BLDC_E54/hpl/dmac/hpl_dmac.c
@@ -49,7 +49,7 @@ DmacDescriptor _write_back_section[DMAC_CH_NUM];
 static struct _dma_resource _resources[DMAC_CH_NUM];
 
 /* DMAC interrupt handler */
-static void _dmac_handler(void);
+static void _dmac_handler(uint8_t);
 
 /* This macro DMAC configuration */
 #define DMAC_CHANNEL_CFG(i, n)                                                                                         \
@@ -130,7 +130,7 @@ void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type typ
 		hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, channel, state);
 	} else if (DMA_TRANSFER_ERROR_CB == type) {
 		hri_dmac_write_CHINTEN_TERR_bit(DMAC, channel, state);
-	} else if (DMA_TRANSFER_SUSPEND_CB == type) {
+	} else if (DMA_SUSPEND_CB == type) {
 		hri_dmac_write_CHINTEN_SUSP_bit(DMAC, channel, state);
 	}
 }
@@ -220,20 +220,25 @@ int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable)
 /**
  * \internal DMAC interrupt handler
  */
-static void _dmac_handler(void)
+static void _dmac_handler(uint8_t channel)
 {
-	uint8_t               channel      = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk);
+	//uint8_t               channel      = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk);
 	struct _dma_resource *tmp_resource = &_resources[channel];
 
-	if (hri_dmac_get_INTPEND_TERR_bit(DMAC)) {
+	if (hri_dmac_get_INTPEND_TERR_bit(DMAC)|hri_dmac_get_CHINTEN_TERR_bit(DMAC,channel)) {
 		hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel);
 		tmp_resource->dma_cb.error(tmp_resource);
-	} else if (hri_dmac_get_INTPEND_TCMPL_bit(DMAC)) {
+	} else if (hri_dmac_get_INTPEND_TCMPL_bit(DMAC)|hri_dmac_get_CHINTEN_TCMPL_bit(DMAC,channel)) {
 		hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC, channel);
 		tmp_resource->dma_cb.transfer_done(tmp_resource);
-	} else if  (hri_dmac_get_INTPEND_SUSP_bit(DMAC)) {
+	} else if  (hri_dmac_get_INTPEND_SUSP_bit(DMAC)|hri_dmac_get_CHINTEN_SUSP_bit(DMAC,channel)) {
 		hri_dmac_clear_CHINTFLAG_SUSP_bit(DMAC, channel);
+		if(channel == 3)
+		{
+			volatile int i = 0;
+		}
 		tmp_resource->dma_cb.suspend(tmp_resource);
+		
 	}
 }
 /**
@@ -241,7 +246,7 @@ static void _dmac_handler(void)
  */
 void DMAC_0_Handler(void)
 {
-	_dmac_handler();
+	_dmac_handler(0);
 	
 	
 }
@@ -250,26 +255,26 @@ void DMAC_0_Handler(void)
  */
 void DMAC_1_Handler(void)
 {
-	_dmac_handler();
+	_dmac_handler(1);
 }
 /**
  * \brief DMAC interrupt handler
  */
 void DMAC_2_Handler(void)
 {
-	_dmac_handler();
+	_dmac_handler(2);
 }
 /**
  * \brief DMAC interrupt handler
  */
 void DMAC_3_Handler(void)
 {
-	_dmac_handler();
+	_dmac_handler(3);
 }
 /**
  * \brief DMAC interrupt handler
  */
 void DMAC_4_Handler(void)
 {
-	_dmac_handler();
+	_dmac_handler(4);
 }
diff --git a/BLDC_E54/BLDC_E54/hpl/doc_lite/tcc.rst b/BLDC_E54/BLDC_E54/hpl/doc_lite/tcc.rst
deleted file mode 100644
index 8007421..0000000
--- a/BLDC_E54/BLDC_E54/hpl/doc_lite/tcc.rst
+++ /dev/null
@@ -1,38 +0,0 @@
-==========
-TCC driver
-==========
-The TCC consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to count events, or it can be configured to count clock pulses. The counter, together with the compare/capture channels, can be configured to time stamp input events, allowing capture of frequency and pulse width. It can also perform waveform generation, such as frequency generation and pulse-width modulation (PWM) 
-
-The timer/counter is clocked by the peripheral clock with optional prescaling or from the event system.
-
-Features
---------
-* Initialization
-
-Applications
-------------
-* Frequency Generation
-* Single-slope PWM (pulse width modulation)
-* Dual-slope PWM
-* Count on event
-* Quadrature decoding
-
-Dependencies
-------------
-* CLK for clock
-* CPUINT/PMIC for Interrupt
-* EVSYS for events
-* UPDI/PDI/JTAG for debug
-* PORT for Waveform Generation
-
-Concurrency
------------
-N/A
-
-Limitations
------------
-N/A
-
-Knows issues and workarounds
-----------------------------
-N/A
diff --git a/BLDC_E54/BLDC_E54/hpl/sercom/hpl_sercom.c b/BLDC_E54/BLDC_E54/hpl/sercom/hpl_sercom.c
index 694a464..748ec86 100644
--- a/BLDC_E54/BLDC_E54/hpl/sercom/hpl_sercom.c
+++ b/BLDC_E54/BLDC_E54/hpl/sercom/hpl_sercom.c
@@ -3361,7 +3361,7 @@ void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_
 		break;
 	case SPI_DEV_CB_DMA_SUSPEND:
 		dev->callbacks.suspend = func;
-		_dma_set_irq_state(_spi_get_rx_dma_channel(dev->prvt), DMA_TRANSFER_SUSPEND_CB, func != NULL);
+		_dma_set_irq_state(_spi_get_rx_dma_channel(dev->prvt), DMA_SUSPEND_CB, func != NULL);
 		break;
 	break;
 		
diff --git a/BLDC_E54/BLDC_E54/hpl/tcc/tcc_lite.c b/BLDC_E54/BLDC_E54/hpl/tcc/tcc_lite.c
deleted file mode 100644
index b12cf80..0000000
--- a/BLDC_E54/BLDC_E54/hpl/tcc/tcc_lite.c
+++ /dev/null
@@ -1,380 +0,0 @@
-
-/**
- * \file
- *
- * \brief TCC related functionality implementation.
- *
- * Copyright (c) 2017 - 2019 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#include "tcc_lite.h"
-
-/**
- * \brief Initialize TCC interface
- */
-int8_t TCC_PWM2_init()
-{
-
-	if (!hri_tcc_is_syncing(TCC0, TCC_SYNCBUSY_SWRST)) {
-		if (hri_tcc_get_CTRLA_reg(TCC0, TCC_CTRLA_ENABLE)) {
-			hri_tcc_clear_CTRLA_ENABLE_bit(TCC0);
-			hri_tcc_wait_for_sync(TCC0, TCC_SYNCBUSY_ENABLE);
-		}
-		hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_SWRST);
-	}
-	hri_tcc_wait_for_sync(TCC0, TCC_SYNCBUSY_SWRST);
-
-	hri_tcc_write_CTRLA_reg(TCC0,
-	                        0 << TCC_CTRLA_ALOCK_Pos             /* Auto Lock: disabled */
-	                            | 0 << TCC_CTRLA_PRESCSYNC_Pos   /* Prescaler and Counter Synchronization: 0 */
-	                            | 0 << TCC_CTRLA_RUNSTDBY_Pos    /* Run in Standby: disabled */
-	                            | 1 << TCC_CTRLA_PRESCALER_Pos); /* Setting: 1 */
-
-	// hri_tcc_write_CTRLB_reg(TCC0,0 << TCC_CTRLBSET_CMD_Pos /* TCC Command: 0 */
-	//		 | 0 << TCC_CTRLBSET_IDXCMD_Pos /* Ramp Index Command: 0 */
-	//		 | 0 << TCC_CTRLBSET_ONESHOT_Pos /* One-Shot: disabled */
-	//		 | 0 << TCC_CTRLBSET_LUPD_Pos /* Lock Update: disabled */
-	//		 | 0 << TCC_CTRLBSET_DIR_Pos); /* Counter Direction: disabled */
-
-	// hri_tcc_write_FCTRLA_reg(TCC0,0x0 << TCC_FCTRLA_FILTERVAL_Pos /* Fault A Filter Value: 0x0 */
-	//		 | 0 << TCC_FCTRLA_CHSEL_Pos /* Fault A Capture Channel: 0 */
-	//		 | 0 << TCC_FCTRLA_HALT_Pos /* Fault A Halt Mode: 0 */
-	//		 | 0 << TCC_FCTRLA_RESTART_Pos /* Fault A Restart: disabled */
-	//		 | 0 << TCC_FCTRLA_BLANK_Pos /* Fault A Blanking Mode: 0 */
-	//		 | 0 << TCC_FCTRLA_QUAL_Pos /* Fault A Qualification: disabled */
-	//		 | 0 << TCC_FCTRLA_KEEP_Pos /* Fault A Keeper: disabled */
-	//		 | 0); /* Fault A Source: 0 */
-
-	// hri_tcc_write_FCTRLB_reg(TCC0,0x0 << TCC_FCTRLB_FILTERVAL_Pos /* Fault B Filter Value: 0x0 */
-	//		 | 0 << TCC_FCTRLB_CHSEL_Pos /* Fault B Capture Channel: 0 */
-	//		 | 0 << TCC_FCTRLB_HALT_Pos /* Fault B Halt Mode: 0 */
-	//		 | 0 << TCC_FCTRLB_RESTART_Pos /* Fault B Restart: disabled */
-	//		 | 0 << TCC_FCTRLB_BLANK_Pos /* Fault B Blanking Mode: 0 */
-	//		 | 0 << TCC_FCTRLB_QUAL_Pos /* Fault B Qualification: disabled */
-	//		 | 0 << TCC_FCTRLB_KEEP_Pos /* Fault B Keeper: disabled */
-	//		 | 0); /* Fault B Source: 0 */
-
-	// hri_tcc_write_DRVCTRL_reg(TCC0,0x0 << TCC_DRVCTRL_FILTERVAL1_Pos /* Non-Recoverable Fault Input 1 Filter Value:
-	// 0x0 */
-	//		 | 0x0 << TCC_DRVCTRL_FILTERVAL0_Pos /* Non-Recoverable Fault Input 0 Filter Value: 0x0 */
-	//		 | 0 << TCC_DRVCTRL_INVEN7_Pos /*  Output Waveform 7 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_INVEN6_Pos /*  Output Waveform 6 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_INVEN5_Pos /*  Output Waveform 5 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_INVEN4_Pos /*  Output Waveform 4 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_INVEN3_Pos /*  Output Waveform 3 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_INVEN2_Pos /*  Output Waveform 2 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_INVEN1_Pos /*  Output Waveform 1 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_INVEN0_Pos /*  Output Waveform 0 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV7_Pos /* Non-Recoverable State 7 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV6_Pos /* Non-Recoverable State 6 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV5_Pos /* Non-Recoverable State 5 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV4_Pos /* Non-Recoverable State 4 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV3_Pos /* Non-Recoverable State 3 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV2_Pos /* Non-Recoverable State 2 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV1_Pos /* Non-Recoverable State 1 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV0_Pos /* Non-Recoverable State 0 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE7_Pos /* Non-Recoverable State 7 Output Enable: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE6_Pos /* Non-Recoverable State 6 Output Enable: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE5_Pos /* Non-Recoverable State 5 Output Enable: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE4_Pos /* Non-Recoverable State 4 Output Enable: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE3_Pos /* Non-Recoverable State 3 Output Enable: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE2_Pos /* Non-Recoverable State 2 Output Enable: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE1_Pos /* Non-Recoverable State 1 Output Enable: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE0_Pos); /* Non-Recoverable State 0 Output Enable: disabled */
-
-	// hri_tcc_write_DBGCTRL_reg(TCC0,0 << TCC_DBGCTRL_FDDBD_Pos /* Fault Detection on Debug Break Detection: disabled
-	// */
-	//		 | 0); /* Run in debug: 0 */
-
-	// hri_tcc_write_CC_reg(TCC0, 0 ,0x0); /* Channel 0 Compare/Capture Value: 0x0 */
-
-	// hri_tcc_write_CC_reg(TCC0, 1 ,0x0); /* Channel 1 Compare/Capture Value: 0x0 */
-
-	// hri_tcc_write_CC_reg(TCC0, 2 ,0x0); /* Channel 2 Compare/Capture Value: 0x0 */
-
-	// hri_tcc_write_CC_reg(TCC0, 3 ,0x0); /* Channel 3 Compare/Capture Value: 0x0 */
-
-	// hri_tcc_write_CC_reg(TCC0, 4 ,0x0); /* Channel 4 Compare/Capture Value: 0x0 */
-
-	// hri_tcc_write_CC_reg(TCC0, 5 ,0x0); /* Channel 5 Compare/Capture Value: 0x0 */
-
-	// hri_tcc_write_WEXCTRL_reg(TCC0,0x0 << TCC_WEXCTRL_DTHS_Pos /* Dead-time High Side Outputs Value: 0x0 */
-	//		 | 0x0 << TCC_WEXCTRL_DTLS_Pos /* Dead-time Low Side Outputs Value: 0x0 */
-	//		 | 0 << TCC_WEXCTRL_DTIEN3_Pos /* Dead-time Insertion Generator 3 Enable: 0 */
-	//		 | 0 << TCC_WEXCTRL_DTIEN2_Pos /* Dead-time Insertion Generator 2 Enable: 0 */
-	//		 | 0 << TCC_WEXCTRL_DTIEN1_Pos /* Dead-time Insertion Generator 1 Enable: 0 */
-	//		 | 0 << TCC_WEXCTRL_DTIEN0_Pos /* Dead-time Insertion Generator 0 Enable: 0 */
-	//		 | 0x0); /* Output Matrix: 0x0 */
-
-	hri_tcc_write_WAVE_reg(TCC0,
-	                       0 << TCC_WAVE_SWAP3_Pos         /* Swap DTI Output Pair 3: disabled */
-	                           | 0 << TCC_WAVE_SWAP2_Pos   /* Swap DTI Output Pair 2: disabled */
-	                           | 0 << TCC_WAVE_SWAP1_Pos   /* Swap DTI Output Pair 1: disabled */
-	                           | 0 << TCC_WAVE_SWAP0_Pos   /* Swap DTI Output Pair 0: disabled */
-	                           | 0 << TCC_WAVE_CICCEN3_Pos /*  Circular Channel 3 Enable: disabled */
-	                           | 0 << TCC_WAVE_CICCEN2_Pos /*  Circular Channel 2 Enable: disabled */
-	                           | 0 << TCC_WAVE_CICCEN1_Pos /*  Circular Channel 1 Enable: disabled */
-	                           | 0 << TCC_WAVE_CICCEN0_Pos /*  Circular Channel 0 Enable: disabled */
-	                           | 1 << TCC_WAVE_POL5_Pos    /* Channel 5 Polarity: enabled */
-	                           | 1 << TCC_WAVE_POL4_Pos    /* Channel 4 Polarity: enabled */
-	                           | 1 << TCC_WAVE_POL3_Pos    /* Channel 3 Polarity: enabled */
-	                           | 1 << TCC_WAVE_POL2_Pos    /* Channel 2 Polarity: enabled */
-	                           | 1 << TCC_WAVE_POL1_Pos    /* Channel 1 Polarity: enabled */
-	                           | 1 << TCC_WAVE_POL0_Pos    /* Channel 0 Polarity: enabled */
-	                           | 0 << TCC_WAVE_CIPEREN_Pos /* Circular period Enable: disabled */
-	                           | 0 << TCC_WAVE_RAMP_Pos    /* Ramp Mode: 0 */
-	                           | 5);                       /* Waveform Generation: 5 */
-
-	// hri_tcc_write_PATT_reg(TCC0,0 << TCC_PATT_PGV3_Pos /* Pattern Generator 3 Output Value: disabled */
-	//		 | 0 << TCC_PATT_PGV2_Pos /* Pattern Generator 2 Output Value: disabled */
-	//		 | 0 << TCC_PATT_PGV1_Pos /* Pattern Generator 1 Output Value: disabled */
-	//		 | 0 << TCC_PATT_PGV0_Pos /* Pattern Generator 0 Output Value: disabled */
-	//		 | 0 << TCC_PATT_PGE3_Pos /* Pattern Generator 3 Output Enable: disabled */
-	//		 | 0 << TCC_PATT_PGE2_Pos /* Pattern Generator 2 Output Enable: disabled */
-	//		 | 0 << TCC_PATT_PGE1_Pos /* Pattern Generator 1 Output Enable: disabled */
-	//		 | 0 << TCC_PATT_PGE0_Pos); /* Pattern Generator 0 Output Enable: disabled */
-
-	hri_tcc_write_PER_reg(TCC0, 0x3e8); /*  Period Value: 0x3e8 */
-
-	hri_tcc_write_EVCTRL_reg(
-	    TCC0,
-	    0 << TCC_EVCTRL_MCEO5_Pos        /* Match or Capture Channel 5 Event Output Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEO4_Pos  /* Match or Capture Channel 4 Event Output Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEO3_Pos  /* Match or Capture Channel 3 Event Output Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEO2_Pos  /* Match or Capture Channel 2 Event Output Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEO1_Pos  /* Match or Capture Channel 1 Event Output Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEO0_Pos  /* Match or Capture Channel 0 Event Output Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEI5_Pos  /* Match or Capture Channel 5 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEI4_Pos  /* Match or Capture Channel 4 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEI3_Pos  /* Match or Capture Channel 3 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEI2_Pos  /* Match or Capture Channel 2 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEI1_Pos  /* Match or Capture Channel 1 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEI0_Pos  /* Match or Capture Channel 0 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_TCEI1_Pos  /* Timer/counter 1 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_TCEI0_Pos  /* Timer/counter 0 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_TCINV1_Pos /* Inverted Event 1 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_TCINV0_Pos /* Inverted Event 0 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_CNTEO_Pos  /* Timer/counter Output Event Enable: disabled */
-	        | 0 << TCC_EVCTRL_TRGEO_Pos  /* Retrigger Output Event Enable: disabled */
-	        | 1 << TCC_EVCTRL_OVFEO_Pos  /* Overflow/Underflow Event Output Enable: enabled */
-	        | 0 << TCC_EVCTRL_CNTSEL_Pos /* Timer/counter Output Event Mode: 0 */
-	        | 0 << TCC_EVCTRL_EVACT1_Pos /* Event 1 Action: 0 */
-	        | 0);                        /* Event 0 Action: 0 */
-
-	// hri_tcc_write_INTEN_reg(TCC0,0 << TCC_INTENSET_MC5_Pos /* Match or Capture Channel 5 Interrupt Enable: disabled
-	// */
-	//		 | 0 << TCC_INTENSET_MC4_Pos /* Match or Capture Channel 4 Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_MC3_Pos /* Match or Capture Channel 3 Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_MC2_Pos /* Match or Capture Channel 2 Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_MC1_Pos /* Match or Capture Channel 1 Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_MC0_Pos /* Match or Capture Channel 0 Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_FAULT1_Pos /* Non-Recoverable Fault 1 Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_FAULT0_Pos /* Non-Recoverable Fault 0 Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_FAULTB_Pos /* Recoverable Fault B Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_FAULTA_Pos /* Recoverable Fault A Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_DFS_Pos /* Non-Recoverable Debug Fault Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_ERR_Pos /* Error Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_CNT_Pos /* Counter Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_TRG_Pos /* Retrigger Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: disabled */
-
-	hri_tcc_write_CTRLA_ENABLE_bit(TCC0, 1 << TCC_CTRLA_ENABLE_Pos); /* Enable: enabled */
-
-	return 0;
-}
-
-/**
- * \brief Initialize TCC interface
- */
-int8_t TCC_PWM_init()
-{
-
-	if (!hri_tcc_is_syncing(TCC1, TCC_SYNCBUSY_SWRST)) {
-		if (hri_tcc_get_CTRLA_reg(TCC1, TCC_CTRLA_ENABLE)) {
-			hri_tcc_clear_CTRLA_ENABLE_bit(TCC1);
-			hri_tcc_wait_for_sync(TCC1, TCC_SYNCBUSY_ENABLE);
-		}
-		hri_tcc_write_CTRLA_reg(TCC1, TCC_CTRLA_SWRST);
-	}
-	hri_tcc_wait_for_sync(TCC1, TCC_SYNCBUSY_SWRST);
-
-	hri_tcc_write_CTRLA_reg(TCC1,
-	                        0 << TCC_CTRLA_ALOCK_Pos             /* Auto Lock: disabled */
-	                            | 0 << TCC_CTRLA_PRESCSYNC_Pos   /* Prescaler and Counter Synchronization: 0 */
-	                            | 0 << TCC_CTRLA_RUNSTDBY_Pos    /* Run in Standby: disabled */
-	                            | 1 << TCC_CTRLA_PRESCALER_Pos); /* Setting: 1 */
-
-	// hri_tcc_write_CTRLB_reg(TCC1,0 << TCC_CTRLBSET_CMD_Pos /* TCC Command: 0 */
-	//		 | 0 << TCC_CTRLBSET_IDXCMD_Pos /* Ramp Index Command: 0 */
-	//		 | 0 << TCC_CTRLBSET_ONESHOT_Pos /* One-Shot: disabled */
-	//		 | 0 << TCC_CTRLBSET_LUPD_Pos /* Lock Update: disabled */
-	//		 | 0 << TCC_CTRLBSET_DIR_Pos); /* Counter Direction: disabled */
-
-	// hri_tcc_write_FCTRLA_reg(TCC1,0x0 << TCC_FCTRLA_FILTERVAL_Pos /* Fault A Filter Value: 0x0 */
-	//		 | 0 << TCC_FCTRLA_CHSEL_Pos /* Fault A Capture Channel: 0 */
-	//		 | 0 << TCC_FCTRLA_HALT_Pos /* Fault A Halt Mode: 0 */
-	//		 | 0 << TCC_FCTRLA_RESTART_Pos /* Fault A Restart: disabled */
-	//		 | 0 << TCC_FCTRLA_BLANK_Pos /* Fault A Blanking Mode: 0 */
-	//		 | 0 << TCC_FCTRLA_QUAL_Pos /* Fault A Qualification: disabled */
-	//		 | 0 << TCC_FCTRLA_KEEP_Pos /* Fault A Keeper: disabled */
-	//		 | 0); /* Fault A Source: 0 */
-
-	// hri_tcc_write_FCTRLB_reg(TCC1,0x0 << TCC_FCTRLB_FILTERVAL_Pos /* Fault B Filter Value: 0x0 */
-	//		 | 0 << TCC_FCTRLB_CHSEL_Pos /* Fault B Capture Channel: 0 */
-	//		 | 0 << TCC_FCTRLB_HALT_Pos /* Fault B Halt Mode: 0 */
-	//		 | 0 << TCC_FCTRLB_RESTART_Pos /* Fault B Restart: disabled */
-	//		 | 0 << TCC_FCTRLB_BLANK_Pos /* Fault B Blanking Mode: 0 */
-	//		 | 0 << TCC_FCTRLB_QUAL_Pos /* Fault B Qualification: disabled */
-	//		 | 0 << TCC_FCTRLB_KEEP_Pos /* Fault B Keeper: disabled */
-	//		 | 0); /* Fault B Source: 0 */
-
-	// hri_tcc_write_DRVCTRL_reg(TCC1,0x0 << TCC_DRVCTRL_FILTERVAL1_Pos /* Non-Recoverable Fault Input 1 Filter Value:
-	// 0x0 */
-	//		 | 0x0 << TCC_DRVCTRL_FILTERVAL0_Pos /* Non-Recoverable Fault Input 0 Filter Value: 0x0 */
-	//		 | 0 << TCC_DRVCTRL_INVEN7_Pos /*  Output Waveform 7 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_INVEN6_Pos /*  Output Waveform 6 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_INVEN5_Pos /*  Output Waveform 5 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_INVEN4_Pos /*  Output Waveform 4 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_INVEN3_Pos /*  Output Waveform 3 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_INVEN2_Pos /*  Output Waveform 2 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_INVEN1_Pos /*  Output Waveform 1 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_INVEN0_Pos /*  Output Waveform 0 Inversion: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV7_Pos /* Non-Recoverable State 7 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV6_Pos /* Non-Recoverable State 6 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV5_Pos /* Non-Recoverable State 5 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV4_Pos /* Non-Recoverable State 4 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV3_Pos /* Non-Recoverable State 3 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV2_Pos /* Non-Recoverable State 2 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV1_Pos /* Non-Recoverable State 1 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRV0_Pos /* Non-Recoverable State 0 Output Value: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE7_Pos /* Non-Recoverable State 7 Output Enable: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE6_Pos /* Non-Recoverable State 6 Output Enable: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE5_Pos /* Non-Recoverable State 5 Output Enable: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE4_Pos /* Non-Recoverable State 4 Output Enable: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE3_Pos /* Non-Recoverable State 3 Output Enable: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE2_Pos /* Non-Recoverable State 2 Output Enable: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE1_Pos /* Non-Recoverable State 1 Output Enable: disabled */
-	//		 | 0 << TCC_DRVCTRL_NRE0_Pos); /* Non-Recoverable State 0 Output Enable: disabled */
-
-	// hri_tcc_write_DBGCTRL_reg(TCC1,0 << TCC_DBGCTRL_FDDBD_Pos /* Fault Detection on Debug Break Detection: disabled
-	// */
-	//		 | 0); /* Run in debug: 0 */
-
-	// hri_tcc_write_CC_reg(TCC1, 0 ,0x0); /* Channel 0 Compare/Capture Value: 0x0 */
-
-	// hri_tcc_write_CC_reg(TCC1, 1 ,0x0); /* Channel 1 Compare/Capture Value: 0x0 */
-
-	// hri_tcc_write_CC_reg(TCC1, 2 ,0x0); /* Channel 2 Compare/Capture Value: 0x0 */
-
-	// hri_tcc_write_CC_reg(TCC1, 3 ,0x0); /* Channel 3 Compare/Capture Value: 0x0 */
-
-	hri_tcc_write_WEXCTRL_reg(TCC1,
-	                          0x0 << TCC_WEXCTRL_DTHS_Pos       /* Dead-time High Side Outputs Value: 0x0 */
-	                              | 0x0 << TCC_WEXCTRL_DTLS_Pos /* Dead-time Low Side Outputs Value: 0x0 */
-	                              | 0 << TCC_WEXCTRL_DTIEN3_Pos /* Dead-time Insertion Generator 3 Enable: 0 */
-	                              | 0 << TCC_WEXCTRL_DTIEN2_Pos /* Dead-time Insertion Generator 2 Enable: 0 */
-	                              | 0 << TCC_WEXCTRL_DTIEN1_Pos /* Dead-time Insertion Generator 1 Enable: 0 */
-	                              | 0 << TCC_WEXCTRL_DTIEN0_Pos /* Dead-time Insertion Generator 0 Enable: 0 */
-	                              | 0x3);                       /* Output Matrix: 0x3 */
-
-	hri_tcc_write_WAVE_reg(TCC1,
-	                       0 << TCC_WAVE_SWAP3_Pos         /* Swap DTI Output Pair 3: disabled */
-	                           | 0 << TCC_WAVE_SWAP2_Pos   /* Swap DTI Output Pair 2: disabled */
-	                           | 0 << TCC_WAVE_SWAP1_Pos   /* Swap DTI Output Pair 1: disabled */
-	                           | 0 << TCC_WAVE_SWAP0_Pos   /* Swap DTI Output Pair 0: disabled */
-	                           | 0 << TCC_WAVE_CICCEN3_Pos /*  Circular Channel 3 Enable: disabled */
-	                           | 0 << TCC_WAVE_CICCEN2_Pos /*  Circular Channel 2 Enable: disabled */
-	                           | 0 << TCC_WAVE_CICCEN1_Pos /*  Circular Channel 1 Enable: disabled */
-	                           | 0 << TCC_WAVE_CICCEN0_Pos /*  Circular Channel 0 Enable: disabled */
-	                           | 0 << TCC_WAVE_POL5_Pos    /* Channel 5 Polarity: disabled */
-	                           | 0 << TCC_WAVE_POL4_Pos    /* Channel 4 Polarity: disabled */
-	                           | 1 << TCC_WAVE_POL3_Pos    /* Channel 3 Polarity: enabled */
-	                           | 1 << TCC_WAVE_POL2_Pos    /* Channel 2 Polarity: enabled */
-	                           | 1 << TCC_WAVE_POL1_Pos    /* Channel 1 Polarity: enabled */
-	                           | 1 << TCC_WAVE_POL0_Pos    /* Channel 0 Polarity: enabled */
-	                           | 0 << TCC_WAVE_CIPEREN_Pos /* Circular period Enable: disabled */
-	                           | 0 << TCC_WAVE_RAMP_Pos    /* Ramp Mode: 0 */
-	                           | 5);                       /* Waveform Generation: 5 */
-
-	// hri_tcc_write_PATT_reg(TCC1,0 << TCC_PATT_PGV3_Pos /* Pattern Generator 3 Output Value: disabled */
-	//		 | 0 << TCC_PATT_PGV2_Pos /* Pattern Generator 2 Output Value: disabled */
-	//		 | 0 << TCC_PATT_PGV1_Pos /* Pattern Generator 1 Output Value: disabled */
-	//		 | 0 << TCC_PATT_PGV0_Pos /* Pattern Generator 0 Output Value: disabled */
-	//		 | 0 << TCC_PATT_PGE3_Pos /* Pattern Generator 3 Output Enable: disabled */
-	//		 | 0 << TCC_PATT_PGE2_Pos /* Pattern Generator 2 Output Enable: disabled */
-	//		 | 0 << TCC_PATT_PGE1_Pos /* Pattern Generator 1 Output Enable: disabled */
-	//		 | 0 << TCC_PATT_PGE0_Pos); /* Pattern Generator 0 Output Enable: disabled */
-
-	hri_tcc_write_PER_reg(TCC1, 0x3e8); /*  Period Value: 0x3e8 */
-
-	hri_tcc_write_EVCTRL_reg(
-	    TCC1,
-	    0 << TCC_EVCTRL_MCEO5_Pos        /* Match or Capture Channel 5 Event Output Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEO4_Pos  /* Match or Capture Channel 4 Event Output Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEO3_Pos  /* Match or Capture Channel 3 Event Output Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEO2_Pos  /* Match or Capture Channel 2 Event Output Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEO1_Pos  /* Match or Capture Channel 1 Event Output Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEO0_Pos  /* Match or Capture Channel 0 Event Output Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEI5_Pos  /* Match or Capture Channel 5 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEI4_Pos  /* Match or Capture Channel 4 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEI3_Pos  /* Match or Capture Channel 3 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEI2_Pos  /* Match or Capture Channel 2 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEI1_Pos  /* Match or Capture Channel 1 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_MCEI0_Pos  /* Match or Capture Channel 0 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_TCEI1_Pos  /* Timer/counter 1 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_TCEI0_Pos  /* Timer/counter 0 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_TCINV1_Pos /* Inverted Event 1 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_TCINV0_Pos /* Inverted Event 0 Event Input Enable: disabled */
-	        | 0 << TCC_EVCTRL_CNTEO_Pos  /* Timer/counter Output Event Enable: disabled */
-	        | 0 << TCC_EVCTRL_TRGEO_Pos  /* Retrigger Output Event Enable: disabled */
-	        | 1 << TCC_EVCTRL_OVFEO_Pos  /* Overflow/Underflow Event Output Enable: enabled */
-	        | 0 << TCC_EVCTRL_CNTSEL_Pos /* Timer/counter Output Event Mode: 0 */
-	        | 0 << TCC_EVCTRL_EVACT1_Pos /* Event 1 Action: 0 */
-	        | 0);                        /* Event 0 Action: 0 */
-
-	// hri_tcc_write_INTEN_reg(TCC1,0 << TCC_INTENSET_MC5_Pos /* Match or Capture Channel 5 Interrupt Enable: disabled
-	// */
-	//		 | 0 << TCC_INTENSET_MC4_Pos /* Match or Capture Channel 4 Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_MC3_Pos /* Match or Capture Channel 3 Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_MC2_Pos /* Match or Capture Channel 2 Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_MC1_Pos /* Match or Capture Channel 1 Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_MC0_Pos /* Match or Capture Channel 0 Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_FAULT1_Pos /* Non-Recoverable Fault 1 Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_FAULT0_Pos /* Non-Recoverable Fault 0 Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_FAULTB_Pos /* Recoverable Fault B Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_FAULTA_Pos /* Recoverable Fault A Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_DFS_Pos /* Non-Recoverable Debug Fault Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_ERR_Pos /* Error Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_CNT_Pos /* Counter Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_TRG_Pos /* Retrigger Interrupt Enable: disabled */
-	//		 | 0 << TCC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: disabled */
-
-	hri_tcc_write_CTRLA_ENABLE_bit(TCC1, 1 << TCC_CTRLA_ENABLE_Pos); /* Enable: enabled */
-
-	return 0;
-}
diff --git a/BLDC_E54/BLDC_E54/hpl/tcc/tcc_lite.h b/BLDC_E54/BLDC_E54/hpl/tcc/tcc_lite.h
deleted file mode 100644
index 67c888b..0000000
--- a/BLDC_E54/BLDC_E54/hpl/tcc/tcc_lite.h
+++ /dev/null
@@ -1,70 +0,0 @@
-
-/**
- * \file
- *
- * \brief TCC related functionality declaration.
- *
- * Copyright (c) 2017 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _TCC_H_INCLUDED
-#define _TCC_H_INCLUDED
-
-#include <compiler.h>
-#include <utils_assert.h>
-
-/**
- * \addtogroup tcc driver
- *
- * \section tcc Revision History
- * - v0.0.0.1 Initial Commit
- *
- *@{
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief Initialize tcc interface
- * \return Initialization status.
- */
-int8_t TCC_PWM2_init();
-
-/**
- * \brief Initialize tcc interface
- * \return Initialization status.
- */
-int8_t TCC_PWM_init();
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _TCC_H_INCLUDED */
diff --git a/BLDC_E54/BLDC_E54/interrupt_handlers.h b/BLDC_E54/BLDC_E54/interrupt_handlers.h
index 42f634c..6bdcd1e 100644
--- a/BLDC_E54/BLDC_E54/interrupt_handlers.h
+++ b/BLDC_E54/BLDC_E54/interrupt_handlers.h
@@ -30,12 +30,13 @@ void TC7_Handler(void)
 		//One_ms_cycle_callback();
 		//gpio_toggle_pin_level(DEBUG_1);
 		One_ms_cycle_callback();
-
+		Motor1.timerflags.motor_telemetry_flag = true;
+		
 	}
 }
 
 // ----------------------------------------------------------------------
-// 	EtherCAT Cycle Timer - 1kHz
+//
 // ----------------------------------------------------------------------
 void TC0_Handler(void)
 {
@@ -58,35 +59,35 @@ void TC0_Handler(void)
 // 	ADC Callback for Motor Phase Current Measurement.  
 // Phase A & B Sampled and converted from LSB to Process Unit PU(Amps)
 // ----------------------------------------------------------------------
-static void adc_cb(const struct adc_async_descriptor *const descr, const uint8_t channel)
-{
-	tic_port(DEBUG_2_PORT);
-	//tic(DEBUG_1);
-	// Filter Out low level noise
-	inline void filter_convert_to_pu(int16_t *phase, float32_t *phase_filtered_pu)
-	{
-		/*
-		if(*phase <= 20 && *phase >= -20 ) *phase_filtered_pu = 0.0f;
-		else(*phase_filtered_pu = (float32_t)(*phase * ADC_LSB_SIZE * ONEON_CURRENT_SENSOR_SENSITIVITY));
-		*/
-		
-		*phase_filtered_pu = (float32_t)(*phase * ADC_LSB_SIZE * ONEON_CURRENT_SENSOR_SENSITIVITY);
-	}
-	volatile int16_t phase_A_current_raw = hri_adc_read_RESULT_reg(descr->device.hw) - Motor1.Voffset_lsb.A;  //Read ADC 0
-	volatile int16_t phase_B_current_raw = (hri_adc_read_RESULT_reg(ADC1) - Motor1.Voffset_lsb.B)*-1;	//Ib is connected backwards //Read ADC 1, synced with ADC0
-	
-	// Covert from LSB to PU (A) and filter out small readings
-	filter_convert_to_pu(&phase_A_current_raw, &Motor1.Iphase_pu.A); 
-	filter_convert_to_pu(&phase_B_current_raw, &Motor1.Iphase_pu.B);
-	// i_c = -i_a - i_b because i_a + i_b + i_c = 0
-	Motor1.Iphase_pu.C = -Motor1.Iphase_pu.A - Motor1.Iphase_pu.B;
-	// Select phase based on Hall State
-	//select_active_phase(Motor1.hall_state, &Motor1); 
-	// Set Current Loop Flag
-	Motor1.timerflags.current_loop_tic = true;
-	//toc(DEBUG_1);
-	toc_port(DEBUG_2_PORT);
-}
+//static void adc_cb(const struct adc_async_descriptor *const descr, const uint8_t channel)
+//{
+	//tic_port(DEBUG_2_PORT);
+	////tic(DEBUG_1);
+	//// Filter Out low level noise
+	//inline void filter_convert_to_pu(int16_t *phase, float32_t *phase_filtered_pu)
+	//{
+		///*
+		//if(*phase <= 20 && *phase >= -20 ) *phase_filtered_pu = 0.0f;
+		//else(*phase_filtered_pu = (float32_t)(*phase * ADC_LSB_SIZE * ONEON_CURRENT_SENSOR_SENSITIVITY));
+		//*/
+		//
+		//*phase_filtered_pu = (float32_t)(*phase * ADC_LSB_SIZE * ONEON_CURRENT_SENSOR_SENSITIVITY);
+	//}
+	//volatile int16_t phase_A_current_raw = hri_adc_read_RESULT_reg(descr->device.hw) - Motor1.Voffset_lsb.A;  //Read ADC 0
+	//volatile int16_t phase_B_current_raw = (hri_adc_read_RESULT_reg(ADC1) - Motor1.Voffset_lsb.B)*-1;	//Ib is connected backwards //Read ADC 1, synced with ADC0
+	//
+	//// Covert from LSB to PU (A) and filter out small readings
+	//filter_convert_to_pu(&phase_A_current_raw, &Motor1.Iphase_pu.A); 
+	//filter_convert_to_pu(&phase_B_current_raw, &Motor1.Iphase_pu.B);
+	//// i_c = -i_a - i_b because i_a + i_b + i_c = 0
+	//Motor1.Iphase_pu.C = -Motor1.Iphase_pu.A - Motor1.Iphase_pu.B;
+	//// Select phase based on Hall State
+	////select_active_phase(Motor1.hall_state, &Motor1); 
+	//// Set Current Loop Flag
+	//Motor1.timerflags.current_loop_tic = true;
+	////toc(DEBUG_1);
+	//toc_port(DEBUG_2_PORT);
+//}
 
 // ----------------------------------------------------------------------
 // 	ADC Callback for Motor Phase Current Measurement.
@@ -104,5 +105,43 @@ static void HW_current_limit_detect_callback(void)
 	
 }
 
+void adc_sram_dma_callback(struct _dma_resource *adc_dma_res)
+{
+	inline void filter_convert_to_pu(int16_t *phase, float32_t *phase_filtered_pu)
+	{
+		*phase_filtered_pu = (float32_t)(*phase * ADC_LSB_SIZE * ONEON_CURRENT_SENSOR_SENSITIVITY);
+	}
+	
+	volatile int16_t phase_A_current_raw;
+	volatile int16_t phase_B_current_raw;
+	
+	/* Motor 1 */
+	phase_A_current_raw = (adc_res[0] - Motor1.Voffset_lsb.A);
+	phase_B_current_raw = (adc_res[1] - Motor1.Voffset_lsb.B)*-1;
+	// Covert from LSB to PU (A) and filter out small readings
+	filter_convert_to_pu(&phase_A_current_raw, &Motor1.Iphase_pu.A); 
+	filter_convert_to_pu(&phase_B_current_raw, &Motor1.Iphase_pu.B);
+	// i_c = -i_a - i_b because i_a + i_b + i_c = 0
+	Motor1.Iphase_pu.C = -Motor1.Iphase_pu.A - Motor1.Iphase_pu.B;
+	
+	/* Motor 2 */
+	phase_A_current_raw = (adc_res[0] - Motor2.Voffset_lsb.A);
+	phase_B_current_raw = (adc_res[1] - Motor2.Voffset_lsb.B)*-1;
+	filter_convert_to_pu(&phase_A_current_raw, &Motor2.Iphase_pu.A);  
+	filter_convert_to_pu(&phase_B_current_raw, &Motor2.Iphase_pu.B);
+	// i_c = -i_a - i_b because i_a + i_b + i_c = 0
+	Motor2.Iphase_pu.C = -Motor2.Iphase_pu.A - Motor2.Iphase_pu.B;
+	
+	/* Motor 3 */
+	phase_A_current_raw = (adc_res[0] - Motor3.Voffset_lsb.A);
+	phase_B_current_raw = (adc_res[1] - Motor3.Voffset_lsb.B)*-1;
+	filter_convert_to_pu(&phase_A_current_raw, &Motor3.Iphase_pu.A);  
+	filter_convert_to_pu(&phase_B_current_raw, &Motor3.Iphase_pu.B);
+	// i_c = -i_a - i_b because i_a + i_b + i_c = 0
+	Motor3.Iphase_pu.C = -Motor3.Iphase_pu.A - Motor3.Iphase_pu.B;
+		
+	// Set Current Loop Flag
+	Motor1.timerflags.current_loop_tic = true;	
+}
 
 #endif /* INTERRUPT_HANDLERS_H_ */
\ No newline at end of file
diff --git a/BLDC_E54/BLDC_E54/main.c b/BLDC_E54/BLDC_E54/main.c
index 79b9866..43884fd 100644
--- a/BLDC_E54/BLDC_E54/main.c
+++ b/BLDC_E54/BLDC_E54/main.c
@@ -64,8 +64,8 @@ inline void CONTROLLER_StateMachine(void)
 					/* Blank */
 	 		    case 6: /* PWM FREQ / 6.25 - 4kHz */
 					calculate_motor_speed();
-					BLDC_runSpeedCntl(&Motor1, Motor1.motor_status.calc_rpm, Motor1.motor_setpoints.desired_speed);
-					//BLDC_runSpeedCntl(&Motor1, Motor1.motor_status.calc_rpm, 2000);
+					//BLDC_runSpeedCntl(&Motor1, Motor1.motor_status.calc_rpm, Motor1.motor_setpoints.desired_speed);
+					BLDC_runSpeedCntl(&Motor1, Motor1.motor_status.calc_rpm, 3000);
 				default: /* PWM FREQ - 25kHz */
 					select_active_phase(&Motor1, Motor1.motor_status.currentHallPattern); 	/* Still measure current */
 					break;
@@ -154,7 +154,16 @@ inline void CONTROLLER_StateMachine(void)
 				case UNKNOWN:                          						
 					break;
 				default: break;
-			}// End switch(switch(applicationStatus.fault))		
+			}// End switch(switch(applicationStatus.fault))	
+			
+			case COMMSTEST:
+			
+			
+			
+			
+			
+			
+				
 		default: break;
 	} // End switch(applicationStatus.currentstate)
 	//gpio_set_pin_level(DRV_RST, true);
@@ -184,11 +193,16 @@ int main(void)
 	BldcInitStruct(&Motor3);
 	BldcInitFunctions();
 		
-	read_zero_current_offset_value();
+	read_zero_current_offset_value(&Motor1);
+	read_zero_current_offset_value(&Motor2);
+	read_zero_current_offset_value(&Motor3);
+	
 	configure_tcc_pwm();
 	config_pins();
 	configure_adc();
 	configure_ethercat_dma_descriptors();
+	adc_init_dma();
+		
 	ethercat_update();
 	custom_logic_enable();
 	configure_TC_CCL_SPEED();
@@ -207,8 +221,7 @@ int main(void)
 		//tic(DEBUG_1_PORT);
 		//toc(DEBUG_1_PORT);
 		
-		if(Motor1.timerflags.motor_telemetry_flag)
-		{
+		if(Motor1.timerflags.motor_telemetry_flag) {
 			Motor1.timerflags.motor_telemetry_flag = false;
 			update_setpoints();
 			update_telemetry();
@@ -222,9 +235,9 @@ int main(void)
 		//}
 		if(Motor1.timerflags.current_loop_tic) {
 			Motor1.timerflags.current_loop_tic = false;
-			tic_port(DEBUG_1_PORT);
+			//tic_port(DEBUG_1_PORT);
 			CONTROLLER_StateMachine();
-			toc_port(DEBUG_1_PORT);
+			//toc_port(DEBUG_1_PORT);
 		}
 		
 		
diff --git a/BLDC_E54/BLDC_E54/statemachine.h b/BLDC_E54/BLDC_E54/statemachine.h
index b36540a..7192bcf 100644
--- a/BLDC_E54/BLDC_E54/statemachine.h
+++ b/BLDC_E54/BLDC_E54/statemachine.h
@@ -22,6 +22,7 @@ typedef enum
 	MOTOR_PVI_CTRL_STATE = 7,
 	MOTOR_STOP = 8,
 	FAULT = 9,
+	COMMSTEST = 10
 } CONTROLLER_FSM;
 
 typedef enum