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fixed master slave spi issue

This commit is contained in:
Nicolas Trimborn 2021-08-29 19:32:49 +02:00
parent e98d8c5085
commit 02ade8660d
26 changed files with 534 additions and 482 deletions
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233
2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart
View File

@ -237,9 +237,9 @@ drivers:
api: HAL:HPL:DMAC
configuration:
dmac_beatsize_0: 32-bit bus transfer
dmac_beatsize_1: 16-bit bus transfer
dmac_beatsize_10: 8-bit bus transfer
dmac_beatsize_11: 8-bit bus transfer
dmac_beatsize_1: 32-bit bus transfer
dmac_beatsize_10: 32-bit bus transfer
dmac_beatsize_11: 32-bit bus transfer
dmac_beatsize_12: 8-bit bus transfer
dmac_beatsize_13: 8-bit bus transfer
dmac_beatsize_14: 8-bit bus transfer
@ -262,16 +262,16 @@ drivers:
dmac_beatsize_3: 32-bit bus transfer
dmac_beatsize_30: 8-bit bus transfer
dmac_beatsize_31: 8-bit bus transfer
dmac_beatsize_4: 8-bit bus transfer
dmac_beatsize_5: 8-bit bus transfer
dmac_beatsize_6: 8-bit bus transfer
dmac_beatsize_7: 8-bit bus transfer
dmac_beatsize_8: 8-bit bus transfer
dmac_beatsize_9: 8-bit bus transfer
dmac_beatsize_4: 16-bit bus transfer
dmac_beatsize_5: 16-bit bus transfer
dmac_beatsize_6: 32-bit bus transfer
dmac_beatsize_7: 32-bit bus transfer
dmac_beatsize_8: 32-bit bus transfer
dmac_beatsize_9: 32-bit bus transfer
dmac_blockact_0: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_1: Channel will be disabled if it is the last block transfer in
the transaction and block interrupt
the transaction
dmac_blockact_10: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_11: Channel will be disabled if it is the last block transfer
@ -292,7 +292,8 @@ drivers:
in the transaction
dmac_blockact_19: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_2: Channel suspend operation is complete
dmac_blockact_2: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_20: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_21: Channel will be disabled if it is the last block transfer
@ -320,19 +321,17 @@ drivers:
dmac_blockact_31: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_4: Channel will be disabled if it is the last block transfer in
the transaction
the transaction and block interrupt
dmac_blockact_5: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_6: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_7: Channel will be disabled if it is the last block transfer in
the transaction
the transaction and block interrupt
dmac_blockact_6: Channel suspend operation is complete
dmac_blockact_7: Channel suspend operation is complete
dmac_blockact_8: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_9: Channel will be disabled if it is the last block transfer in
the transaction
dmac_channel_0_settings: true
dmac_channel_10_settings: false
dmac_channel_0_settings: false
dmac_channel_10_settings: true
dmac_channel_11_settings: false
dmac_channel_12_settings: false
dmac_channel_13_settings: false
@ -357,12 +356,12 @@ drivers:
dmac_channel_30_settings: false
dmac_channel_31_settings: false
dmac_channel_3_settings: true
dmac_channel_4_settings: false
dmac_channel_5_settings: false
dmac_channel_4_settings: true
dmac_channel_5_settings: true
dmac_channel_6_settings: false
dmac_channel_7_settings: false
dmac_channel_8_settings: false
dmac_channel_9_settings: false
dmac_channel_7_settings: true
dmac_channel_8_settings: true
dmac_channel_9_settings: true
dmac_dbgrun: false
dmac_dstinc_0: true
dmac_dstinc_1: true
@ -376,7 +375,7 @@ drivers:
dmac_dstinc_17: false
dmac_dstinc_18: false
dmac_dstinc_19: false
dmac_dstinc_2: false
dmac_dstinc_2: true
dmac_dstinc_20: false
dmac_dstinc_21: false
dmac_dstinc_22: false
@ -387,11 +386,11 @@ drivers:
dmac_dstinc_27: false
dmac_dstinc_28: false
dmac_dstinc_29: false
dmac_dstinc_3: false
dmac_dstinc_3: true
dmac_dstinc_30: false
dmac_dstinc_31: false
dmac_dstinc_4: false
dmac_dstinc_5: false
dmac_dstinc_4: true
dmac_dstinc_5: true
dmac_dstinc_6: false
dmac_dstinc_7: false
dmac_dstinc_8: false
@ -409,7 +408,7 @@ drivers:
dmac_evact_17: No action
dmac_evact_18: No action
dmac_evact_19: No action
dmac_evact_2: Channel resume operation
dmac_evact_2: No action
dmac_evact_20: No action
dmac_evact_21: No action
dmac_evact_22: No action
@ -425,8 +424,8 @@ drivers:
dmac_evact_31: No action
dmac_evact_4: No action
dmac_evact_5: No action
dmac_evact_6: No action
dmac_evact_7: No action
dmac_evact_6: Channel resume operation
dmac_evact_7: Channel resume operation
dmac_evact_8: No action
dmac_evact_9: No action
dmac_evie_0: false
@ -457,12 +456,12 @@ drivers:
dmac_evie_31: false
dmac_evie_4: false
dmac_evie_5: false
dmac_evie_6: false
dmac_evie_7: false
dmac_evie_6: true
dmac_evie_7: true
dmac_evie_8: false
dmac_evie_9: false
dmac_evoe_0: false
dmac_evoe_1: false
dmac_evoe_1: true
dmac_evoe_10: false
dmac_evoe_11: false
dmac_evoe_12: false
@ -473,7 +472,7 @@ drivers:
dmac_evoe_17: false
dmac_evoe_18: false
dmac_evoe_19: false
dmac_evoe_2: false
dmac_evoe_2: true
dmac_evoe_20: false
dmac_evoe_21: false
dmac_evoe_22: false
@ -494,7 +493,7 @@ drivers:
dmac_evoe_8: false
dmac_evoe_9: false
dmac_evosel_0: Event generation disabled
dmac_evosel_1: Event generation disabled
dmac_evosel_1: Event strobe when block transfer complete
dmac_evosel_10: Event generation disabled
dmac_evosel_11: Event generation disabled
dmac_evosel_12: Event generation disabled
@ -505,7 +504,7 @@ drivers:
dmac_evosel_17: Event generation disabled
dmac_evosel_18: Event generation disabled
dmac_evosel_19: Event generation disabled
dmac_evosel_2: Event generation disabled
dmac_evosel_2: Event strobe when beat transfer complete
dmac_evosel_20: Event generation disabled
dmac_evosel_21: Event generation disabled
dmac_evosel_22: Event generation disabled
@ -571,8 +570,8 @@ drivers:
dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
dmac_runstdby_0: true
dmac_runstdby_1: true
dmac_runstdby_10: false
dmac_runstdby_11: false
dmac_runstdby_10: true
dmac_runstdby_11: true
dmac_runstdby_12: false
dmac_runstdby_13: false
dmac_runstdby_14: false
@ -595,16 +594,16 @@ drivers:
dmac_runstdby_3: true
dmac_runstdby_30: false
dmac_runstdby_31: false
dmac_runstdby_4: false
dmac_runstdby_5: false
dmac_runstdby_6: false
dmac_runstdby_7: false
dmac_runstdby_8: false
dmac_runstdby_9: false
dmac_runstdby_4: true
dmac_runstdby_5: true
dmac_runstdby_6: true
dmac_runstdby_7: true
dmac_runstdby_8: true
dmac_runstdby_9: true
dmac_srcinc_0: false
dmac_srcinc_1: false
dmac_srcinc_10: false
dmac_srcinc_11: false
dmac_srcinc_10: true
dmac_srcinc_11: true
dmac_srcinc_12: false
dmac_srcinc_13: false
dmac_srcinc_14: false
@ -613,7 +612,7 @@ drivers:
dmac_srcinc_17: false
dmac_srcinc_18: false
dmac_srcinc_19: false
dmac_srcinc_2: true
dmac_srcinc_2: false
dmac_srcinc_20: false
dmac_srcinc_21: false
dmac_srcinc_22: false
@ -624,19 +623,19 @@ drivers:
dmac_srcinc_27: false
dmac_srcinc_28: false
dmac_srcinc_29: false
dmac_srcinc_3: true
dmac_srcinc_3: false
dmac_srcinc_30: false
dmac_srcinc_31: false
dmac_srcinc_4: false
dmac_srcinc_5: false
dmac_srcinc_6: false
dmac_srcinc_7: false
dmac_srcinc_8: false
dmac_srcinc_9: false
dmac_srcinc_6: true
dmac_srcinc_7: true
dmac_srcinc_8: true
dmac_srcinc_9: true
dmac_stepsel_0: Step size settings apply to the destination address
dmac_stepsel_1: Step size settings apply to the source address
dmac_stepsel_10: Step size settings apply to the destination address
dmac_stepsel_11: Step size settings apply to the destination address
dmac_stepsel_1: Step size settings apply to the destination address
dmac_stepsel_10: Step size settings apply to the source address
dmac_stepsel_11: Step size settings apply to the source address
dmac_stepsel_12: Step size settings apply to the destination address
dmac_stepsel_13: Step size settings apply to the destination address
dmac_stepsel_14: Step size settings apply to the destination address
@ -645,7 +644,7 @@ drivers:
dmac_stepsel_17: Step size settings apply to the destination address
dmac_stepsel_18: Step size settings apply to the destination address
dmac_stepsel_19: Step size settings apply to the destination address
dmac_stepsel_2: Step size settings apply to the source address
dmac_stepsel_2: Step size settings apply to the destination address
dmac_stepsel_20: Step size settings apply to the destination address
dmac_stepsel_21: Step size settings apply to the destination address
dmac_stepsel_22: Step size settings apply to the destination address
@ -656,15 +655,15 @@ drivers:
dmac_stepsel_27: Step size settings apply to the destination address
dmac_stepsel_28: Step size settings apply to the destination address
dmac_stepsel_29: Step size settings apply to the destination address
dmac_stepsel_3: Step size settings apply to the source address
dmac_stepsel_3: Step size settings apply to the destination address
dmac_stepsel_30: Step size settings apply to the destination address
dmac_stepsel_31: Step size settings apply to the destination address
dmac_stepsel_4: Step size settings apply to the destination address
dmac_stepsel_5: Step size settings apply to the destination address
dmac_stepsel_6: Step size settings apply to the destination address
dmac_stepsel_7: Step size settings apply to the destination address
dmac_stepsel_8: Step size settings apply to the destination address
dmac_stepsel_9: Step size settings apply to the destination address
dmac_stepsel_4: Step size settings apply to the source address
dmac_stepsel_5: Step size settings apply to the source address
dmac_stepsel_6: Step size settings apply to the source address
dmac_stepsel_7: Step size settings apply to the source address
dmac_stepsel_8: Step size settings apply to the source address
dmac_stepsel_9: Step size settings apply to the source address
dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1
@ -697,10 +696,10 @@ drivers:
dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_trifsrc_0: SERCOM1 RX Trigger
dmac_trifsrc_1: ADC1 Result Ready Trigger
dmac_trifsrc_10: Only software/event triggers
dmac_trifsrc_11: Only software/event triggers
dmac_trifsrc_0: QSPI Rx Trigger
dmac_trifsrc_1: SERCOM1 RX Trigger
dmac_trifsrc_10: SERCOM1 TX Trigger
dmac_trifsrc_11: QSPI Tx Trigger
dmac_trifsrc_12: Only software/event triggers
dmac_trifsrc_13: Only software/event triggers
dmac_trifsrc_14: Only software/event triggers
@ -709,7 +708,7 @@ drivers:
dmac_trifsrc_17: Only software/event triggers
dmac_trifsrc_18: Only software/event triggers
dmac_trifsrc_19: Only software/event triggers
dmac_trifsrc_2: ADC1 Sequencing Trigger
dmac_trifsrc_2: SERCOM2 RX Trigger
dmac_trifsrc_20: Only software/event triggers
dmac_trifsrc_21: Only software/event triggers
dmac_trifsrc_22: Only software/event triggers
@ -720,19 +719,19 @@ drivers:
dmac_trifsrc_27: Only software/event triggers
dmac_trifsrc_28: Only software/event triggers
dmac_trifsrc_29: Only software/event triggers
dmac_trifsrc_3: SERCOM1 TX Trigger
dmac_trifsrc_3: SERCOM5 RX Trigger
dmac_trifsrc_30: Only software/event triggers
dmac_trifsrc_31: Only software/event triggers
dmac_trifsrc_4: Only software/event triggers
dmac_trifsrc_5: Only software/event triggers
dmac_trifsrc_6: Only software/event triggers
dmac_trifsrc_7: Only software/event triggers
dmac_trifsrc_8: Only software/event triggers
dmac_trifsrc_9: Only software/event triggers
dmac_trifsrc_4: ADC0 Result Ready Trigger
dmac_trifsrc_5: ADC1 Result Ready Trigger
dmac_trifsrc_6: ADC0 Sequencing Trigger
dmac_trifsrc_7: ADC1 Sequencing Trigger
dmac_trifsrc_8: SERCOM2 TX Trigger
dmac_trifsrc_9: SERCOM5 TX Trigger
dmac_trigact_0: One trigger required for each beat transfer
dmac_trigact_1: One trigger required for each beat transfer
dmac_trigact_10: One trigger required for each block transfer
dmac_trigact_11: One trigger required for each block transfer
dmac_trigact_10: One trigger required for each beat transfer
dmac_trigact_11: One trigger required for each beat transfer
dmac_trigact_12: One trigger required for each block transfer
dmac_trigact_13: One trigger required for each block transfer
dmac_trigact_14: One trigger required for each block transfer
@ -755,12 +754,12 @@ drivers:
dmac_trigact_3: One trigger required for each beat transfer
dmac_trigact_30: One trigger required for each block transfer
dmac_trigact_31: One trigger required for each block transfer
dmac_trigact_4: One trigger required for each block transfer
dmac_trigact_5: One trigger required for each block transfer
dmac_trigact_4: One trigger required for each beat transfer
dmac_trigact_5: One trigger required for each beat transfer
dmac_trigact_6: One trigger required for each block transfer
dmac_trigact_7: One trigger required for each block transfer
dmac_trigact_8: One trigger required for each block transfer
dmac_trigact_9: One trigger required for each block transfer
dmac_trigact_7: One trigger required for each beat transfer
dmac_trigact_8: One trigger required for each beat transfer
dmac_trigact_9: One trigger required for each beat transfer
optional_signals: []
variant: null
clocks:
@ -926,11 +925,11 @@ drivers:
evsys_channel_1: Channel 3
evsys_channel_10: No channel output selected
evsys_channel_11: No channel output selected
evsys_channel_12: No channel output selected
evsys_channel_12: Channel 0
evsys_channel_17: No channel output selected
evsys_channel_18: No channel output selected
evsys_channel_19: No channel output selected
evsys_channel_2: No channel output selected
evsys_channel_2: Channel 4
evsys_channel_20: No channel output selected
evsys_channel_21: No channel output selected
evsys_channel_22: No channel output selected
@ -982,7 +981,7 @@ drivers:
evsys_channel_64: No channel output selected
evsys_channel_65: No channel output selected
evsys_channel_66: No channel output selected
evsys_channel_7: Channel 0
evsys_channel_7: No channel output selected
evsys_channel_8: No channel output selected
evsys_channel_9: No channel output selected
evsys_channel_setting_0: true
@ -1011,8 +1010,8 @@ drivers:
evsys_channel_setting_3: true
evsys_channel_setting_30: false
evsys_channel_setting_31: false
evsys_channel_setting_4: false
evsys_channel_setting_5: false
evsys_channel_setting_4: true
evsys_channel_setting_5: true
evsys_channel_setting_6: false
evsys_channel_setting_7: false
evsys_channel_setting_8: false
@ -1063,16 +1062,16 @@ drivers:
path
evsys_edgsel_29: No event output when using the resynchronized or synchronous
path
evsys_edgsel_3: No event output when using the resynchronized or synchronous
path
evsys_edgsel_3: Event is detected on the rising edge of the signal from event
generator
evsys_edgsel_30: No event output when using the resynchronized or synchronous
path
evsys_edgsel_31: No event output when using the resynchronized or synchronous
path
evsys_edgsel_4: No event output when using the resynchronized or synchronous
path
evsys_edgsel_5: No event output when using the resynchronized or synchronous
path
evsys_edgsel_4: Event is detected on the rising edge of the signal from event
generator
evsys_edgsel_5: Event is detected on the rising edge of the signal from event
generator
evsys_edgsel_6: No event output when using the resynchronized or synchronous
path
evsys_edgsel_7: No event output when using the resynchronized or synchronous
@ -1104,11 +1103,11 @@ drivers:
evsys_evd_27: false
evsys_evd_28: false
evsys_evd_29: false
evsys_evd_3: false
evsys_evd_3: true
evsys_evd_30: false
evsys_evd_31: false
evsys_evd_4: false
evsys_evd_5: false
evsys_evd_4: true
evsys_evd_5: true
evsys_evd_6: false
evsys_evd_7: false
evsys_evd_8: false
@ -1139,8 +1138,8 @@ drivers:
evsys_evgen_3: TC0 match/capture 0
evsys_evgen_30: No event generator
evsys_evgen_31: No event generator
evsys_evgen_4: No event generator
evsys_evgen_5: No event generator
evsys_evgen_4: DMAC channel 1
evsys_evgen_5: DMAC channel 2
evsys_evgen_6: No event generator
evsys_evgen_7: No event generator
evsys_evgen_8: No event generator
@ -1643,7 +1642,7 @@ drivers:
api: HAL:HPL:PORT
configuration:
enable_port_input_event_0: true
enable_port_input_event_1: false
enable_port_input_event_1: true
enable_port_input_event_2: false
enable_port_input_event_3: false
porta_event_action_0: Output register of pin will be set to level of event
@ -1659,15 +1658,15 @@ drivers:
porta_input_event_enable_2: false
porta_input_event_enable_3: false
portb_event_action_0: Clear output register of pin on event
portb_event_action_1: Output register of pin will be set to level of event
portb_event_action_1: Set output register of pin on event
portb_event_action_2: Output register of pin will be set to level of event
portb_event_action_3: Output register of pin will be set to level of event
portb_event_pin_identifier_0: 22
portb_event_pin_identifier_1: 0
portb_event_pin_identifier_1: 22
portb_event_pin_identifier_2: 0
portb_event_pin_identifier_3: 0
portb_input_event_enable_0: true
portb_input_event_enable_1: false
portb_input_event_enable_1: true
portb_input_event_enable_2: false
portb_input_event_enable_3: false
optional_signals: []
@ -1760,8 +1759,8 @@ drivers:
spi_master_arch_runstdby: false
spi_master_baud_rate: 2000000
spi_master_character_size: 8 bits
spi_master_dma_rx_channel: 0
spi_master_dma_tx_channel: 3
spi_master_dma_rx_channel: 1
spi_master_dma_tx_channel: 10
spi_master_dummybyte: 511
spi_master_rx_channel: true
spi_master_rx_enable: true
@ -1882,12 +1881,12 @@ drivers:
slow_gclk_selection: Generic clock generator 3
TIMER_0:
user_label: TIMER_0
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::TC0::driver_config_definition::16-bit.Counter.Mode::Lite:TC:Timer
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::TC0::driver_config_definition::8-bit.Counter.Mode::Lite:TC:Timer
functionality: Timer
api: Lite:TC:Timer
configuration:
cc_cc0: 1874
cc_cc1: 0
cc_cc0: 117
cc_cc1: 180
cc_control: true
count_control: false
count_count: 0
@ -1900,13 +1899,13 @@ drivers:
ctrla_copen0: false
ctrla_copen1: false
ctrla_enable: true
ctrla_mode: 0
ctrla_mode: 1
ctrla_ondemand: false
ctrla_prescaler: DIV64
ctrla_prescaler: DIV1024
ctrla_prescsync: GCLK
ctrla_runstdby: false
ctrlbset_cmd: NONE
ctrlbset_control: false
ctrlbset_control: true
ctrlbset_dir: false
ctrlbset_lupd: false
ctrlbset_oneshot: false
@ -1918,17 +1917,19 @@ drivers:
evctrl_control: true
evctrl_evact: 'OFF'
evctrl_mceo0: true
evctrl_mceo1: false
evctrl_ovfeo: false
evctrl_mceo1: true
evctrl_ovfeo: true
evctrl_tcei: false
evctrl_tcinv: false
intenset_control: true
intenset_err: false
intenset_mc0: true
intenset_mc1: false
intenset_mc0: false
intenset_mc1: true
intenset_ovf: false
per_control: true
per_per: 255
wave_control: true
wave_wavegen: MFRQ
wave_wavegen: NFRQ
optional_signals: []
variant: null
clocks:

162
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_dmac_config.h
View File

@ -105,7 +105,7 @@
// <e> Channel 0 settings
// <id> dmac_channel_0_settings
#ifndef CONF_DMAC_CHANNEL_0_SETTINGS
#define CONF_DMAC_CHANNEL_0_SETTINGS 1
#define CONF_DMAC_CHANNEL_0_SETTINGS 0
#endif
// <q> Channel Run in Standby
@ -214,7 +214,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_0
#ifndef CONF_DMAC_TRIGSRC_0
#define CONF_DMAC_TRIGSRC_0 6
#define CONF_DMAC_TRIGSRC_0 83
#endif
// <o> Channel Arbitration Level
@ -438,7 +438,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_1
#ifndef CONF_DMAC_TRIGSRC_1
#define CONF_DMAC_TRIGSRC_1 70
#define CONF_DMAC_TRIGSRC_1 6
#endif
// <o> Channel Arbitration Level
@ -456,7 +456,7 @@
// <i> Indicates whether channel event generation is enabled or not
// <id> dmac_evoe_1
#ifndef CONF_DMAC_EVOE_1
#define CONF_DMAC_EVOE_1 0
#define CONF_DMAC_EVOE_1 1
#endif
// <q> Channel Event Input
@ -501,7 +501,7 @@
// <i> Defines whether source or destination addresses are using the step size settings
// <id> dmac_stepsel_1
#ifndef CONF_DMAC_STEPSEL_1
#define CONF_DMAC_STEPSEL_1 1
#define CONF_DMAC_STEPSEL_1 0
#endif
// <q> Source Address Increment
@ -525,7 +525,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_1
#ifndef CONF_DMAC_BEATSIZE_1
#define CONF_DMAC_BEATSIZE_1 1
#define CONF_DMAC_BEATSIZE_1 2
#endif
// <o> Block Action
@ -536,7 +536,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_1
#ifndef CONF_DMAC_BLOCKACT_1
#define CONF_DMAC_BLOCKACT_1 1
#define CONF_DMAC_BLOCKACT_1 0
#endif
// <o> Event Output Selection
@ -546,7 +546,7 @@
// <i> Defines the event output selection
// <id> dmac_evosel_1
#ifndef CONF_DMAC_EVOSEL_1
#define CONF_DMAC_EVOSEL_1 0
#define CONF_DMAC_EVOSEL_1 1
#endif
// </e>
@ -662,7 +662,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_2
#ifndef CONF_DMAC_TRIGSRC_2
#define CONF_DMAC_TRIGSRC_2 71
#define CONF_DMAC_TRIGSRC_2 8
#endif
// <o> Channel Arbitration Level
@ -680,7 +680,7 @@
// <i> Indicates whether channel event generation is enabled or not
// <id> dmac_evoe_2
#ifndef CONF_DMAC_EVOE_2
#define CONF_DMAC_EVOE_2 0
#define CONF_DMAC_EVOE_2 1
#endif
// <q> Channel Event Input
@ -701,7 +701,7 @@
// <i> Defines the event input action
// <id> dmac_evact_2
#ifndef CONF_DMAC_EVACT_2
#define CONF_DMAC_EVACT_2 5
#define CONF_DMAC_EVACT_2 0
#endif
// <o> Address Increment Step Size
@ -725,21 +725,21 @@
// <i> Defines whether source or destination addresses are using the step size settings
// <id> dmac_stepsel_2
#ifndef CONF_DMAC_STEPSEL_2
#define CONF_DMAC_STEPSEL_2 1
#define CONF_DMAC_STEPSEL_2 0
#endif
// <q> Source Address Increment
// <i> Indicates whether the source address incrementation is enabled or not
// <id> dmac_srcinc_2
#ifndef CONF_DMAC_SRCINC_2
#define CONF_DMAC_SRCINC_2 1
#define CONF_DMAC_SRCINC_2 0
#endif
// <q> Destination Address Increment
// <i> Indicates whether the destination address incrementation is enabled or not
// <id> dmac_dstinc_2
#ifndef CONF_DMAC_DSTINC_2
#define CONF_DMAC_DSTINC_2 0
#define CONF_DMAC_DSTINC_2 1
#endif
// <o> Beat Size
@ -760,7 +760,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_2
#ifndef CONF_DMAC_BLOCKACT_2
#define CONF_DMAC_BLOCKACT_2 2
#define CONF_DMAC_BLOCKACT_2 0
#endif
// <o> Event Output Selection
@ -770,7 +770,7 @@
// <i> Defines the event output selection
// <id> dmac_evosel_2
#ifndef CONF_DMAC_EVOSEL_2
#define CONF_DMAC_EVOSEL_2 0
#define CONF_DMAC_EVOSEL_2 3
#endif
// </e>
@ -886,7 +886,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_3
#ifndef CONF_DMAC_TRIGSRC_3
#define CONF_DMAC_TRIGSRC_3 7
#define CONF_DMAC_TRIGSRC_3 14
#endif
// <o> Channel Arbitration Level
@ -949,21 +949,21 @@
// <i> Defines whether source or destination addresses are using the step size settings
// <id> dmac_stepsel_3
#ifndef CONF_DMAC_STEPSEL_3
#define CONF_DMAC_STEPSEL_3 1
#define CONF_DMAC_STEPSEL_3 0
#endif
// <q> Source Address Increment
// <i> Indicates whether the source address incrementation is enabled or not
// <id> dmac_srcinc_3
#ifndef CONF_DMAC_SRCINC_3
#define CONF_DMAC_SRCINC_3 1
#define CONF_DMAC_SRCINC_3 0
#endif
// <q> Destination Address Increment
// <i> Indicates whether the destination address incrementation is enabled or not
// <id> dmac_dstinc_3
#ifndef CONF_DMAC_DSTINC_3
#define CONF_DMAC_DSTINC_3 0
#define CONF_DMAC_DSTINC_3 1
#endif
// <o> Beat Size
@ -1001,14 +1001,14 @@
// <e> Channel 4 settings
// <id> dmac_channel_4_settings
#ifndef CONF_DMAC_CHANNEL_4_SETTINGS
#define CONF_DMAC_CHANNEL_4_SETTINGS 0
#define CONF_DMAC_CHANNEL_4_SETTINGS 1
#endif
// <q> Channel Run in Standby
// <i> Indicates whether channel 4 is running in standby mode or not
// <id> dmac_runstdby_4
#ifndef CONF_DMAC_RUNSTDBY_4
#define CONF_DMAC_RUNSTDBY_4 0
#define CONF_DMAC_RUNSTDBY_4 1
#endif
// <o> Trigger action
@ -1018,7 +1018,7 @@
// <i> Defines the trigger action used for a transfer
// <id> dmac_trigact_4
#ifndef CONF_DMAC_TRIGACT_4
#define CONF_DMAC_TRIGACT_4 0
#define CONF_DMAC_TRIGACT_4 2
#endif
// <o> Trigger source
@ -1110,7 +1110,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_4
#ifndef CONF_DMAC_TRIGSRC_4
#define CONF_DMAC_TRIGSRC_4 0
#define CONF_DMAC_TRIGSRC_4 68
#endif
// <o> Channel Arbitration Level
@ -1173,7 +1173,7 @@
// <i> Defines whether source or destination addresses are using the step size settings
// <id> dmac_stepsel_4
#ifndef CONF_DMAC_STEPSEL_4
#define CONF_DMAC_STEPSEL_4 0
#define CONF_DMAC_STEPSEL_4 1
#endif
// <q> Source Address Increment
@ -1187,7 +1187,7 @@
// <i> Indicates whether the destination address incrementation is enabled or not
// <id> dmac_dstinc_4
#ifndef CONF_DMAC_DSTINC_4
#define CONF_DMAC_DSTINC_4 0
#define CONF_DMAC_DSTINC_4 1
#endif
// <o> Beat Size
@ -1197,7 +1197,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_4
#ifndef CONF_DMAC_BEATSIZE_4
#define CONF_DMAC_BEATSIZE_4 0
#define CONF_DMAC_BEATSIZE_4 1
#endif
// <o> Block Action
@ -1208,7 +1208,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_4
#ifndef CONF_DMAC_BLOCKACT_4
#define CONF_DMAC_BLOCKACT_4 0
#define CONF_DMAC_BLOCKACT_4 1
#endif
// <o> Event Output Selection
@ -1225,14 +1225,14 @@
// <e> Channel 5 settings
// <id> dmac_channel_5_settings
#ifndef CONF_DMAC_CHANNEL_5_SETTINGS
#define CONF_DMAC_CHANNEL_5_SETTINGS 0
#define CONF_DMAC_CHANNEL_5_SETTINGS 1
#endif
// <q> Channel Run in Standby
// <i> Indicates whether channel 5 is running in standby mode or not
// <id> dmac_runstdby_5
#ifndef CONF_DMAC_RUNSTDBY_5
#define CONF_DMAC_RUNSTDBY_5 0
#define CONF_DMAC_RUNSTDBY_5 1
#endif
// <o> Trigger action
@ -1242,7 +1242,7 @@
// <i> Defines the trigger action used for a transfer
// <id> dmac_trigact_5
#ifndef CONF_DMAC_TRIGACT_5
#define CONF_DMAC_TRIGACT_5 0
#define CONF_DMAC_TRIGACT_5 2
#endif
// <o> Trigger source
@ -1334,7 +1334,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_5
#ifndef CONF_DMAC_TRIGSRC_5
#define CONF_DMAC_TRIGSRC_5 0
#define CONF_DMAC_TRIGSRC_5 70
#endif
// <o> Channel Arbitration Level
@ -1397,7 +1397,7 @@
// <i> Defines whether source or destination addresses are using the step size settings
// <id> dmac_stepsel_5
#ifndef CONF_DMAC_STEPSEL_5
#define CONF_DMAC_STEPSEL_5 0
#define CONF_DMAC_STEPSEL_5 1
#endif
// <q> Source Address Increment
@ -1411,7 +1411,7 @@
// <i> Indicates whether the destination address incrementation is enabled or not
// <id> dmac_dstinc_5
#ifndef CONF_DMAC_DSTINC_5
#define CONF_DMAC_DSTINC_5 0
#define CONF_DMAC_DSTINC_5 1
#endif
// <o> Beat Size
@ -1421,7 +1421,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_5
#ifndef CONF_DMAC_BEATSIZE_5
#define CONF_DMAC_BEATSIZE_5 0
#define CONF_DMAC_BEATSIZE_5 1
#endif
// <o> Block Action
@ -1432,7 +1432,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_5
#ifndef CONF_DMAC_BLOCKACT_5
#define CONF_DMAC_BLOCKACT_5 0
#define CONF_DMAC_BLOCKACT_5 1
#endif
// <o> Event Output Selection
@ -1456,7 +1456,7 @@
// <i> Indicates whether channel 6 is running in standby mode or not
// <id> dmac_runstdby_6
#ifndef CONF_DMAC_RUNSTDBY_6
#define CONF_DMAC_RUNSTDBY_6 0
#define CONF_DMAC_RUNSTDBY_6 1
#endif
// <o> Trigger action
@ -1558,7 +1558,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_6
#ifndef CONF_DMAC_TRIGSRC_6
#define CONF_DMAC_TRIGSRC_6 0
#define CONF_DMAC_TRIGSRC_6 69
#endif
// <o> Channel Arbitration Level
@ -1583,7 +1583,7 @@
// <i> Indicates whether channel event reception is enabled or not
// <id> dmac_evie_6
#ifndef CONF_DMAC_EVIE_6
#define CONF_DMAC_EVIE_6 0
#define CONF_DMAC_EVIE_6 1
#endif
// <o> Event Input Action
@ -1597,7 +1597,7 @@
// <i> Defines the event input action
// <id> dmac_evact_6
#ifndef CONF_DMAC_EVACT_6
#define CONF_DMAC_EVACT_6 0
#define CONF_DMAC_EVACT_6 5
#endif
// <o> Address Increment Step Size
@ -1621,14 +1621,14 @@
// <i> Defines whether source or destination addresses are using the step size settings
// <id> dmac_stepsel_6
#ifndef CONF_DMAC_STEPSEL_6
#define CONF_DMAC_STEPSEL_6 0
#define CONF_DMAC_STEPSEL_6 1
#endif
// <q> Source Address Increment
// <i> Indicates whether the source address incrementation is enabled or not
// <id> dmac_srcinc_6
#ifndef CONF_DMAC_SRCINC_6
#define CONF_DMAC_SRCINC_6 0
#define CONF_DMAC_SRCINC_6 1
#endif
// <q> Destination Address Increment
@ -1645,7 +1645,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_6
#ifndef CONF_DMAC_BEATSIZE_6
#define CONF_DMAC_BEATSIZE_6 0
#define CONF_DMAC_BEATSIZE_6 2
#endif
// <o> Block Action
@ -1656,7 +1656,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_6
#ifndef CONF_DMAC_BLOCKACT_6
#define CONF_DMAC_BLOCKACT_6 0
#define CONF_DMAC_BLOCKACT_6 2
#endif
// <o> Event Output Selection
@ -1673,14 +1673,14 @@
// <e> Channel 7 settings
// <id> dmac_channel_7_settings
#ifndef CONF_DMAC_CHANNEL_7_SETTINGS
#define CONF_DMAC_CHANNEL_7_SETTINGS 0
#define CONF_DMAC_CHANNEL_7_SETTINGS 1
#endif
// <q> Channel Run in Standby
// <i> Indicates whether channel 7 is running in standby mode or not
// <id> dmac_runstdby_7
#ifndef CONF_DMAC_RUNSTDBY_7
#define CONF_DMAC_RUNSTDBY_7 0
#define CONF_DMAC_RUNSTDBY_7 1
#endif
// <o> Trigger action
@ -1690,7 +1690,7 @@
// <i> Defines the trigger action used for a transfer
// <id> dmac_trigact_7
#ifndef CONF_DMAC_TRIGACT_7
#define CONF_DMAC_TRIGACT_7 0
#define CONF_DMAC_TRIGACT_7 2
#endif
// <o> Trigger source
@ -1782,7 +1782,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_7
#ifndef CONF_DMAC_TRIGSRC_7
#define CONF_DMAC_TRIGSRC_7 0
#define CONF_DMAC_TRIGSRC_7 71
#endif
// <o> Channel Arbitration Level
@ -1807,7 +1807,7 @@
// <i> Indicates whether channel event reception is enabled or not
// <id> dmac_evie_7
#ifndef CONF_DMAC_EVIE_7
#define CONF_DMAC_EVIE_7 0
#define CONF_DMAC_EVIE_7 1
#endif
// <o> Event Input Action
@ -1821,7 +1821,7 @@
// <i> Defines the event input action
// <id> dmac_evact_7
#ifndef CONF_DMAC_EVACT_7
#define CONF_DMAC_EVACT_7 0
#define CONF_DMAC_EVACT_7 5
#endif
// <o> Address Increment Step Size
@ -1845,14 +1845,14 @@
// <i> Defines whether source or destination addresses are using the step size settings
// <id> dmac_stepsel_7
#ifndef CONF_DMAC_STEPSEL_7
#define CONF_DMAC_STEPSEL_7 0
#define CONF_DMAC_STEPSEL_7 1
#endif
// <q> Source Address Increment
// <i> Indicates whether the source address incrementation is enabled or not
// <id> dmac_srcinc_7
#ifndef CONF_DMAC_SRCINC_7
#define CONF_DMAC_SRCINC_7 0
#define CONF_DMAC_SRCINC_7 1
#endif
// <q> Destination Address Increment
@ -1869,7 +1869,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_7
#ifndef CONF_DMAC_BEATSIZE_7
#define CONF_DMAC_BEATSIZE_7 0
#define CONF_DMAC_BEATSIZE_7 2
#endif
// <o> Block Action
@ -1880,7 +1880,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_7
#ifndef CONF_DMAC_BLOCKACT_7
#define CONF_DMAC_BLOCKACT_7 0
#define CONF_DMAC_BLOCKACT_7 2
#endif
// <o> Event Output Selection
@ -1897,14 +1897,14 @@
// <e> Channel 8 settings
// <id> dmac_channel_8_settings
#ifndef CONF_DMAC_CHANNEL_8_SETTINGS
#define CONF_DMAC_CHANNEL_8_SETTINGS 0
#define CONF_DMAC_CHANNEL_8_SETTINGS 1
#endif
// <q> Channel Run in Standby
// <i> Indicates whether channel 8 is running in standby mode or not
// <id> dmac_runstdby_8
#ifndef CONF_DMAC_RUNSTDBY_8
#define CONF_DMAC_RUNSTDBY_8 0
#define CONF_DMAC_RUNSTDBY_8 1
#endif
// <o> Trigger action
@ -1914,7 +1914,7 @@
// <i> Defines the trigger action used for a transfer
// <id> dmac_trigact_8
#ifndef CONF_DMAC_TRIGACT_8
#define CONF_DMAC_TRIGACT_8 0
#define CONF_DMAC_TRIGACT_8 2
#endif
// <o> Trigger source
@ -2006,7 +2006,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_8
#ifndef CONF_DMAC_TRIGSRC_8
#define CONF_DMAC_TRIGSRC_8 0
#define CONF_DMAC_TRIGSRC_8 9
#endif
// <o> Channel Arbitration Level
@ -2069,14 +2069,14 @@
// <i> Defines whether source or destination addresses are using the step size settings
// <id> dmac_stepsel_8
#ifndef CONF_DMAC_STEPSEL_8
#define CONF_DMAC_STEPSEL_8 0
#define CONF_DMAC_STEPSEL_8 1
#endif
// <q> Source Address Increment
// <i> Indicates whether the source address incrementation is enabled or not
// <id> dmac_srcinc_8
#ifndef CONF_DMAC_SRCINC_8
#define CONF_DMAC_SRCINC_8 0
#define CONF_DMAC_SRCINC_8 1
#endif
// <q> Destination Address Increment
@ -2093,7 +2093,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_8
#ifndef CONF_DMAC_BEATSIZE_8
#define CONF_DMAC_BEATSIZE_8 0
#define CONF_DMAC_BEATSIZE_8 2
#endif
// <o> Block Action
@ -2121,14 +2121,14 @@
// <e> Channel 9 settings
// <id> dmac_channel_9_settings
#ifndef CONF_DMAC_CHANNEL_9_SETTINGS
#define CONF_DMAC_CHANNEL_9_SETTINGS 0
#define CONF_DMAC_CHANNEL_9_SETTINGS 1
#endif
// <q> Channel Run in Standby
// <i> Indicates whether channel 9 is running in standby mode or not
// <id> dmac_runstdby_9
#ifndef CONF_DMAC_RUNSTDBY_9
#define CONF_DMAC_RUNSTDBY_9 0
#define CONF_DMAC_RUNSTDBY_9 1
#endif
// <o> Trigger action
@ -2138,7 +2138,7 @@
// <i> Defines the trigger action used for a transfer
// <id> dmac_trigact_9
#ifndef CONF_DMAC_TRIGACT_9
#define CONF_DMAC_TRIGACT_9 0
#define CONF_DMAC_TRIGACT_9 2
#endif
// <o> Trigger source
@ -2230,7 +2230,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_9
#ifndef CONF_DMAC_TRIGSRC_9
#define CONF_DMAC_TRIGSRC_9 0
#define CONF_DMAC_TRIGSRC_9 15
#endif
// <o> Channel Arbitration Level
@ -2293,14 +2293,14 @@
// <i> Defines whether source or destination addresses are using the step size settings
// <id> dmac_stepsel_9
#ifndef CONF_DMAC_STEPSEL_9
#define CONF_DMAC_STEPSEL_9 0
#define CONF_DMAC_STEPSEL_9 1
#endif
// <q> Source Address Increment
// <i> Indicates whether the source address incrementation is enabled or not
// <id> dmac_srcinc_9
#ifndef CONF_DMAC_SRCINC_9
#define CONF_DMAC_SRCINC_9 0
#define CONF_DMAC_SRCINC_9 1
#endif
// <q> Destination Address Increment
@ -2317,7 +2317,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_9
#ifndef CONF_DMAC_BEATSIZE_9
#define CONF_DMAC_BEATSIZE_9 0
#define CONF_DMAC_BEATSIZE_9 2
#endif
// <o> Block Action
@ -2345,14 +2345,14 @@
// <e> Channel 10 settings
// <id> dmac_channel_10_settings
#ifndef CONF_DMAC_CHANNEL_10_SETTINGS
#define CONF_DMAC_CHANNEL_10_SETTINGS 0
#define CONF_DMAC_CHANNEL_10_SETTINGS 1
#endif
// <q> Channel Run in Standby
// <i> Indicates whether channel 10 is running in standby mode or not
// <id> dmac_runstdby_10
#ifndef CONF_DMAC_RUNSTDBY_10
#define CONF_DMAC_RUNSTDBY_10 0
#define CONF_DMAC_RUNSTDBY_10 1
#endif
// <o> Trigger action
@ -2362,7 +2362,7 @@
// <i> Defines the trigger action used for a transfer
// <id> dmac_trigact_10
#ifndef CONF_DMAC_TRIGACT_10
#define CONF_DMAC_TRIGACT_10 0
#define CONF_DMAC_TRIGACT_10 2
#endif
// <o> Trigger source
@ -2454,7 +2454,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_10
#ifndef CONF_DMAC_TRIGSRC_10
#define CONF_DMAC_TRIGSRC_10 0
#define CONF_DMAC_TRIGSRC_10 7
#endif
// <o> Channel Arbitration Level
@ -2517,14 +2517,14 @@
// <i> Defines whether source or destination addresses are using the step size settings
// <id> dmac_stepsel_10
#ifndef CONF_DMAC_STEPSEL_10
#define CONF_DMAC_STEPSEL_10 0
#define CONF_DMAC_STEPSEL_10 1
#endif
// <q> Source Address Increment
// <i> Indicates whether the source address incrementation is enabled or not
// <id> dmac_srcinc_10
#ifndef CONF_DMAC_SRCINC_10
#define CONF_DMAC_SRCINC_10 0
#define CONF_DMAC_SRCINC_10 1
#endif
// <q> Destination Address Increment
@ -2541,7 +2541,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_10
#ifndef CONF_DMAC_BEATSIZE_10
#define CONF_DMAC_BEATSIZE_10 0
#define CONF_DMAC_BEATSIZE_10 2
#endif
// <o> Block Action
@ -2576,7 +2576,7 @@
// <i> Indicates whether channel 11 is running in standby mode or not
// <id> dmac_runstdby_11
#ifndef CONF_DMAC_RUNSTDBY_11
#define CONF_DMAC_RUNSTDBY_11 0
#define CONF_DMAC_RUNSTDBY_11 1
#endif
// <o> Trigger action
@ -2586,7 +2586,7 @@
// <i> Defines the trigger action used for a transfer
// <id> dmac_trigact_11
#ifndef CONF_DMAC_TRIGACT_11
#define CONF_DMAC_TRIGACT_11 0
#define CONF_DMAC_TRIGACT_11 2
#endif
// <o> Trigger source
@ -2678,7 +2678,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_11
#ifndef CONF_DMAC_TRIGSRC_11
#define CONF_DMAC_TRIGSRC_11 0
#define CONF_DMAC_TRIGSRC_11 84
#endif
// <o> Channel Arbitration Level
@ -2741,14 +2741,14 @@
// <i> Defines whether source or destination addresses are using the step size settings
// <id> dmac_stepsel_11
#ifndef CONF_DMAC_STEPSEL_11
#define CONF_DMAC_STEPSEL_11 0
#define CONF_DMAC_STEPSEL_11 1
#endif
// <q> Source Address Increment
// <i> Indicates whether the source address incrementation is enabled or not
// <id> dmac_srcinc_11
#ifndef CONF_DMAC_SRCINC_11
#define CONF_DMAC_SRCINC_11 0
#define CONF_DMAC_SRCINC_11 1
#endif
// <q> Destination Address Increment
@ -2765,7 +2765,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_11
#ifndef CONF_DMAC_BEATSIZE_11
#define CONF_DMAC_BEATSIZE_11 0
#define CONF_DMAC_BEATSIZE_11 2
#endif
// <o> Block Action

26
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_evsys_config.h
View File

@ -561,7 +561,7 @@
// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
// <id> evsys_edgsel_3
#ifndef CONF_EDGSEL_3
#define CONF_EDGSEL_3 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
#define CONF_EDGSEL_3 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
#endif
// <y> Path selection
@ -709,7 +709,7 @@
// <i> Indicates whether event detected interrupt is enabled or not
// <id> evsys_evd_3
#ifndef CONF_EVD_3
#define CONF_EVD_3 0
#define CONF_EVD_3 1
#endif
// <q> On demand clock
@ -731,7 +731,7 @@
// <e> Channel 4 settings
// <id> evsys_channel_setting_4
#ifndef CONF_EVSYS_CHANNEL_SETTINGS_4
#define CONF_EVSYS_CHANNEL_SETTINGS_4 0
#define CONF_EVSYS_CHANNEL_SETTINGS_4 1
#endif
// <y> Edge detection
@ -742,7 +742,7 @@
// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
// <id> evsys_edgsel_4
#ifndef CONF_EDGSEL_4
#define CONF_EDGSEL_4 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
#define CONF_EDGSEL_4 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
#endif
// <y> Path selection
@ -876,7 +876,7 @@
// <0x77=>CCL LUT output 3
// <id> evsys_evgen_4
#ifndef CONF_EVGEN_4
#define CONF_EVGEN_4 0
#define CONF_EVGEN_4 35
#endif
// <q> Overrun channel interrupt
@ -890,7 +890,7 @@
// <i> Indicates whether event detected interrupt is enabled or not
// <id> evsys_evd_4
#ifndef CONF_EVD_4
#define CONF_EVD_4 0
#define CONF_EVD_4 1
#endif
// <q> On demand clock
@ -912,7 +912,7 @@
// <e> Channel 5 settings
// <id> evsys_channel_setting_5
#ifndef CONF_EVSYS_CHANNEL_SETTINGS_5
#define CONF_EVSYS_CHANNEL_SETTINGS_5 0
#define CONF_EVSYS_CHANNEL_SETTINGS_5 1
#endif
// <y> Edge detection
@ -923,7 +923,7 @@
// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
// <id> evsys_edgsel_5
#ifndef CONF_EDGSEL_5
#define CONF_EDGSEL_5 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
#define CONF_EDGSEL_5 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
#endif
// <y> Path selection
@ -1057,7 +1057,7 @@
// <0x77=>CCL LUT output 3
// <id> evsys_evgen_5
#ifndef CONF_EVGEN_5
#define CONF_EVGEN_5 0
#define CONF_EVGEN_5 36
#endif
// <q> Overrun channel interrupt
@ -1071,7 +1071,7 @@
// <i> Indicates whether event detected interrupt is enabled or not
// <id> evsys_evd_5
#ifndef CONF_EVD_5
#define CONF_EVD_5 0
#define CONF_EVD_5 1
#endif
// <q> On demand clock
@ -5920,7 +5920,7 @@
// <id> evsys_channel_2
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_2
#define CONF_CHANNEL_2 0
#define CONF_CHANNEL_2 5
#endif
// <o> Channel selection for PORT event 2
@ -6122,7 +6122,7 @@
// <id> evsys_channel_7
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_7
#define CONF_CHANNEL_7 1
#define CONF_CHANNEL_7 0
#endif
// <o> Channel selection for DMAC channel 3
@ -6322,7 +6322,7 @@
// <id> evsys_channel_12
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_12
#define CONF_CHANNEL_12 0
#define CONF_CHANNEL_12 1
#endif
//</h>

8
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_port_config.h
View File

@ -72,7 +72,7 @@
// <e> PORT Input Event 1 configuration
// <id> enable_port_input_event_1
#ifndef CONF_PORT_EVCTRL_PORT_1
#define CONF_PORT_EVCTRL_PORT_1 0
#define CONF_PORT_EVCTRL_PORT_1 1
#endif
// <h> PORT Input Event 1 configuration on PORT A
@ -109,14 +109,14 @@
// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
// <id> portb_input_event_enable_1
#ifndef CONF_PORTB_EVCTRL_PORTEI_1
#define CONF_PORTB_EVCTRL_PORTEI_1 0x0
#define CONF_PORTB_EVCTRL_PORTEI_1 0x1
#endif
// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_1
#ifndef CONF_PORTB_EVCTRL_PID_1
#define CONF_PORTB_EVCTRL_PID_1 0x0
#define CONF_PORTB_EVCTRL_PID_1 0x16
#endif
// <o> PORTB Event 1 Action
@ -127,7 +127,7 @@
// <i> These bits define the event action the PORT B will perform on event input 1
// <id> portb_event_action_1
#ifndef CONF_PORTB_EVCTRL_EVACT_1
#define CONF_PORTB_EVCTRL_EVACT_1 0
#define CONF_PORTB_EVCTRL_EVACT_1 1
#endif
// </h>

4
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_sercom_config.h
View File

@ -15,7 +15,7 @@
//<i> This defines DMA channel to be used
//<id> spi_master_dma_tx_channel
#ifndef CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL
#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 3
#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 10
#endif
// <e> SPI RX Channel Enable
@ -28,7 +28,7 @@
//<i> This defines DMA channel to be used
//<id> spi_master_dma_rx_channel
#ifndef CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL
#define CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL 0
#define CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL 1
#endif
// </e>

6
2_Motor_Master/Motor_Master/Motor_Master/EtherCAT_SlaveDef.h
View File

@ -166,7 +166,8 @@ static void update_telemetry(void)
*M1_Status = Motor1.motor_state.fault;
*M1_Mode = Motor1.motor_state.currentstate;
*M1_Joint_rel_position = Motor1.motor_status.Num_Steps;
*M1_Joint_abs_position = Motor1.motor_status.abs_position;
*M1_Joint_abs_position = Motor1.motor_setpoints.desired_position + 1 ;
//*M1_Joint_abs_position = Motor1.motor_status.abs_position;
//*M1_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1])+1);
*M1_Motor_current_bus = convert_to_mA(Motor1.Iphase_pu.Bus);
*M1_Motor_currentPhA = convert_to_mA(Motor1.Iphase_pu.A);
@ -180,7 +181,8 @@ static void update_telemetry(void)
*M2_Status = Motor2.motor_state.fault;
*M2_Mode = Motor2.motor_state.currentstate;
*M2_Joint_rel_position = Motor2.motor_status.Num_Steps;
*M2_Joint_abs_position = Motor2.motor_status.abs_position;
//*M2_Joint_abs_position = Motor2.motor_status.abs_position;
*M2_Joint_abs_position = Motor2.motor_setpoints.desired_position + 1 ;
//*M1_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1])+1);
*M2_Motor_current_bus = convert_to_mA( Motor2.Iphase_pu.Bus);
*M2_Motor_currentPhA = convert_to_mA( Motor2.Iphase_pu.A);

6
2_Motor_Master/Motor_Master/Motor_Master/Ethercat_SlaveDef.h
View File

@ -166,7 +166,8 @@ static void update_telemetry(void)
*M1_Status = Motor1.motor_state.fault;
*M1_Mode = Motor1.motor_state.currentstate;
*M1_Joint_rel_position = Motor1.motor_status.Num_Steps;
*M1_Joint_abs_position = Motor1.motor_status.abs_position;
*M1_Joint_abs_position = Motor1.motor_setpoints.desired_position + 1 ;
//*M1_Joint_abs_position = Motor1.motor_status.abs_position;
//*M1_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1])+1);
*M1_Motor_current_bus = convert_to_mA(Motor1.Iphase_pu.Bus);
*M1_Motor_currentPhA = convert_to_mA(Motor1.Iphase_pu.A);
@ -180,7 +181,8 @@ static void update_telemetry(void)
*M2_Status = Motor2.motor_state.fault;
*M2_Mode = Motor2.motor_state.currentstate;
*M2_Joint_rel_position = Motor2.motor_status.Num_Steps;
*M2_Joint_abs_position = Motor2.motor_status.abs_position;
//*M2_Joint_abs_position = Motor2.motor_status.abs_position;
*M2_Joint_abs_position = Motor2.motor_setpoints.desired_position + 1 ;
//*M1_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1])+1);
*M2_Motor_current_bus = convert_to_mA( Motor2.Iphase_pu.Bus);
*M2_Motor_currentPhA = convert_to_mA( Motor2.Iphase_pu.A);

18
2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj
View File

@ -150,7 +150,7 @@
<AcmeProjectActionInfo Action="File" Source="hri/hri_usb_e51.h" IsConfig="false" Hash="x6M7vYgNCS2oECqykr5+yw" />
<AcmeProjectActionInfo Action="File" Source="hri/hri_wdt_e51.h" IsConfig="false" Hash="o9Rg/hyuMzwOCphVc7uG1w" />
<AcmeProjectActionInfo Action="File" Source="main.c" IsConfig="false" Hash="k0AH7j+BrmdFhBPzCCMptA" />
<AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="U0r+mqNyUZcAht0NLNN5yg" />
<AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="G20g4A90o1iiMw5JKqZlrQ" />
<AcmeProjectActionInfo Action="File" Source="driver_init.h" IsConfig="false" Hash="NyJtBqCuH2RlTy0iltvcfg" />
<AcmeProjectActionInfo Action="File" Source="atmel_start_pins.h" IsConfig="false" Hash="q332kmNEqTBha3F9F86pCg" />
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="yuNriNBbj5kyY6X2I3Qu+A" />
@ -197,7 +197,7 @@
<AcmeProjectActionInfo Action="File" Source="hpl/qspi/hpl_qspi.c" IsConfig="false" Hash="woXbbCFkSWus6J14PHJlHw" />
<AcmeProjectActionInfo Action="File" Source="hpl/ramecc/hpl_ramecc.c" IsConfig="false" Hash="pMdmwVWBg16VG8HOwA3DPw" />
<AcmeProjectActionInfo Action="File" Source="hpl/sercom/hpl_sercom.c" IsConfig="false" Hash="hcMq5dgdlyb9xXr1YOQnMQ" />
<AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.c" IsConfig="false" Hash="TvX0gjbe0pQlKc43XVzIRQ" />
<AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.c" IsConfig="false" Hash="rgTvxuBnL9g4Ehy4toqpuA" />
<AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.h" IsConfig="false" Hash="zTBTKMmLh2GsbqmbMsUX8g" />
<AcmeProjectActionInfo Action="File" Source="hpl/tcc/hpl_tcc.c" IsConfig="false" Hash="DC3UZSTUv1CDjekNxClhVg" />
<AcmeProjectActionInfo Action="File" Source="hpl/tcc/hpl_tcc.h" IsConfig="false" Hash="rdWkAK12qkOYV59tWwzy6A" />
@ -206,16 +206,16 @@
<AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="IJeJ3sDxG9f3mmsLxoMLlA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_ccl_config.h" IsConfig="true" Hash="Q1yijLwNXjFOsGrwEEma+g" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="ZoER5eKK8H7JWexdQhfwww" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="G4WVXUcIlVMxjaDgFB7QRQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="S8xJxIaG6pS6BEvDgxKh9w" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="UCqlM36hOu88a+CHb/vycw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="razEOr+ddCtzmAhy4QVzhg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_mclk_config.h" IsConfig="true" Hash="pxBzoQXTG66x4dbzVzxteg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_osc32kctrl_config.h" IsConfig="true" Hash="HgvzEqDUH4jq/syjj/+G+Q" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Uje5LXAS+nQpGryt9t0fYA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="hX4+5+KlqrwduLW2+CPKfg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="OHReh3YoteXQnOg0JJMWVg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_qspi_config.h" IsConfig="true" Hash="CwZ360eeEYs7T9SYFSvDug" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="NOEuutypdbfpBKOWCPUPuA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="0jM1u/XQkwzOqyPduvYuCA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_tcc_config.h" IsConfig="true" Hash="2LU7afZ/3Yx7FE2KzF9dSQ" />
<AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="s/tLl+lpMPQWNUrjuAL0rQ" />
</AcmeActionInfos>
@ -382,7 +382,6 @@
<armgcc.compiler.directories.IncludePaths>
<ListValues>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -407,6 +406,7 @@
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
</ListValues>
</armgcc.compiler.directories.IncludePaths>
<armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
@ -433,7 +433,6 @@
<armgcc.assembler.general.IncludePaths>
<ListValues>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -458,13 +457,13 @@
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
</ListValues>
</armgcc.assembler.general.IncludePaths>
<armgcc.assembler.debugging.DebugLevel>Default (-g)</armgcc.assembler.debugging.DebugLevel>
<armgcc.preprocessingassembler.general.IncludePaths>
<ListValues>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -489,6 +488,7 @@
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
</ListValues>
</armgcc.preprocessingassembler.general.IncludePaths>
<armgcc.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcc.preprocessingassembler.debugging.DebugLevel>

123
2_Motor_Master/Motor_Master/Motor_Master/configuration.h
View File

@ -15,13 +15,17 @@
#include "atmel_start_pins.h"
#include "bldc.h"
#include "interrupts.h"
#include "hpl_sercom_config.h"
// ----------------------------------------------------------------------
// ADC DMA Initialization
// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
// ----------------------------------------------------------------------
#define DMAC_CHANNEL_ADC_SEQ 2U
#define DMAC_CHANNEL_ADC_SRAM 1U
#define CONF_ADC_0_ADC_RES_READY_CHANNEL 4U
#define CONF_ADC_1_ADC_RES_READY_CHANNEL 5U
#define CONF_ADC_0_SEQUENCER_CHANNEL 6U
#define CONF_ADC_1_SEQUENCER_CHANNEL 7U
/* Single Ended */
//const uint32_t adc_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808};
@ -36,14 +40,7 @@ struct _dma_resource *adc_dmac_sequence_resource;
// PWM Timer Initialization
// ----------------------------------------------------------------------
inline static void configure_tcc_pwm(void)
{
//gpio_set_pin_pull_mode(M1_HALLA, GPIO_PULL_UP);
//gpio_set_pin_pull_mode(M1_HALLB, GPIO_PULL_UP);
//gpio_set_pin_pull_mode(M1_HALLC, GPIO_PULL_UP);
//gpio_set_pin_pull_mode(M2_HALLA, GPIO_PULL_UP);
//gpio_set_pin_pull_mode(M2_HALLB, GPIO_PULL_UP);
//gpio_set_pin_pull_mode(M2_HALLC, GPIO_PULL_UP);
{
/* TCC0 */
hri_tcc_set_WEXCTRL_OTMX_bf(TCC0, 0x02);
@ -92,17 +89,33 @@ inline static void configure_tcc_pwm(void)
}
inline void configure_adc(void)
/* Peripherals should be configured before interacting with dma
* CH0 - QSPI_RX - For ECAT DMA Mode - Currently Disabled in ASTART
* CH1 - SERCOM1_RX(SPI1) - Master-Slave IF - Beat Transfer Event Drives CS Pin
* CH2 - SERCOM2_RX(SPI2) - Expansion IF (EMG) - Beat Transfer Event Drives CS Pin
* CH3 - SERCOM5_RX(SPI3) - Angle Sensor
* CH4 - ADC0 - Result Ready (Unused on master) - Currently Disabled in ASTART
* CH5 - ADC1 - Result Ready
* CH6 - ADC0 - Sequencer (Unused on master) - Currently Disabled in ASTART
* CH7 - ADC1 - Sequencer - Triggered by TCC0 overflow event
* CH8 - SERCOM2_TX(SPI2)
* CH9 - SERCOM5_TX(SPI3)
* CH10 - SERCOM1_TX(SPI1)
* CH11 - QSPI_TX - For ECAT DMA Mode - Currently Disabled in ASTART
*/
inline static void init_dma(void)
{
adc_sync_enable_channel(&ADC_1, 0);
//adc_sync_enable_channel(&ADC_1, 0);
//adc_async_register_callback(&ADC_0, 0, ADC_ASYNC_CONVERT_CB, adc_cb);
//adc_async_register_callback(&ADC_1, 0, ADC_ASYNC_CONVERT_CB, convert_cb_ADC_1);
//adc_async_start_conversion(&ADC_0);
//adc_async_start_conversion(&ADC_1);
spi_master_init_dma_descriptors();
adc_init_dma_descriptors();
}
inline static void adc_init_dma(void)
// ----------------------------------------------------------------------
// ADC Initialization
// ----------------------------------------------------------------------
inline void adc_init_dma_descriptors(void)
{
adc_sram_dmac_init();
adc_dmac_sequence_init();
@ -110,39 +123,34 @@ inline static void adc_init_dma(void)
hri_adc_set_DSEQCTRL_AUTOSTART_bit(ADC1);
}
inline void adc_dmac_sequence_init()
{
/* Configure the DMAC source address, destination address,
* next descriptor address, data count and Enable the DMAC Channel
*/
_dma_set_source_address(DMAC_CHANNEL_ADC_SEQ, (const void *)adc_seq_regs);
_dma_set_destination_address(DMAC_CHANNEL_ADC_SEQ, (const void *)&ADC1->DSEQDATA.reg);
_dma_set_data_amount(DMAC_CHANNEL_ADC_SEQ, 4);
_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SEQ, DMAC_CHANNEL_ADC_SEQ);
_dma_enable_transaction(DMAC_CHANNEL_ADC_SEQ, false);
//_dma_get_channel_resource(&adc_dmac_sequence_resource, DMAC_CHANNEL_ADC_SEQ);
//adc_dmac_sequence_resource[0].dma_cb.error = dummy2;
//adc_dmac_sequence_resource[0].dma_cb.suspend = dummy3;
//adc_dmac_sequence_resource[0].dma_cb.transfer_done = dummy4;
hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[DMAC_CHANNEL_ADC_SEQ], 0x01); //Suspend
_dma_set_source_address(CONF_ADC_1_SEQUENCER_CHANNEL, (const void *)adc_seq_regs);
_dma_set_destination_address(CONF_ADC_1_SEQUENCER_CHANNEL, (const void *)&ADC1->DSEQDATA.reg);
_dma_set_data_amount(CONF_ADC_1_SEQUENCER_CHANNEL, 4);
_dma_set_next_descriptor(CONF_ADC_1_SEQUENCER_CHANNEL, CONF_ADC_1_SEQUENCER_CHANNEL);
_dma_enable_transaction(CONF_ADC_1_SEQUENCER_CHANNEL, false);
hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[CONF_ADC_1_SEQUENCER_CHANNEL], 0x01); //Suspend
}
inline void adc_sram_dmac_init()
{
/* Configure the DMAC source address, destination address,
* next descriptor address, data count and Enable the DMAC Channel */
_dma_set_source_address(DMAC_CHANNEL_ADC_SRAM, (const void *)&ADC1->RESULT.reg);
_dma_set_destination_address(DMAC_CHANNEL_ADC_SRAM, (const void *)adc_res);
_dma_set_data_amount(DMAC_CHANNEL_ADC_SRAM, 4);
_dma_set_irq_state(DMAC_CHANNEL_ADC_SRAM, DMA_TRANSFER_COMPLETE_CB, true);
_dma_get_channel_resource(&adc_sram_dma_resource, DMAC_CHANNEL_ADC_SRAM);
_dma_set_source_address(CONF_ADC_1_ADC_RES_READY_CHANNEL, (const void *)&ADC1->RESULT.reg);
_dma_set_destination_address(CONF_ADC_1_ADC_RES_READY_CHANNEL, (const void *)adc_res);
_dma_set_data_amount(CONF_ADC_1_ADC_RES_READY_CHANNEL, 4);
_dma_set_irq_state(CONF_ADC_1_ADC_RES_READY_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
_dma_get_channel_resource(&adc_sram_dma_resource, CONF_ADC_1_ADC_RES_READY_CHANNEL);
adc_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback;
_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SRAM, DMAC_CHANNEL_ADC_SRAM);
_dma_enable_transaction(DMAC_CHANNEL_ADC_SRAM, false);
_dma_set_next_descriptor(CONF_ADC_1_ADC_RES_READY_CHANNEL, CONF_ADC_1_ADC_RES_READY_CHANNEL); /*?????*/
_dma_enable_transaction(CONF_ADC_1_ADC_RES_READY_CHANNEL, false);
}
// ----------------------------------------------------------------------
// Init SPI DMA communication between Master & Slave Board
// SPI DMA communication between Master & Slave Board
// ----------------------------------------------------------------------
#define MASTER_BUFFER_SIZE 64
@ -152,40 +160,41 @@ inline void adc_sram_dmac_init()
extern DmacDescriptor _descriptor_section[DMAC_CH_NUM];
extern DmacDescriptor _write_back_section[DMAC_CH_NUM];
#define DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE 0u
#define DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT 3U
void boardToBoardTransferInit(void)
{
struct io_descriptor *io;
spi_m_dma_get_io_descriptor(&SPI_1_MSIF, &io);
spi_m_dma_register_callback(&SPI_1_MSIF, SPI_M_DMA_CB_RX_DONE, b2bTransferComplete_cb);
//spi_m_dma_register_callback(&SPI_1_MSIF, SPI_M_DMA_CB_RX_DONE, b2bTransferComplete_cb);
//SERCOM4->SPI.CTRLC.bit.DATA32B = true;
SERCOM1->SPI.CTRLC.bit.ICSPACE = 5;
SERCOM1->SPI.LENGTH.bit.LENEN = true;
SERCOM1->SPI.LENGTH.bit.LEN = 64;
SERCOM1->SPI.CTRLC.bit.ICSPACE = 4;
SERCOM1->SPI.CTRLC.bit.DATA32B= true;
gpio_set_pin_level(SPI1_CS, true);
spi_m_dma_enable(&SPI_1_MSIF);
}
void init_spi_master_dma_descriptors()
void spi_master_init_dma_descriptors()
{
_dma_set_source_address(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE,
_dma_set_source_address(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL,
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
_dma_set_destination_address(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, &QSPI_tx_buffer[16]);
_dma_set_data_amount(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, MASTER_BUFFER_SIZE_LONG);
_dma_set_destination_address(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, &QSPI_tx_buffer[16]);
_dma_set_data_amount(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, MASTER_BUFFER_SIZE_LONG);
_dma_set_next_descriptor(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL);
_dma_set_source_address(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT, &QSPI_rx_buffer[16]);
_dma_set_destination_address(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT,
_dma_set_source_address(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL, &QSPI_rx_buffer[16]);
_dma_set_destination_address(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL,
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
_dma_set_data_amount(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT, MASTER_BUFFER_SIZE_LONG);
_dma_set_data_amount(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL, MASTER_BUFFER_SIZE_LONG);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE]);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT]);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL]);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL]);
/* callback */
struct _dma_resource *resource_rx, *resource_tx;
_dma_get_channel_resource(&resource_rx, DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE);
_dma_get_channel_resource(&resource_tx, DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT);
//struct _dma_resource *resource_rx, *resource_tx;
//_dma_get_channel_resource(&resource_rx, CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL);
//_dma_get_channel_resource(&resource_tx, CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL);
//resource_rx->dma_cb.transfer_done = spi_slave_rx_complete_cb;
//resource_tx->dma_cb.transfer_done = b2bTransferComplete_cb;
@ -195,4 +204,6 @@ void init_spi_master_dma_descriptors()
}
#endif /* CONFIGURATION_H_ */

2
2_Motor_Master/Motor_Master/Motor_Master/driver_init.c
View File

@ -163,6 +163,8 @@ void EVENT_SYSTEM_0_init(void)
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_1, CONF_GCLK_EVSYS_CHANNEL_1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_2, CONF_GCLK_EVSYS_CHANNEL_2_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_3, CONF_GCLK_EVSYS_CHANNEL_3_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_4, CONF_GCLK_EVSYS_CHANNEL_4_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_5, CONF_GCLK_EVSYS_CHANNEL_5_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);

33
2_Motor_Master/Motor_Master/Motor_Master/hpl/tc/tc_lite.c
View File

@ -60,8 +60,8 @@ int8_t TIMER_0_init()
| 0 << TC_CTRLA_PRESCSYNC_Pos /* Prescaler and Counter Synchronization: 0 */
| 0 << TC_CTRLA_ONDEMAND_Pos /* Clock On Demand: disabled */
| 0 << TC_CTRLA_RUNSTDBY_Pos /* Run in Standby: disabled */
| 5 << TC_CTRLA_PRESCALER_Pos /* Setting: 5 */
| 0x0 << TC_CTRLA_MODE_Pos); /* Operating Mode: 0x0 */
| 7 << TC_CTRLA_PRESCALER_Pos /* Setting: 7 */
| 0x1 << TC_CTRLA_MODE_Pos); /* Operating Mode: 0x1 */
hri_tc_write_CTRLB_reg(TC0,
0 << TC_CTRLBSET_CMD_Pos /* Command: 0 */
@ -69,31 +69,32 @@ int8_t TIMER_0_init()
| 0 << TC_CTRLBCLR_LUPD_Pos /* Setting: disabled */
| 0 << TC_CTRLBSET_DIR_Pos); /* Counter Direction: disabled */
hri_tc_write_WAVE_reg(TC0,1); /* Waveform Generation Mode: 0 */
// hri_tc_write_WAVE_reg(TC0,0); /* Waveform Generation Mode: 0 */
// hri_tc_write_DRVCTRL_reg(TC0,0 << TC_DRVCTRL_INVEN1_Pos /* Output Waveform 1 Invert Enable: disabled */
// | 0 << TC_DRVCTRL_INVEN0_Pos); /* Output Waveform 0 Invert Enable: disabled */
// hri_tc_write_DBGCTRL_reg(TC0,0); /* Run in debug: 0 */
hri_tccount16_write_CC_reg(TC0, 0, 0x752); /* Compare/Capture Value: 0x752 */
hri_tccount8_write_CC_reg(TC0, 0, 0x75); /* Compare/Capture Value: 0x75 */
// hri_tccount16_write_CC_reg(TC0, 1 ,0x0); /* Compare/Capture Value: 0x0 */
hri_tccount8_write_CC_reg(TC0, 1, 0xb4); /* Compare/Capture Value: 0xb4 */
// hri_tccount16_write_COUNT_reg(TC0,0x0); /* Counter Value: 0x0 */
// hri_tccount8_write_COUNT_reg(TC0,0x0); /* Counter Value: 0x0 */
hri_tc_write_EVCTRL_reg(
TC0,
1 << TC_EVCTRL_MCEO0_Pos /* Match or Capture Channel 0 Event Output Enable: enabled */
| 0 << TC_EVCTRL_MCEO1_Pos /* Match or Capture Channel 1 Event Output Enable: disabled */
| 0 << TC_EVCTRL_OVFEO_Pos /* Overflow/Underflow Event Output Enable: disabled */
| 0 << TC_EVCTRL_TCEI_Pos /* TC Event Input: disabled */
| 0 << TC_EVCTRL_TCINV_Pos /* TC Inverted Event Input: disabled */
| 0); /* Event Action: 0 */
hri_tc_write_PER_reg(TC0, 0xff); /* Period Value: 0xff */
hri_tc_write_EVCTRL_reg(TC0,
1 << TC_EVCTRL_MCEO0_Pos /* Match or Capture Channel 0 Event Output Enable: enabled */
| 1 << TC_EVCTRL_MCEO1_Pos /* Match or Capture Channel 1 Event Output Enable: enabled */
| 1 << TC_EVCTRL_OVFEO_Pos /* Overflow/Underflow Event Output Enable: enabled */
| 0 << TC_EVCTRL_TCEI_Pos /* TC Event Input: disabled */
| 0 << TC_EVCTRL_TCINV_Pos /* TC Inverted Event Input: disabled */
| 0); /* Event Action: 0 */
hri_tc_write_INTEN_reg(TC0,
1 << TC_INTENSET_MC0_Pos /* Match or Capture Channel 0 Interrupt Enable: enabled */
| 0 << TC_INTENSET_MC1_Pos /* Match or Capture Channel 1 Interrupt Enable: disabled */
0 << TC_INTENSET_MC0_Pos /* Match or Capture Channel 0 Interrupt Enable: disabled */
| 1 << TC_INTENSET_MC1_Pos /* Match or Capture Channel 1 Interrupt Enable: enabled */
| 0 << TC_INTENSET_ERR_Pos /* Error Interrupt Enable: disabled */
| 0 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: disabled */

64
2_Motor_Master/Motor_Master/Motor_Master/interrupts.h
View File

@ -9,26 +9,52 @@
#ifndef INTERRUPTS_H_
#define INTERRUPTS_H_
static void One_ms_cycle_callback(const struct timer_task *const timer_task)
{
if ((ecat_state == wait2)|(ecat_state == wait))
/* TC0 - Interrupt Handler
* Configured to trigger @ 1ms
*/
void TC0_Handler( void ){
if (TC0->COUNT8.INTFLAG.bit.OVF && TC0->COUNT8.INTENSET.bit.OVF)
{
ecat_state= write_fifo;
run_ECAT =true;
TC0->COUNT8.INTFLAG.bit.OVF = 0x01;
}
if (TC0->COUNT8.INTFLAG.bit.MC0 && TC0->COUNT8.INTENSET.bit.MC0)
{
TC0->COUNT8.INTFLAG.bit.MC0 = 0x01;
}
if (TC0->COUNT8.INTFLAG.bit.MC1 && TC0->COUNT8.INTENSET.bit.MC1)
{
TC0->COUNT8.INTFLAG.bit.MC1 = 0x01;
if ((ecat_state == wait2)|(ecat_state == wait))
{
ecat_state= write_fifo;
run_ECAT =true;
}
Motor1.timerflags.motor_telemetry_flag = true;
}
Motor1.timerflags.motor_telemetry_flag = true;
Motor2.timerflags.motor_telemetry_flag = true;
/*Master Slave Transfer */
//tx_buffer[0] += 1;
//tx_buffer[31] += 1;
//gpio_set_pin_level(SPI1_CS, false);
//spi_m_dma_transfer(&SPI_1_MSIF, (uint8_t*)Slave_1.tx_buffer, (uint8_t*)Slave_1.rx_buffer, MASTER_BUFFER_SIZE);
//run_ECAT = true;
}
//static void One_ms_cycle_callback(const struct timer_task *const timer_task)
//{
//if ((ecat_state == wait2)|(ecat_state == wait))
//{
//ecat_state= write_fifo;
//run_ECAT =true;
//}
//Motor1.timerflags.motor_telemetry_flag = true;
//Motor2.timerflags.motor_telemetry_flag = true;
//
//
///*Master Slave Transfer */
////tx_buffer[0] += 1;
////tx_buffer[31] += 1;
////gpio_set_pin_level(SPI1_CS, false);
////spi_m_dma_transfer(&SPI_1_MSIF, (uint8_t*)Slave_1.tx_buffer, (uint8_t*)Slave_1.rx_buffer, MASTER_BUFFER_SIZE);
//
////run_ECAT = true;
//}
// ----------------------------------------------------------------------
// Master/Slave IF Callback
@ -36,8 +62,8 @@ static void One_ms_cycle_callback(const struct timer_task *const timer_task)
static void b2bTransferComplete_cb(struct _dma_resource *resource)
{
PORT->Group[1].OUTSET.reg = (1<<GPIO_PIN(SPI1_CS));
volatile int x = 0;
//PORT->Group[1].OUTSET.reg = (1<<GPIO_PIN(SPI1_CS));
//volatile int x = 0;
//PORT->Group[GPIO_PORTB].OUTCLR.reg = (1<<Slave_1->SS_pin);
//gpio_set_pin_level(SPI1_CS, true);
}
@ -50,7 +76,7 @@ static void b2bTransferComplete_cb(struct _dma_resource *resource)
// ----------------------------------------------------------------------
static void pwm_cb(const struct pwm_descriptor *const descr)
{
volatile int x = 0;
}
void adc_sram_dma_callback(struct _dma_resource *adc_dma_res)

51
2_Motor_Master/Motor_Master/Motor_Master/main.c
View File

@ -48,14 +48,7 @@ void process_currents()
Motor2.timerflags.current_loop_tic = true;
}
void TC0_Handler( void ){
if (TC0->COUNT16.INTFLAG.bit.MC0 == 0x01){
TC0->COUNT16.INTFLAG.bit.MC0 = 0x01;
Motor1.timerflags.motor_telemetry_flag = true;
}
}
void enable_NVIC_IRQ(void)
{
@ -72,7 +65,7 @@ void enable_NVIC_IRQ(void)
NVIC_EnableIRQ(TCC1_0_IRQn);
NVIC_EnableIRQ(EIC_2_IRQn);
NVIC_EnableIRQ(SERCOM1_1_IRQn);
NVIC_SetPriority(SERCOM1_1_IRQn, 1);
//NVIC_SetPriority(SERCOM1_1_IRQn, 1);
NVIC_EnableIRQ(TC0_IRQn);
//NVIC_EnableIRQ(TC0_IRQn);
//NVIC_SetPriority(EIC_2_IRQn, 3);
@ -95,8 +88,11 @@ void APPLICATION_StateMachine(void)
case SYSTEM_INIT:
/* Toggle driver reset Latch */
gpio_set_pin_level(M1_RST, true);
delay_us(100);
gpio_set_pin_level(M1_RST, false);
delay_us(100);
gpio_set_pin_level(M2_RST, true);
delay_us(100);
gpio_set_pin_level(M2_RST, false);
/* Update State Variables */
applicationStatus.previousstate = applicationStatus.currentstate;
@ -157,17 +153,16 @@ int main(void)
configure_tcc_pwm();
adc_sync_enable_channel(&ADC_1, 6);
/* SPI & DMA Configs */
/* SPI Config */
boardToBoardTransferInit();
init_spi_master_dma_descriptors();
adc_init_dma();
/* DMA Configs */
init_dma();
ECAT_STATE_MACHINE();
custom_logic_enable();
//angle_sensor_init();
//initialize_ads();
/* External IRQ Config */
custom_logic_enable();
enable_NVIC_IRQ();
__enable_irq();
@ -176,24 +171,30 @@ int main(void)
/* Replace with your application code */
while (1) {
//if (Motor1.timerflags.adc_readings_ready_tic) {process_currents();}
if (Motor1.timerflags.adc_readings_ready_tic) {process_currents();}
if (Motor1.timerflags.motor_telemetry_flag) {
Motor1.timerflags.motor_telemetry_flag = false;
update_telemetry();
update_setpoints();
if (DMAC->Channel[DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT].CHSTATUS.bit.PEND == true)
Motor1.timerflags.motor_telemetry_flag = false;
delay_us(10);
DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
if (DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHSTATUS.bit.PEND == true)
{
volatile int x = 0;
}
//PORT->Group[1].OUTCLR.reg = (1<<GPIO_PIN(SPI1_CS));
DMAC->Channel[DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
DMAC->Channel[DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
//_dma_enable_transaction(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, false);
//_dma_enable_transaction(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT, false);
int16_t* angles;
update_telemetry();
update_setpoints();
//PORT->Group[1].OUTCLR.reg = (1<<GPIO_PIN(SPI1_CS));
//_dma_enable_transaction(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, false);
//_dma_enable_transaction(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL, false);
volatile int16_t* angles = 0;
//angles = read_angle();
//Motor1.motor_status.abs_position = degrees(angles[0]);
//Motor2.motor_status.abs_position = degrees(angles[1]);

20
2_Motor_Slave/Motor_Slave/Motor_Slave/.atmelstart/atmel_start_config.atstart
View File

@ -1410,11 +1410,11 @@ drivers:
functionality: System
api: HAL:HPL:GCLK
configuration:
$input: 12000000
$input_id: External Crystal Oscillator 8-48MHz (XOSC1)
RESERVED_InputFreq: 12000000
RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1)
_$freq_output_Generic clock generator 0: 120000000
$input: 100000000
$input_id: Digital Phase Locked Loop (DPLL1)
RESERVED_InputFreq: 100000000
RESERVED_InputFreq_id: Digital Phase Locked Loop (DPLL1)
_$freq_output_Generic clock generator 0: 100000000
_$freq_output_Generic clock generator 1: 2000000
_$freq_output_Generic clock generator 10: 12000000
_$freq_output_Generic clock generator 11: 12000000
@ -1556,11 +1556,11 @@ drivers:
functionality: System
api: HAL:HPL:MCLK
configuration:
$input: 120000000
$input: 100000000
$input_id: Generic clock generator 0
RESERVED_InputFreq: 120000000
RESERVED_InputFreq: 100000000
RESERVED_InputFreq_id: Generic clock generator 0
_$freq_output_CPU: 120000000
_$freq_output_CPU: 100000000
cpu_clock_source: Generic clock generator 0
cpu_div: '1'
enable_cpu_clock: true
@ -1623,7 +1623,7 @@ drivers:
RESERVED_InputFreq_id: Generic clock generator 1
_$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
_$freq_output_Digital Phase Locked Loop (DPLL0): 47985664
_$freq_output_Digital Phase Locked Loop (DPLL1): 120000000
_$freq_output_Digital Phase Locked Loop (DPLL1): 100000000
_$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000
_$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000
dfll_arch_bplckc: false
@ -1674,7 +1674,7 @@ drivers:
fdpll1_arch_wuf: false
fdpll1_clock_dcofilter: 0
fdpll1_clock_div: 0
fdpll1_ldr: 59
fdpll1_ldr: 49
fdpll1_ldrfrac: 0
fdpll1_ref_clock: Generic clock generator 1
xosc0_arch_cfden: false

2
2_Motor_Slave/Motor_Slave/Motor_Slave/Config/hpl_oscctrl_config.h
View File

@ -568,7 +568,7 @@
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
// <id> fdpll1_ldr
#ifndef CONF_FDPLL1_LDR
#define CONF_FDPLL1_LDR 0x3b
#define CONF_FDPLL1_LDR 0x31
#endif
// <o> Clock Divider <0x0-0x7FF>

52
2_Motor_Slave/Motor_Slave/Motor_Slave/Config/peripheral_clk_config.h
View File

@ -41,7 +41,7 @@
* \brief ADC0's Clock frequency
*/
#ifndef CONF_GCLK_ADC0_FREQUENCY
#define CONF_GCLK_ADC0_FREQUENCY 120000000
#define CONF_GCLK_ADC0_FREQUENCY 100000000
#endif
// <y> ADC Clock Source
@ -81,7 +81,7 @@
* \brief ADC1's Clock frequency
*/
#ifndef CONF_GCLK_ADC1_FREQUENCY
#define CONF_GCLK_ADC1_FREQUENCY 120000000
#define CONF_GCLK_ADC1_FREQUENCY 100000000
#endif
// <y> CCL Clock Source
@ -121,7 +121,7 @@
* \brief CCL's Clock frequency
*/
#ifndef CONF_GCLK_CCL_FREQUENCY
#define CONF_GCLK_CCL_FREQUENCY 120000000
#define CONF_GCLK_CCL_FREQUENCY 100000000
#endif
// <y> EIC Clock Source
@ -161,7 +161,7 @@
* \brief EIC's Clock frequency
*/
#ifndef CONF_GCLK_EIC_FREQUENCY
#define CONF_GCLK_EIC_FREQUENCY 120000000
#define CONF_GCLK_EIC_FREQUENCY 100000000
#endif
// <y> EVSYS Channel 0 Clock Source
@ -202,7 +202,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000
#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 100000000
#endif
// <y> EVSYS Channel 1 Clock Source
@ -243,7 +243,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000
#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 100000000
#endif
// <y> EVSYS Channel 2 Clock Source
@ -284,7 +284,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000
#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 100000000
#endif
// <y> EVSYS Channel 3 Clock Source
@ -325,7 +325,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000
#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 100000000
#endif
// <y> EVSYS Channel 4 Clock Source
@ -366,7 +366,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000
#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 100000000
#endif
// <y> EVSYS Channel 5 Clock Source
@ -407,7 +407,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000
#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 100000000
#endif
// <y> EVSYS Channel 6 Clock Source
@ -448,7 +448,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000
#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 100000000
#endif
// <y> EVSYS Channel 7 Clock Source
@ -489,7 +489,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000
#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 100000000
#endif
// <y> EVSYS Channel 8 Clock Source
@ -530,7 +530,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000
#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 100000000
#endif
// <y> EVSYS Channel 9 Clock Source
@ -571,7 +571,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000
#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 100000000
#endif
// <y> EVSYS Channel 10 Clock Source
@ -612,7 +612,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000
#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 100000000
#endif
// <y> EVSYS Channel 11 Clock Source
@ -653,7 +653,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000
#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 100000000
#endif
/**
@ -661,7 +661,7 @@
* \brief CPU's Clock frequency
*/
#ifndef CONF_CPU_FREQUENCY
#define CONF_CPU_FREQUENCY 120000000
#define CONF_CPU_FREQUENCY 100000000
#endif
// <y> Core Clock Source
@ -733,7 +733,7 @@
* \brief SERCOM0's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 120000000
#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 100000000
#endif
/**
@ -813,7 +813,7 @@
* \brief SERCOM1's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 120000000
#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 100000000
#endif
/**
@ -893,7 +893,7 @@
* \brief SERCOM2's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 120000000
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 100000000
#endif
/**
@ -973,7 +973,7 @@
* \brief SERCOM5's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 120000000
#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 100000000
#endif
/**
@ -1021,7 +1021,7 @@
* \brief TC0's Clock frequency
*/
#ifndef CONF_GCLK_TC0_FREQUENCY
#define CONF_GCLK_TC0_FREQUENCY 120000000
#define CONF_GCLK_TC0_FREQUENCY 100000000
#endif
// <y> TC Clock Source
@ -1061,7 +1061,7 @@
* \brief TC2's Clock frequency
*/
#ifndef CONF_GCLK_TC2_FREQUENCY
#define CONF_GCLK_TC2_FREQUENCY 120000000
#define CONF_GCLK_TC2_FREQUENCY 100000000
#endif
// <y> TC Clock Source
@ -1101,7 +1101,7 @@
* \brief TC4's Clock frequency
*/
#ifndef CONF_GCLK_TC4_FREQUENCY
#define CONF_GCLK_TC4_FREQUENCY 120000000
#define CONF_GCLK_TC4_FREQUENCY 100000000
#endif
// <y> TCC Clock Source
@ -1141,7 +1141,7 @@
* \brief TCC0's Clock frequency
*/
#ifndef CONF_GCLK_TCC0_FREQUENCY
#define CONF_GCLK_TCC0_FREQUENCY 120000000
#define CONF_GCLK_TCC0_FREQUENCY 100000000
#endif
// <y> TCC Clock Source
@ -1181,7 +1181,7 @@
* \brief TCC1's Clock frequency
*/
#ifndef CONF_GCLK_TCC1_FREQUENCY
#define CONF_GCLK_TCC1_FREQUENCY 120000000
#define CONF_GCLK_TCC1_FREQUENCY 100000000
#endif
// <<< end of configuration section >>>

4
2_Motor_Slave/Motor_Slave/Motor_Slave/MSIF_slave.h
View File

@ -160,7 +160,7 @@ static void update_telemetry(void)
*M3_Status = Motor1.motor_state.fault;
*M3_Mode = Motor1.motor_state.currentstate;
*M3_Joint_rel_position = Motor1.motor_status.Num_Steps;
//*M3_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[1];
*M3_Joint_abs_position = Motor1.motor_setpoints.desired_position + 1 ;
//*M3_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1]+1);
*M3_Motor_current_bus = convert_to_mA(Motor1.Iphase_pu.Bus);
*M3_Motor_currentPhA = convert_to_mA(Motor1.Iphase_pu.A);
@ -174,7 +174,7 @@ static void update_telemetry(void)
*M4_Status = Motor2.motor_state.fault;
*M4_Mode = Motor2.motor_state.currentstate;
*M4_Joint_rel_position = Motor2.motor_status.Num_Steps;
//*M3_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[1];
*M4_Joint_abs_position = Motor2.motor_setpoints.desired_position + 1 ;
//*M3_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1]+1);
*M4_Motor_current_bus = convert_to_mA( Motor2.Iphase_pu.Bus);
*M4_Motor_currentPhA = convert_to_mA( Motor2.Iphase_pu.A);

6
2_Motor_Slave/Motor_Slave/Motor_Slave/Motor_Slave.cproj
View File

@ -218,12 +218,12 @@
<AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_mclk_config.h" IsConfig="true" Hash="pxBzoQXTG66x4dbzVzxteg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_osc32kctrl_config.h" IsConfig="true" Hash="HgvzEqDUH4jq/syjj/+G+Q" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Uje5LXAS+nQpGryt9t0fYA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Xe5v62bijwZLOPLD+rPcrA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="rMTNR+5FXtu+wfT1NbfRRA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="Vm7v7a4F40Wzv368v+pLEw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_tc_config.h" IsConfig="true" Hash="T93Kr6C+WDuufZob89oPeg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_tcc_config.h" IsConfig="true" Hash="2LU7afZ/3Yx7FE2KzF9dSQ" />
<AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="6eU7+fZNEY4RDC37iHjvJQ" />
<AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="GuMSQybrrAFfKR9u1GzqsQ" />
<AcmeProjectActionInfo Action="File" Source="config/bno055_config.h" IsConfig="true" Hash="2hRq4Yx9B3nZuMEdrYIG8Q" />
</AcmeActionInfos>
<NonsecureFilesInfo />
@ -419,7 +419,7 @@
<armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
<armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
<armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
<armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
<armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
<armgcc.linker.general.UseNewlibNano>True</armgcc.linker.general.UseNewlibNano>
<armgcc.linker.libraries.Libraries>
<ListValues>

10
2_Motor_Slave/Motor_Slave/Motor_Slave/configuration.h
View File

@ -174,8 +174,10 @@ void boardToBoardTransferInit(void)
{
hri_sercomspi_set_CTRLB_PLOADEN_bit(SPI_1_MSIF.dev.prvt);
SERCOM1->SPI.CTRLC.bit.ICSPACE = 5;
//SERCOM1->SPI.CTRLC.bit.ICSPACE = 5;
SERCOM1->SPI.CTRLC.bit.DATA32B= true;
//SERCOM1->SPI.LENGTH.bit.LENEN = true;
//SERCOM1->SPI.LENGTH.bit.LEN = 16;
spi_s_sync_enable(&SPI_1_MSIF);
}
@ -185,12 +187,14 @@ void init_spi_slave_dma_descriptors()
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
_dma_set_destination_address(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, &SPI_rx_buffer[0]);
_dma_set_data_amount(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, SLAVE_BUFFER_SIZE_LONG);
_dma_set_next_descriptor(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, CONF_SERCOM_1_RECEIVE_DMA_CHANNEL);
_dma_set_source_address(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, &SPI_tx_buffer[0]);
_dma_set_destination_address(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL,
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
_dma_set_data_amount(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, SLAVE_BUFFER_SIZE_LONG);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_RECEIVE_DMA_CHANNEL]);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL]);
/* callback */
@ -212,12 +216,12 @@ void spi_s_sync_enable_ss_detect(void *hw, bool state)
NVIC_ClearPendingIRQ((IRQn_Type)SERCOM1_1_IRQn);
NVIC_EnableIRQ((IRQn_Type)SERCOM1_1_IRQn);
if (state) {
//hri_sercomspi_set_INTEN_TXC_bit(hw);
hri_sercomspi_set_INTEN_TXC_bit(hw);
//hri_sercomspi_set_INTEN_SSL_bit(hw);
//hri_sercomspi_set_INTEN_SSL_bit(hw);
//SERCOM_SPI_INTENSET_SSL
} else {
//hri_sercomspi_clear_INTEN_TXC_bit(hw);
hri_sercomspi_clear_INTEN_TXC_bit(hw);
//hri_sercomspi_clear_INTEN_SSL_bit(hw);
}
}

133
2_Motor_Slave/Motor_Slave/Motor_Slave/interrupts.h
View File

@ -1,54 +1,54 @@
/*
* interrupts.h
*
* Created: 02/08/2021 21:54:14
* Author: Nick-XMG
*/
#ifndef INTERRUPTS_H_
#define INTERRUPTS_H_
// ----------------------------------------------------------------------
// ADC Callback for Motor Phase Current Measurement.
// Phase A & B Sampled and converted from LSB to Process Unit PU(Amps)
// ----------------------------------------------------------------------
static void pwm_cb(const struct pwm_descriptor *const descr)
{
}
void adc_sram_dma_callback(struct _dma_resource *adc_dma_res)
{
Motor1.timerflags.adc_readings_ready_tic = true;
Motor2.timerflags.adc_readings_ready_tic = true;
}
// ----------------------------------------------------------------------
// EtherCAT Cycle Timer - 1kHz
// ----------------------------------------------------------------------
void TC2_Handler(void)
{
if (TC2->COUNT32.INTFLAG.bit.OVF == 0x01) {
TC2->COUNT32.INTFLAG.bit.OVF = 0x01;
Motor1.motor_status.calc_rpm = 0;
}
}
// ----------------------------------------------------------------------
//
// ----------------------------------------------------------------------
void TC4_Handler(void)
{
if (TC4->COUNT32.INTFLAG.bit.OVF == 0x01) {
TC4->COUNT32.INTFLAG.bit.OVF = 0x01;
Motor2.motor_status.calc_rpm = 0;
}
}
/*
* interrupts.h
*
* Created: 02/08/2021 21:54:14
* Author: Nick-XMG
*/
#ifndef INTERRUPTS_H_
#define INTERRUPTS_H_
#include "hpl_dma.h"
// ----------------------------------------------------------------------
// ADC Callback for Motor Phase Current Measurement.
// Phase A & B Sampled and converted from LSB to Process Unit PU(Amps)
// ----------------------------------------------------------------------
static void pwm_cb(const struct pwm_descriptor *const descr)
{
}
void adc_sram_dma_callback(struct _dma_resource *adc_dma_res)
{
Motor1.timerflags.adc_readings_ready_tic = true;
Motor2.timerflags.adc_readings_ready_tic = true;
}
// ----------------------------------------------------------------------
// EtherCAT Cycle Timer - 1kHz
// ----------------------------------------------------------------------
void TC2_Handler(void)
{
if (TC2->COUNT32.INTFLAG.bit.OVF == 0x01) {
TC2->COUNT32.INTFLAG.bit.OVF = 0x01;
Motor1.motor_status.calc_rpm = 0;
}
}
// ----------------------------------------------------------------------
//
// ----------------------------------------------------------------------
void TC4_Handler(void)
{
if (TC4->COUNT32.INTFLAG.bit.OVF == 0x01) {
TC4->COUNT32.INTFLAG.bit.OVF = 0x01;
Motor2.motor_status.calc_rpm = 0;
}
}
static void M1_RESET_BAR(void)
{
volatile int x = 0;
@ -59,20 +59,21 @@ static void M2_RESET_BAR(void)
volatile int x = 0;
}
// ----------------------------------------------------------------------
// Master/Slave IF Callback
// ----------------------------------------------------------------------
static void b2bTransferComplete_cb(struct _dma_resource *resource)
{
DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
DMAC->Channel[3].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
volatile int x = 0;
//PORT->Group[GPIO_PORTB].OUTCLR.reg = (1<<Slave_1->SS_pin);
//gpio_set_pin_level(SPI1_CS, true);
// ----------------------------------------------------------------------
// Master/Slave IF Callback
// ----------------------------------------------------------------------
static void b2bTransferComplete_cb(struct _dma_resource *resource)
{
//_dma_enable_transaction(0, false); //_dma_enable_transaction(3, false);
DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
DMAC->Channel[3].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
//volatile int x = 0;
//PORT->Group[GPIO_PORTB].OUTCLR.reg = (1<<Slave_1->SS_pin);
//gpio_set_pin_level(SPI1_CS, true);
}
#endif /* INTERRUPTS_H_ */

25
2_Motor_Slave/Motor_Slave/Motor_Slave/main.c
View File

@ -86,7 +86,9 @@ void SERCOM1_1_Handler()
//SERCOM1->SPI.INTFLAG.bit.TXC = 0x01;
//SPI_tx_buffer[0] += 1;
//tx_buffer[31] += 1;
DMAC->Channel[3].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
//_dma_enable_transaction(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, false);
//_dma_enable_transaction(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, false);
@ -107,8 +109,8 @@ void SERCOM1_3_Handler()
//tx_buffer[31] += 1;
//
//DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
//DMAC->Channel[1].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
DMAC->Channel[3].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
//_dma_enable_transaction(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, false);
//_dma_enable_transaction(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, false);
@ -132,14 +134,14 @@ void enable_NVIC_IRQ(void)
//NVIC_EnableIRQ(TC4_IRQn); // TC4: M2_Speed_Timer
NVIC_EnableIRQ(DMAC_0_IRQn);
NVIC_EnableIRQ(DMAC_1_IRQn);
NVIC_SetPriority(DMAC_0_IRQn, 2);
NVIC_SetPriority(ADC1_0_IRQn, 3);
// NVIC_SetPriority(DMAC_0_IRQn, 2);
//NVIC_SetPriority(ADC1_0_IRQn, 3);
NVIC_EnableIRQ(TCC0_0_IRQn);
NVIC_EnableIRQ(TCC1_0_IRQn);
NVIC_EnableIRQ(SERCOM1_3_IRQn);
//NVIC_SetPriority(SERCOM1_3_IRQn, 0);
//NVIC_EnableIRQ(SERCOM1_1_IRQn);
//NVIC_SetPriority(SERCOM1_1_IRQn, 1);
NVIC_SetPriority(SERCOM1_3_IRQn, 0);
NVIC_EnableIRQ(SERCOM1_1_IRQn);
NVIC_SetPriority(SERCOM1_1_IRQn, 0);
//NVIC_EnableIRQ(SERCOM1_3_IRQn);
//NVIC_EnableIRQ(EIC_5_IRQn);
}
@ -214,19 +216,18 @@ int main(void)
{
/* Initializes MCU, drivers and middleware */
atmel_start_init();
__disable_irq();
BldcInitStruct(&Motor1, &FH_22mm24BXTR);
BldcInitStruct(&Motor2, &FH_22mm24BXTR_temp);
Motor1.readHall = &readHallSensorM1;
Motor2.readHall = &readHallSensorM2;
read_zero_current_offset_value(&Motor1, &Motor2);
__disable_irq();
//config_qspi();
configure_tcc_pwm();
adc_sync_enable_channel(&ADC_1, 6);
//ECAT_STATE_MACHINE();
//adc_init_dma();
adc_init_dma();
boardToBoardTransferInit();
init_spi_slave_dma_descriptors();

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Twincat/MotorData/.vs/MotorData/v15/.suo
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Twincat/MotorData/Scope Project1.svdx
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28
Twincat/MotorData/TwinCAT Measurement Project1/Scope Project1.tcscopex
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@ -65,7 +65,7 @@
<DataType>REAL32</DataType>
<DisplayColor>Black</DisplayColor>
<Enabled>true</Enabled>
<FileHandle>1</FileHandle>
<FileHandle>0</FileHandle>
<ForceOversampling>false</ForceOversampling>
<Guid>24de5fd2-67a3-4d17-9b2f-e37ef463e046</Guid>
<IndexGroup>16448</IndexGroup>
@ -146,7 +146,7 @@
<DataType>REAL32</DataType>
<DisplayColor>Black</DisplayColor>
<Enabled>true</Enabled>
<FileHandle>2</FileHandle>
<FileHandle>0</FileHandle>
<ForceOversampling>false</ForceOversampling>
<Guid>050df458-283b-4aab-9c50-02776e050173</Guid>
<IndexGroup>16448</IndexGroup>
@ -227,7 +227,7 @@
<DataType>REAL32</DataType>
<DisplayColor>Black</DisplayColor>
<Enabled>true</Enabled>
<FileHandle>3</FileHandle>
<FileHandle>0</FileHandle>
<ForceOversampling>false</ForceOversampling>
<Guid>eda5e08a-a0c1-46d5-a386-55a53fe55cb8</Guid>
<IndexGroup>16448</IndexGroup>
@ -308,7 +308,7 @@
<DataType>REAL32</DataType>
<DisplayColor>Black</DisplayColor>
<Enabled>true</Enabled>
<FileHandle>4</FileHandle>
<FileHandle>0</FileHandle>
<ForceOversampling>false</ForceOversampling>
<Guid>72a5bcb2-9496-4a66-8ac2-c891ae65b624</Guid>
<IndexGroup>16448</IndexGroup>
@ -389,7 +389,7 @@
<DataType>INT16</DataType>
<DisplayColor>Black</DisplayColor>
<Enabled>true</Enabled>
<FileHandle>5</FileHandle>
<FileHandle>0</FileHandle>
<ForceOversampling>false</ForceOversampling>
<Guid>13dad77b-fd32-432c-abcb-0963197b16db</Guid>
<IndexGroup>61472</IndexGroup>
@ -470,7 +470,7 @@
<DataType>INT16</DataType>
<DisplayColor>Black</DisplayColor>
<Enabled>true</Enabled>
<FileHandle>6</FileHandle>
<FileHandle>0</FileHandle>
<ForceOversampling>false</ForceOversampling>
<Guid>cf06dfb5-6728-427c-a868-4f8a80c4ce1b</Guid>
<IndexGroup>61488</IndexGroup>
@ -551,7 +551,7 @@
<DataType>INT16</DataType>
<DisplayColor>Black</DisplayColor>
<Enabled>true</Enabled>
<FileHandle>7</FileHandle>
<FileHandle>0</FileHandle>
<ForceOversampling>false</ForceOversampling>
<Guid>8d7766a1-e5c2-4084-b1e1-2a1cde8bc625</Guid>
<IndexGroup>61472</IndexGroup>
@ -632,7 +632,7 @@
<DataType>INT16</DataType>
<DisplayColor>Black</DisplayColor>
<Enabled>true</Enabled>
<FileHandle>8</FileHandle>
<FileHandle>0</FileHandle>
<ForceOversampling>false</ForceOversampling>
<Guid>8b889ab1-8104-4807-8962-50fc84d9d53b</Guid>
<IndexGroup>61488</IndexGroup>
@ -713,7 +713,7 @@
<DataType>INT16</DataType>
<DisplayColor>Black</DisplayColor>
<Enabled>true</Enabled>
<FileHandle>9</FileHandle>
<FileHandle>0</FileHandle>
<ForceOversampling>false</ForceOversampling>
<Guid>92af127e-8066-47e6-907d-f3e7f8932f20</Guid>
<IndexGroup>61472</IndexGroup>
@ -794,7 +794,7 @@
<DataType>INT16</DataType>
<DisplayColor>Black</DisplayColor>
<Enabled>true</Enabled>
<FileHandle>10</FileHandle>
<FileHandle>0</FileHandle>
<ForceOversampling>false</ForceOversampling>
<Guid>18d32ea4-6af2-440c-b6ce-6c8e7e4d7815</Guid>
<IndexGroup>61488</IndexGroup>
@ -875,7 +875,7 @@
<DataType>INT16</DataType>
<DisplayColor>Black</DisplayColor>
<Enabled>true</Enabled>
<FileHandle>11</FileHandle>
<FileHandle>0</FileHandle>
<ForceOversampling>false</ForceOversampling>
<Guid>6ac2c5bb-eae6-475a-b849-7e5b7c9c9565</Guid>
<IndexGroup>61472</IndexGroup>
@ -956,7 +956,7 @@
<DataType>INT16</DataType>
<DisplayColor>Black</DisplayColor>
<Enabled>true</Enabled>
<FileHandle>12</FileHandle>
<FileHandle>0</FileHandle>
<ForceOversampling>false</ForceOversampling>
<Guid>1e7a9f36-2614-4cf7-b72a-1117927e93e9</Guid>
<IndexGroup>61488</IndexGroup>
@ -1037,7 +1037,7 @@
<DataType>INT16</DataType>
<DisplayColor>Black</DisplayColor>
<Enabled>true</Enabled>
<FileHandle>13</FileHandle>
<FileHandle>0</FileHandle>
<ForceOversampling>false</ForceOversampling>
<Guid>00293ced-5f18-4418-aa61-3cce818122c1</Guid>
<IndexGroup>61472</IndexGroup>
@ -1118,7 +1118,7 @@
<DataType>INT16</DataType>
<DisplayColor>Black</DisplayColor>
<Enabled>true</Enabled>
<FileHandle>14</FileHandle>
<FileHandle>0</FileHandle>
<ForceOversampling>false</ForceOversampling>
<Guid>da0d5fd3-5da6-475d-bd83-771d47fa228f</Guid>
<IndexGroup>61472</IndexGroup>