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fixed bldc and started adding ads1299 dma

This commit is contained in:
Nicolas Trimborn 2021-08-30 22:07:28 +02:00
parent bb7413ec60
commit 1f5905d213
27 changed files with 1898 additions and 57 deletions
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20
2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart
View File

@ -776,8 +776,8 @@ drivers:
eic_arch_asynch11: false
eic_arch_asynch12: false
eic_arch_asynch13: false
eic_arch_asynch14: true
eic_arch_asynch15: true
eic_arch_asynch14: false
eic_arch_asynch15: false
eic_arch_asynch2: true
eic_arch_asynch3: false
eic_arch_asynch4: false
@ -841,8 +841,8 @@ drivers:
eic_arch_filten11: false
eic_arch_filten12: false
eic_arch_filten13: false
eic_arch_filten14: false
eic_arch_filten15: false
eic_arch_filten14: true
eic_arch_filten15: true
eic_arch_filten2: false
eic_arch_filten3: false
eic_arch_filten4: false
@ -863,8 +863,8 @@ drivers:
eic_arch_sense11: No detection
eic_arch_sense12: No detection
eic_arch_sense13: No detection
eic_arch_sense14: Both-edges detection
eic_arch_sense15: Both-edges detection
eic_arch_sense14: Falling-edge detection
eic_arch_sense15: Falling-edge detection
eic_arch_sense2: Falling-edge detection
eic_arch_sense3: No detection
eic_arch_sense4: No detection
@ -1018,8 +1018,8 @@ drivers:
evsys_channel_setting_9: false
evsys_edgsel_0: No event output when using the resynchronized or synchronous
path
evsys_edgsel_1: No event output when using the resynchronized or synchronous
path
evsys_edgsel_1: Event is detected on the rising edge of the signal from event
generator
evsys_edgsel_10: No event output when using the resynchronized or synchronous
path
evsys_edgsel_11: No event output when using the resynchronized or synchronous
@ -1040,8 +1040,8 @@ drivers:
path
evsys_edgsel_19: No event output when using the resynchronized or synchronous
path
evsys_edgsel_2: No event output when using the resynchronized or synchronous
path
evsys_edgsel_2: Event is detected on the rising edge of the signal from event
generator
evsys_edgsel_20: No event output when using the resynchronized or synchronous
path
evsys_edgsel_21: No event output when using the resynchronized or synchronous

2
2_Motor_Master/Motor_Master/Motor_Master/ADS1299.c
View File

@ -256,7 +256,7 @@ void ADS1299_RDATA() { // use in Stop Read Continuous mode when DRDY goes low
int32_t* ADS1299_UPDATECHANNELDATA()
{
uint8_t inByte;
int nchan=4; //assume 8 channel. If needed, it automatically changes to 16 automatically in a later block.
int nchan=8; //assume 8 channel. If needed, it automatically changes to 16 automatically in a later block.
gpio_set_pin_level(ADS1299.SS_pin, false); // open SPI
// READ CHANNEL DATA FROM FIRST ADS IN DAISY LINE

3
2_Motor_Master/Motor_Master/Motor_Master/ADS1299.h
View File

@ -53,6 +53,7 @@
#define CONFIG4 0x17
volatile int32_t _channel_data[8];
volatile uint32_t ads1299_buffer[6];
/* Struct Definitions */
@ -62,7 +63,7 @@ volatile struct SPI_ADS1299 {
volatile uint32_t SS_pin;
volatile uint32_t reset_pin;
volatile uint8_t regData [24];
volatile int32_t* channel_data; // Must Equal n_dev
volatile int32_t* channel_data;
volatile int16_t stat_1;
};

12
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_eic_config.h
View File

@ -756,7 +756,7 @@
// <i> Indicates whether the external interrupt 14 filter is enabled or not
// <id> eic_arch_filten14
#ifndef CONF_EIC_FILTEN14
#define CONF_EIC_FILTEN14 0
#define CONF_EIC_FILTEN14 1
#endif
// <q> External Interrupt 14 Debounce Enable
@ -783,14 +783,14 @@
// <i> This defines input sense trigger
// <id> eic_arch_sense14
#ifndef CONF_EIC_SENSE14
#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_BOTH_Val
#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_FALL_Val
#endif
// <q> External Interrupt 14 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch14
#ifndef CONF_EIC_ASYNCH14
#define CONF_EIC_ASYNCH14 1
#define CONF_EIC_ASYNCH14 0
#endif
// </e>
@ -805,7 +805,7 @@
// <i> Indicates whether the external interrupt 15 filter is enabled or not
// <id> eic_arch_filten15
#ifndef CONF_EIC_FILTEN15
#define CONF_EIC_FILTEN15 0
#define CONF_EIC_FILTEN15 1
#endif
// <q> External Interrupt 15 Debounce Enable
@ -832,14 +832,14 @@
// <i> This defines input sense trigger
// <id> eic_arch_sense15
#ifndef CONF_EIC_SENSE15
#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_BOTH_Val
#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_FALL_Val
#endif
// <q> External Interrupt 15 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch15
#ifndef CONF_EIC_ASYNCH15
#define CONF_EIC_ASYNCH15 1
#define CONF_EIC_ASYNCH15 0
#endif
// </e>

4
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_evsys_config.h
View File

@ -199,7 +199,7 @@
// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
// <id> evsys_edgsel_1
#ifndef CONF_EDGSEL_1
#define CONF_EDGSEL_1 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
#define CONF_EDGSEL_1 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
#endif
// <y> Path selection
@ -380,7 +380,7 @@
// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
// <id> evsys_edgsel_2
#ifndef CONF_EDGSEL_2
#define CONF_EDGSEL_2 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
#define CONF_EDGSEL_2 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
#endif
// <y> Path selection

180
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_tc_config.h Normal file
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@ -0,0 +1,180 @@
/* Auto-generated config file hpl_tc_config.h */
#ifndef HPL_TC_CONFIG_H
#define HPL_TC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef CONF_TC0_ENABLE
#define CONF_TC0_ENABLE 1
#endif
#include "peripheral_clk_config.h"
// <h> Basic configuration
// <o> Prescaler
// <0x0=> No division
// <0x1=> Divide by 2
// <0x2=> Divide by 4
// <0x3=> Divide by 8
// <0x4=> Divide by 16
// <0x5=> Divide by 64
// <0x6=> Divide by 256
// <0x7=> Divide by 1024
// <i> This defines the prescaler value
// <id> timer_prescaler
#ifndef CONF_TC0_PRESCALER
#define CONF_TC0_PRESCALER 0x3
#endif
// <o> Length of one timer tick in uS <0-4294967295>
// <id> timer_tick
#ifndef CONF_TC0_TIMER_TICK
#define CONF_TC0_TIMER_TICK 100
#endif
// </h>
// <e> Advanced configuration
// <id> timer_advanced_configuration
#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE
#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 1
#endif
// <y> Prescaler and Counter Synchronization Selection
// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
// <id> tc_arch_presync
#ifndef CONF_TC0_PRESCSYNC
#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
#endif
// <q> Run in standby
// <i> Indicates whether the module will continue to run in standby sleep mode
// <id> tc_arch_runstdby
#ifndef CONF_TC0_RUNSTDBY
#define CONF_TC0_RUNSTDBY 0
#endif
// <q> Run in debug mode
// <i> Indicates whether the module will run in debug mode
// <id> tc_arch_dbgrun
#ifndef CONF_TC0_DBGRUN
#define CONF_TC0_DBGRUN 0
#endif
// <q> Run on demand
// <i> Run if requested by some other peripheral in the device
// <id> tc_arch_ondemand
#ifndef CONF_TC0_ONDEMAND
#define CONF_TC0_ONDEMAND 0
#endif
// </e>
// <e> Event control
// <id> timer_event_control
#ifndef CONF_TC0_EVENT_CONTROL_ENABLE
#define CONF_TC0_EVENT_CONTROL_ENABLE 1
#endif
// <q> Output Event On Match or Capture on Channel 0
// <i> Enable output of event on timer tick
// <id> tc_arch_mceo0
#ifndef CONF_TC0_MCEO0
#define CONF_TC0_MCEO0 1
#endif
// <q> Output Event On Match or Capture on Channel 1
// <i> Enable output of event on timer tick
// <id> tc_arch_mceo1
#ifndef CONF_TC0_MCEO1
#define CONF_TC0_MCEO1 1
#endif
// <q> Output Event On Timer Tick
// <i> Enable output of event on timer tick
// <id> tc_arch_ovfeo
#ifndef CONF_TC0_OVFEO
#define CONF_TC0_OVFEO 0
#endif
// <q> Event Input
// <i> Enable asynchronous input events
// <id> tc_arch_tcei
#ifndef CONF_TC0_TCEI
#define CONF_TC0_TCEI 0
#endif
// <q> Inverted Event Input
// <i> Invert the asynchronous input events
// <id> tc_arch_tcinv
#ifndef CONF_TC0_TCINV
#define CONF_TC0_TCINV 0
#endif
// <o> Event action
// <0=> Event action disabled
// <1=> Start, restart or re-trigger TC on event
// <2=> Count on event
// <3=> Start on event
// <4=> Time stamp capture
// <5=> Period captured in CC0, pulse width in CC1
// <6=> Period captured in CC1, pulse width in CC0
// <7=> Pulse width capture
// <i> Event which will be performed on an event
//<id> tc_arch_evact
#ifndef CONF_TC0_EVACT
#define CONF_TC0_EVACT 0
#endif
// </e>
// Default values which the driver needs in order to work correctly
// Mode set to 32-bit
#ifndef CONF_TC0_MODE
#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val
#endif
// CC 1 register set to 0
#ifndef CONF_TC0_CC1
#define CONF_TC0_CC1 0
#endif
#ifndef CONF_TC0_ALOCK
#define CONF_TC0_ALOCK 0
#endif
// Not used in 32-bit mode
#define CONF_TC0_PER 0
// Calculating correct top value based on requested tick interval.
#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER)
// Prescaler set to 64
#if CONF_TC0_PRESCALER > 0x4
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 64
#endif
// Prescaler set to 256
#if CONF_TC0_PRESCALER > 0x5
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 256
#endif
// Prescaler set to 1024
#if CONF_TC0_PRESCALER > 0x6
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 1024
#endif
#ifndef CONF_TC0_CC0
#define CONF_TC0_CC0 \
(uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE)))
#endif
// <<< end of configuration section >>>
#endif // HPL_TC_CONFIG_H

126
2_Motor_Master/Motor_Master/Motor_Master/Debug.xml Normal file
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@ -0,0 +1,126 @@
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1
2_Motor_Master/Motor_Master/Motor_Master/EtherCAT_SlaveDef.h
View File

@ -13,6 +13,7 @@
#include "arm_math.h"
extern volatile int32_t _channel_data[8];
extern volatile uint32_t ads1299_buffer[6];
//Write To Ecat Total Bytes (XX bytes)
/* Motor 1*/

1
2_Motor_Master/Motor_Master/Motor_Master/Ethercat_SlaveDef.h
View File

@ -13,6 +13,7 @@
#include "arm_math.h"
extern volatile int32_t _channel_data[8];
extern volatile uint32_t ads1299_buffer[6];
//Write To Ecat Total Bytes (XX bytes)
/* Motor 1*/

10
2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj
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@ -207,8 +207,8 @@
<AcmeProjectActionInfo Action="File" Source="config/hpl_ccl_config.h" IsConfig="true" Hash="Q1yijLwNXjFOsGrwEEma+g" />
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<AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="S8xJxIaG6pS6BEvDgxKh9w" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="razEOr+ddCtzmAhy4QVzhg" />
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<AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_mclk_config.h" IsConfig="true" Hash="pxBzoQXTG66x4dbzVzxteg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_osc32kctrl_config.h" IsConfig="true" Hash="HgvzEqDUH4jq/syjj/+G+Q" />
@ -382,6 +382,7 @@
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<Value>../Config</Value>
<Value>../</Value>
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@ -406,7 +407,6 @@
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@ -433,6 +433,7 @@
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<Value>../Config</Value>
<Value>../</Value>
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@ -457,13 +458,13 @@
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<Value>../Config</Value>
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@ -488,7 +489,6 @@
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122
2_Motor_Master/Motor_Master/Motor_Master/Release.xml Normal file
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@ -0,0 +1,122 @@
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10
2_Motor_Master/Motor_Master/Motor_Master/bldc.c
View File

@ -49,7 +49,8 @@ void motor_StateMachine(BLDCMotor_t* const motor)
case MOTOR_VI_CTRL_STATE:
switch (motor->regulation_loop_count) {
case 0: /* PWM FREQ / 25 - 1kHz */
case 5: case 10: case 15: case 20:/* PWM FREQ / 5 - 5kHz */
//case 5: case 10: case 15: case 20:/* PWM FREQ / 5 - 5kHz */
case 5: case 15: /* PWM FREQ / 5 - 5kHz */
calculate_motor_speed(motor);
BLDC_runSpeedCntl(motor, (float32_t)motor->motor_status.calc_rpm, (float32_t)motor->motor_setpoints.desired_speed);
default: /* PWM FREQ - 25kHz */
@ -93,6 +94,7 @@ void BldcInitStruct(BLDCMotor_t* const motor, BLDCMotor_param_t * const motor_pa
// Assign Motor Parameters:
// ----------------------------------------------------------------------
motor->motor_param = motor_param;
// ----------------------------------------------------------------------
// Initialize State Machine:
@ -218,9 +220,9 @@ void exec_commutation(BLDCMotor_t* const motor)
if (currentHall == INVALID_HALL_7)
{
motor->motor_state.currentstate == MOTOR_FAULT;
motor->motor_state.fault == MOTOR_HALLSENSORINVALID;
return;
///motor->motor_state.currentstate == MOTOR_FAULT;
//motor->motor_state.fault == MOTOR_HALLSENSORINVALID;
//return;
}
// ----------------------------------------------------------------------

54
2_Motor_Master/Motor_Master/Motor_Master/configuration.h
View File

@ -16,7 +16,7 @@
#include "bldc.h"
#include "interrupts.h"
#include "hpl_sercom_config.h"
#include "ADS1299.h"
// ----------------------------------------------------------------------
// ADC DMA Initialization
// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
@ -89,9 +89,6 @@ static void configure_tcc_pwm(void)
}
static void adc_dmac_sequence_init()
{
/* Configure the DMAC source address, destination address,
@ -184,6 +181,47 @@ static void spi_master_init_dma_descriptors()
}
// ----------------------------------------------------------------------
// SPI DMA communication ADS1299
// ----------------------------------------------------------------------
//
#define CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL 2U
#define CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL 8U
#define ADS_BUFFER_SIZE 6
/* 219 Bites total
* Number format is 24 bit
* 7 (uint_32) - 24 bits
*/
extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
//
static void spi_ads1299_init_dma_descriptors()
{
_dma_set_source_address(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL,
(uint32_t *)&(((SercomSpi *)(SPI_2.dev.prvt))->DATA.reg));
_dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, &QSPI_rx_buffer[10]);
_dma_set_data_amount(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, ADS_BUFFER_SIZE);
_dma_set_next_descriptor(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL);
_dma_set_source_address(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, &ads1299_buffer[0]);
_dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL,
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
_dma_set_data_amount(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, ADS_BUFFER_SIZE);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL]);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL]);
}
// ----------------------------------------------------------------------
// Overall DMA Init
// ----------------------------------------------------------------------
/* Peripherals should be configured before interacting with dma
* CH0 - QSPI_RX - For ECAT DMA Mode - Currently Disabled in ASTART
* CH1 - SERCOM1_RX(SPI1) - Master-Slave IF - Beat Transfer Event Drives CS Pin
@ -193,15 +231,17 @@ static void spi_master_init_dma_descriptors()
* CH5 - ADC1 - Result Ready
* CH6 - ADC0 - Sequencer (Unused on master) - Currently Disabled in ASTART
* CH7 - ADC1 - Sequencer - Triggered by TCC0 overflow event
* CH8 - SERCOM2_TX(SPI2)
* CH9 - SERCOM5_TX(SPI3)
* CH10 - SERCOM1_TX(SPI1)
* CH8 - SERCOM2_TX(SPI2) - Master-Slave IF
* CH9 - SERCOM5_TX(SPI3) - Expansion IF (EMG)
* CH10 - SERCOM1_TX(SPI1) - Angle Sensor
* CH11 - QSPI_TX - For ECAT DMA Mode - Currently Disabled in ASTART
*/
static void init_dma(void)
{
spi_master_init_dma_descriptors();
spi_ads1299_init_dma_descriptors();
adc_init_dma_descriptors();
}

52
2_Motor_Master/Motor_Master/Motor_Master/hal/documentation/timer.rst Normal file
View File

@ -0,0 +1,52 @@
============================
The Timer driver (bare-bone)
============================
The Timer driver provides means for delayed and periodical function invocation.
A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has
been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a
configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically
changes execution delays and periods for all tasks in the timers task queue.
A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue
and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on
the period set in the task configuration.
In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to
reuse the memory of expired task in the callback.
Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available.
Features
--------
* Initialization and de-initialization
* Starting and stopping
* Timer tasks - periodical invocation of functions
* Changing and obtaining of the period of a timer
Applications
------------
* Delayed and periodical function execution for middle-ware stacks and applications.
Dependencies
------------
* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt.
Concurrency
-----------
The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during
the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed
until the task adding or removing is complete.
The task queue is not protected from the access by interrupts not used by the driver. Due to this
it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes
the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver.
Limitations
-----------
* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts.
* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task.
Knows issues and workarounds
----------------------------
Not applicable

206
2_Motor_Master/Motor_Master/Motor_Master/hal/include/hal_timer.h Normal file
View File

@ -0,0 +1,206 @@
/**
* \file
*
* \brief Timer task functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_TIMER_H_INCLUDED
#define _HAL_TIMER_H_INCLUDED
#include <utils_list.h>
#include <hpl_timer.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_timer
*
* @{
*/
/**
* \brief Timer mode type
*/
enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT };
/**
* \brief Timer task descriptor
*
* The timer task descriptor forward declaration.
*/
struct timer_task;
/**
* \brief Timer task callback function type
*/
typedef void (*timer_cb_t)(const struct timer_task *const timer_task);
/**
* \brief Timer task structure
*/
struct timer_task {
struct list_element elem; /*! List element. */
uint32_t time_label; /*! Absolute timer start time. */
uint32_t interval; /*! Number of timer ticks before calling the task. */
timer_cb_t cb; /*! Function pointer to the task. */
enum timer_task_mode mode; /*! Task mode: one shot or repeat. */
};
/**
* \brief Timer structure
*/
struct timer_descriptor {
struct _timer_device device;
uint32_t time;
struct list_descriptor tasks; /*! Timer tasks list. */
volatile uint8_t flags;
};
/**
* \brief Initialize timer
*
* This function initializes the given timer.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[out] descr A timer descriptor to initialize
* \param[in] hw The pointer to the hardware instance
* \param[in] func The pointer to a set of function pointers
*
* \return Initialization status.
*/
int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func);
/**
* \brief Deinitialize timer
*
* This function deinitializes the given timer.
* It checks if the given hardware is initialized and if the given hardware is
* permitted to be deinitialized.
*
* \param[in] descr A timer descriptor to deinitialize
*
* \return De-initialization status.
*/
int32_t timer_deinit(struct timer_descriptor *const descr);
/**
* \brief Start timer
*
* This function starts the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to start
*
* \return Timer starting status.
*/
int32_t timer_start(struct timer_descriptor *const descr);
/**
* \brief Stop timer
*
* This function stops the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to stop
*
* \return Timer stopping status.
*/
int32_t timer_stop(struct timer_descriptor *const descr);
/**
* \brief Set amount of clock cycles per timer tick
*
* This function sets the amount of clock cycles per timer tick for the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to stop
* \param[in] clock_cycles The amount of clock cycles per tick to set
*
* \return Setting clock cycles amount status.
*/
int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles);
/**
* \brief Retrieve the amount of clock cycles in a tick
*
* This function retrieves how many clock cycles there are in a single timer tick.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to convert ticks to
* clock cycles
* \param[out] cycles The amount of clock cycles
*
* \return The status of clock cycles retrieving.
*/
int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles);
/**
* \brief Add timer task
*
* This function adds the given timer task to the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to add task to
* \param[in] task A task to add
*
* \return Timer's task adding status.
*/
int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task);
/**
* \brief Remove timer task
*
* This function removes the given timer task from the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to remove task from
* \param[in] task A task to remove
*
* \return Timer's task removing status.
*/
int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t timer_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_TIMER_H_INCLUDED */

250
2_Motor_Master/Motor_Master/Motor_Master/hal/src/hal_timer.c Normal file
View File

@ -0,0 +1,250 @@
/**
* \file
*
* \brief Timer functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_timer.h"
#include <utils_assert.h>
#include <utils.h>
#include <hal_atomic.h>
#include <hpl_irq.h>
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief Timer flags
*/
#define TIMER_FLAG_QUEUE_IS_TAKEN 1
#define TIMER_FLAG_INTERRUPT_TRIGERRED 2
static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time);
static void timer_process_counted(struct _timer_device *device);
/**
* \brief Initialize timer
*/
int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func)
{
ASSERT(descr && hw);
_timer_init(&descr->device, hw);
descr->time = 0;
descr->device.timer_cb.period_expired = timer_process_counted;
return ERR_NONE;
}
/**
* \brief Deinitialize timer
*/
int32_t timer_deinit(struct timer_descriptor *const descr)
{
ASSERT(descr);
_timer_deinit(&descr->device);
return ERR_NONE;
}
/**
* \brief Start timer
*/
int32_t timer_start(struct timer_descriptor *const descr)
{
ASSERT(descr);
if (_timer_is_started(&descr->device)) {
return ERR_DENIED;
}
_timer_start(&descr->device);
return ERR_NONE;
}
/**
* \brief Stop timer
*/
int32_t timer_stop(struct timer_descriptor *const descr)
{
ASSERT(descr);
if (!_timer_is_started(&descr->device)) {
return ERR_DENIED;
}
_timer_stop(&descr->device);
return ERR_NONE;
}
/**
* \brief Set amount of clock cycler per timer tick
*/
int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles)
{
ASSERT(descr);
_timer_set_period(&descr->device, clock_cycles);
return ERR_NONE;
}
/**
* \brief Add timer task
*/
int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task)
{
ASSERT(descr && task);
descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN;
if (is_list_element(&descr->tasks, task)) {
descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN;
ASSERT(false);
return ERR_ALREADY_INITIALIZED;
}
task->time_label = descr->time;
timer_add_timer_task(&descr->tasks, task, descr->time);
descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN;
if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) {
CRITICAL_SECTION_ENTER()
descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED;
_timer_set_irq(&descr->device);
CRITICAL_SECTION_LEAVE()
}
return ERR_NONE;
}
/**
* \brief Remove timer task
*/
int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task)
{
ASSERT(descr && task);
descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN;
if (!is_list_element(&descr->tasks, task)) {
descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN;
ASSERT(false);
return ERR_NOT_FOUND;
}
list_delete_element(&descr->tasks, task);
descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN;
if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) {
CRITICAL_SECTION_ENTER()
descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED;
_timer_set_irq(&descr->device);
CRITICAL_SECTION_LEAVE()
}
return ERR_NONE;
}
/**
* \brief Retrieve the amount of clock cycles in a tick
*/
int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles)
{
ASSERT(descr && cycles);
*cycles = _timer_get_period(&descr->device);
return ERR_NONE;
}
/**
* \brief Retrieve the current driver version
*/
uint32_t timer_get_version(void)
{
return DRIVER_VERSION;
}
/**
* \internal Insert a timer task into sorted timer's list
*
* \param[in] head The pointer to the head of timer task list
* \param[in] task The pointer to task to add
* \param[in] time Current timer time
*/
static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time)
{
struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list);
if (!head) {
list_insert_as_head(list, new_task);
return;
}
for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) {
uint32_t time_left;
if (it->time_label <= time) {
time_left = it->interval - (time - it->time_label);
} else {
time_left = it->interval - (0xFFFFFFFF - it->time_label) - time;
}
if (time_left >= new_task->interval)
break;
prev = it;
}
if (it == head) {
list_insert_as_head(list, new_task);
} else {
list_insert_after(prev, new_task);
}
}
/**
* \internal Process interrupts
*/
static void timer_process_counted(struct _timer_device *device)
{
struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device);
struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks);
uint32_t time = ++timer->time;
if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) {
timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED;
return;
}
while (it && ((time - it->time_label) >= it->interval)) {
struct timer_task *tmp = it;
list_remove_head(&timer->tasks);
if (TIMER_TASK_REPEAT == tmp->mode) {
tmp->time_label = time;
timer_add_timer_task(&timer->tasks, tmp, time);
}
it = (struct timer_task *)list_get_head(&timer->tasks);
tmp->cb(tmp);
}
}

357
2_Motor_Master/Motor_Master/Motor_Master/hpl/tc/hpl_tc.c Normal file
View File

@ -0,0 +1,357 @@
/**
* \file
*
* \brief SAM TC
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_pwm.h>
#include <hpl_tc_config.h>
#include <hpl_timer.h>
#include <utils.h>
#include <utils_assert.h>
#include <hpl_tc_base.h>
#ifndef CONF_TC0_ENABLE
#define CONF_TC0_ENABLE 0
#endif
#ifndef CONF_TC1_ENABLE
#define CONF_TC1_ENABLE 0
#endif
#ifndef CONF_TC2_ENABLE
#define CONF_TC2_ENABLE 0
#endif
#ifndef CONF_TC3_ENABLE
#define CONF_TC3_ENABLE 0
#endif
#ifndef CONF_TC4_ENABLE
#define CONF_TC4_ENABLE 0
#endif
#ifndef CONF_TC5_ENABLE
#define CONF_TC5_ENABLE 0
#endif
#ifndef CONF_TC6_ENABLE
#define CONF_TC6_ENABLE 0
#endif
#ifndef CONF_TC7_ENABLE
#define CONF_TC7_ENABLE 0
#endif
/**
* \brief Macro is used to fill usart configuration structure based on its
* number
*
* \param[in] n The number of structures
*/
#define TC_CONFIGURATION(n) \
{ \
n, TC##n##_IRQn, \
TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC) \
| (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) | (CONF_TC##n##_ONDEMAND << TC_CTRLA_ONDEMAND_Pos) \
| TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_ALOCK << TC_CTRLA_ALOCK_Pos), \
(CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos) \
| (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos) \
| (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos), \
(CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1, \
}
/**
* \brief TC configuration type
*/
struct tc_configuration {
uint8_t number;
IRQn_Type irq;
hri_tc_ctrla_reg_t ctrl_a;
hri_tc_evctrl_reg_t event_ctrl;
hri_tc_dbgctrl_reg_t dbg_ctrl;
hri_tccount8_per_reg_t per;
hri_tccount32_cc_reg_t cc0;
hri_tccount32_cc_reg_t cc1;
};
/**
* \brief Array of TC configurations
*/
static struct tc_configuration _tcs[] = {
#if CONF_TC0_ENABLE == 1
TC_CONFIGURATION(0),
#endif
#if CONF_TC1_ENABLE == 1
TC_CONFIGURATION(1),
#endif
#if CONF_TC2_ENABLE == 1
TC_CONFIGURATION(2),
#endif
#if CONF_TC3_ENABLE == 1
TC_CONFIGURATION(3),
#endif
#if CONF_TC4_ENABLE == 1
TC_CONFIGURATION(4),
#endif
#if CONF_TC5_ENABLE == 1
TC_CONFIGURATION(5),
#endif
#if CONF_TC6_ENABLE == 1
TC_CONFIGURATION(6),
#endif
#if CONF_TC7_ENABLE == 1
TC_CONFIGURATION(7),
#endif
};
static struct _timer_device *_tc0_dev = NULL;
static struct _pwm_device *_tc2_dev = NULL;
static struct _pwm_device *_tc4_dev = NULL;
static int8_t get_tc_index(const void *const hw);
static void _tc_init_irq_param(const void *const hw, void *dev);
static inline uint8_t _get_hardware_offset(const void *const hw);
/**
* \brief Initialize TC
*/
int32_t _timer_init(struct _timer_device *const device, void *const hw)
{
int8_t i = get_tc_index(hw);
device->hw = hw;
ASSERT(ARRAY_SIZE(_tcs));
if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) {
if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) {
hri_tc_clear_CTRLA_ENABLE_bit(hw);
hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE);
}
hri_tc_write_CTRLA_reg(hw, TC_CTRLA_SWRST);
}
hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a);
hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl);
hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl);
hri_tc_write_WAVE_reg(hw, TC_WAVE_WAVEGEN_MFRQ);
if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0);
hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1);
} else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) {
hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0);
hri_tccount16_write_CC_reg(hw, 1, (uint16_t)_tcs[i].cc1);
} else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT8) {
hri_tccount8_write_CC_reg(hw, 0, (uint8_t)_tcs[i].cc0);
hri_tccount8_write_CC_reg(hw, 1, (uint8_t)_tcs[i].cc1);
hri_tccount8_write_PER_reg(hw, _tcs[i].per);
}
hri_tc_set_INTEN_OVF_bit(hw);
_tc_init_irq_param(hw, (void *)device);
NVIC_DisableIRQ(_tcs[i].irq);
NVIC_ClearPendingIRQ(_tcs[i].irq);
NVIC_EnableIRQ(_tcs[i].irq);
return ERR_NONE;
}
/**
* \brief De-initialize TC
*/
void _timer_deinit(struct _timer_device *const device)
{
void *const hw = device->hw;
int8_t i = get_tc_index(hw);
ASSERT(ARRAY_SIZE(_tcs));
NVIC_DisableIRQ(_tcs[i].irq);
hri_tc_clear_CTRLA_ENABLE_bit(hw);
hri_tc_set_CTRLA_SWRST_bit(hw);
}
/**
* \brief Start hardware timer
*/
void _timer_start(struct _timer_device *const device)
{
hri_tc_set_CTRLA_ENABLE_bit(device->hw);
}
/**
* \brief Stop hardware timer
*/
void _timer_stop(struct _timer_device *const device)
{
hri_tc_clear_CTRLA_ENABLE_bit(device->hw);
}
/**
* \brief Set timer period
*/
void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles)
{
void *const hw = device->hw;
if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
hri_tccount32_write_CC_reg(hw, 0, clock_cycles);
} else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
hri_tccount16_write_CC_reg(hw, 0, (uint16_t)clock_cycles);
} else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
hri_tccount8_write_PER_reg(hw, clock_cycles);
}
}
/**
* \brief Retrieve timer period
*/
uint32_t _timer_get_period(const struct _timer_device *const device)
{
void *const hw = device->hw;
if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
return hri_tccount32_read_CC_reg(hw, 0);
} else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
return hri_tccount16_read_CC_reg(hw, 0);
} else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
return hri_tccount8_read_PER_reg(hw);
}
return 0;
}
/**
* \brief Check if timer is running
*/
bool _timer_is_started(const struct _timer_device *const device)
{
return hri_tc_get_CTRLA_ENABLE_bit(device->hw);
}
/**
* \brief Retrieve timer helper functions
*/
struct _timer_hpl_interface *_tc_get_timer(void)
{
return NULL;
}
/**
* \brief Retrieve pwm helper functions
*/
struct _pwm_hpl_interface *_tc_get_pwm(void)
{
return NULL;
}
/**
* \brief Set timer IRQ
*
* \param[in] hw The pointer to hardware instance
*/
void _timer_set_irq(struct _timer_device *const device)
{
void *const hw = device->hw;
int8_t i = get_tc_index(hw);
ASSERT(ARRAY_SIZE(_tcs));
_irq_set(_tcs[i].irq);
}
/**
* \internal TC interrupt handler for Timer
*
* \param[in] instance TC instance number
*/
static void tc_interrupt_handler(struct _timer_device *device)
{
void *const hw = device->hw;
if (hri_tc_get_interrupt_OVF_bit(hw)) {
hri_tc_clear_interrupt_OVF_bit(hw);
device->timer_cb.period_expired(device);
}
}
/**
* \brief TC interrupt handler
*/
void TC0_Handler(void)
{
tc_interrupt_handler(_tc0_dev);
}
/**
* \internal Retrieve TC index
*
* \param[in] hw The pointer to hardware instance
*
* \return The index of TC configuration
*/
static int8_t get_tc_index(const void *const hw)
{
uint8_t index = _get_hardware_offset(hw);
uint8_t i;
for (i = 0; i < ARRAY_SIZE(_tcs); i++) {
if (_tcs[i].number == index) {
return i;
}
}
ASSERT(false);
return -1;
}
/**
* \brief Init irq param with the given tc hardware instance
*/
static void _tc_init_irq_param(const void *const hw, void *dev)
{
if (hw == TC0) {
_tc0_dev = (struct _timer_device *)dev;
}
if (hw == TC2) {
_tc2_dev = (struct _pwm_device *)dev;
}
if (hw == TC4) {
_tc4_dev = (struct _pwm_device *)dev;
}
}
/**
* \internal Retrieve TC hardware index
*
* \param[in] hw The pointer to hardware instance
*/
static inline uint8_t _get_hardware_offset(const void *const hw)
{
/* List of available TC modules. */
Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
/* Find index for TC instance. */
for (uint32_t i = 0; i < TC_INST_NUM; i++) {
if ((uint32_t)hw == (uint32_t)tc_modules[i]) {
return i;
}
}
return 0;
}

77
2_Motor_Master/Motor_Master/Motor_Master/hpl/tc/hpl_tc_base.h Normal file
View File

@ -0,0 +1,77 @@
/**
* \file
*
* \brief SAM Timer/Counter
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*/
#ifndef _HPL_TC_BASE_H_INCLUDED
#define _HPL_TC_BASE_H_INCLUDED
#include <hpl_timer.h>
#include <hpl_pwm.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup tc_group TC Hardware Proxy Layer
*
* \section tc_hpl_rev Revision History
* - v0.0.0.1 Initial Commit
*
*@{
*/
/**
* \name HPL functions
*/
//@{
/**
* \brief Retrieve timer helper functions
*
* \return A pointer to set of timer helper functions
*/
struct _timer_hpl_interface *_tc_get_timer(void);
/**
* \brief Retrieve pwm helper functions
*
* \return A pointer to set of pwm helper functions
*/
struct _pwm_hpl_interface *_tc_get_pwm(void);
//@}
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HPL_TC_BASE_H_INCLUDED */

2
2_Motor_Master/Motor_Master/Motor_Master/hpl/tc/tc_lite.c
View File

@ -78,7 +78,7 @@ int8_t TIMER_0_init()
hri_tccount8_write_CC_reg(TC0, 0, 0x75); /* Compare/Capture Value: 0x75 */
hri_tccount8_write_CC_reg(TC0, 1, 0xc4); /* Compare/Capture Value: 0xb4 */
hri_tccount8_write_CC_reg(TC0, 1, 0xb4); /* Compare/Capture Value: 0xb4 */
// hri_tccount8_write_COUNT_reg(TC0,0x0); /* Counter Value: 0x0 */

7
2_Motor_Master/Motor_Master/Motor_Master/interrupts.h
View File

@ -9,6 +9,7 @@
#ifndef INTERRUPTS_H_
#define INTERRUPTS_H_
#include "configuration.h"
/* TC0 - Interrupt Handler
* Configured to trigger @ 1ms
@ -112,11 +113,15 @@ void TC4_Handler(void)
static void M1_RESET_BAR(void)
{
volatile int x = 0;
Motor1.motor_state.currentstate = MOTOR_FAULT;
Motor1.motor_state.fault = MOTOR_DRIVER_OVER_CURRENT;
}
static void M2_RESET_BAR(void)
{
volatile int x = 0;
Motor2.motor_state.currentstate = MOTOR_FAULT;
Motor2.motor_state.fault = MOTOR_DRIVER_OVER_CURRENT;
}
// ----------------------------------------------------------------------
@ -124,6 +129,8 @@ static void M2_RESET_BAR(void)
// ----------------------------------------------------------------------
void ADS1299_dataReadyISR(void)
{
DMAC->Channel[2].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
DMAC->Channel[8].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
//ADS1299.data_ReadyFlag = true;
//int32_t* temp = ADS1299_UPDATECHANNELDATA();
volatile int x = 1;

40
2_Motor_Master/Motor_Master/Motor_Master/main.c
View File

@ -8,13 +8,15 @@
#include "EtherCAT_QSPI.h"
//#include "MSIF_master.h"
#include "configuration.h"
#include "interrupts.h"
#include "bldc.h"
#include "bldc_types.h"
#include "EtherCAT_SlaveDef.h"
#include "interrupts.h"
#include "statemachine.h"
#include "angle_sensors.h"
#include "ADS1299.h"
@ -29,8 +31,8 @@ void process_currents()
volatile int16_t phase_A_current_raw, phase_B_current_raw;
/* Motor 1 */
phase_A_current_raw = (adc1_res[0] + Motor1.Voffset_lsb.A);
phase_B_current_raw = (adc1_res[1] + Motor1.Voffset_lsb.B)*-1;
phase_A_current_raw = (adc1_res[0] - Motor1.Voffset_lsb.A);
phase_B_current_raw = (adc1_res[1] - Motor1.Voffset_lsb.B)*-1;
// Covert from LSB to PU (A) and filter out small readings
Motor1.Iphase_pu.A = phase_A_current_raw * LSB_TO_PU;
Motor1.Iphase_pu.B = phase_B_current_raw * LSB_TO_PU;
@ -38,8 +40,8 @@ void process_currents()
Motor1.Iphase_pu.C = -Motor1.Iphase_pu.A - Motor1.Iphase_pu.B;
/* Motor 2 negative is A instead of B*/
phase_A_current_raw = (adc1_res[2] + Motor2.Voffset_lsb.A);
phase_B_current_raw = (adc1_res[3] + Motor2.Voffset_lsb.B)*-1;
phase_A_current_raw = (adc1_res[2] - Motor2.Voffset_lsb.A);
phase_B_current_raw = (adc1_res[3] - Motor2.Voffset_lsb.B)*-1;
// Covert from LSB to PU (A) and filter out small readings
Motor2.Iphase_pu.A = phase_A_current_raw * LSB_TO_PU;
Motor2.Iphase_pu.B = phase_B_current_raw * LSB_TO_PU;
@ -65,8 +67,9 @@ void enable_NVIC_IRQ(void)
NVIC_SetPriority(DMAC_0_IRQn, 2);
NVIC_SetPriority(ADC1_0_IRQn, 3);
NVIC_EnableIRQ(TCC0_0_IRQn);
NVIC_EnableIRQ(TCC1_0_IRQn);
//NVIC_EnableIRQ(TCC1_0_IRQn);
NVIC_EnableIRQ(EIC_2_IRQn);
NVIC_EnableIRQ(SERCOM1_1_IRQn);
//NVIC_SetPriority(SERCOM1_1_IRQn, 1);
NVIC_EnableIRQ(TC0_IRQn);
@ -74,6 +77,12 @@ void enable_NVIC_IRQ(void)
//NVIC_SetPriority(EIC_2_IRQn, 3);
//NVIC_SetPriority(TCC0_0_IRQn, 3);
//NVIC_EnableIRQ(EIC_5_IRQn);
/* Reset Latch Interrupt */
ext_irq_register(PIN_PB30, M1_RESET_BAR);
ext_irq_register(PIN_PB31, M2_RESET_BAR);
NVIC_EnableIRQ(EIC_14_IRQn);
NVIC_EnableIRQ(EIC_15_IRQn);
}
void APPLICATION_StateMachine(void)
@ -91,11 +100,8 @@ void APPLICATION_StateMachine(void)
case SYSTEM_INIT:
/* Toggle driver reset Latch */
gpio_set_pin_level(M1_RST, true);
delay_ms(1);
gpio_set_pin_level(M1_RST, false);
delay_ms(1);
gpio_set_pin_level(M2_RST, true);
delay_ms(1);
gpio_set_pin_level(M2_RST, false);
/* Update State Variables */
applicationStatus.previousstate = applicationStatus.currentstate;
@ -163,14 +169,16 @@ int main(void)
ECAT_STATE_MACHINE();
//angle_sensor_init();
//initialize_ads();
initialize_ads();
/* External IRQ Config */
custom_logic_enable();
enable_NVIC_IRQ();
__enable_irq();
//ext_irq_register(GPIO_PIN(ADS_DATA_RDY), ADS1299_dataReadyISR);
//ADS1299_START();
ext_irq_register(GPIO_PIN(ADS_DATA_RDY), ADS1299_dataReadyISR);
__enable_irq();
ADS1299_START();
enable_NVIC_IRQ();
/* Replace with your application code */
while (1) {
@ -179,7 +187,7 @@ int main(void)
if (Motor1.timerflags.motor_telemetry_flag) {
Motor1.timerflags.motor_telemetry_flag = false;
delay_us(10);
//delay_us(10);
DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
@ -191,7 +199,7 @@ int main(void)
update_telemetry();
update_setpoints();
//PORT->Group[1].OUTCLR.reg = (1<<GPIO_PIN(SPI1_CS));
//_dma_enable_transaction(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, false);

6
2_Motor_Master/Motor_Master/Motor_Master/motorparameters.h
View File

@ -169,13 +169,13 @@ const static BLDCMotor_param_t FH_32mm12BXTR = {
.motor_LD_H = 0.000331,
.motor_LQ_H = 0.000331,
.motor_Flux_WB = 0.0063879968,
.motor_Max_Spd_RPM = 1000,
.motor_Max_Spd_RPM = 2000,
.motor_MeasureRange_RPM = 3200, //(1.2f * MOTOR_MAX_SPD_RPM)f // give 20% headroom
.motor_Max_Spd_ELEC = 12000, //(MOTOR_MAX_SPD_RPM/60)*MOTOR_POLEPAIRS
.motor_Max_Current_IDC_A = (1.2),
.controller_param.Pid_Speed.Kp = 0.0004f,
.controller_param.Pid_Speed.Kp = 0.0003f,
.controller_param.Pid_Speed.Ki = 0.0000001f,
.controller_param.Pi_Pos.Kp = 50.0f,
.controller_param.Pi_Pos.Kp = 40.0f,
.controller_param.Pi_Pos.Ki = 0.000f,
//.controller_param.Pid_Speed.Kp = 0.00002f,
//.controller_param.Pid_Speed.Ki = 0.0f,

5
2_Motor_Slave/Motor_Slave/Motor_Slave/interrupts.h
View File

@ -52,11 +52,16 @@ void TC4_Handler(void)
static void M1_RESET_BAR(void)
{
volatile int x = 0;
Motor1.motor_state.currentstate = MOTOR_FAULT;
Motor1.motor_state.fault = MOTOR_DRIVER_OVER_CURRENT;
}
static void M2_RESET_BAR(void)
{
volatile int x = 0;
Motor2.motor_state.currentstate = MOTOR_FAULT;
Motor2.motor_state.fault = MOTOR_DRIVER_OVER_CURRENT;
}
// ----------------------------------------------------------------------

6
2_Motor_Slave/Motor_Slave/Motor_Slave/main.c
View File

@ -144,6 +144,12 @@ void enable_NVIC_IRQ(void)
NVIC_SetPriority(SERCOM1_1_IRQn, 0);
//NVIC_EnableIRQ(SERCOM1_3_IRQn);
//NVIC_EnableIRQ(EIC_5_IRQn);
/* Reset Latch Interrupt */
ext_irq_register(PIN_PB30, M1_RESET_BAR);
ext_irq_register(PIN_PB31, M2_RESET_BAR);
NVIC_EnableIRQ(EIC_14_IRQn);
NVIC_EnableIRQ(EIC_15_IRQn);
}
void APPLICATION_StateMachine(void)

BIN
Twincat/MotorData/.vs/MotorData/v15/.suo
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BIN
Twincat/MotorData/Scope Project1.svdx
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402
Twincat/MotorData/TwinCAT Measurement Project1/Scope Project1.tcscopex
View File

@ -16,7 +16,7 @@
<Layout>&lt;?xml version="1.0" encoding="utf-16"?&gt;
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@ -1176,6 +1176,168 @@
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@ -3286,6 +3448,125 @@
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@ -3587,6 +3868,125 @@
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