diff --git a/2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart b/2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart index fa34563..7d0b936 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart +++ b/2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart @@ -440,7 +440,7 @@ drivers: dmac_evie_17: false dmac_evie_18: false dmac_evie_19: false - dmac_evie_2: true + dmac_evie_2: false dmac_evie_20: false dmac_evie_21: false dmac_evie_22: false @@ -504,7 +504,7 @@ drivers: dmac_evosel_17: Event generation disabled dmac_evosel_18: Event generation disabled dmac_evosel_19: Event generation disabled - dmac_evosel_2: Event strobe when beat transfer complete + dmac_evosel_2: Event strobe when block transfer complete dmac_evosel_20: Event generation disabled dmac_evosel_21: Event generation disabled dmac_evosel_22: Event generation disabled @@ -940,7 +940,7 @@ drivers: evsys_channel_27: No channel output selected evsys_channel_28: No channel output selected evsys_channel_29: No channel output selected - evsys_channel_3: No channel output selected + evsys_channel_3: Channel 5 evsys_channel_30: No channel output selected evsys_channel_31: No channel output selected evsys_channel_32: No channel output selected @@ -1011,7 +1011,7 @@ drivers: evsys_channel_setting_30: false evsys_channel_setting_31: false evsys_channel_setting_4: true - evsys_channel_setting_5: true + evsys_channel_setting_5: false evsys_channel_setting_6: false evsys_channel_setting_7: false evsys_channel_setting_8: false @@ -1344,11 +1344,11 @@ drivers: functionality: System api: HAL:HPL:GCLK configuration: - $input: 12000000 - $input_id: External Crystal Oscillator 8-48MHz (XOSC1) - RESERVED_InputFreq: 12000000 - RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1) - _$freq_output_Generic clock generator 0: 120000000 + $input: 100000000 + $input_id: Digital Phase Locked Loop (DPLL1) + RESERVED_InputFreq: 100000000 + RESERVED_InputFreq_id: Digital Phase Locked Loop (DPLL1) + _$freq_output_Generic clock generator 0: 100000000 _$freq_output_Generic clock generator 1: 2000000 _$freq_output_Generic clock generator 10: 12000000 _$freq_output_Generic clock generator 11: 12000000 @@ -1490,11 +1490,11 @@ drivers: functionality: System api: HAL:HPL:MCLK configuration: - $input: 120000000 + $input: 100000000 $input_id: Generic clock generator 0 - RESERVED_InputFreq: 120000000 + RESERVED_InputFreq: 100000000 RESERVED_InputFreq_id: Generic clock generator 0 - _$freq_output_CPU: 120000000 + _$freq_output_CPU: 100000000 cpu_clock_source: Generic clock generator 0 cpu_div: '1' enable_cpu_clock: true @@ -1557,7 +1557,7 @@ drivers: RESERVED_InputFreq_id: Generic clock generator 1 _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000 _$freq_output_Digital Phase Locked Loop (DPLL0): 47985664 - _$freq_output_Digital Phase Locked Loop (DPLL1): 120000000 + _$freq_output_Digital Phase Locked Loop (DPLL1): 100000000 _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000 _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000 dfll_arch_bplckc: false @@ -1608,7 +1608,7 @@ drivers: fdpll1_arch_wuf: false fdpll1_clock_dcofilter: 0 fdpll1_clock_div: 0 - fdpll1_ldr: 59 + fdpll1_ldr: 49 fdpll1_ldrfrac: 0 fdpll1_ref_clock: Generic clock generator 1 xosc0_arch_cfden: false @@ -1647,11 +1647,11 @@ drivers: enable_port_input_event_3: false porta_event_action_0: Output register of pin will be set to level of event porta_event_action_1: Output register of pin will be set to level of event - porta_event_action_2: Output register of pin will be set to level of event + porta_event_action_2: Set output register of pin on event porta_event_action_3: Output register of pin will be set to level of event porta_event_pin_identifier_0: 0 porta_event_pin_identifier_1: 0 - porta_event_pin_identifier_2: 0 + porta_event_pin_identifier_2: 14 porta_event_pin_identifier_3: 0 porta_input_event_enable_0: false porta_input_event_enable_1: false @@ -1802,9 +1802,9 @@ drivers: spi_master_arch_cpol: SCK is low when idle spi_master_arch_dbgstop: Keep running spi_master_arch_dord: MSB first - spi_master_arch_ibon: In data stream + spi_master_arch_ibon: On buffer overflow spi_master_arch_runstdby: false - spi_master_baud_rate: 4000000 + spi_master_baud_rate: 1000000 spi_master_character_size: 8 bits spi_master_dummybyte: 511 spi_master_rx_enable: true @@ -1848,7 +1848,7 @@ drivers: spi_master_arch_dord: MSB first spi_master_arch_ibon: In data stream spi_master_arch_runstdby: false - spi_master_baud_rate: 8000000 + spi_master_baud_rate: 1000000 spi_master_character_size: 8 bits spi_master_dummybyte: 511 spi_master_rx_enable: true diff --git a/2_Motor_Master/Motor_Master/Motor_Master/ADS1299.c b/2_Motor_Master/Motor_Master/Motor_Master/ADS1299.c index dc469a1..29fbe58 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/ADS1299.c +++ b/2_Motor_Master/Motor_Master/Motor_Master/ADS1299.c @@ -72,8 +72,8 @@ void initialize_ads() ADS1299_WREG(LOFF,0x02); // Set LOFF Register for(uint8_t i=CH1SET; i<=CH4SET; i++) // set up to modify the 4 channel setting registers { - ADS1299.regData[i] = 0x68; // the regData array mirrors the ADS1299 register addresses - //ADS1299.regData[i] = 0x6D; // Test signal + //ADS1299.reg_data[i] = 0x68; // the regData array mirrors the ADS1299 register addresses + ADS1299.reg_data[i] = 0x6D; // Test signal } ADS1299_WREGS(CH1SET,3); // write new channel settings ADS1299_WREG(BIAS_SENSP,0xFF); // Set BIAS_SENSP Register @@ -120,8 +120,22 @@ void ADS1299_START() { //start data conversion gpio_set_pin_level(ADS1299.SS_pin, false); _transfer_byte(ADS1299.SPI_descr, _START); gpio_set_pin_level(ADS1299.SS_pin, true); + delay_us(20); + init_streaming_mode(); + } +void init_streaming_mode() +{ + spi_m_sync_disable(ADS1299.SPI_descr); + /* Change to 32-Bit Mode */ + SERCOM2->SPI.CTRLC.bit.ICSPACE = 4; + SERCOM2->SPI.CTRLC.bit.DATA32B= true; + SERCOM2->SPI.LENGTH.bit.LENEN = true; + SERCOM2->SPI.LENGTH.bit.LEN = 3; + /* Init SPI*/ + spi_m_sync_enable(ADS1299.SPI_descr); +} void ADS1299_STOP() { //stop data conversion gpio_set_pin_level(ADS1299.SS_pin, false); _transfer_byte(ADS1299.SPI_descr, _STOP); @@ -151,9 +165,9 @@ uint8_t ADS1299_RREG(uint8_t _address) gpio_set_pin_level(ADS1299.SS_pin, false); _transfer_byte(ADS1299.SPI_descr, opcode1); _transfer_byte(ADS1299.SPI_descr, 0x00); - ADS1299.regData[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00); + ADS1299.reg_data[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00); gpio_set_pin_level(ADS1299.SS_pin, true); - return ADS1299.regData[_address]; + return ADS1299.reg_data[_address]; } // Read more than one register starting at _address @@ -164,7 +178,7 @@ void ADS1299_RREGS(uint8_t _address, uint8_t _numRegistersMinusOne) _transfer_byte(ADS1299.SPI_descr, opcode1); _transfer_byte(ADS1299.SPI_descr, _numRegistersMinusOne); for(int i = 0; i <= _numRegistersMinusOne; i++){ // add register uint8_t to mirror array - ADS1299.regData[_address + i] = _transfer_byte(ADS1299.SPI_descr, 0x00); + ADS1299.reg_data[_address + i] = _transfer_byte(ADS1299.SPI_descr, 0x00); } //ADS1299.regData[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00); gpio_set_pin_level(ADS1299.SS_pin, true); @@ -177,7 +191,7 @@ void ADS1299_WREG(uint8_t _address, uint8_t _value) { // Write ONE register _transfer_byte(ADS1299.SPI_descr, 0x00); // Send number of registers to read -1 _transfer_byte(ADS1299.SPI_descr, _value); // Write the value to the register gpio_set_pin_level(ADS1299.SS_pin, true); // close SPI - ADS1299.regData[_address] = _value; // update the mirror array + ADS1299.reg_data[_address] = _value; // update the mirror array } void ADS1299_WREGS(uint8_t _address, uint8_t _numRegistersMinusOne) { @@ -186,7 +200,7 @@ void ADS1299_WREGS(uint8_t _address, uint8_t _numRegistersMinusOne) { _transfer_byte(ADS1299.SPI_descr, opcode1); // Send WREG command & address _transfer_byte(ADS1299.SPI_descr, _numRegistersMinusOne); // Send number of registers to read -1 for (int i=_address; i <=(_address + _numRegistersMinusOne); i++){ - _transfer_byte(ADS1299.SPI_descr, ADS1299.regData[i]); // Write to the registers + _transfer_byte(ADS1299.SPI_descr, ADS1299.reg_data[i]); // Write to the registers } gpio_set_pin_level(ADS1299.SS_pin, true); // close SPI } @@ -268,7 +282,7 @@ int32_t* ADS1299_UPDATECHANNELDATA() for(int i = 0; i<8; i++){ for(int j=0; j<3; j++){ // read 24 bits of channel data from 1st ADS in 8 3 byte chunks inByte = _transfer_byte(ADS1299.SPI_descr, 0x00); - _channel_data[i] = (_channel_data[i]<<8) | inByte; + _ads1299_channel_data[i] = (_ads1299_channel_data[i]<<8) | inByte; } } @@ -276,13 +290,13 @@ int32_t* ADS1299_UPDATECHANNELDATA() //reformat the numbers for(int i=0; i Indicates whether channel event reception is enabled or not // dmac_evie_2 #ifndef CONF_DMAC_EVIE_2 -#define CONF_DMAC_EVIE_2 1 +#define CONF_DMAC_EVIE_2 0 #endif // Event Input Action @@ -770,7 +770,7 @@ // Defines the event output selection // dmac_evosel_2 #ifndef CONF_DMAC_EVOSEL_2 -#define CONF_DMAC_EVOSEL_2 3 +#define CONF_DMAC_EVOSEL_2 1 #endif // diff --git a/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_evsys_config.h b/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_evsys_config.h index b92ee9d..2ca2d1b 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_evsys_config.h +++ b/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_evsys_config.h @@ -912,7 +912,7 @@ // Channel 5 settings // evsys_channel_setting_5 #ifndef CONF_EVSYS_CHANNEL_SETTINGS_5 -#define CONF_EVSYS_CHANNEL_SETTINGS_5 1 +#define CONF_EVSYS_CHANNEL_SETTINGS_5 0 #endif // Edge detection @@ -5960,7 +5960,7 @@ // evsys_channel_3 // Indicates which channel is chosen for user #ifndef CONF_CHANNEL_3 -#define CONF_CHANNEL_3 0 +#define CONF_CHANNEL_3 6 #endif // Channel selection for PORT event 3 diff --git a/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_oscctrl_config.h b/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_oscctrl_config.h index 3fc7613..b62c2bc 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_oscctrl_config.h +++ b/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_oscctrl_config.h @@ -568,7 +568,7 @@ // Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register // fdpll1_ldr #ifndef CONF_FDPLL1_LDR -#define CONF_FDPLL1_LDR 0x3b +#define CONF_FDPLL1_LDR 0x31 #endif // Clock Divider <0x0-0x7FF> diff --git a/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_port_config.h b/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_port_config.h index 81661ca..0fdac54 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_port_config.h +++ b/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_port_config.h @@ -153,7 +153,7 @@ // These bits define the I/O pin from port A on which the event action will be performed // porta_event_pin_identifier_2 #ifndef CONF_PORTA_EVCTRL_PID_2 -#define CONF_PORTA_EVCTRL_PID_2 0x0 +#define CONF_PORTA_EVCTRL_PID_2 0xe #endif // PORTA Event 2 Action @@ -164,7 +164,7 @@ // These bits define the event action the PORT A will perform on event input 2 // porta_event_action_2 #ifndef CONF_PORTA_EVCTRL_EVACT_2 -#define CONF_PORTA_EVCTRL_EVACT_2 0 +#define CONF_PORTA_EVCTRL_EVACT_2 1 #endif // diff --git a/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_sercom_config.h b/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_sercom_config.h index fc6b1b2..0de38f7 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_sercom_config.h +++ b/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_sercom_config.h @@ -218,7 +218,7 @@ // The SPI data transfer rate // spi_master_baud_rate #ifndef CONF_SERCOM_2_SPI_BAUD -#define CONF_SERCOM_2_SPI_BAUD 4000000 +#define CONF_SERCOM_2_SPI_BAUD 1000000 #endif // @@ -269,7 +269,7 @@ // <0x1=>On buffer overflow // spi_master_arch_ibon #ifndef CONF_SERCOM_2_SPI_IBON -#define CONF_SERCOM_2_SPI_IBON 0x0 +#define CONF_SERCOM_2_SPI_IBON 0x1 #endif // Run in stand-by @@ -377,7 +377,7 @@ // The SPI data transfer rate // spi_master_baud_rate #ifndef CONF_SERCOM_5_SPI_BAUD -#define CONF_SERCOM_5_SPI_BAUD 8000000 +#define CONF_SERCOM_5_SPI_BAUD 1000000 #endif // diff --git a/2_Motor_Master/Motor_Master/Motor_Master/Config/peripheral_clk_config.h b/2_Motor_Master/Motor_Master/Motor_Master/Config/peripheral_clk_config.h index 69adb5c..8610b04 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/Config/peripheral_clk_config.h +++ b/2_Motor_Master/Motor_Master/Motor_Master/Config/peripheral_clk_config.h @@ -41,7 +41,7 @@ * \brief ADC1's Clock frequency */ #ifndef CONF_GCLK_ADC1_FREQUENCY -#define CONF_GCLK_ADC1_FREQUENCY 120000000 +#define CONF_GCLK_ADC1_FREQUENCY 100000000 #endif // CCL Clock Source @@ -81,7 +81,7 @@ * \brief CCL's Clock frequency */ #ifndef CONF_GCLK_CCL_FREQUENCY -#define CONF_GCLK_CCL_FREQUENCY 120000000 +#define CONF_GCLK_CCL_FREQUENCY 100000000 #endif // EIC Clock Source @@ -121,7 +121,7 @@ * \brief EIC's Clock frequency */ #ifndef CONF_GCLK_EIC_FREQUENCY -#define CONF_GCLK_EIC_FREQUENCY 120000000 +#define CONF_GCLK_EIC_FREQUENCY 100000000 #endif // EVSYS Channel 0 Clock Source @@ -162,7 +162,7 @@ */ #ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000 +#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 100000000 #endif // EVSYS Channel 1 Clock Source @@ -203,7 +203,7 @@ */ #ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000 +#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 100000000 #endif // EVSYS Channel 2 Clock Source @@ -244,7 +244,7 @@ */ #ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000 +#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 100000000 #endif // EVSYS Channel 3 Clock Source @@ -285,7 +285,7 @@ */ #ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000 +#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 100000000 #endif // EVSYS Channel 4 Clock Source @@ -326,7 +326,7 @@ */ #ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000 +#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 100000000 #endif // EVSYS Channel 5 Clock Source @@ -367,7 +367,7 @@ */ #ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000 +#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 100000000 #endif // EVSYS Channel 6 Clock Source @@ -408,7 +408,7 @@ */ #ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000 +#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 100000000 #endif // EVSYS Channel 7 Clock Source @@ -449,7 +449,7 @@ */ #ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000 +#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 100000000 #endif // EVSYS Channel 8 Clock Source @@ -490,7 +490,7 @@ */ #ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000 +#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 100000000 #endif // EVSYS Channel 9 Clock Source @@ -531,7 +531,7 @@ */ #ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000 +#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 100000000 #endif // EVSYS Channel 10 Clock Source @@ -572,7 +572,7 @@ */ #ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000 +#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 100000000 #endif // EVSYS Channel 11 Clock Source @@ -613,7 +613,7 @@ */ #ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000 +#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 100000000 #endif /** @@ -621,7 +621,7 @@ * \brief CPU's Clock frequency */ #ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 120000000 +#define CONF_CPU_FREQUENCY 100000000 #endif // Core Clock Source @@ -693,7 +693,7 @@ * \brief SERCOM1's Core Clock frequency */ #ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY -#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 120000000 +#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 100000000 #endif /** @@ -773,7 +773,7 @@ * \brief SERCOM2's Core Clock frequency */ #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY -#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 120000000 +#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 100000000 #endif /** @@ -853,7 +853,7 @@ * \brief SERCOM5's Core Clock frequency */ #ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY -#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 120000000 +#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 100000000 #endif /** @@ -901,7 +901,7 @@ * \brief TC0's Clock frequency */ #ifndef CONF_GCLK_TC0_FREQUENCY -#define CONF_GCLK_TC0_FREQUENCY 120000000 +#define CONF_GCLK_TC0_FREQUENCY 100000000 #endif // TC Clock Source @@ -941,7 +941,7 @@ * \brief TC2's Clock frequency */ #ifndef CONF_GCLK_TC2_FREQUENCY -#define CONF_GCLK_TC2_FREQUENCY 120000000 +#define CONF_GCLK_TC2_FREQUENCY 100000000 #endif // TC Clock Source @@ -981,7 +981,7 @@ * \brief TC4's Clock frequency */ #ifndef CONF_GCLK_TC4_FREQUENCY -#define CONF_GCLK_TC4_FREQUENCY 120000000 +#define CONF_GCLK_TC4_FREQUENCY 100000000 #endif // TCC Clock Source @@ -1021,7 +1021,7 @@ * \brief TCC0's Clock frequency */ #ifndef CONF_GCLK_TCC0_FREQUENCY -#define CONF_GCLK_TCC0_FREQUENCY 120000000 +#define CONF_GCLK_TCC0_FREQUENCY 100000000 #endif // TCC Clock Source @@ -1061,7 +1061,7 @@ * \brief TCC1's Clock frequency */ #ifndef CONF_GCLK_TCC1_FREQUENCY -#define CONF_GCLK_TCC1_FREQUENCY 120000000 +#define CONF_GCLK_TCC1_FREQUENCY 100000000 #endif // <<< end of configuration section >>> diff --git a/2_Motor_Master/Motor_Master/Motor_Master/EtherCAT_SlaveDef.h b/2_Motor_Master/Motor_Master/Motor_Master/EtherCAT_SlaveDef.h index 27d1c3e..dfc6c65 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/EtherCAT_SlaveDef.h +++ b/2_Motor_Master/Motor_Master/Motor_Master/EtherCAT_SlaveDef.h @@ -11,9 +11,12 @@ #include "Ethercat_QSPI.h" #include "arm_math.h" +#include "ADS1299.h" + +extern volatile uint8_t _ads1299_reg_data[24]; +extern volatile int32_t _ads1299_channel_data[9]; +extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE]; -extern volatile int32_t _channel_data[8]; -extern volatile uint32_t ads1299_buffer[6]; //Write To Ecat Total Bytes (XX bytes) /* Motor 1*/ @@ -195,10 +198,10 @@ static void update_telemetry(void) *M2_Motor_speed = (int16_t)Motor2.motor_status.calc_rpm; //*M2_Joint_abs_position = Motor2.motor_status.actualDirection; - *EMG_CH1 = _channel_data[0]; - *EMG_CH2 = _channel_data[1]; - *EMG_CH3 = _channel_data[2]; - *EMG_CH4 = _channel_data[3]; + *EMG_CH1 = _ads1299_channel_data[0]; + *EMG_CH2 = _ads1299_channel_data[1]; + *EMG_CH3 = _ads1299_channel_data[2]; + *EMG_CH4 = _ads1299_channel_data[3]; //*EMG_CH1 = 1; //*EMG_CH2 = 2; //*EMG_CH3 = 3; diff --git a/2_Motor_Master/Motor_Master/Motor_Master/Ethercat_SlaveDef.h b/2_Motor_Master/Motor_Master/Motor_Master/Ethercat_SlaveDef.h index 27d1c3e..dfc6c65 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/Ethercat_SlaveDef.h +++ b/2_Motor_Master/Motor_Master/Motor_Master/Ethercat_SlaveDef.h @@ -11,9 +11,12 @@ #include "Ethercat_QSPI.h" #include "arm_math.h" +#include "ADS1299.h" + +extern volatile uint8_t _ads1299_reg_data[24]; +extern volatile int32_t _ads1299_channel_data[9]; +extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE]; -extern volatile int32_t _channel_data[8]; -extern volatile uint32_t ads1299_buffer[6]; //Write To Ecat Total Bytes (XX bytes) /* Motor 1*/ @@ -195,10 +198,10 @@ static void update_telemetry(void) *M2_Motor_speed = (int16_t)Motor2.motor_status.calc_rpm; //*M2_Joint_abs_position = Motor2.motor_status.actualDirection; - *EMG_CH1 = _channel_data[0]; - *EMG_CH2 = _channel_data[1]; - *EMG_CH3 = _channel_data[2]; - *EMG_CH4 = _channel_data[3]; + *EMG_CH1 = _ads1299_channel_data[0]; + *EMG_CH2 = _ads1299_channel_data[1]; + *EMG_CH3 = _ads1299_channel_data[2]; + *EMG_CH4 = _ads1299_channel_data[3]; //*EMG_CH1 = 1; //*EMG_CH2 = 2; //*EMG_CH3 = 3; diff --git a/2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj b/2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj index d7df212..92d86df 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj +++ b/2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj @@ -206,18 +206,18 @@ - + - + - - + + - + - + diff --git a/2_Motor_Master/Motor_Master/Motor_Master/configuration.h b/2_Motor_Master/Motor_Master/Motor_Master/configuration.h index 8461b0d..17346e6 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/configuration.h +++ b/2_Motor_Master/Motor_Master/Motor_Master/configuration.h @@ -17,6 +17,7 @@ #include "interrupts.h" #include "hpl_sercom_config.h" #include "ADS1299.h" +#include "hpl_spi_m_dma.h" // ---------------------------------------------------------------------- // ADC DMA Initialization // M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6] @@ -144,8 +145,8 @@ static void boardToBoardTransferInit(void) spi_m_dma_get_io_descriptor(&SPI_1_MSIF, &io); //spi_m_dma_register_callback(&SPI_1_MSIF, SPI_M_DMA_CB_RX_DONE, b2bTransferComplete_cb); //SERCOM4->SPI.CTRLC.bit.DATA32B = true; - SERCOM1->SPI.LENGTH.bit.LENEN = true; - SERCOM1->SPI.LENGTH.bit.LEN = 64; + //SERCOM1->SPI.LENGTH.bit.LENEN = true; + //SERCOM1->SPI.LENGTH.bit.LEN = 64; SERCOM1->SPI.CTRLC.bit.ICSPACE = 4; SERCOM1->SPI.CTRLC.bit.DATA32B= true; @@ -188,7 +189,7 @@ static void spi_master_init_dma_descriptors() #define CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL 2U #define CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL 8U -#define ADS_BUFFER_SIZE 6 + /* 219 Bites total @@ -196,25 +197,38 @@ static void spi_master_init_dma_descriptors() * 7 (uint_32) - 24 bits */ extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE]; - // static void spi_ads1299_init_dma_descriptors() { _dma_set_source_address(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, (uint32_t *)&(((SercomSpi *)(SPI_2.dev.prvt))->DATA.reg)); - _dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, &QSPI_rx_buffer[10]); + _dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, &_ads1299_channel_data[0]); _dma_set_data_amount(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, ADS_BUFFER_SIZE); - _dma_set_next_descriptor(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL); + //_dma_set_next_descriptor(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL); _dma_set_source_address(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, &ads1299_buffer[0]); _dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, - (uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg)); + (uint32_t *)&(((SercomSpi *)(SPI_2.dev.prvt))->DATA.reg)); _dma_set_data_amount(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, ADS_BUFFER_SIZE); hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL]); hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL]); + + + /* callback */ + struct _dma_resource *resource_rx, *resource_tx; + _dma_get_channel_resource(&resource_rx, CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL); + _dma_get_channel_resource(&resource_tx, CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL); + resource_rx->dma_cb.transfer_done = ADS1299_Transfer_Complete_cb; + //resource_rx->dma_cb.error = ADS1299_Transfer_error_cb; + + /* Enable DMA transfer complete interrupt */ + _dma_set_irq_state(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true); + //_dma_set_irq_state(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, DMA_TRANSFER_ERROR_CB, true); + + } @@ -231,9 +245,9 @@ static void spi_ads1299_init_dma_descriptors() * CH5 - ADC1 - Result Ready * CH6 - ADC0 - Sequencer (Unused on master) - Currently Disabled in ASTART * CH7 - ADC1 - Sequencer - Triggered by TCC0 overflow event -* CH8 - SERCOM2_TX(SPI2) - Master-Slave IF -* CH9 - SERCOM5_TX(SPI3) - Expansion IF (EMG) -* CH10 - SERCOM1_TX(SPI1) - Angle Sensor +* CH8 - SERCOM2_TX(SPI2) - Expansion IF (EMG) +* CH9 - SERCOM5_TX(SPI3) - Angle Sensor +* CH10 - SERCOM1_TX(SPI1) - Master-Slave IF * CH11 - QSPI_TX - For ECAT DMA Mode - Currently Disabled in ASTART */ static void init_dma(void) diff --git a/2_Motor_Master/Motor_Master/Motor_Master/interrupts.h b/2_Motor_Master/Motor_Master/Motor_Master/interrupts.h index 3853c8c..2867fbc 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/interrupts.h +++ b/2_Motor_Master/Motor_Master/Motor_Master/interrupts.h @@ -10,6 +10,7 @@ #define INTERRUPTS_H_ #include "configuration.h" +#include "ADS1299.h" /* TC0 - Interrupt Handler * Configured to trigger @ 1ms @@ -66,6 +67,7 @@ static void b2bTransferComplete_cb(struct _dma_resource *resource) //volatile int x = 0; //PORT->Group[GPIO_PORTB].OUTCLR.reg = (1<SS_pin); //gpio_set_pin_level(SPI1_CS, true); + volatile int x = 0; } @@ -129,14 +131,24 @@ static void M2_RESET_BAR(void) // ---------------------------------------------------------------------- void ADS1299_dataReadyISR(void) { - DMAC->Channel[2].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - DMAC->Channel[8].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - //ADS1299.data_ReadyFlag = true; + + ADS1299.data_ReadyFlag = true; //int32_t* temp = ADS1299_UPDATECHANNELDATA(); volatile int x = 1; } +void ADS1299_Transfer_Complete_cb(void) +{ + PORT->Group[0].OUTSET.reg = (1<SPI.STATUS.bit.BUFOVF = 1; + //PORT->Group[0].OUTSET.reg = (1<Group[0].OUTCLR.reg = (1<Channel[2].CHSTATUS.bit.FERR == true) || (DMAC->Channel[8].CHSTATUS.bit.FERR == true)) + { + volatile int x = 0; + } + + DMAC->Channel[2].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC->Channel[8].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + //_dma_enable_transaction(2, false); + //_dma_enable_transaction(8, false); + + //ADS1299_UPDATECHANNELDATA(); } diff --git a/2_Motor_Master/Motor_Master/Motor_Master/motorparameters.h b/2_Motor_Master/Motor_Master/Motor_Master/motorparameters.h index ef04cde..9fe285d 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/motorparameters.h +++ b/2_Motor_Master/Motor_Master/Motor_Master/motorparameters.h @@ -154,7 +154,7 @@ const static BLDCMotor_param_t FH_22mm24BXTR = { .controller_param.Pid_Speed.Kp = 0.00004f, .controller_param.Pid_Speed.Ki = 0.0000001f, //.controller_param.Pid_Speed.Ki = 0.0000001f, - .controller_param.Pi_Pos.Kp = 50.0f, + .controller_param.Pi_Pos.Kp = 30.0f, .controller_param.Pi_Pos.Ki = 0.0f, .motor_MaxPWM = 600.0, }; @@ -175,7 +175,7 @@ const static BLDCMotor_param_t FH_32mm12BXTR = { .motor_Max_Current_IDC_A = (1.2), .controller_param.Pid_Speed.Kp = 0.0003f, .controller_param.Pid_Speed.Ki = 0.0000001f, - .controller_param.Pi_Pos.Kp = 40.0f, + .controller_param.Pi_Pos.Kp = 30.0f, .controller_param.Pi_Pos.Ki = 0.000f, //.controller_param.Pid_Speed.Kp = 0.00002f, //.controller_param.Pid_Speed.Ki = 0.0f, diff --git a/Twincat/MotorData/.vs/MotorData/v15/.suo b/Twincat/MotorData/.vs/MotorData/v15/.suo index 54f98fc..ef9ed93 100644 Binary files a/Twincat/MotorData/.vs/MotorData/v15/.suo and b/Twincat/MotorData/.vs/MotorData/v15/.suo differ