From 2f5a303a0a598aee9c6456987b583e3d4cab2613 Mon Sep 17 00:00:00 2001 From: Nicolas Trimborn Date: Wed, 28 Jul 2021 23:24:30 +0200 Subject: [PATCH] Got Master/Slave Comms working --- .../.atmelstart/AtmelStart.env_conf | 6 + .../.atmelstart/AtmelStart.gpdsc | 239 + .../.atmelstart/atmel_start_config.atstart | 1610 ++ .../Master_Slave_IF_TestMaster/A1335.c | 520 + .../Master_Slave_IF_TestMaster/A1335.h | 45 + .../Master_Slave_IF_TestMaster/AS5048.c | 186 + .../Master_Slave_IF_TestMaster/AS5048.h | 38 + .../Config/RTE_Components.h | 54 + .../Config/hpl_cmcc_config.h | 54 + .../Config/hpl_dmac_config.h | 7277 +++++++ .../Config/hpl_evsys_config.h | 8363 ++++++++ .../Config/hpl_gclk_config.h | 920 + .../Config/hpl_mclk_config.h | 104 + .../Config/hpl_osc32kctrl_config.h | 165 + .../Config/hpl_oscctrl_config.h | 640 + .../Config/hpl_port_config.h | 522 + .../Config/hpl_sercom_config.h | 618 + .../Config/hpl_tc_config.h | 180 + .../Config/peripheral_clk_config.h | 789 + .../Config/spi_slave_dma_config.h | 47 + .../Config/stdio_redirect_config.h | 9 + .../Master_Slave_IF_TestMaster/Default.xml | 475 + .../Device_Startup/same54p20a_flash.ld | 163 + .../Device_Startup/same54p20a_sram.ld | 162 + .../Device_Startup/startup_same54.c | 546 + .../Device_Startup/system_same54.c | 64 + ...ster_Slave_IF_TestMaster.componentinfo.xml | 169 + .../Master_Slave_IF_TestMaster.cproj | 971 + .../Master_Slave_IF_TestMaster/atmel_start.c | 10 + .../Master_Slave_IF_TestMaster/atmel_start.h | 19 + .../atmel_start_pins.h | 41 + .../documentation/stdio.rst | 34 + .../Master_Slave_IF_TestMaster/driver_init.c | 219 + .../Master_Slave_IF_TestMaster/driver_init.h | 60 + .../examples/driver_examples.c | 90 + .../examples/driver_examples.h | 24 + .../hal/documentation/evsys.rst | 24 + .../hal/documentation/spi_master_dma.rst | 56 + .../hal/documentation/spi_master_sync.rst | 51 + .../hal/documentation/timer.rst | 52 + .../hal/documentation/usart_sync.rst | 58 + .../hal/include/hal_atomic.h | 120 + .../hal/include/hal_cache.h | 96 + .../hal/include/hal_delay.h | 89 + .../hal/include/hal_evsys.h | 116 + .../hal/include/hal_gpio.h | 201 + .../hal/include/hal_init.h | 72 + .../hal/include/hal_io.h | 110 + .../hal/include/hal_sleep.h | 74 + .../hal/include/hal_spi_m_dma.h | 257 + .../hal/include/hal_spi_m_sync.h | 221 + .../hal/include/hal_timer.h | 206 + .../hal/include/hal_usart_sync.h | 247 + .../hal/include/hpl_cmcc.h | 277 + .../hal/include/hpl_core.h | 56 + .../hal/include/hpl_delay.h | 97 + .../hal/include/hpl_dma.h | 176 + .../hal/include/hpl_evsys.h | 94 + .../hal/include/hpl_gpio.h | 185 + .../hal/include/hpl_i2c_m_async.h | 205 + .../hal/include/hpl_i2c_m_sync.h | 185 + .../hal/include/hpl_i2c_s_async.h | 184 + .../hal/include/hpl_i2c_s_sync.h | 184 + .../hal/include/hpl_init.h | 124 + .../hal/include/hpl_irq.h | 116 + .../hal/include/hpl_missing_features.h | 37 + .../hal/include/hpl_pwm.h | 193 + .../hal/include/hpl_ramecc.h | 100 + .../hal/include/hpl_reset.h | 93 + .../hal/include/hpl_sleep.h | 88 + .../hal/include/hpl_spi.h | 163 + .../hal/include/hpl_spi_async.h | 131 + .../hal/include/hpl_spi_dma.h | 88 + .../hal/include/hpl_spi_m_async.h | 243 + .../hal/include/hpl_spi_m_dma.h | 182 + .../hal/include/hpl_spi_m_sync.h | 166 + .../hal/include/hpl_spi_s_async.h | 232 + .../hal/include/hpl_spi_s_sync.h | 232 + .../hal/include/hpl_spi_sync.h | 70 + .../hal/include/hpl_timer.h | 160 + .../hal/include/hpl_usart.h | 113 + .../hal/include/hpl_usart_async.h | 270 + .../hal/include/hpl_usart_sync.h | 254 + .../hal/src/hal_atomic.c | 66 + .../hal/src/hal_cache.c | 78 + .../hal/src/hal_delay.c | 80 + .../hal/src/hal_evsys.c | 98 + .../hal/src/hal_gpio.c | 44 + .../hal/src/hal_init.c | 47 + .../hal/src/hal_io.c | 63 + .../hal/src/hal_sleep.c | 73 + .../hal/src/hal_spi_m_dma.c | 183 + .../hal/src/hal_spi_m_sync.c | 201 + .../hal/src/hal_timer.c | 250 + .../hal/src/hal_usart_sync.c | 276 + .../hal/utils/include/compiler.h | 64 + .../hal/utils/include/err_codes.h | 73 + .../hal/utils/include/events.h | 54 + .../hal/utils/include/parts.h | 41 + .../hal/utils/include/utils.h | 368 + .../hal/utils/include/utils_assert.h | 93 + .../hal/utils/include/utils_event.h | 115 + .../hal/utils/include/utils_increment_macro.h | 308 + .../hal/utils/include/utils_list.h | 164 + .../hal/utils/include/utils_repeat_macro.h | 322 + .../hal/utils/src/utils_assert.c | 46 + .../hal/utils/src/utils_event.c | 125 + .../hal/utils/src/utils_list.c | 136 + .../hal/utils/src/utils_syscalls.c | 152 + .../hpl/cmcc/hpl_cmcc.c | 354 + .../hpl/core/hpl_core_m4.c | 241 + .../hpl/core/hpl_core_port.h | 61 + .../hpl/core/hpl_init.c | 78 + .../hpl/dmac/hpl_dmac.c | 260 + .../hpl/evsys/hpl_evsys.c | 140 + .../hpl/gclk/hpl_gclk.c | 312 + .../hpl/gclk/hpl_gclk_base.h | 87 + .../hpl/mclk/hpl_mclk.c | 44 + .../hpl/osc32kctrl/hpl_osc32kctrl.c | 82 + .../hpl/oscctrl/hpl_oscctrl.c | 230 + .../hpl/pm/hpl_pm.c | 68 + .../hpl/pm/hpl_pm_base.h | 45 + .../hpl/port/hpl_gpio_base.h | 172 + .../hpl/ramecc/hpl_ramecc.c | 83 + .../hpl/sercom/hpl_sercom.c | 3385 +++ .../hpl/tc/hpl_tc.c | 347 + .../hpl/tc/hpl_tc_base.h | 77 + .../hri/hri_ac_e54.h | 1836 ++ .../hri/hri_adc_e54.h | 3663 ++++ .../hri/hri_aes_e54.h | 1287 ++ .../hri/hri_can_e54.h | 16997 ++++++++++++++++ .../hri/hri_ccl_e54.h | 776 + .../hri/hri_cmcc_e54.h | 361 + .../hri/hri_dac_e54.h | 1706 ++ .../hri/hri_dmac_e54.h | 6800 +++++++ .../hri/hri_dsu_e54.h | 1256 ++ .../Master_Slave_IF_TestMaster/hri/hri_e54.h | 76 + .../hri/hri_eic_e54.h | 1838 ++ .../hri/hri_evsys_e54.h | 1707 ++ .../hri/hri_freqm_e54.h | 464 + .../hri/hri_gclk_e54.h | 805 + .../hri/hri_gmac_e54.h | 3766 ++++ .../hri/hri_hmatrixb_e54.h | 237 + .../hri/hri_i2s_e54.h | 3032 +++ .../hri/hri_icm_e54.h | 761 + .../hri/hri_mclk_e54.h | 3556 ++++ .../hri/hri_nvmctrl_e54.h | 1618 ++ .../hri/hri_osc32kctrl_e54.h | 1199 ++ .../hri/hri_oscctrl_e54.h | 4441 ++++ .../hri/hri_pac_e54.h | 1514 ++ .../hri/hri_pcc_e54.h | 298 + .../hri/hri_pdec_e54.h | 2684 +++ .../hri/hri_pm_e54.h | 820 + .../hri/hri_port_e54.h | 2528 +++ .../hri/hri_qspi_e54.h | 2058 ++ .../hri/hri_ramecc_e54.h | 362 + .../hri/hri_rstc_e54.h | 142 + .../hri/hri_rtc_e54.h | 10139 +++++++++ .../hri/hri_sdhc_e54.h | 7477 +++++++ .../hri/hri_sercom_e54.h | 8892 ++++++++ .../hri/hri_supc_e54.h | 1769 ++ .../hri/hri_tc_e54.h | 3003 +++ .../hri/hri_tcc_e54.h | 9992 +++++++++ .../hri/hri_trng_e54.h | 380 + .../hri/hri_usb_e54.h | 9335 +++++++++ .../hri/hri_wdt_e54.h | 617 + .../Master_Slave_IF_TestMaster/main.c | 134 + .../stdio_redirect/gcc/read.c | 53 + .../stdio_redirect/gcc/write.c | 53 + .../stdio_redirect/stdio_io.c | 74 + .../stdio_redirect/stdio_io.h | 81 + .../Master_Slave_IF_TestMaster/stdio_start.c | 23 + .../Master_Slave_IF_TestMaster/stdio_start.h | 31 + .../Master_Slave_IF_Test_Master.atsln | 22 + Examples/AS5048A | 2 +- .../.atmelstart/AtmelStart.env_conf | 6 + .../.atmelstart/AtmelStart.gpdsc | 239 + .../.atmelstart/atmel_start_config.atstart | 1610 ++ .../Master_Slave_IF_TestMaster/A1335.c | 520 + .../Master_Slave_IF_TestMaster/A1335.h | 45 + .../Master_Slave_IF_TestMaster/AS5048.c | 186 + .../Master_Slave_IF_TestMaster/AS5048.h | 38 + .../Config/RTE_Components.h | 54 + .../Config/hpl_cmcc_config.h | 54 + .../Config/hpl_dmac_config.h | 7277 +++++++ .../Config/hpl_evsys_config.h | 8363 ++++++++ .../Config/hpl_gclk_config.h | 920 + .../Config/hpl_mclk_config.h | 104 + .../Config/hpl_osc32kctrl_config.h | 165 + .../Config/hpl_oscctrl_config.h | 640 + .../Config/hpl_port_config.h | 522 + .../Config/hpl_sercom_config.h | 618 + .../Config/hpl_tc_config.h | 180 + .../Config/peripheral_clk_config.h | 789 + .../Config/spi_slave_dma_config.h | 47 + .../Config/stdio_redirect_config.h | 9 + .../Master_Slave_IF_TestMaster/Default.xml | 475 + .../Device_Startup/same54p20a_flash.ld | 163 + .../Device_Startup/same54p20a_sram.ld | 162 + .../Device_Startup/startup_same54.c | 546 + .../Device_Startup/system_same54.c | 64 + ...ster_Slave_IF_TestMaster.componentinfo.xml | 169 + .../Master_Slave_IF_TestMaster.cproj | 971 + .../Master_Slave_IF_TestMaster/atmel_start.c | 10 + .../Master_Slave_IF_TestMaster/atmel_start.h | 19 + .../atmel_start_pins.h | 41 + .../documentation/stdio.rst | 34 + .../Master_Slave_IF_TestMaster/driver_init.c | 219 + .../Master_Slave_IF_TestMaster/driver_init.h | 60 + .../examples/driver_examples.c | 90 + .../examples/driver_examples.h | 24 + .../hal/documentation/evsys.rst | 24 + .../hal/documentation/spi_master_dma.rst | 56 + .../hal/documentation/spi_master_sync.rst | 51 + .../hal/documentation/timer.rst | 52 + .../hal/documentation/usart_sync.rst | 58 + .../hal/include/hal_atomic.h | 120 + .../hal/include/hal_cache.h | 96 + .../hal/include/hal_delay.h | 89 + .../hal/include/hal_evsys.h | 116 + .../hal/include/hal_gpio.h | 201 + .../hal/include/hal_init.h | 72 + .../hal/include/hal_io.h | 110 + .../hal/include/hal_sleep.h | 74 + .../hal/include/hal_spi_m_dma.h | 257 + .../hal/include/hal_spi_m_sync.h | 221 + .../hal/include/hal_timer.h | 206 + .../hal/include/hal_usart_sync.h | 247 + .../hal/include/hpl_cmcc.h | 277 + .../hal/include/hpl_core.h | 56 + .../hal/include/hpl_delay.h | 97 + .../hal/include/hpl_dma.h | 176 + .../hal/include/hpl_evsys.h | 94 + .../hal/include/hpl_gpio.h | 185 + .../hal/include/hpl_i2c_m_async.h | 205 + .../hal/include/hpl_i2c_m_sync.h | 185 + .../hal/include/hpl_i2c_s_async.h | 184 + .../hal/include/hpl_i2c_s_sync.h | 184 + .../hal/include/hpl_init.h | 124 + .../hal/include/hpl_irq.h | 116 + .../hal/include/hpl_missing_features.h | 37 + .../hal/include/hpl_pwm.h | 193 + .../hal/include/hpl_ramecc.h | 100 + .../hal/include/hpl_reset.h | 93 + .../hal/include/hpl_sleep.h | 88 + .../hal/include/hpl_spi.h | 163 + .../hal/include/hpl_spi_async.h | 131 + .../hal/include/hpl_spi_dma.h | 88 + .../hal/include/hpl_spi_m_async.h | 243 + .../hal/include/hpl_spi_m_dma.h | 182 + .../hal/include/hpl_spi_m_sync.h | 166 + .../hal/include/hpl_spi_s_async.h | 232 + .../hal/include/hpl_spi_s_sync.h | 232 + .../hal/include/hpl_spi_sync.h | 70 + .../hal/include/hpl_timer.h | 160 + .../hal/include/hpl_usart.h | 113 + .../hal/include/hpl_usart_async.h | 270 + .../hal/include/hpl_usart_sync.h | 254 + .../hal/src/hal_atomic.c | 66 + .../hal/src/hal_cache.c | 78 + .../hal/src/hal_delay.c | 80 + .../hal/src/hal_evsys.c | 98 + .../hal/src/hal_gpio.c | 44 + .../hal/src/hal_init.c | 47 + .../hal/src/hal_io.c | 63 + .../hal/src/hal_sleep.c | 73 + .../hal/src/hal_spi_m_dma.c | 183 + .../hal/src/hal_spi_m_sync.c | 201 + .../hal/src/hal_timer.c | 250 + .../hal/src/hal_usart_sync.c | 276 + .../hal/utils/include/compiler.h | 64 + .../hal/utils/include/err_codes.h | 73 + .../hal/utils/include/events.h | 54 + .../hal/utils/include/parts.h | 41 + .../hal/utils/include/utils.h | 368 + .../hal/utils/include/utils_assert.h | 93 + .../hal/utils/include/utils_event.h | 115 + .../hal/utils/include/utils_increment_macro.h | 308 + .../hal/utils/include/utils_list.h | 164 + .../hal/utils/include/utils_repeat_macro.h | 322 + .../hal/utils/src/utils_assert.c | 46 + .../hal/utils/src/utils_event.c | 125 + .../hal/utils/src/utils_list.c | 136 + .../hal/utils/src/utils_syscalls.c | 152 + .../hpl/cmcc/hpl_cmcc.c | 354 + .../hpl/core/hpl_core_m4.c | 241 + .../hpl/core/hpl_core_port.h | 61 + .../hpl/core/hpl_init.c | 78 + .../hpl/dmac/hpl_dmac.c | 260 + .../hpl/evsys/hpl_evsys.c | 140 + .../hpl/gclk/hpl_gclk.c | 312 + .../hpl/gclk/hpl_gclk_base.h | 87 + .../hpl/mclk/hpl_mclk.c | 44 + .../hpl/osc32kctrl/hpl_osc32kctrl.c | 82 + .../hpl/oscctrl/hpl_oscctrl.c | 230 + .../hpl/pm/hpl_pm.c | 68 + .../hpl/pm/hpl_pm_base.h | 45 + .../hpl/port/hpl_gpio_base.h | 172 + .../hpl/ramecc/hpl_ramecc.c | 83 + .../hpl/sercom/hpl_sercom.c | 3385 +++ .../hpl/tc/hpl_tc.c | 347 + .../hpl/tc/hpl_tc_base.h | 77 + .../hri/hri_ac_e54.h | 1836 ++ .../hri/hri_adc_e54.h | 3663 ++++ .../hri/hri_aes_e54.h | 1287 ++ .../hri/hri_can_e54.h | 16997 ++++++++++++++++ .../hri/hri_ccl_e54.h | 776 + .../hri/hri_cmcc_e54.h | 361 + .../hri/hri_dac_e54.h | 1706 ++ .../hri/hri_dmac_e54.h | 6800 +++++++ .../hri/hri_dsu_e54.h | 1256 ++ .../Master_Slave_IF_TestMaster/hri/hri_e54.h | 76 + .../hri/hri_eic_e54.h | 1838 ++ .../hri/hri_evsys_e54.h | 1707 ++ .../hri/hri_freqm_e54.h | 464 + .../hri/hri_gclk_e54.h | 805 + .../hri/hri_gmac_e54.h | 3766 ++++ .../hri/hri_hmatrixb_e54.h | 237 + .../hri/hri_i2s_e54.h | 3032 +++ .../hri/hri_icm_e54.h | 761 + .../hri/hri_mclk_e54.h | 3556 ++++ .../hri/hri_nvmctrl_e54.h | 1618 ++ .../hri/hri_osc32kctrl_e54.h | 1199 ++ .../hri/hri_oscctrl_e54.h | 4441 ++++ .../hri/hri_pac_e54.h | 1514 ++ .../hri/hri_pcc_e54.h | 298 + .../hri/hri_pdec_e54.h | 2684 +++ .../hri/hri_pm_e54.h | 820 + .../hri/hri_port_e54.h | 2528 +++ .../hri/hri_qspi_e54.h | 2058 ++ .../hri/hri_ramecc_e54.h | 362 + .../hri/hri_rstc_e54.h | 142 + .../hri/hri_rtc_e54.h | 10139 +++++++++ .../hri/hri_sdhc_e54.h | 7477 +++++++ .../hri/hri_sercom_e54.h | 8892 ++++++++ .../hri/hri_supc_e54.h | 1769 ++ .../hri/hri_tc_e54.h | 3003 +++ .../hri/hri_tcc_e54.h | 9992 +++++++++ .../hri/hri_trng_e54.h | 380 + .../hri/hri_usb_e54.h | 9335 +++++++++ .../hri/hri_wdt_e54.h | 617 + .../Master_Slave_IF_TestMaster/main.c | 134 + .../stdio_redirect/gcc/read.c | 53 + .../stdio_redirect/gcc/write.c | 53 + .../stdio_redirect/stdio_io.c | 74 + .../stdio_redirect/stdio_io.h | 81 + .../Master_Slave_IF_TestMaster/stdio_start.c | 23 + .../Master_Slave_IF_TestMaster/stdio_start.h | 31 + .../Master_Slave_IF_Test_Master.atsln | 22 + .../Board_to_Board_Coms.atsln | 22 + .../.atmelstart/AtmelStart.env_conf | 6 + .../.atmelstart/AtmelStart.gpdsc | 236 + .../.atmelstart/atmel_start_config.atstart | 1541 ++ .../Board_to_Board_Coms.componentinfo.xml | 169 + .../Board_to_Board_Coms.cproj | 949 + .../Config/RTE_Components.h | 54 + .../Config/hpl_cmcc_config.h | 54 + .../Config/hpl_dmac_config.h | 7277 +++++++ .../Config/hpl_evsys_config.h | 8363 ++++++++ .../Config/hpl_gclk_config.h | 920 + .../Config/hpl_mclk_config.h | 104 + .../Config/hpl_osc32kctrl_config.h | 165 + .../Config/hpl_oscctrl_config.h | 640 + .../Config/hpl_port_config.h | 522 + .../Config/hpl_sercom_config.h | 459 + .../Config/hpl_tc_config.h | 180 + .../Config/peripheral_clk_config.h | 709 + .../Config/stdio_redirect_config.h | 9 + .../Board_to_Board_Coms/Default.xml | 475 + .../Device_Startup/same54p20a_flash.ld | 163 + .../Device_Startup/same54p20a_sram.ld | 162 + .../Device_Startup/startup_same54.c | 546 + .../Device_Startup/system_same54.c | 64 + .../Board_to_Board_Coms/atmel_start.c | 10 + .../Board_to_Board_Coms/atmel_start.h | 19 + .../Board_to_Board_Coms/atmel_start_pins.h | 37 + .../documentation/stdio.rst | 34 + .../Board_to_Board_Coms/driver_init.c | 145 + .../Board_to_Board_Coms/driver_init.h | 54 + .../examples/driver_examples.c | 76 + .../examples/driver_examples.h | 24 + .../hal/documentation/evsys.rst | 24 + .../hal/documentation/spi_master_dma.rst | 56 + .../hal/documentation/timer.rst | 52 + .../hal/documentation/usart_sync.rst | 58 + .../hal/include/hal_atomic.h | 120 + .../hal/include/hal_cache.h | 96 + .../hal/include/hal_delay.h | 89 + .../hal/include/hal_evsys.h | 116 + .../hal/include/hal_gpio.h | 201 + .../hal/include/hal_init.h | 72 + .../Board_to_Board_Coms/hal/include/hal_io.h | 110 + .../hal/include/hal_sleep.h | 74 + .../hal/include/hal_spi_m_dma.h | 257 + .../hal/include/hal_timer.h | 206 + .../hal/include/hal_usart_sync.h | 247 + .../hal/include/hpl_cmcc.h | 277 + .../hal/include/hpl_core.h | 56 + .../hal/include/hpl_delay.h | 97 + .../Board_to_Board_Coms/hal/include/hpl_dma.h | 176 + .../hal/include/hpl_evsys.h | 94 + .../hal/include/hpl_gpio.h | 185 + .../hal/include/hpl_i2c_m_async.h | 205 + .../hal/include/hpl_i2c_m_sync.h | 185 + .../hal/include/hpl_i2c_s_async.h | 184 + .../hal/include/hpl_i2c_s_sync.h | 184 + .../hal/include/hpl_init.h | 124 + .../Board_to_Board_Coms/hal/include/hpl_irq.h | 116 + .../hal/include/hpl_missing_features.h | 37 + .../Board_to_Board_Coms/hal/include/hpl_pwm.h | 193 + .../hal/include/hpl_ramecc.h | 100 + .../hal/include/hpl_reset.h | 93 + .../hal/include/hpl_sleep.h | 88 + .../Board_to_Board_Coms/hal/include/hpl_spi.h | 163 + .../hal/include/hpl_spi_async.h | 131 + .../hal/include/hpl_spi_dma.h | 88 + .../hal/include/hpl_spi_m_async.h | 243 + .../hal/include/hpl_spi_m_dma.h | 182 + .../hal/include/hpl_spi_m_sync.h | 166 + .../hal/include/hpl_spi_s_async.h | 232 + .../hal/include/hpl_spi_s_sync.h | 232 + .../hal/include/hpl_spi_sync.h | 70 + .../hal/include/hpl_timer.h | 160 + .../hal/include/hpl_usart.h | 113 + .../hal/include/hpl_usart_async.h | 270 + .../hal/include/hpl_usart_sync.h | 254 + .../Board_to_Board_Coms/hal/src/hal_atomic.c | 66 + .../Board_to_Board_Coms/hal/src/hal_cache.c | 78 + .../Board_to_Board_Coms/hal/src/hal_delay.c | 80 + .../Board_to_Board_Coms/hal/src/hal_evsys.c | 98 + .../Board_to_Board_Coms/hal/src/hal_gpio.c | 44 + .../Board_to_Board_Coms/hal/src/hal_init.c | 47 + .../Board_to_Board_Coms/hal/src/hal_io.c | 63 + .../Board_to_Board_Coms/hal/src/hal_sleep.c | 73 + .../hal/src/hal_spi_m_dma.c | 183 + .../Board_to_Board_Coms/hal/src/hal_timer.c | 250 + .../hal/src/hal_usart_sync.c | 276 + .../hal/utils/include/compiler.h | 64 + .../hal/utils/include/err_codes.h | 73 + .../hal/utils/include/events.h | 54 + .../hal/utils/include/parts.h | 41 + .../hal/utils/include/utils.h | 368 + .../hal/utils/include/utils_assert.h | 93 + .../hal/utils/include/utils_event.h | 115 + .../hal/utils/include/utils_increment_macro.h | 308 + .../hal/utils/include/utils_list.h | 164 + .../hal/utils/include/utils_repeat_macro.h | 322 + .../hal/utils/src/utils_assert.c | 46 + .../hal/utils/src/utils_event.c | 125 + .../hal/utils/src/utils_list.c | 136 + .../hal/utils/src/utils_syscalls.c | 152 + .../Board_to_Board_Coms/hpl/cmcc/hpl_cmcc.c | 354 + .../hpl/core/hpl_core_m4.c | 241 + .../hpl/core/hpl_core_port.h | 61 + .../Board_to_Board_Coms/hpl/core/hpl_init.c | 78 + .../Board_to_Board_Coms/hpl/dmac/hpl_dmac.c | 260 + .../Board_to_Board_Coms/hpl/evsys/hpl_evsys.c | 140 + .../Board_to_Board_Coms/hpl/gclk/hpl_gclk.c | 312 + .../hpl/gclk/hpl_gclk_base.h | 87 + .../Board_to_Board_Coms/hpl/mclk/hpl_mclk.c | 44 + .../hpl/osc32kctrl/hpl_osc32kctrl.c | 82 + .../hpl/oscctrl/hpl_oscctrl.c | 230 + .../Board_to_Board_Coms/hpl/pm/hpl_pm.c | 68 + .../Board_to_Board_Coms/hpl/pm/hpl_pm_base.h | 45 + .../hpl/port/hpl_gpio_base.h | 172 + .../hpl/ramecc/hpl_ramecc.c | 83 + .../hpl/sercom/hpl_sercom.c | 3385 +++ .../Board_to_Board_Coms/hpl/tc/hpl_tc.c | 347 + .../Board_to_Board_Coms/hpl/tc/hpl_tc_base.h | 77 + .../Board_to_Board_Coms/hri/hri_ac_e54.h | 1836 ++ .../Board_to_Board_Coms/hri/hri_adc_e54.h | 3663 ++++ .../Board_to_Board_Coms/hri/hri_aes_e54.h | 1287 ++ .../Board_to_Board_Coms/hri/hri_can_e54.h | 16997 ++++++++++++++++ .../Board_to_Board_Coms/hri/hri_ccl_e54.h | 776 + .../Board_to_Board_Coms/hri/hri_cmcc_e54.h | 361 + .../Board_to_Board_Coms/hri/hri_dac_e54.h | 1706 ++ .../Board_to_Board_Coms/hri/hri_dmac_e54.h | 6800 +++++++ .../Board_to_Board_Coms/hri/hri_dsu_e54.h | 1256 ++ .../Board_to_Board_Coms/hri/hri_e54.h | 76 + .../Board_to_Board_Coms/hri/hri_eic_e54.h | 1838 ++ .../Board_to_Board_Coms/hri/hri_evsys_e54.h | 1707 ++ .../Board_to_Board_Coms/hri/hri_freqm_e54.h | 464 + .../Board_to_Board_Coms/hri/hri_gclk_e54.h | 805 + .../Board_to_Board_Coms/hri/hri_gmac_e54.h | 3766 ++++ .../hri/hri_hmatrixb_e54.h | 237 + .../Board_to_Board_Coms/hri/hri_i2s_e54.h | 3032 +++ .../Board_to_Board_Coms/hri/hri_icm_e54.h | 761 + .../Board_to_Board_Coms/hri/hri_mclk_e54.h | 3556 ++++ .../Board_to_Board_Coms/hri/hri_nvmctrl_e54.h | 1618 ++ .../hri/hri_osc32kctrl_e54.h | 1199 ++ .../Board_to_Board_Coms/hri/hri_oscctrl_e54.h | 4441 ++++ .../Board_to_Board_Coms/hri/hri_pac_e54.h | 1514 ++ .../Board_to_Board_Coms/hri/hri_pcc_e54.h | 298 + .../Board_to_Board_Coms/hri/hri_pdec_e54.h | 2684 +++ .../Board_to_Board_Coms/hri/hri_pm_e54.h | 820 + .../Board_to_Board_Coms/hri/hri_port_e54.h | 2528 +++ .../Board_to_Board_Coms/hri/hri_qspi_e54.h | 2058 ++ .../Board_to_Board_Coms/hri/hri_ramecc_e54.h | 362 + .../Board_to_Board_Coms/hri/hri_rstc_e54.h | 142 + .../Board_to_Board_Coms/hri/hri_rtc_e54.h | 10139 +++++++++ .../Board_to_Board_Coms/hri/hri_sdhc_e54.h | 7477 +++++++ .../Board_to_Board_Coms/hri/hri_sercom_e54.h | 8892 ++++++++ .../Board_to_Board_Coms/hri/hri_supc_e54.h | 1769 ++ .../Board_to_Board_Coms/hri/hri_tc_e54.h | 3003 +++ .../Board_to_Board_Coms/hri/hri_tcc_e54.h | 9992 +++++++++ .../Board_to_Board_Coms/hri/hri_trng_e54.h | 380 + .../Board_to_Board_Coms/hri/hri_usb_e54.h | 9335 +++++++++ .../Board_to_Board_Coms/hri/hri_wdt_e54.h | 617 + .../Board_to_Board_Coms/main.c | 75 + .../stdio_redirect/gcc/read.c | 53 + .../stdio_redirect/gcc/write.c | 53 + .../stdio_redirect/stdio_io.c | 74 + .../stdio_redirect/stdio_io.h | 81 + .../Board_to_Board_Coms/stdio_start.c | 23 + .../Board_to_Board_Coms/stdio_start.h | 31 + .../Board_to_Board_Coms_Slave.atsln | 22 + .../.atmelstart/AtmelStart.env_conf | 6 + .../.atmelstart/AtmelStart.gpdsc | 210 + .../.atmelstart/atmel_start_config.atstart | 723 + ...oard_to_Board_Coms_Slave.componentinfo.xml | 169 + .../Board_to_Board_Coms_Slave.cproj | 835 + .../Board_to_Board_Coms_Slave/Default.xml | 475 + .../Device_Startup/samc21j18a_flash.ld | 143 + .../Device_Startup/samc21j18a_sram.ld | 142 + .../Device_Startup/startup_samc21.c | 271 + .../Device_Startup/system_samc21.c | 64 + .../Board_to_Board_Coms_Slave/atmel_start.c | 10 + .../Board_to_Board_Coms_Slave/atmel_start.h | 19 + .../atmel_start_pins.h | 32 + .../config/RTE_Components.h | 54 + .../config/hpl_divas_config.h | 13 + .../config/hpl_dmac_config.h | 3474 ++++ .../config/hpl_gclk_config.h | 608 + .../config/hpl_mclk_config.h | 72 + .../config/hpl_osc32kctrl_config.h | 229 + .../config/hpl_oscctrl_config.h | 308 + .../config/hpl_port_config.h | 284 + .../config/hpl_sercom_config.h | 427 + .../config/peripheral_clk_config.h | 145 + .../config/stdio_redirect_config.h | 9 + .../documentation/stdio.rst | 34 + .../Board_to_Board_Coms_Slave/driver_init.c | 115 + .../Board_to_Board_Coms_Slave/driver_init.h | 50 + .../examples/driver_examples.c | 37 + .../examples/driver_examples.h | 20 + .../hal/documentation/spi_slave_sync.rst | 60 + .../hal/documentation/usart_sync.rst | 58 + .../hal/include/hal_atomic.h | 120 + .../hal/include/hal_delay.h | 89 + .../hal/include/hal_gpio.h | 201 + .../hal/include/hal_init.h | 72 + .../hal/include/hal_io.h | 110 + .../hal/include/hal_sleep.h | 74 + .../hal/include/hal_spi_s_sync.h | 204 + .../hal/include/hal_usart_sync.h | 247 + .../hal/include/hpl_core.h | 56 + .../hal/include/hpl_delay.h | 97 + .../hal/include/hpl_div.h | 59 + .../hal/include/hpl_dma.h | 176 + .../hal/include/hpl_gpio.h | 185 + .../hal/include/hpl_i2c_m_async.h | 205 + .../hal/include/hpl_i2c_m_sync.h | 185 + .../hal/include/hpl_i2c_s_async.h | 184 + .../hal/include/hpl_i2c_s_sync.h | 184 + .../hal/include/hpl_init.h | 124 + .../hal/include/hpl_irq.h | 116 + .../hal/include/hpl_missing_features.h | 37 + .../hal/include/hpl_reset.h | 92 + .../hal/include/hpl_sleep.h | 88 + .../hal/include/hpl_spi.h | 163 + .../hal/include/hpl_spi_async.h | 131 + .../hal/include/hpl_spi_m_async.h | 243 + .../hal/include/hpl_spi_m_dma.h | 182 + .../hal/include/hpl_spi_m_sync.h | 166 + .../hal/include/hpl_spi_s_async.h | 232 + .../hal/include/hpl_spi_s_sync.h | 232 + .../hal/include/hpl_spi_sync.h | 70 + .../hal/include/hpl_usart.h | 113 + .../hal/include/hpl_usart_async.h | 270 + .../hal/include/hpl_usart_sync.h | 254 + .../hal/src/hal_atomic.c | 66 + .../hal/src/hal_delay.c | 80 + .../hal/src/hal_gpio.c | 44 + .../hal/src/hal_init.c | 47 + .../hal/src/hal_io.c | 63 + .../hal/src/hal_sleep.c | 73 + .../hal/src/hal_spi_s_sync.c | 262 + .../hal/src/hal_usart_sync.c | 276 + .../hal/utils/include/compiler.h | 64 + .../hal/utils/include/err_codes.h | 73 + .../hal/utils/include/events.h | 54 + .../hal/utils/include/parts.h | 41 + .../hal/utils/include/utils.h | 368 + .../hal/utils/include/utils_assert.h | 93 + .../hal/utils/include/utils_event.h | 115 + .../hal/utils/include/utils_increment_macro.h | 308 + .../hal/utils/include/utils_list.h | 164 + .../hal/utils/include/utils_repeat_macro.h | 322 + .../hal/utils/src/utils_assert.c | 46 + .../hal/utils/src/utils_event.c | 125 + .../hal/utils/src/utils_list.c | 136 + .../hal/utils/src/utils_syscalls.c | 152 + .../hpl/core/hpl_core_m0plus_base.c | 232 + .../hpl/core/hpl_core_port.h | 61 + .../hpl/core/hpl_init.c | 75 + .../hpl/divas/hpl_divas.c | 128 + .../hpl/dmac/hpl_dmac.c | 244 + .../hpl/gclk/hpl_gclk.c | 246 + .../hpl/gclk/hpl_gclk_base.h | 87 + .../hpl/mclk/hpl_mclk.c | 44 + .../hpl/osc32kctrl/hpl_osc32kctrl.c | 107 + .../hpl/oscctrl/hpl_oscctrl.c | 121 + .../Board_to_Board_Coms_Slave/hpl/pm/hpl_pm.c | 64 + .../hpl/pm/hpl_pm_base.h | 45 + .../hpl/port/hpl_gpio_base.h | 170 + .../hpl/sercom/hpl_sercom.c | 2929 +++ .../hri/hri_ac_c21.h | 2241 ++ .../hri/hri_adc_c21.h | 2847 +++ .../Board_to_Board_Coms_Slave/hri/hri_c21.h | 73 + .../hri/hri_can_c21.h | 16997 ++++++++++++++++ .../hri/hri_ccl_c21.h | 776 + .../hri/hri_dac_c21.h | 966 + .../hri/hri_divas_c21.h | 546 + .../hri/hri_dmac_c21.h | 4339 ++++ .../hri/hri_dsu_c21.h | 1187 ++ .../hri/hri_eic_c21.h | 1463 ++ .../hri/hri_evsys_c21.h | 1725 ++ .../hri/hri_freqm_c21.h | 464 + .../hri/hri_gclk_c21.h | 790 + .../hri/hri_hmatrixb_c21.h | 408 + .../hri/hri_mclk_c21.h | 2490 +++ .../hri/hri_mpu_c21.h | 266 + .../hri/hri_mtb_c21.h | 551 + .../hri/hri_nvic_c21.h | 269 + .../hri/hri_nvmctrl_c21.h | 1103 + .../hri/hri_osc32kctrl_c21.h | 1500 ++ .../hri/hri_oscctrl_c21.h | 2509 +++ .../hri/hri_pac_c21.h | 1176 ++ .../hri/hri_pm_c21.h | 279 + .../hri/hri_port_c21.h | 2357 +++ .../hri/hri_rstc_c21.h | 103 + .../hri/hri_rtc_c21.h | 6175 ++++++ .../hri/hri_sdadc_c21.h | 2543 +++ .../hri/hri_sercom_c21.h | 7754 +++++++ .../hri/hri_supc_c21.h | 1560 ++ .../hri/hri_systemcontrol_c21.h | 498 + .../hri/hri_systick_c21.h | 219 + .../hri/hri_tc_c21.h | 2899 +++ .../hri/hri_tcc_c21.h | 9462 +++++++++ .../hri/hri_tsens_c21.h | 1396 ++ .../hri/hri_wdt_c21.h | 617 + .../Board_to_Board_Coms_Slave/main.c | 112 + .../stdio_redirect/gcc/read.c | 53 + .../stdio_redirect/gcc/write.c | 53 + .../stdio_redirect/stdio_io.c | 74 + .../stdio_redirect/stdio_io.h | 81 + .../Board_to_Board_Coms_Slave/stdio_start.c | 23 + .../Board_to_Board_Coms_Slave/stdio_start.h | 31 + .../.atmelstart/AtmelStart.gpdsc | 8 + .../.atmelstart/atmel_start_config.atstart | 61 +- .../Config/hpl_tc_config.h | 180 + .../Master_Slave_IF_TestMaster.cproj | 43 +- .../Master_Slave_IF_TestMaster/driver_init.c | 16 +- .../Master_Slave_IF_TestMaster/driver_init.h | 8 +- .../examples/driver_examples.c | 27 + .../examples/driver_examples.h | 2 + .../hal/documentation/timer.rst | 52 + .../hal/include/hal_timer.h | 206 + .../hal/include/hpl_pwm.h | 193 + .../hal/include/hpl_timer.h | 160 + .../hal/src/hal_timer.c | 250 + .../hpl/tc/hpl_tc.c | 352 + .../hpl/tc/hpl_tc_base.h | 77 + .../hpl/tc/tc_lite.c | 66 - .../hpl/tc/tc_lite.h | 6 - .../Master_Slave_IF_TestMaster/main.c | 42 +- .../Master_Slave_IF_TestMaster/A1335.c | 112 +- .../Master_Slave_IF_TestMaster/A1335.h | 24 +- .../Master_Slave_IF_TestMaster/AS5048.c | 186 + .../Master_Slave_IF_TestMaster/AS5048.h | 38 + .../Master_Slave_IF_TestMaster.cproj | 6 + .../Master_Slave_IF_TestMaster/main.c | 7 +- 682 files changed, 589964 insertions(+), 230 deletions(-) create mode 100644 Backup/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.env_conf create mode 100644 Backup/Angle Sensor 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100644 Backup/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_tc_config.h create mode 100644 Backup/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/peripheral_clk_config.h create mode 100644 Backup/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/spi_slave_dma_config.h create mode 100644 Backup/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/stdio_redirect_config.h create mode 100644 Backup/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Default.xml create mode 100644 Backup/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_flash.ld create mode 100644 Backup/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_sram.ld create mode 100644 Backup/Angle Sensor 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create mode 100644 Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/hpl_tc_base.h create mode 100644 Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/AS5048.c create mode 100644 Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/AS5048.h diff --git a/Backup/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.env_conf b/Backup/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.env_conf new file mode 100644 index 0000000..2033451 --- /dev/null +++ b/Backup/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.env_conf @@ -0,0 +1,6 @@ + + + + + + diff --git a/Backup/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.gpdsc b/Backup/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.gpdsc new file mode 100644 index 0000000..54104a9 --- /dev/null +++ b/Backup/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.gpdsc @@ -0,0 +1,239 @@ + + Atmel + My Project + Project generated by Atmel Start + http://start.atmel.com/ + + Initial version + + + Configuration Files generated by Atmel Start + + + + Atmel Start + + http://start.atmel.com/ + + + + + + + + + Dependency on CMSIS core and Device Startup components + + + + + + + + + + + + + + + + + + + + + + + + + Atmel Start Framework + #define ATMEL_START + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/atmel_start_config.atstart b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/atmel_start_config.atstart new file mode 100644 index 0000000..cd5a840 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/atmel_start_config.atstart @@ -0,0 +1,1610 @@ +format_version: '2' +name: My Project +versions: + api: '1.0' + backend: 1.8.580 + commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c + content: unknown + content_pack_name: unknown + format: '2' + frontend: 1.8.580 + packs_version_avr8: 1.0.1463 + packs_version_qtouch: unknown + packs_version_sam: 1.0.1726 + version_backend: 1.8.580 + version_frontend: '' +board: + identifier: SAME54XplainedPro + device: SAME54P20A-AU +details: null +application: null +middlewares: + STDIO_REDIRECT_0: + user_label: STDIO_REDIRECT_0 + configuration: {} + definition: Atmel:STDIO_redirect:0.0.1::STDIO_Redirect + functionality: STDIO_Redirect + api: STDIO:Redirect:IO + dependencies: + Target IO: TARGET_IO +drivers: + CMCC: + user_label: CMCC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC + functionality: System + api: HAL:HPL:CMCC + configuration: + cache_size: 4 KB + cmcc_advanced_configuration: false + cmcc_clock_gating_disable: false + cmcc_data_cache_disable: false + cmcc_enable: false + cmcc_inst_cache_disable: false + optional_signals: [] + variant: null + clocks: + domain_group: null + DMAC: + user_label: DMAC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + functionality: System + api: HAL:HPL:DMAC + configuration: + dmac_beatsize_0: 8-bit bus transfer + dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_10: 8-bit bus transfer + dmac_beatsize_11: 8-bit bus transfer + dmac_beatsize_12: 8-bit bus transfer + dmac_beatsize_13: 8-bit bus transfer + dmac_beatsize_14: 8-bit bus transfer + dmac_beatsize_15: 8-bit bus transfer + dmac_beatsize_16: 8-bit bus transfer + dmac_beatsize_17: 8-bit bus transfer + dmac_beatsize_18: 8-bit bus transfer + dmac_beatsize_19: 8-bit bus transfer + dmac_beatsize_2: 8-bit bus transfer + dmac_beatsize_20: 8-bit bus transfer + dmac_beatsize_21: 8-bit bus transfer + dmac_beatsize_22: 8-bit bus transfer + dmac_beatsize_23: 8-bit bus transfer + dmac_beatsize_24: 8-bit bus transfer + dmac_beatsize_25: 8-bit bus transfer + dmac_beatsize_26: 8-bit bus transfer + dmac_beatsize_27: 8-bit bus transfer + dmac_beatsize_28: 8-bit bus transfer + dmac_beatsize_29: 8-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer + dmac_beatsize_30: 8-bit bus transfer + dmac_beatsize_31: 8-bit bus transfer + dmac_beatsize_4: 8-bit bus transfer + dmac_beatsize_5: 8-bit bus transfer + dmac_beatsize_6: 8-bit bus transfer + dmac_beatsize_7: 8-bit bus transfer + dmac_beatsize_8: 8-bit bus transfer + dmac_beatsize_9: 8-bit bus transfer + dmac_blockact_0: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_1: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_10: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_11: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_12: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_13: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_14: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_15: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_16: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_17: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_18: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_19: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_2: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_20: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_21: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_22: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_23: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_24: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_25: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_26: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_27: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_28: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_29: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_3: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_30: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_31: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_4: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_5: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_6: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_7: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_8: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_9: Channel will be disabled if it is the last block transfer in + the transaction + dmac_channel_0_settings: false + dmac_channel_10_settings: false + dmac_channel_11_settings: false + dmac_channel_12_settings: false + dmac_channel_13_settings: false + dmac_channel_14_settings: false + dmac_channel_15_settings: false + dmac_channel_16_settings: false + dmac_channel_17_settings: false + dmac_channel_18_settings: false + dmac_channel_19_settings: false + dmac_channel_1_settings: false + dmac_channel_20_settings: false + dmac_channel_21_settings: false + dmac_channel_22_settings: false + dmac_channel_23_settings: false + dmac_channel_24_settings: false + dmac_channel_25_settings: false + dmac_channel_26_settings: false + dmac_channel_27_settings: false + dmac_channel_28_settings: false + dmac_channel_29_settings: false + dmac_channel_2_settings: true + dmac_channel_30_settings: false + dmac_channel_31_settings: false + dmac_channel_3_settings: true + dmac_channel_4_settings: false + dmac_channel_5_settings: false + dmac_channel_6_settings: false + dmac_channel_7_settings: false + dmac_channel_8_settings: false + dmac_channel_9_settings: false + dmac_dbgrun: false + dmac_dstinc_0: false + dmac_dstinc_1: false + dmac_dstinc_10: false + dmac_dstinc_11: false + dmac_dstinc_12: false + dmac_dstinc_13: false + dmac_dstinc_14: false + dmac_dstinc_15: false + dmac_dstinc_16: false + dmac_dstinc_17: false + dmac_dstinc_18: false + dmac_dstinc_19: false + dmac_dstinc_2: false + dmac_dstinc_20: false + dmac_dstinc_21: false + dmac_dstinc_22: false + dmac_dstinc_23: false + dmac_dstinc_24: false + dmac_dstinc_25: false + dmac_dstinc_26: false + dmac_dstinc_27: false + dmac_dstinc_28: false + dmac_dstinc_29: false + dmac_dstinc_3: true + dmac_dstinc_30: false + dmac_dstinc_31: false + dmac_dstinc_4: false + dmac_dstinc_5: false + dmac_dstinc_6: false + dmac_dstinc_7: false + dmac_dstinc_8: false + dmac_dstinc_9: false + dmac_enable: true + dmac_evact_0: No action + dmac_evact_1: No action + dmac_evact_10: No action + dmac_evact_11: No action + dmac_evact_12: No action + dmac_evact_13: No action + dmac_evact_14: No action + dmac_evact_15: No action + dmac_evact_16: No action + dmac_evact_17: No action + dmac_evact_18: No action + dmac_evact_19: No action + dmac_evact_2: No action + dmac_evact_20: No action + dmac_evact_21: No action + dmac_evact_22: No action + dmac_evact_23: No action + dmac_evact_24: No action + dmac_evact_25: No action + dmac_evact_26: No action + dmac_evact_27: No action + dmac_evact_28: No action + dmac_evact_29: No action + dmac_evact_3: No action + dmac_evact_30: No action + dmac_evact_31: No action + dmac_evact_4: No action + dmac_evact_5: No action + dmac_evact_6: No action + dmac_evact_7: No action + dmac_evact_8: No action + dmac_evact_9: No action + dmac_evie_0: false + dmac_evie_1: false + dmac_evie_10: false + dmac_evie_11: false + dmac_evie_12: false + dmac_evie_13: false + dmac_evie_14: false + dmac_evie_15: false + dmac_evie_16: false + dmac_evie_17: false + dmac_evie_18: false + dmac_evie_19: false + dmac_evie_2: false + dmac_evie_20: false + dmac_evie_21: false + dmac_evie_22: false + dmac_evie_23: false + dmac_evie_24: false + dmac_evie_25: false + dmac_evie_26: false + dmac_evie_27: false + dmac_evie_28: false + dmac_evie_29: false + dmac_evie_3: false + dmac_evie_30: false + dmac_evie_31: false + dmac_evie_4: false + dmac_evie_5: false + dmac_evie_6: false + dmac_evie_7: false + dmac_evie_8: false + dmac_evie_9: false + dmac_evoe_0: false + dmac_evoe_1: false + dmac_evoe_10: false + dmac_evoe_11: false + dmac_evoe_12: false + dmac_evoe_13: false + dmac_evoe_14: false + dmac_evoe_15: false + dmac_evoe_16: false + dmac_evoe_17: false + dmac_evoe_18: false + dmac_evoe_19: false + dmac_evoe_2: false + dmac_evoe_20: false + dmac_evoe_21: false + dmac_evoe_22: false + dmac_evoe_23: false + dmac_evoe_24: false + dmac_evoe_25: false + dmac_evoe_26: false + dmac_evoe_27: false + dmac_evoe_28: false + dmac_evoe_29: false + dmac_evoe_3: false + dmac_evoe_30: false + dmac_evoe_31: false + dmac_evoe_4: false + dmac_evoe_5: false + dmac_evoe_6: false + dmac_evoe_7: false + dmac_evoe_8: false + dmac_evoe_9: false + dmac_evosel_0: Event generation disabled + dmac_evosel_1: Event generation disabled + dmac_evosel_10: Event generation disabled + dmac_evosel_11: Event generation disabled + dmac_evosel_12: Event generation disabled + dmac_evosel_13: Event generation disabled + dmac_evosel_14: Event generation disabled + dmac_evosel_15: Event generation disabled + dmac_evosel_16: Event generation disabled + dmac_evosel_17: Event generation disabled + dmac_evosel_18: Event generation disabled + dmac_evosel_19: Event generation disabled + dmac_evosel_2: Event generation disabled + dmac_evosel_20: Event generation disabled + dmac_evosel_21: Event generation disabled + dmac_evosel_22: Event generation disabled + dmac_evosel_23: Event generation disabled + dmac_evosel_24: Event generation disabled + dmac_evosel_25: Event generation disabled + dmac_evosel_26: Event generation disabled + dmac_evosel_27: Event generation disabled + dmac_evosel_28: Event generation disabled + dmac_evosel_29: Event generation disabled + dmac_evosel_3: Event generation disabled + dmac_evosel_30: Event generation disabled + dmac_evosel_31: Event generation disabled + dmac_evosel_4: Event generation disabled + dmac_evosel_5: Event generation disabled + dmac_evosel_6: Event generation disabled + dmac_evosel_7: Event generation disabled + dmac_evosel_8: Event generation disabled + dmac_evosel_9: Event generation disabled + dmac_lvl_0: Channel priority 0 + dmac_lvl_1: Channel priority 0 + dmac_lvl_10: Channel priority 0 + dmac_lvl_11: Channel priority 0 + dmac_lvl_12: Channel priority 0 + dmac_lvl_13: Channel priority 0 + dmac_lvl_14: Channel priority 0 + dmac_lvl_15: Channel priority 0 + dmac_lvl_16: Channel priority 0 + dmac_lvl_17: Channel priority 0 + dmac_lvl_18: Channel priority 0 + dmac_lvl_19: Channel priority 0 + dmac_lvl_2: Channel priority 0 + dmac_lvl_20: Channel priority 0 + dmac_lvl_21: Channel priority 0 + dmac_lvl_22: Channel priority 0 + dmac_lvl_23: Channel priority 0 + dmac_lvl_24: Channel priority 0 + dmac_lvl_25: Channel priority 0 + dmac_lvl_26: Channel priority 0 + dmac_lvl_27: Channel priority 0 + dmac_lvl_28: Channel priority 0 + dmac_lvl_29: Channel priority 0 + dmac_lvl_3: Channel priority 0 + dmac_lvl_30: Channel priority 0 + dmac_lvl_31: Channel priority 0 + dmac_lvl_4: Channel priority 0 + dmac_lvl_5: Channel priority 0 + dmac_lvl_6: Channel priority 0 + dmac_lvl_7: Channel priority 0 + dmac_lvl_8: Channel priority 0 + dmac_lvl_9: Channel priority 0 + dmac_lvlen0: true + dmac_lvlen1: true + dmac_lvlen2: true + dmac_lvlen3: false + dmac_lvlpri0: 0 + dmac_lvlpri1: 0 + dmac_lvlpri2: 0 + dmac_lvlpri3: 0 + dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 + dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 + dmac_rrlvlen2: Round-robin arbitration scheme for channel with priority 2 + dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 + dmac_runstdby_0: false + dmac_runstdby_1: false + dmac_runstdby_10: false + dmac_runstdby_11: false + dmac_runstdby_12: false + dmac_runstdby_13: false + dmac_runstdby_14: false + dmac_runstdby_15: false + dmac_runstdby_16: false + dmac_runstdby_17: false + dmac_runstdby_18: false + dmac_runstdby_19: false + dmac_runstdby_2: false + dmac_runstdby_20: false + dmac_runstdby_21: false + dmac_runstdby_22: false + dmac_runstdby_23: false + dmac_runstdby_24: false + dmac_runstdby_25: false + dmac_runstdby_26: false + dmac_runstdby_27: false + dmac_runstdby_28: false + dmac_runstdby_29: false + dmac_runstdby_3: false + dmac_runstdby_30: false + dmac_runstdby_31: false + dmac_runstdby_4: false + dmac_runstdby_5: false + dmac_runstdby_6: false + dmac_runstdby_7: false + dmac_runstdby_8: false + dmac_runstdby_9: false + dmac_srcinc_0: false + dmac_srcinc_1: false + dmac_srcinc_10: false + dmac_srcinc_11: false + dmac_srcinc_12: false + dmac_srcinc_13: false + dmac_srcinc_14: false + dmac_srcinc_15: false + dmac_srcinc_16: false + dmac_srcinc_17: false + dmac_srcinc_18: false + dmac_srcinc_19: false + dmac_srcinc_2: true + dmac_srcinc_20: false + dmac_srcinc_21: false + dmac_srcinc_22: false + dmac_srcinc_23: false + dmac_srcinc_24: false + dmac_srcinc_25: false + dmac_srcinc_26: false + dmac_srcinc_27: false + dmac_srcinc_28: false + dmac_srcinc_29: false + dmac_srcinc_3: false + dmac_srcinc_30: false + dmac_srcinc_31: false + dmac_srcinc_4: false + dmac_srcinc_5: false + dmac_srcinc_6: false + dmac_srcinc_7: false + dmac_srcinc_8: false + dmac_srcinc_9: false + dmac_stepsel_0: Step size settings apply to the destination address + dmac_stepsel_1: Step size settings apply to the destination address + dmac_stepsel_10: Step size settings apply to the destination address + dmac_stepsel_11: Step size settings apply to the destination address + dmac_stepsel_12: Step size settings apply to the destination address + dmac_stepsel_13: Step size settings apply to the destination address + dmac_stepsel_14: Step size settings apply to the destination address + dmac_stepsel_15: Step size settings apply to the destination address + dmac_stepsel_16: Step size settings apply to the destination address + dmac_stepsel_17: Step size settings apply to the destination address + dmac_stepsel_18: Step size settings apply to the destination address + dmac_stepsel_19: Step size settings apply to the destination address + dmac_stepsel_2: Step size settings apply to the source address + dmac_stepsel_20: Step size settings apply to the destination address + dmac_stepsel_21: Step size settings apply to the destination address + dmac_stepsel_22: Step size settings apply to the destination address + dmac_stepsel_23: Step size settings apply to the destination address + dmac_stepsel_24: Step size settings apply to the destination address + dmac_stepsel_25: Step size settings apply to the destination address + dmac_stepsel_26: Step size settings apply to the destination address + dmac_stepsel_27: Step size settings apply to the destination address + dmac_stepsel_28: Step size settings apply to the destination address + dmac_stepsel_29: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_30: Step size settings apply to the destination address + dmac_stepsel_31: Step size settings apply to the destination address + dmac_stepsel_4: Step size settings apply to the destination address + dmac_stepsel_5: Step size settings apply to the destination address + dmac_stepsel_6: Step size settings apply to the destination address + dmac_stepsel_7: Step size settings apply to the destination address + dmac_stepsel_8: Step size settings apply to the destination address + dmac_stepsel_9: Step size settings apply to the destination address + dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_trifsrc_0: Only software/event triggers + dmac_trifsrc_1: Only software/event triggers + dmac_trifsrc_10: Only software/event triggers + dmac_trifsrc_11: Only software/event triggers + dmac_trifsrc_12: Only software/event triggers + dmac_trifsrc_13: Only software/event triggers + dmac_trifsrc_14: Only software/event triggers + dmac_trifsrc_15: Only software/event triggers + dmac_trifsrc_16: Only software/event triggers + dmac_trifsrc_17: Only software/event triggers + dmac_trifsrc_18: Only software/event triggers + dmac_trifsrc_19: Only software/event triggers + dmac_trifsrc_2: SERCOM4 TX Trigger + dmac_trifsrc_20: Only software/event triggers + dmac_trifsrc_21: Only software/event triggers + dmac_trifsrc_22: Only software/event triggers + dmac_trifsrc_23: Only software/event triggers + dmac_trifsrc_24: Only software/event triggers + dmac_trifsrc_25: Only software/event triggers + dmac_trifsrc_26: Only software/event triggers + dmac_trifsrc_27: Only software/event triggers + dmac_trifsrc_28: Only software/event triggers + dmac_trifsrc_29: Only software/event triggers + dmac_trifsrc_3: SERCOM4 RX Trigger + dmac_trifsrc_30: Only software/event triggers + dmac_trifsrc_31: Only software/event triggers + dmac_trifsrc_4: Only software/event triggers + dmac_trifsrc_5: Only software/event triggers + dmac_trifsrc_6: Only software/event triggers + dmac_trifsrc_7: Only software/event triggers + dmac_trifsrc_8: Only software/event triggers + dmac_trifsrc_9: Only software/event triggers + dmac_trigact_0: One trigger required for each block transfer + dmac_trigact_1: One trigger required for each block transfer + dmac_trigact_10: One trigger required for each block transfer + dmac_trigact_11: One trigger required for each block transfer + dmac_trigact_12: One trigger required for each block transfer + dmac_trigact_13: One trigger required for each block transfer + dmac_trigact_14: One trigger required for each block transfer + dmac_trigact_15: One trigger required for each block transfer + dmac_trigact_16: One trigger required for each block transfer + dmac_trigact_17: One trigger required for each block transfer + dmac_trigact_18: One trigger required for each block transfer + dmac_trigact_19: One trigger required for each block transfer + dmac_trigact_2: One trigger required for each beat transfer + dmac_trigact_20: One trigger required for each block transfer + dmac_trigact_21: One trigger required for each block transfer + dmac_trigact_22: One trigger required for each block transfer + dmac_trigact_23: One trigger required for each block transfer + dmac_trigact_24: One trigger required for each block transfer + dmac_trigact_25: One trigger required for each block transfer + dmac_trigact_26: One trigger required for each block transfer + dmac_trigact_27: One trigger required for each block transfer + dmac_trigact_28: One trigger required for each block transfer + dmac_trigact_29: One trigger required for each block transfer + dmac_trigact_3: One trigger required for each beat transfer + dmac_trigact_30: One trigger required for each block transfer + dmac_trigact_31: One trigger required for each block transfer + dmac_trigact_4: One trigger required for each block transfer + dmac_trigact_5: One trigger required for each block transfer + dmac_trigact_6: One trigger required for each block transfer + dmac_trigact_7: One trigger required for each block transfer + dmac_trigact_8: One trigger required for each block transfer + dmac_trigact_9: One trigger required for each block transfer + optional_signals: [] + variant: null + clocks: + domain_group: null + EVENT_SYSTEM_0: + user_label: EVENT_SYSTEM_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::EVSYS::driver_config_definition::Event.System::HAL:Driver:Event.system + functionality: Event_System + api: HAL:Driver:Event_system + configuration: + evsys_channel_0: No channel output selected + evsys_channel_1: No channel output selected + evsys_channel_10: Channel 0 + evsys_channel_11: Channel 0 + evsys_channel_12: Channel 0 + evsys_channel_17: No channel output selected + evsys_channel_18: No channel output selected + evsys_channel_19: No channel output selected + evsys_channel_2: No channel output selected + evsys_channel_20: No channel output selected + evsys_channel_21: No channel output selected + evsys_channel_22: No channel output selected + evsys_channel_23: No channel output selected + evsys_channel_24: No channel output selected + evsys_channel_25: No channel output selected + evsys_channel_26: No channel output selected + evsys_channel_27: No channel output selected + evsys_channel_28: No channel output selected + evsys_channel_29: No channel output selected + evsys_channel_3: No channel output selected + evsys_channel_30: No channel output selected + evsys_channel_31: No channel output selected + evsys_channel_32: No channel output selected + evsys_channel_33: No channel output selected + evsys_channel_34: No channel output selected + evsys_channel_35: No channel output selected + evsys_channel_36: No channel output selected + evsys_channel_37: No channel output selected + evsys_channel_38: No channel output selected + evsys_channel_39: No channel output selected + evsys_channel_4: No channel output selected + evsys_channel_40: No channel output selected + evsys_channel_41: No channel output selected + evsys_channel_42: No channel output selected + evsys_channel_43: No channel output selected + evsys_channel_44: No channel output selected + evsys_channel_45: No channel output selected + evsys_channel_46: No channel output selected + evsys_channel_47: No channel output selected + evsys_channel_48: No channel output selected + evsys_channel_49: No channel output selected + evsys_channel_5: Channel 0 + evsys_channel_50: No channel output selected + evsys_channel_51: No channel output selected + evsys_channel_52: No channel output selected + evsys_channel_53: No channel output selected + evsys_channel_54: No channel output selected + evsys_channel_55: No channel output selected + evsys_channel_56: No channel output selected + evsys_channel_57: No channel output selected + evsys_channel_58: No channel output selected + evsys_channel_59: No channel output selected + evsys_channel_6: Channel 0 + evsys_channel_60: No channel output selected + evsys_channel_61: No channel output selected + evsys_channel_62: No channel output selected + evsys_channel_63: No channel output selected + evsys_channel_64: No channel output selected + evsys_channel_65: No channel output selected + evsys_channel_66: No channel output selected + evsys_channel_7: Channel 0 + evsys_channel_8: Channel 0 + evsys_channel_9: Channel 0 + evsys_channel_setting_0: true + evsys_channel_setting_1: false + evsys_channel_setting_10: false + evsys_channel_setting_11: false + evsys_channel_setting_12: false + evsys_channel_setting_13: false + evsys_channel_setting_14: false + evsys_channel_setting_15: false + evsys_channel_setting_16: false + evsys_channel_setting_17: false + evsys_channel_setting_18: false + evsys_channel_setting_19: false + evsys_channel_setting_2: false + evsys_channel_setting_20: false + evsys_channel_setting_21: false + evsys_channel_setting_22: false + evsys_channel_setting_23: false + evsys_channel_setting_24: false + evsys_channel_setting_25: false + evsys_channel_setting_26: false + evsys_channel_setting_27: false + evsys_channel_setting_28: false + evsys_channel_setting_29: false + evsys_channel_setting_3: false + evsys_channel_setting_30: false + evsys_channel_setting_31: false + evsys_channel_setting_4: false + evsys_channel_setting_5: false + evsys_channel_setting_6: false + evsys_channel_setting_7: false + evsys_channel_setting_8: false + evsys_channel_setting_9: false + evsys_edgsel_0: No event output when using the resynchronized or synchronous + path + evsys_edgsel_1: No event output when using the resynchronized or synchronous + path + evsys_edgsel_10: No event output when using the resynchronized or synchronous + path + evsys_edgsel_11: No event output when using the resynchronized or synchronous + path + evsys_edgsel_12: No event output when using the resynchronized or synchronous + path + evsys_edgsel_13: No event output when using the resynchronized or synchronous + path + evsys_edgsel_14: No event output when using the resynchronized or synchronous + path + evsys_edgsel_15: No event output when using the resynchronized or synchronous + path + evsys_edgsel_16: No event output when using the resynchronized or synchronous + path + evsys_edgsel_17: No event output when using the resynchronized or synchronous + path + evsys_edgsel_18: No event output when using the resynchronized or synchronous + path + evsys_edgsel_19: No event output when using the resynchronized or synchronous + path + evsys_edgsel_2: No event output when using the resynchronized or synchronous + path + evsys_edgsel_20: No event output when using the resynchronized or synchronous + path + evsys_edgsel_21: No event output when using the resynchronized or synchronous + path + evsys_edgsel_22: No event output when using the resynchronized or synchronous + path + evsys_edgsel_23: No event output when using the resynchronized or synchronous + path + evsys_edgsel_24: No event output when using the resynchronized or synchronous + path + evsys_edgsel_25: No event output when using the resynchronized or synchronous + path + evsys_edgsel_26: No event output when using the resynchronized or synchronous + path + evsys_edgsel_27: No event output when using the resynchronized or synchronous + path + evsys_edgsel_28: No event output when using the resynchronized or synchronous + path + evsys_edgsel_29: No event output when using the resynchronized or synchronous + path + evsys_edgsel_3: No event output when using the resynchronized or synchronous + path + evsys_edgsel_30: No event output when using the resynchronized or synchronous + path + evsys_edgsel_31: No event output when using the resynchronized or synchronous + path + evsys_edgsel_4: No event output when using the resynchronized or synchronous + path + evsys_edgsel_5: No event output when using the resynchronized or synchronous + path + evsys_edgsel_6: No event output when using the resynchronized or synchronous + path + evsys_edgsel_7: No event output when using the resynchronized or synchronous + path + evsys_edgsel_8: No event output when using the resynchronized or synchronous + path + evsys_edgsel_9: No event output when using the resynchronized or synchronous + path + evsys_evd_0: false + evsys_evd_1: false + evsys_evd_10: false + evsys_evd_11: false + evsys_evd_12: false + evsys_evd_13: false + evsys_evd_14: false + evsys_evd_15: false + evsys_evd_16: false + evsys_evd_17: false + evsys_evd_18: false + evsys_evd_19: false + evsys_evd_2: false + evsys_evd_20: false + evsys_evd_21: false + evsys_evd_22: false + evsys_evd_23: false + evsys_evd_24: false + evsys_evd_25: false + evsys_evd_26: false + evsys_evd_27: false + evsys_evd_28: false + evsys_evd_29: false + evsys_evd_3: false + evsys_evd_30: false + evsys_evd_31: false + evsys_evd_4: false + evsys_evd_5: false + evsys_evd_6: false + evsys_evd_7: false + evsys_evd_8: false + evsys_evd_9: false + evsys_evgen_0: TC0 overflow + evsys_evgen_1: No event generator + evsys_evgen_10: No event generator + evsys_evgen_11: No event generator + evsys_evgen_12: No event generator + evsys_evgen_13: No event generator + evsys_evgen_14: No event generator + evsys_evgen_15: No event generator + evsys_evgen_16: No event generator + evsys_evgen_17: No event generator + evsys_evgen_18: No event generator + evsys_evgen_19: No event generator + evsys_evgen_2: No event generator + evsys_evgen_20: No event generator + evsys_evgen_21: No event generator + evsys_evgen_22: No event generator + evsys_evgen_23: No event generator + evsys_evgen_24: No event generator + evsys_evgen_25: No event generator + evsys_evgen_26: No event generator + evsys_evgen_27: No event generator + evsys_evgen_28: No event generator + evsys_evgen_29: No event generator + evsys_evgen_3: No event generator + evsys_evgen_30: No event generator + evsys_evgen_31: No event generator + evsys_evgen_4: No event generator + evsys_evgen_5: No event generator + evsys_evgen_6: No event generator + evsys_evgen_7: No event generator + evsys_evgen_8: No event generator + evsys_evgen_9: No event generator + evsys_ondemand_0: false + evsys_ondemand_1: false + evsys_ondemand_10: false + evsys_ondemand_11: false + evsys_ondemand_12: false + evsys_ondemand_13: false + evsys_ondemand_14: false + evsys_ondemand_15: false + evsys_ondemand_16: false + evsys_ondemand_17: false + evsys_ondemand_18: false + evsys_ondemand_19: false + evsys_ondemand_2: false + evsys_ondemand_20: false + evsys_ondemand_21: false + evsys_ondemand_22: false + evsys_ondemand_23: false + evsys_ondemand_24: false + evsys_ondemand_25: false + evsys_ondemand_26: false + evsys_ondemand_27: false + evsys_ondemand_28: false + evsys_ondemand_29: false + evsys_ondemand_3: false + evsys_ondemand_30: false + evsys_ondemand_31: false + evsys_ondemand_4: false + evsys_ondemand_5: false + evsys_ondemand_6: false + evsys_ondemand_7: false + evsys_ondemand_8: false + evsys_ondemand_9: false + evsys_ovr_0: false + evsys_ovr_1: false + evsys_ovr_10: false + evsys_ovr_11: false + evsys_ovr_12: false + evsys_ovr_13: false + evsys_ovr_14: false + evsys_ovr_15: false + evsys_ovr_16: false + evsys_ovr_17: false + evsys_ovr_18: false + evsys_ovr_19: false + evsys_ovr_2: false + evsys_ovr_20: false + evsys_ovr_21: false + evsys_ovr_22: false + evsys_ovr_23: false + evsys_ovr_24: false + evsys_ovr_25: false + evsys_ovr_26: false + evsys_ovr_27: false + evsys_ovr_28: false + evsys_ovr_29: false + evsys_ovr_3: false + evsys_ovr_30: false + evsys_ovr_31: false + evsys_ovr_4: false + evsys_ovr_5: false + evsys_ovr_6: false + evsys_ovr_7: false + evsys_ovr_8: false + evsys_ovr_9: false + evsys_path_0: Asynchronous path + evsys_path_1: Synchronous path + evsys_path_10: Synchronous path + evsys_path_11: Synchronous path + evsys_path_12: Synchronous path + evsys_path_13: Synchronous path + evsys_path_14: Synchronous path + evsys_path_15: Synchronous path + evsys_path_16: Synchronous path + evsys_path_17: Synchronous path + evsys_path_18: Synchronous path + evsys_path_19: Synchronous path + evsys_path_2: Synchronous path + evsys_path_20: Synchronous path + evsys_path_21: Synchronous path + evsys_path_22: Synchronous path + evsys_path_23: Synchronous path + evsys_path_24: Synchronous path + evsys_path_25: Synchronous path + evsys_path_26: Synchronous path + evsys_path_27: Synchronous path + evsys_path_28: Synchronous path + evsys_path_29: Synchronous path + evsys_path_3: Synchronous path + evsys_path_30: Synchronous path + evsys_path_31: Synchronous path + evsys_path_4: Synchronous path + evsys_path_5: Synchronous path + evsys_path_6: Synchronous path + evsys_path_7: Synchronous path + evsys_path_8: Synchronous path + evsys_path_9: Synchronous path + evsys_runstdby_0: false + evsys_runstdby_1: false + evsys_runstdby_10: false + evsys_runstdby_11: false + evsys_runstdby_12: false + evsys_runstdby_13: false + evsys_runstdby_14: false + evsys_runstdby_15: false + evsys_runstdby_16: false + evsys_runstdby_17: false + evsys_runstdby_18: false + evsys_runstdby_19: false + evsys_runstdby_2: false + evsys_runstdby_20: false + evsys_runstdby_21: false + evsys_runstdby_22: false + evsys_runstdby_23: false + evsys_runstdby_24: false + evsys_runstdby_25: false + evsys_runstdby_26: false + evsys_runstdby_27: false + evsys_runstdby_28: false + evsys_runstdby_29: false + evsys_runstdby_3: false + evsys_runstdby_30: false + evsys_runstdby_31: false + evsys_runstdby_4: false + evsys_runstdby_5: false + evsys_runstdby_6: false + evsys_runstdby_7: false + evsys_runstdby_8: false + evsys_runstdby_9: false + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: Channel 0 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 1 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 2 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 3 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 4 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 5 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 6 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 7 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 8 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 9 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 10 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 11 + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + evsys_clk_selection_0: Generic clock generator 0 + evsys_clk_selection_1: Generic clock generator 0 + evsys_clk_selection_10: Generic clock generator 0 + evsys_clk_selection_11: Generic clock generator 0 + evsys_clk_selection_2: Generic clock generator 0 + evsys_clk_selection_3: Generic clock generator 0 + evsys_clk_selection_4: Generic clock generator 0 + evsys_clk_selection_5: Generic clock generator 0 + evsys_clk_selection_6: Generic clock generator 0 + evsys_clk_selection_7: Generic clock generator 0 + evsys_clk_selection_8: Generic clock generator 0 + evsys_clk_selection_9: Generic clock generator 0 + GCLK: + user_label: GCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + functionality: System + api: HAL:HPL:GCLK + configuration: + $input: 12000000 + $input_id: External Crystal Oscillator 8-48MHz (XOSC1) + RESERVED_InputFreq: 12000000 + RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1) + _$freq_output_Generic clock generator 0: 12000000 + _$freq_output_Generic clock generator 1: 48000000 + _$freq_output_Generic clock generator 10: 12000000 + _$freq_output_Generic clock generator 11: 12000000 + _$freq_output_Generic clock generator 2: 3000000 + _$freq_output_Generic clock generator 3: 32768 + _$freq_output_Generic clock generator 4: 12000000 + _$freq_output_Generic clock generator 5: 12000000 + _$freq_output_Generic clock generator 6: 12000000 + _$freq_output_Generic clock generator 7: 12000000 + _$freq_output_Generic clock generator 8: 12000000 + _$freq_output_Generic clock generator 9: 12000000 + enable_gclk_gen_0: true + enable_gclk_gen_0__externalclock: 1000000 + enable_gclk_gen_1: false + enable_gclk_gen_10: false + enable_gclk_gen_10__externalclock: 1000000 + enable_gclk_gen_11: false + enable_gclk_gen_11__externalclock: 1000000 + enable_gclk_gen_1__externalclock: 1000000 + enable_gclk_gen_2: false + enable_gclk_gen_2__externalclock: 1000000 + enable_gclk_gen_3: false + enable_gclk_gen_3__externalclock: 1000000 + enable_gclk_gen_4: false + enable_gclk_gen_4__externalclock: 1000000 + enable_gclk_gen_5: false + enable_gclk_gen_5__externalclock: 1000000 + enable_gclk_gen_6: false + enable_gclk_gen_6__externalclock: 1000000 + enable_gclk_gen_7: false + enable_gclk_gen_7__externalclock: 1000000 + enable_gclk_gen_8: false + enable_gclk_gen_8__externalclock: 1000000 + enable_gclk_gen_9: false + enable_gclk_gen_9__externalclock: 1000000 + gclk_arch_gen_0_enable: true + gclk_arch_gen_0_idc: false + gclk_arch_gen_0_oe: false + gclk_arch_gen_0_oov: false + gclk_arch_gen_0_runstdby: false + gclk_arch_gen_10_enable: false + gclk_arch_gen_10_idc: false + gclk_arch_gen_10_oe: false + gclk_arch_gen_10_oov: false + gclk_arch_gen_10_runstdby: false + gclk_arch_gen_11_enable: false + gclk_arch_gen_11_idc: false + gclk_arch_gen_11_oe: false + gclk_arch_gen_11_oov: false + gclk_arch_gen_11_runstdby: false + gclk_arch_gen_1_enable: false + gclk_arch_gen_1_idc: false + gclk_arch_gen_1_oe: false + gclk_arch_gen_1_oov: false + gclk_arch_gen_1_runstdby: false + gclk_arch_gen_2_enable: false + gclk_arch_gen_2_idc: false + gclk_arch_gen_2_oe: false + gclk_arch_gen_2_oov: false + gclk_arch_gen_2_runstdby: false + gclk_arch_gen_3_enable: false + gclk_arch_gen_3_idc: false + gclk_arch_gen_3_oe: false + gclk_arch_gen_3_oov: false + gclk_arch_gen_3_runstdby: false + gclk_arch_gen_4_enable: false + gclk_arch_gen_4_idc: false + gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oov: false + gclk_arch_gen_4_runstdby: false + gclk_arch_gen_5_enable: false + gclk_arch_gen_5_idc: false + gclk_arch_gen_5_oe: false + gclk_arch_gen_5_oov: false + gclk_arch_gen_5_runstdby: false + gclk_arch_gen_6_enable: false + gclk_arch_gen_6_idc: false + gclk_arch_gen_6_oe: false + gclk_arch_gen_6_oov: false + gclk_arch_gen_6_runstdby: false + gclk_arch_gen_7_enable: false + gclk_arch_gen_7_idc: false + gclk_arch_gen_7_oe: false + gclk_arch_gen_7_oov: false + gclk_arch_gen_7_runstdby: false + gclk_arch_gen_8_enable: false + gclk_arch_gen_8_idc: false + gclk_arch_gen_8_oe: false + gclk_arch_gen_8_oov: false + gclk_arch_gen_8_runstdby: false + gclk_arch_gen_9_enable: false + gclk_arch_gen_9_idc: false + gclk_arch_gen_9_oe: false + gclk_arch_gen_9_oov: false + gclk_arch_gen_9_runstdby: false + gclk_gen_0_div: 1 + gclk_gen_0_div_sel: false + gclk_gen_0_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_10_div: 1 + gclk_gen_10_div_sel: false + gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_11_div: 1 + gclk_gen_11_div_sel: false + gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_1_div: 1 + gclk_gen_1_div_sel: false + gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) + gclk_gen_2_div: 1 + gclk_gen_2_div_sel: true + gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_3_div: 1 + gclk_gen_3_div_sel: false + gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) + gclk_gen_4_div: 1 + gclk_gen_4_div_sel: false + gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_5_div: 1 + gclk_gen_5_div_sel: false + gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_6_div: 1 + gclk_gen_6_div_sel: false + gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_7_div: 1 + gclk_gen_7_div_sel: false + gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_8_div: 1 + gclk_gen_8_div_sel: false + gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_9_div: 1 + gclk_gen_9_div_sel: false + gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + optional_signals: [] + variant: null + clocks: + domain_group: null + MCLK: + user_label: MCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + functionality: System + api: HAL:HPL:MCLK + configuration: + $input: 12000000 + $input_id: Generic clock generator 0 + RESERVED_InputFreq: 12000000 + RESERVED_InputFreq_id: Generic clock generator 0 + _$freq_output_CPU: 12000000 + cpu_clock_source: Generic clock generator 0 + cpu_div: '1' + enable_cpu_clock: true + mclk_arch_bupdiv: Divide by 8 + mclk_arch_hsdiv: Divide by 1 + mclk_arch_lpdiv: Divide by 4 + nvm_wait_states: '0' + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: CPU + input: CPU + external: false + external_frequency: 0 + configuration: {} + OSC32KCTRL: + user_label: OSC32KCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + functionality: System + api: HAL:HPL:OSC32KCTRL + configuration: + $input: 32768 + $input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + RESERVED_InputFreq: 32768 + RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + _$freq_output_RTC source: 32768 + enable_osculp32k: true + enable_rtc_source: false + enable_xosc32k: false + osculp32k_calib: 0 + osculp32k_calib_enable: false + rtc_1khz_selection: false + rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + xosc32k_arch_cfden: false + xosc32k_arch_cfdeo: false + xosc32k_arch_cgm: Standard mode + xosc32k_arch_en1k: false + xosc32k_arch_en32k: false + xosc32k_arch_enable: false + xosc32k_arch_ondemand: true + xosc32k_arch_runstdby: false + xosc32k_arch_startup: 62592us + xosc32k_arch_swben: false + xosc32k_arch_xtalen: true + optional_signals: [] + variant: null + clocks: + domain_group: null + OSCCTRL: + user_label: OSCCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + functionality: System + api: HAL:HPL:OSCCTRL + configuration: + $input: 32768 + $input_id: 32kHz External Crystal Oscillator (XOSC32K) + RESERVED_InputFreq: 32768 + RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K) + _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000 + _$freq_output_Digital Phase Locked Loop (DPLL0): 47985664 + _$freq_output_Digital Phase Locked Loop (DPLL1): 47985664 + _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000 + _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000 + dfll_arch_bplckc: false + dfll_arch_calibration: false + dfll_arch_ccdis: false + dfll_arch_coarse: 31 + dfll_arch_cstep: 1 + dfll_arch_enable: false + dfll_arch_fine: 128 + dfll_arch_fstep: 1 + dfll_arch_llaw: false + dfll_arch_ondemand: false + dfll_arch_qldis: false + dfll_arch_runstdby: false + dfll_arch_stable: false + dfll_arch_usbcrm: false + dfll_arch_waitlock: true + dfll_mode: Open Loop Mode + dfll_mul: 0 + dfll_ref_clock: Generic clock generator 3 + enable_dfll: false + enable_fdpll0: false + enable_fdpll1: false + enable_xosc0: false + enable_xosc1: true + fdpll0_arch_dcoen: false + fdpll0_arch_enable: false + fdpll0_arch_filter: 0 + fdpll0_arch_lbypass: false + fdpll0_arch_ltime: No time-out, automatic lock + fdpll0_arch_ondemand: false + fdpll0_arch_refclk: XOSC32K clock reference + fdpll0_arch_runstdby: false + fdpll0_arch_wuf: false + fdpll0_clock_dcofilter: 0 + fdpll0_clock_div: 0 + fdpll0_ldr: 1463 + fdpll0_ldrfrac: 13 + fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + fdpll1_arch_dcoen: false + fdpll1_arch_enable: false + fdpll1_arch_filter: 0 + fdpll1_arch_lbypass: false + fdpll1_arch_ltime: No time-out, automatic lock + fdpll1_arch_ondemand: false + fdpll1_arch_refclk: XOSC32K clock reference + fdpll1_arch_runstdby: false + fdpll1_arch_wuf: false + fdpll1_clock_dcofilter: 0 + fdpll1_clock_div: 0 + fdpll1_ldr: 1463 + fdpll1_ldrfrac: 13 + fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + xosc0_arch_cfden: false + xosc0_arch_enable: false + xosc0_arch_enalc: false + xosc0_arch_lowbufgain: false + xosc0_arch_ondemand: false + xosc0_arch_runstdby: false + xosc0_arch_startup: 31us + xosc0_arch_swben: false + xosc0_arch_xtalen: false + xosc0_frequency: 12000000 + xosc1_arch_cfden: false + xosc1_arch_enable: true + xosc1_arch_enalc: false + xosc1_arch_lowbufgain: false + xosc1_arch_ondemand: false + xosc1_arch_runstdby: false + xosc1_arch_startup: 31us + xosc1_arch_swben: false + xosc1_arch_xtalen: true + xosc1_frequency: 12000000 + optional_signals: [] + variant: null + clocks: + domain_group: null + PORT: + user_label: PORT + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT + functionality: System + api: HAL:HPL:PORT + configuration: + enable_port_input_event_0: false + enable_port_input_event_1: false + enable_port_input_event_2: false + enable_port_input_event_3: false + porta_event_action_0: Output register of pin will be set to level of event + porta_event_action_1: Output register of pin will be set to level of event + porta_event_action_2: Output register of pin will be set to level of event + porta_event_action_3: Output register of pin will be set to level of event + porta_event_pin_identifier_0: 0 + porta_event_pin_identifier_1: 0 + porta_event_pin_identifier_2: 0 + porta_event_pin_identifier_3: 0 + porta_input_event_enable_0: false + porta_input_event_enable_1: false + porta_input_event_enable_2: false + porta_input_event_enable_3: false + portb_event_action_0: Output register of pin will be set to level of event + portb_event_action_1: Output register of pin will be set to level of event + portb_event_action_2: Output register of pin will be set to level of event + portb_event_action_3: Output register of pin will be set to level of event + portb_event_pin_identifier_0: 0 + portb_event_pin_identifier_1: 0 + portb_event_pin_identifier_2: 0 + portb_event_pin_identifier_3: 0 + portb_input_event_enable_0: false + portb_input_event_enable_1: false + portb_input_event_enable_2: false + portb_input_event_enable_3: false + portc_event_action_0: Output register of pin will be set to level of event + portc_event_action_1: Output register of pin will be set to level of event + portc_event_action_2: Output register of pin will be set to level of event + portc_event_action_3: Output register of pin will be set to level of event + portc_event_pin_identifier_0: 0 + portc_event_pin_identifier_1: 0 + portc_event_pin_identifier_2: 0 + portc_event_pin_identifier_3: 0 + portc_input_event_enable_0: false + portc_input_event_enable_1: false + portc_input_event_enable_2: false + portc_input_event_enable_3: false + portd_event_action_0: Output register of pin will be set to level of event + portd_event_action_1: Output register of pin will be set to level of event + portd_event_action_2: Output register of pin will be set to level of event + portd_event_action_3: Output register of pin will be set to level of event + portd_event_pin_identifier_0: 0 + portd_event_pin_identifier_1: 0 + portd_event_pin_identifier_2: 0 + portd_event_pin_identifier_3: 0 + portd_input_event_enable_0: false + portd_input_event_enable_1: false + portd_input_event_enable_2: false + portd_input_event_enable_3: false + optional_signals: [] + variant: null + clocks: + domain_group: null + RAMECC: + user_label: RAMECC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC + functionality: System + api: HAL:HPL:RAMECC + configuration: {} + optional_signals: [] + variant: null + clocks: + domain_group: null + TARGET_IO: + user_label: TARGET_IO + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Sync + functionality: USART + api: HAL:Driver:USART_Sync + configuration: + usart_advanced: false + usart_arch_clock_mode: USART with internal clock + usart_arch_cloden: false + usart_arch_dbgstop: Keep running + usart_arch_dord: LSB is transmitted first + usart_arch_enc: No encoding + usart_arch_fractional: 0 + usart_arch_ibon: false + usart_arch_lin_slave_enable: Disable + usart_arch_runstdby: false + usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) + usart_arch_sampr: 16x arithmetic + usart_arch_sfde: false + usart_baud_rate: 9600 + usart_character_size: 8 bits + usart_parity: No parity + usart_rx_enable: true + usart_stop_bit: One stop bit + usart_tx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=1, CMODE=0 + required_signals: + - name: SERCOM2/PAD/0 + pad: PB25 + label: TX + - name: SERCOM2/PAD/1 + pad: PB24 + label: RX + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + SPI_0: + user_label: SPI_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM4::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.DMA + functionality: SPI + api: HAL:Driver:SPI_Master_DMA + configuration: + spi_master_advanced: false + spi_master_arch_cpha: Sample input on leading edge + spi_master_arch_cpol: SCK is low when idle + spi_master_arch_dbgstop: Keep running + spi_master_arch_dord: MSB first + spi_master_arch_ibon: In data stream + spi_master_arch_runstdby: false + spi_master_baud_rate: 1000000 + spi_master_character_size: 8 bits + spi_master_dma_rx_channel: 3 + spi_master_dma_tx_channel: 2 + spi_master_dummybyte: 511 + spi_master_rx_channel: true + spi_master_rx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=3 + required_signals: + - name: SERCOM4/PAD/0 + pad: PB27 + label: MOSI + - name: SERCOM4/PAD/1 + pad: PB26 + label: SCK + - name: SERCOM4/PAD/3 + pad: PB29 + label: MISO + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + SPI_1: + user_label: SPI_1 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM6::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.Sync + functionality: SPI + api: HAL:Driver:SPI_Master_Sync + configuration: + spi_master_advanced: true + spi_master_arch_cpha: Sample input on trailing edge + spi_master_arch_cpol: SCK is high when idle + spi_master_arch_dbgstop: Keep running + spi_master_arch_dord: MSB first + spi_master_arch_ibon: In data stream + spi_master_arch_runstdby: false + spi_master_baud_rate: 1000000 + spi_master_character_size: 8 bits + spi_master_dummybyte: 511 + spi_master_rx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=3 + required_signals: + - name: SERCOM6/PAD/0 + pad: PC04 + label: MOSI + - name: SERCOM6/PAD/1 + pad: PC05 + label: SCK + - name: SERCOM6/PAD/3 + pad: PC07 + label: MISO + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + TIMER_0: + user_label: TIMER_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC0::driver_config_definition::Timer::HAL:Driver:Timer + functionality: Timer + api: HAL:Driver:Timer + configuration: + tc_arch_dbgrun: false + tc_arch_evact: Event action disabled + tc_arch_mceo0: false + tc_arch_mceo1: false + tc_arch_ondemand: false + tc_arch_ovfeo: false + tc_arch_presync: Reload or reset counter on next GCLK + tc_arch_runstdby: false + tc_arch_tcei: false + tc_arch_tcinv: false + timer_advanced_configuration: false + timer_event_control: true + timer_prescaler: Divide by 8 + timer_tick: 1000 + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: TC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + tc_gclk_selection: Generic clock generator 0 +pads: + PC04: + name: PC04 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC04 + mode: Digital output + user_label: PC04 + configuration: null + PC05: + name: PC05 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC05 + mode: Digital output + user_label: PC05 + configuration: null + Angle_SS: + name: PC06 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC06 + mode: Digital output + user_label: Angle_SS + configuration: + pad_initial_level: High + PC07: + name: PC07 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC07 + mode: Digital input + user_label: PC07 + configuration: null + PB24: + name: PB24 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB24 + mode: Peripheral IO + user_label: PB24 + configuration: null + PB25: + name: PB25 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB25 + mode: Peripheral IO + user_label: PB25 + configuration: null + PB26: + name: PB26 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB26 + mode: Digital output + user_label: PB26 + configuration: null + PB27: + name: PB27 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB27 + mode: Digital output + user_label: PB27 + configuration: null + SPI_CS: + name: PB28 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB28 + mode: Digital output + user_label: SPI_CS + configuration: + pad_initial_level: High + PB29: + name: PB29 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB29 + mode: Digital input + user_label: PB29 + configuration: null +toolchain_options: [] +static_files: [] diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/A1335.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/A1335.c new file mode 100644 index 0000000..579d542 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/A1335.c @@ -0,0 +1,520 @@ +/* + * A1335.c + * + * Created: 24/07/2021 17:54:33 + * Author: Nick-XMG + */ +#include "A1335.h" + +//--- Normal Write Registers ---// +#define EWA (0x02U) // Extended Write Address +#define EWD (0x04U) // Extended Write Data +#define EWCS (0x08U) // Extended Write Control and Status +#define ERA (0x0AU) // Extended Read Address +#define ERCS (0x0CU) // Extended Read Control and Status +#define ERD (0x0EU) // Extended Read Data +#define CTRL (0x1EU) // Device control +#define ANG (0x20U) // Current angle and related data +#define STA (0x22U) // Device status +#define ERR (0x24U) // Device error status +#define XERR (0x26U) // Extended error status +#define TSEN (0x28U) // Temperature sensor data +#define FIELD (0x2AU) // Magnetic field strength +#define ERM (0x34U) // Device error status masking +#define XERM (0x36U) // Extended error status masking + +const uint32_t WRITE = 0x40; +const uint32_t READ = 0x00; +const uint32_t COMMAND_MASK = 0xC0; +const uint32_t ADDRESS_MASK = 0x3F; + +//--- Extended Write Registers ---// +#define ORATE (0xFFD0) // Output Rate +//--- Errors ---// +#define kNOERROR 0 +#define kPRIMARYREADERROR 1 +#define kEXTENDEDREADTIMEOUTERROR 2 +#define kPRIMARYWRITEERROR 3 +#define kEXTENDEDWRITETIMEOUTERROR 4 +#define kCRCERROR 5 +#define kUNABLETOCHANGEPROCESSORSTATE 6 + +bool debugPrint = true; + +struct SPI_A1335 A1 = { + .SPI_descr = NULL, + .io_descr = NULL, + .state = 0, + .SS_pin = Angle_SS, + .tx_buffer = NULL, + .rx_buffer = NULL, + +}; + +void a1335_init(struct spi_m_sync_descriptor *spi, struct SPI_A1335 *Sn) +{ + Sn->SPI_descr = spi; + // Set Mode 3 : CPOL = 1; CPHA = 1; + hri_sercomspi_write_CTRLA_CPOL_bit(spi->dev.prvt, true); + hri_sercomspi_write_CTRLA_CPHA_bit(spi->dev.prvt, true); + //Get IO descriptor + spi_m_sync_get_io_descriptor(Sn->SPI_descr, &Sn->io_descr); + spi_m_sync_enable(Sn->SPI_descr); + gpio_set_pin_level(Sn->SS_pin, true); + if(Sn->io_descr == NULL || Sn->SPI_descr == NULL) + { + Sn->state = 4; + } else { + Sn->state = 1; + } +} + +void a1335_State_Machine(struct SPI_A1335 *Sn) +{ + volatile uint16_t angle; + switch(Sn->state){ + case 0: // Default un-initialized State + break; + case 1: // State After angleSensor_init. Configure Sensor + Sn->state++; + break; + case 2: // Synchronous blocking read + a1335_getRotationInDegrees(Sn); + break; + case 3: // Continuously Read Angle (DMA) + break; + case 4: // Error State + break; + } +} + +/* + * getRawRotation + * + * Read Raw Angle Register Value + */ +uint16_t a1335_getRawRotation(struct SPI_A1335 *Sn) +{ + uint16_t rawAngle; + PrimaryRead(Sn, ANG, &rawAngle); + return rawAngle; +} + +/* + * getRotationInDegrees + * + * Read angle register and return angle in Degrees + */ +float a1335_getRotationInDegrees(struct SPI_A1335 *Sn) +{ + uint16_t rawAngle = a1335_getRawRotation(Sn); + float angleDegrees; + if (CalculateParity(rawAngle)) + { + angleDegrees = (float)(rawAngle & 0x0FFF) * 360.0 / 4096.0; + if (debugPrint) + { + printf("Angle = "); + printf("%f", angleDegrees); + printf(" Degrees\n\r"); + } + } + else + { + printf("Parity error on Angle read\n\r"); + } + return angleDegrees; +} + +/* + * CalculateParity + * + * From the 16 bit input, calculate the parity + */ +bool CalculateParity(uint16_t input) +{ + uint16_t count = 0; + + // Count up the number of 1s in the input + for (int index = 0; index < 16; ++index) + { + if ((input & 1) == 1) + { + ++count; + } + + input >>= 1; + } + + // return true if there is an odd number of 1s + return (count & 1) != 0; +} + +/* + * CalculateCRC + * + * Take the 16bit input and generate a 4bit CRC + * Polynomial = x^4 + x^1 + 1 + * LFSR preset to all 1's + */ +uint8_t CalculateCRC(uint16_t input) +{ + bool CRC0 = true; + bool CRC1 = true; + bool CRC2 = true; + bool CRC3 = true; + int i; + bool DoInvert; + uint16_t mask = 0x8000; + + for (i = 0; i < 16; ++i) + { + DoInvert = ((input & mask) != 0) ^ CRC3; // XOR required? + + CRC3 = CRC2; + CRC2 = CRC1; + CRC1 = CRC0 ^ DoInvert; + CRC0 = DoInvert; + mask >>= 1; + } + + return (CRC3 ? 8U : 0U) + (CRC2 ? 4U : 0U) + (CRC1 ? 2U : 0U) + (CRC0 ? 1U : 0U); +} + +/* + * PrimaryRead + * + * Read from the primary serial registers + */ +uint16_t PrimaryRead(struct SPI_A1335 *Sn, uint16_t address, uint16_t* value) +{ + + uint8_t in_buf[2], out_buf[2]; + uint16_t returnedVal; + + uint16_t command = ((address & ADDRESS_MASK) | READ) << 8; + //Split the command into two bytes + out_buf[1] = command & 0xFF; + out_buf[0] = ( command >> 8 ) & 0xFF; + gpio_set_pin_level(Sn->SS_pin, false); + a1335_transfer16(Sn, command); + gpio_set_pin_level(Sn->SS_pin, true); + + /* Send again to Get Response */ + gpio_set_pin_level(Sn->SS_pin, false); + returnedVal = a1335_transfer16(Sn, command); + gpio_set_pin_level(Sn->SS_pin, true); + +// printf("In_buff= "); +// /* Print Received data by SPI Master from SPI Slave on Console */ +// for (int i = 0; i < 2; i++) { +// printf("%u", in_buf[i]); +// } +// printf("\n\r"); *value = returnedVal; + + + if(debugPrint) { + printf("Returned val = %u \n\r", returnedVal); + } + + + return kNOERROR; +} + +uint16_t a1335_transfer16(struct SPI_A1335 *Sn, uint16_t value) +{ + uint8_t in_buf[2], out_buf[2]; + uint16_t wordRead; + + out_buf[1] = value & 0xFF; + out_buf[0] = ( value >> 8 ) & 0xFF; + struct spi_xfer xfer; + xfer.rxbuf = in_buf; + xfer.txbuf = (uint8_t *)out_buf; + xfer.size = 2; + spi_m_sync_transfer(Sn->SPI_descr, &xfer); + wordRead = (uint16_t)((in_buf[0] << 8) | in_buf[1]); + return wordRead; +} + +/* + * PrimaryWrite + * + * Write to the primary serial registers + */ +uint16_t PrimaryWrite(uint16_t cs, uint16_t address, uint16_t value) +{ + //if (includeCRC) + //{ + //SPI.beginTransaction(SPISettings(1000000, MSBFIRST, SPI_MODE3)); +// + //// On the Teensy, SPI0_CTAR0 is used to describe the SPI transaction for transfer + //// while SPI0_CTAR1 is used to describe the SPI transaction for transfer16. + //// To do a 20 bit transfer, change the length of the transaction to 4 bits for transfer + //// and do a transfer16 followed by a transfer. + ////uint32_t oldSPI0_CTAR0 = SPI0_CTAR0; + //// SPI0_CTAR0 = (SPI0_CTAR0 & 0x87FFFFFF) | SPI_CTAR_FMSZ(3); // using SPI0_CTAR0 to send 4 bits +// + //// Combine the register address and the command into one byte + //uint16_t command = (((address & ADDRESS_MASK) | WRITE) << 8) | ((value >> 8) & 0x0FF); + //uint8_t crcCommand = CalculateCRC(command); +// + //// take the chip select low to select the device: + //digitalWrite(cs, LOW); +// + //SPI.transfer16(command); // Send most significant byte of register data + //SPI.transfer(crcCommand); // Send the crc +// + //// take the chip select high to de-select: + //digitalWrite(cs, HIGH); +// + //command = ((((address + 1) & ADDRESS_MASK) | WRITE) << 8 ) | (value & 0x0FF); + //crcCommand = CalculateCRC(command); +// + //// take the chip select low to select the device: + //digitalWrite(cs, LOW); +// + //SPI.transfer16(command); // Send least significant byte of register data + //SPI.transfer(crcCommand); // Send the crc +// + //// take the chip select high to de-select: + //digitalWrite(cs, HIGH); +// + //// Restore the 8 bit description + ////SPI0_CTAR0 = oldSPI0_CTAR0; +// + //SPI.endTransaction(); + //} + //else + //{ + //SPI.beginTransaction(SPISettings(1000000, MSBFIRST, SPI_MODE3)); +// + //// Combine the register address and the command into one byte + //uint16_t command = ((address & ADDRESS_MASK) | WRITE) << 8; +// + //// take the chip select low to select the device: + //digitalWrite(cs, LOW); +// + //SPI.transfer16(command | ((value >> 8) & 0x0FF)); // Send most significant byte of register data +// + //// take the chip select high to de-select: + //digitalWrite(cs, HIGH); +// + //command = (((address + 1) & ADDRESS_MASK) | WRITE) << 8; + //// take the chip select low to select the device: + //digitalWrite(cs, LOW); +// + //SPI.transfer16(command | (value & 0x0FF)); // Send least significant byte of register data +// + //// take the chip select high to de-select: + //digitalWrite(cs, HIGH); +// + //SPI.endTransaction(); + //} + + return kNOERROR; +} + +/* + * ExtendedRead + * + * Read from the SRAM, EEPROM, AUX or Extended Registers + */ +uint16_t ExtendedRead(uint16_t cs, uint16_t address, uint32_t value) +{ + //uint16_t results; + //uint16_t readFlags; + //uint32_t timeout; + //uint16_t valueMSW; + //uint16_t valueLSW; + //uint32_t currentTime; +// + //// Write the address to the Extended Read Address register + //results = PrimaryWrite(cs, 0x0A, address & 0xFFFF); +// + //if (results != kNOERROR) + //{ + //return results; + //} +// + //// Initiate the extended read + //results = PrimaryWrite(cs, 0x0C, 0x8000); + // + //if (results != kNOERROR) + //{ + //return results; + //} +// + //timeout = millis() + 100L; +// + //do // Wait for the read to be complete + //{ + //results = PrimaryRead(cs, 0x0C, readFlags); + // + //if (results != kNOERROR) + //{ + //return results; + //} +// + //// Make sure the read is not taking too long + //currentTime = millis(); + //if (timeout < currentTime) + //{ + //return kEXTENDEDREADTIMEOUTERROR; + //} + //} while ((readFlags & 0x0001) != 0x0001); + // + //// Read the most significant word from the extended read data + //results = PrimaryRead(cs, 0x0E, valueMSW); +// + //if (results != kNOERROR) + //{ + //return results; + //} +// + //// Read the least significant word from the extended read data + //results = PrimaryRead(cs, 0x10, valueLSW); +// + //// Combine them + //value = ((uint32_t)valueMSW << 16) + valueLSW; +// + //return results; +} + +/* + * ExtendedWrite + * + * Write to the SRAM, EEPROM, AUX or Extended Access Commands + */ +uint16_t ExtendedWrite(uint16_t cs, uint16_t address, uint32_t value) +{ + //uint16_t results; + //uint16_t writeFlags; + //uint32_t timeout; +// + //// Write into the extended address register + //results = PrimaryWrite(cs, 0x02, address & 0xFFFF); + // + //if (results != kNOERROR) + //{ + //return results; + //} +// + //// Write the MSW (Most significant word) into the high order write data register + //results = PrimaryWrite(cs, 0x04, (value >> 16) & 0xFFFF); + // + //if (results != kNOERROR) + //{ + //return results; + //} +// + //// Write the LSW (Least significant word) into the low order write data register + //results = PrimaryWrite(cs, 0x06, value & 0xFFFF); + // + //if (results != kNOERROR) + //{ + //return results; + //} +// + //// Start the write process + //results = PrimaryWrite(cs, 0x08, 0x8000); + // + //if (results != kNOERROR) + //{ + //return results; + //} +// + //// If writing to the EEPROM, generate the Program + //// Pulses on Vcc + //if ((address >= 0x300) && (address < 0x320)) + //{ + //// Send the Program Pulses + //// Need hardware which this example does not have. + //} +// + //timeout = millis() + 100; +// + //// Wait for the write to complete + //do + //{ + //results = PrimaryRead(cs, 0x08, writeFlags); + // + //if (results != kNOERROR) + //{ + //return results; + //} +// + //if (timeout < millis()) + //{ + //return kEXTENDEDWRITETIMEOUTERROR; + //} + //} while ((writeFlags & 0x0001) != 0x0001); +// + //return results; +} + +/* + * SetProcessorStateToIdle + * + * Change the processor state to idle + * This is needed to write EEPROM, change ORATE or perform certain self tests + */ +uint16_t SetProcessorStateToIdle(uint8_t cs) +{ + //uint16_t results; + //uint16_t value; + // + //// Write the enter idle state command into the control register + //results = PrimaryWrite(cs, 0x1F, 0x8046); + // + //if (results == kNOERROR) + //{ + //delay(1); +// + //// Read the status register to see if the processor is in the idle state + //results = PrimaryRead(cs, 0x22, value); + // + //if (results == kNOERROR) + //{ + //if ((value & 0x00FF) != 0x0010) + //{ + //return kUNABLETOCHANGEPROCESSORSTATE; + //} + //} + //} + // + //return results; +} + +/* + * SetProcessorStateToRun + * + * Change the processor state to run + * This is needed to process angles + */ +uint16_t SetProcessorStateToRun(uint8_t cs) +{ + //uint16_t results; + //uint16_t value; + // + //// Write the enter idle state command into the control register + //results = PrimaryWrite(cs, 0x1F, 0xC046); + // + //if (results == kNOERROR) + //{ + //delay(1); +// + //// Read the status register to see if the processor is in the idle state + //results = PrimaryRead(cs, 0x22, value); + // + //if (results == kNOERROR) + //{ + //if ((value & 0x00FF) != 0x0011) + //{ + //return kUNABLETOCHANGEPROCESSORSTATE; + //} + //} + //} + // + //return results; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/A1335.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/A1335.h new file mode 100644 index 0000000..043c609 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/A1335.h @@ -0,0 +1,45 @@ +/* + * A1335.h + * + * Created: 24/07/2021 17:53:53 + * Author: Nick-XMG + */ + + +#ifndef A1335_H_ +#define A1335_H_ +#include + +struct SPI_A1335 { + struct spi_m_sync_descriptor *SPI_descr; + struct io_descriptor *io_descr; + uint8_t state; + uint32_t SS_pin; + struct spi_xfer xfer; + uint8_t *tx_buffer; + uint8_t *rx_buffer; +}; + +struct SPI_A1335 A1; +struct io_descriptor *io; + +void a1335_init(struct spi_m_sync_descriptor *spi, struct SPI_A1335 *Sn); +void a1335_State_Machine(struct SPI_A1335 *Sn); + +uint16_t PrimaryRead(struct SPI_A1335 *Sn, uint16_t address, uint16_t* value); +uint16_t PrimaryWrite(uint16_t cs, uint16_t address, uint16_t value); +uint16_t ExtendedRead(uint16_t cs, uint16_t address, uint32_t value); +uint16_t ExtendedWrite(uint16_t cs, uint16_t address, uint32_t value); +uint16_t SetProcessorStateToRun(uint8_t cs); +uint16_t SetProcessorStateToIdle(uint8_t cs); +uint16_t SetProcessorStateToRun(uint8_t cs); +bool CalculateParity(uint16_t input); +uint8_t CalculateCRC(uint16_t input); +uint16_t a1335_transfer16(struct SPI_A1335 *Sn, uint16_t value); + +uint16_t a1335_getRawRotation(struct SPI_A1335 *Sn); +float a1335_getRotationInDegrees(struct SPI_A1335 *Sn); +uint16_t getErrors(void); + + +#endif /* A1335_H_ */ \ No newline at end of file diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/AS5048.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/AS5048.c new file mode 100644 index 0000000..4e04fd4 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/AS5048.c @@ -0,0 +1,186 @@ +/* + * AS5048.c + * + * Created: 27/07/2021 16:13:20 + * Author: Nick-XMG + */ + +#include "AS5048.h" + +#define AS5048A_CMD_NOP (0x0000) +#define AS5048A_READ (0x4000) +#define AS5048A_CLEAR_ERROR_FLAG (0x0001) +#define AS5048A_PROGRAMMING_CONTROL (0x0003) +#define AS5048A_OTP_REGISTER_ZERO_POS_HIGH (0x0016) +#define AS5048A_OTP_REGISTER_ZERO_POS_LOW (0x0017) +#define AS5048A_DIAG_AGC (0x3FFD) +#define AS5048A_MAGNITUDE (0x3FFE) +#define AS5048A_ANGLE (0x3FFF) + + +#define AS5048A_MAX_VALUE (8191.0f) + +static bool debugPrint = true; + +struct SPI_AS5048 AS_1 = { + .SPI_descr = NULL, + .io_descr = NULL, + .flags = 0, + .state = 0, + .SS_pin = Angle_SS, + .tx_buffer = NULL, + .rx_buffer = NULL, + +}; + +void as5048a_State_Machine(struct SPI_AS5048 *Sn) +{ + volatile uint16_t angle; + switch(Sn->state) { + case 0: // Default un-initialized State + break; + case 1: // State After angleSensor_init. Configure Sensor + Sn->state++; + break; + case 2: // Synchronous blocking read + as5048a_getRotationInDegrees(Sn); + break; + case 3: // Continuously Read Angle (DMA) + break; + case 4: // Error State + break; + } +} + +void as5048a_init(struct spi_m_sync_descriptor *spi, struct SPI_AS5048 *Sn) +{ + Sn->SPI_descr = spi; + spi_m_sync_disable(&SPI_1); + + // Set Mode 1 : CPOL = 0; CPHA = 1; + hri_sercomspi_write_CTRLA_CPOL_bit(&SPI_1, false); + hri_sercomspi_write_CTRLA_CPHA_bit(&SPI_1, true); + + //Get IO descriptor + spi_m_sync_get_io_descriptor(Sn->SPI_descr, &Sn->io_descr); + spi_m_sync_enable(&SPI_1); + gpio_set_pin_level(Sn->SS_pin, true); + if(Sn->io_descr == NULL || Sn->SPI_descr == NULL) { + Sn->state = 4; + } else { + Sn->state = 1; + } +} + +uint16_t as5048a_read(struct SPI_AS5048 *Sn, uint16_t address) +{ + uint8_t in_buf[2], out_buf[2]; + uint16_t returnedVal; + + volatile uint16_t command = 0b0100000000000000; // PAR=0 R/W=R + command = command | address; + + //Add a parity bit on the the MSB + command |= ((uint16_t)as5048a_CalcEvenParity(command)<<15); + + //Split the command into two bytes + out_buf[1] = command & 0xFF; + out_buf[0] = ( command >> 8 ) & 0xFF; + + /* Send Command */ + gpio_set_pin_level(Sn->SS_pin, false); + as5048a_transfer16(Sn, command); + gpio_set_pin_level(Sn->SS_pin, true); + + /* Send again to Get Response */ + gpio_set_pin_level(Sn->SS_pin, false); + returnedVal = as5048a_transfer16(Sn, command); + gpio_set_pin_level(Sn->SS_pin, true); + + // printf("In_buff= "); + // /* Print Received data by SPI Master from SPI Slave on Console */ + // for (int i = 0; i < 2; i++) { + // printf("%u", in_buf[i]); + // } + // printf("\n\r"); if(debugPrint) { + printf("Returned val = %u \n\r", returnedVal); + } + + + if (returnedVal & 0x4000) { + Sn->flags = 1; + } else { + Sn->flags = 0; + } + + //Return the data, stripping the parity and error bits + return (( ( in_buf[1] & 0xFF ) << 8 ) | ( in_buf[0] & 0xFF )) & ~0xC000; +} + +/* + * getRawRotation + * + * Read Raw Angle Register Value + */ +uint16_t as5048a_getRawRotation(struct SPI_AS5048 *Sn) +{ + volatile uint16_t rawAngle = as5048a_read(Sn, AS5048A_ANGLE); + return rawAngle; +} + +int16_t as5048a_getRotation(struct SPI_AS5048 *Sn) +{ + uint16_t data; + int16_t rotation; + + data = as5048a_getRawRotation(Sn); + rotation = (int16_t)(data); //- static_cast(this->position); + if (rotation > AS5048A_MAX_VALUE) { + rotation = -((0x3FFF) - rotation); //more than -180 + } + + return rotation; + +} + +/* +* getRotationInDegrees +* +* Read angle register and return angle in Degrees +*/ +float as5048a_getRotationInDegrees(struct SPI_AS5048 *Sn) +{ + uint16_t rawAngle = as5048a_getRotation(Sn); + float angleDegrees = 360.0 * (rawAngle + AS5048A_MAX_VALUE) / (AS5048A_MAX_VALUE * 2.0);; + + return angleDegrees; +} + + +uint16_t as5048a_transfer16(struct SPI_AS5048 *Sn, uint16_t value) +{ + uint8_t in_buf[2], out_buf[2]; + uint16_t wordRead; + + out_buf[1] = value & 0xFF; + out_buf[0] = ( value >> 8 ) & 0xFF; + struct spi_xfer xfer; + xfer.rxbuf = in_buf; + xfer.txbuf = (uint8_t *)out_buf; + xfer.size = 2; + spi_m_sync_transfer(Sn->SPI_descr, &xfer); + wordRead = (uint16_t)((in_buf[0] << 8) | in_buf[1]); + return wordRead; +} + +uint8_t as5048a_CalcEvenParity(uint16_t value) { + uint8_t cnt = 0; + uint8_t i; + for (i = 0; i < 16; i++) { + if (value & 0x1) { + cnt++; + } + value >>= 1; + } + return cnt & 0x1; +} \ No newline at end of file diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/AS5048.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/AS5048.h new file mode 100644 index 0000000..533d944 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/AS5048.h @@ -0,0 +1,38 @@ +/* + * AS5048.h + * + * Created: 27/07/2021 16:12:53 + * Author: Nick-XMG + */ + +#ifndef AS5048_H_ +#define AS5048_H_ +#include + + +struct SPI_AS5048 { + struct spi_m_sync_descriptor *SPI_descr; + struct io_descriptor *io_descr; + uint8_t state; + uint8_t flags; + uint32_t SS_pin; + uint8_t *tx_buffer; + uint8_t *rx_buffer; +}; + +struct SPI_AS5048 AS_1; + +void as5048a_init(struct spi_m_sync_descriptor *spi, struct SPI_AS5048 *Sn); +void as5048a_State_Machine(struct SPI_AS5048 *Sn); +// +///* Sensor Specific Read Functions */ +uint16_t as5048a_read(struct SPI_AS5048 *Sn, uint16_t address); +uint16_t as5048a_getRawRotation(struct SPI_AS5048 *Sn); +int16_t as5048a_getRotation(struct SPI_AS5048 *Sn); +float as5048a_getRotationInDegrees(struct SPI_AS5048 *Sn); +// +///* Support Functions */ +uint16_t as5048a_transfer16(struct SPI_AS5048 *Sn, uint16_t value); +uint8_t as5048a_CalcEvenParity(uint16_t value); + +#endif /* AS5048_H_ */ \ No newline at end of file diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/RTE_Components.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/RTE_Components.h new file mode 100644 index 0000000..9e09382 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/RTE_Components.h @@ -0,0 +1,54 @@ + /** + * \file + * + * \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME) + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \acme_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \acme_license_stop + * + * Project: Master_Slave_IF_TestMaster + * Target: ATSAME54P20A + * + **/ + + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +#define ATMEL_START + +#endif /* RTE_COMPONENTS_H */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_cmcc_config.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_cmcc_config.h new file mode 100644 index 0000000..8590736 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_cmcc_config.h @@ -0,0 +1,54 @@ +/* Auto-generated config file hpl_cmcc_config.h */ +#ifndef HPL_CMCC_CONFIG_H +#define HPL_CMCC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Configuration + +// Cache enable +// Defines the cache should be enabled or not. +// cmcc_enable +#ifndef CONF_CMCC_ENABLE +#define CONF_CMCC_ENABLE 0x0 +#endif + +// Cache Size +// Defines the cache memory size to be configured. +// <0x0=>1 KB +// <0x1=>2 KB +// <0x2=>4 KB +// cache_size +#ifndef CONF_CMCC_CACHE_SIZE +#define CONF_CMCC_CACHE_SIZE 0x2 +#endif + +// Advanced Configuration +// cmcc_advanced_configuration +// Data cache disable +// Defines the data cache should be disabled or not. +// cmcc_data_cache_disable +#ifndef CONF_CMCC_DATA_CACHE_DISABLE +#define CONF_CMCC_DATA_CACHE_DISABLE 0x0 +#endif + +// Instruction cache disable +// Defines the Instruction cache should be disabled or not. +// cmcc_inst_cache_disable +#ifndef CONF_CMCC_INST_CACHE_DISABLE +#define CONF_CMCC_INST_CACHE_DISABLE 0x0 +#endif + +// Clock Gating disable +// Defines the clock gating should be disabled or not. +// cmcc_clock_gating_disable +#ifndef CONF_CMCC_CLK_GATING_DISABLE +#define CONF_CMCC_CLK_GATING_DISABLE 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_CMCC_CONFIG_H diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_dmac_config.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_dmac_config.h new file mode 100644 index 0000000..a09dbe3 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_dmac_config.h @@ -0,0 +1,7277 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 1 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 1 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 1 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 1 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 1 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 0 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 0 is running in standby mode or not +// dmac_runstdby_0 +#ifndef CONF_DMAC_RUNSTDBY_0 +#define CONF_DMAC_RUNSTDBY_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 1 is running in standby mode or not +// dmac_runstdby_1 +#ifndef CONF_DMAC_RUNSTDBY_1 +#define CONF_DMAC_RUNSTDBY_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 1 +#endif + +// Channel Run in Standby +// Indicates whether channel 2 is running in standby mode or not +// dmac_runstdby_2 +#ifndef CONF_DMAC_RUNSTDBY_2 +#define CONF_DMAC_RUNSTDBY_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 2 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 13 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 1 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 1 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 1 +#endif + +// Channel Run in Standby +// Indicates whether channel 3 is running in standby mode or not +// dmac_runstdby_3 +#ifndef CONF_DMAC_RUNSTDBY_3 +#define CONF_DMAC_RUNSTDBY_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 2 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 12 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 1 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 4 is running in standby mode or not +// dmac_runstdby_4 +#ifndef CONF_DMAC_RUNSTDBY_4 +#define CONF_DMAC_RUNSTDBY_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 5 is running in standby mode or not +// dmac_runstdby_5 +#ifndef CONF_DMAC_RUNSTDBY_5 +#define CONF_DMAC_RUNSTDBY_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 6 is running in standby mode or not +// dmac_runstdby_6 +#ifndef CONF_DMAC_RUNSTDBY_6 +#define CONF_DMAC_RUNSTDBY_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 7 is running in standby mode or not +// dmac_runstdby_7 +#ifndef CONF_DMAC_RUNSTDBY_7 +#define CONF_DMAC_RUNSTDBY_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 8 is running in standby mode or not +// dmac_runstdby_8 +#ifndef CONF_DMAC_RUNSTDBY_8 +#define CONF_DMAC_RUNSTDBY_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 9 is running in standby mode or not +// dmac_runstdby_9 +#ifndef CONF_DMAC_RUNSTDBY_9 +#define CONF_DMAC_RUNSTDBY_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 10 is running in standby mode or not +// dmac_runstdby_10 +#ifndef CONF_DMAC_RUNSTDBY_10 +#define CONF_DMAC_RUNSTDBY_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 11 is running in standby mode or not +// dmac_runstdby_11 +#ifndef CONF_DMAC_RUNSTDBY_11 +#define CONF_DMAC_RUNSTDBY_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 12 is running in standby mode or not +// dmac_runstdby_12 +#ifndef CONF_DMAC_RUNSTDBY_12 +#define CONF_DMAC_RUNSTDBY_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 13 is running in standby mode or not +// dmac_runstdby_13 +#ifndef CONF_DMAC_RUNSTDBY_13 +#define CONF_DMAC_RUNSTDBY_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 14 is running in standby mode or not +// dmac_runstdby_14 +#ifndef CONF_DMAC_RUNSTDBY_14 +#define CONF_DMAC_RUNSTDBY_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 15 is running in standby mode or not +// dmac_runstdby_15 +#ifndef CONF_DMAC_RUNSTDBY_15 +#define CONF_DMAC_RUNSTDBY_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// Channel 16 settings +// dmac_channel_16_settings +#ifndef CONF_DMAC_CHANNEL_16_SETTINGS +#define CONF_DMAC_CHANNEL_16_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 16 is running in standby mode or not +// dmac_runstdby_16 +#ifndef CONF_DMAC_RUNSTDBY_16 +#define CONF_DMAC_RUNSTDBY_16 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_16 +#ifndef CONF_DMAC_TRIGACT_16 +#define CONF_DMAC_TRIGACT_16 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_16 +#ifndef CONF_DMAC_TRIGSRC_16 +#define CONF_DMAC_TRIGSRC_16 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_16 +#ifndef CONF_DMAC_LVL_16 +#define CONF_DMAC_LVL_16 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_16 +#ifndef CONF_DMAC_EVOE_16 +#define CONF_DMAC_EVOE_16 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_16 +#ifndef CONF_DMAC_EVIE_16 +#define CONF_DMAC_EVIE_16 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_16 +#ifndef CONF_DMAC_EVACT_16 +#define CONF_DMAC_EVACT_16 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_16 +#ifndef CONF_DMAC_STEPSIZE_16 +#define CONF_DMAC_STEPSIZE_16 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_16 +#ifndef CONF_DMAC_STEPSEL_16 +#define CONF_DMAC_STEPSEL_16 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_16 +#ifndef CONF_DMAC_SRCINC_16 +#define CONF_DMAC_SRCINC_16 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_16 +#ifndef CONF_DMAC_DSTINC_16 +#define CONF_DMAC_DSTINC_16 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_16 +#ifndef CONF_DMAC_BEATSIZE_16 +#define CONF_DMAC_BEATSIZE_16 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_16 +#ifndef CONF_DMAC_BLOCKACT_16 +#define CONF_DMAC_BLOCKACT_16 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_16 +#ifndef CONF_DMAC_EVOSEL_16 +#define CONF_DMAC_EVOSEL_16 0 +#endif +// + +// Channel 17 settings +// dmac_channel_17_settings +#ifndef CONF_DMAC_CHANNEL_17_SETTINGS +#define CONF_DMAC_CHANNEL_17_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 17 is running in standby mode or not +// dmac_runstdby_17 +#ifndef CONF_DMAC_RUNSTDBY_17 +#define CONF_DMAC_RUNSTDBY_17 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_17 +#ifndef CONF_DMAC_TRIGACT_17 +#define CONF_DMAC_TRIGACT_17 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_17 +#ifndef CONF_DMAC_TRIGSRC_17 +#define CONF_DMAC_TRIGSRC_17 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_17 +#ifndef CONF_DMAC_LVL_17 +#define CONF_DMAC_LVL_17 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_17 +#ifndef CONF_DMAC_EVOE_17 +#define CONF_DMAC_EVOE_17 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_17 +#ifndef CONF_DMAC_EVIE_17 +#define CONF_DMAC_EVIE_17 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_17 +#ifndef CONF_DMAC_EVACT_17 +#define CONF_DMAC_EVACT_17 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_17 +#ifndef CONF_DMAC_STEPSIZE_17 +#define CONF_DMAC_STEPSIZE_17 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_17 +#ifndef CONF_DMAC_STEPSEL_17 +#define CONF_DMAC_STEPSEL_17 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_17 +#ifndef CONF_DMAC_SRCINC_17 +#define CONF_DMAC_SRCINC_17 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_17 +#ifndef CONF_DMAC_DSTINC_17 +#define CONF_DMAC_DSTINC_17 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_17 +#ifndef CONF_DMAC_BEATSIZE_17 +#define CONF_DMAC_BEATSIZE_17 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_17 +#ifndef CONF_DMAC_BLOCKACT_17 +#define CONF_DMAC_BLOCKACT_17 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_17 +#ifndef CONF_DMAC_EVOSEL_17 +#define CONF_DMAC_EVOSEL_17 0 +#endif +// + +// Channel 18 settings +// dmac_channel_18_settings +#ifndef CONF_DMAC_CHANNEL_18_SETTINGS +#define CONF_DMAC_CHANNEL_18_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 18 is running in standby mode or not +// dmac_runstdby_18 +#ifndef CONF_DMAC_RUNSTDBY_18 +#define CONF_DMAC_RUNSTDBY_18 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_18 +#ifndef CONF_DMAC_TRIGACT_18 +#define CONF_DMAC_TRIGACT_18 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_18 +#ifndef CONF_DMAC_TRIGSRC_18 +#define CONF_DMAC_TRIGSRC_18 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_18 +#ifndef CONF_DMAC_LVL_18 +#define CONF_DMAC_LVL_18 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_18 +#ifndef CONF_DMAC_EVOE_18 +#define CONF_DMAC_EVOE_18 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_18 +#ifndef CONF_DMAC_EVIE_18 +#define CONF_DMAC_EVIE_18 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_18 +#ifndef CONF_DMAC_EVACT_18 +#define CONF_DMAC_EVACT_18 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_18 +#ifndef CONF_DMAC_STEPSIZE_18 +#define CONF_DMAC_STEPSIZE_18 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_18 +#ifndef CONF_DMAC_STEPSEL_18 +#define CONF_DMAC_STEPSEL_18 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_18 +#ifndef CONF_DMAC_SRCINC_18 +#define CONF_DMAC_SRCINC_18 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_18 +#ifndef CONF_DMAC_DSTINC_18 +#define CONF_DMAC_DSTINC_18 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_18 +#ifndef CONF_DMAC_BEATSIZE_18 +#define CONF_DMAC_BEATSIZE_18 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_18 +#ifndef CONF_DMAC_BLOCKACT_18 +#define CONF_DMAC_BLOCKACT_18 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_18 +#ifndef CONF_DMAC_EVOSEL_18 +#define CONF_DMAC_EVOSEL_18 0 +#endif +// + +// Channel 19 settings +// dmac_channel_19_settings +#ifndef CONF_DMAC_CHANNEL_19_SETTINGS +#define CONF_DMAC_CHANNEL_19_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 19 is running in standby mode or not +// dmac_runstdby_19 +#ifndef CONF_DMAC_RUNSTDBY_19 +#define CONF_DMAC_RUNSTDBY_19 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_19 +#ifndef CONF_DMAC_TRIGACT_19 +#define CONF_DMAC_TRIGACT_19 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_19 +#ifndef CONF_DMAC_TRIGSRC_19 +#define CONF_DMAC_TRIGSRC_19 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_19 +#ifndef CONF_DMAC_LVL_19 +#define CONF_DMAC_LVL_19 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_19 +#ifndef CONF_DMAC_EVOE_19 +#define CONF_DMAC_EVOE_19 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_19 +#ifndef CONF_DMAC_EVIE_19 +#define CONF_DMAC_EVIE_19 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_19 +#ifndef CONF_DMAC_EVACT_19 +#define CONF_DMAC_EVACT_19 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_19 +#ifndef CONF_DMAC_STEPSIZE_19 +#define CONF_DMAC_STEPSIZE_19 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_19 +#ifndef CONF_DMAC_STEPSEL_19 +#define CONF_DMAC_STEPSEL_19 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_19 +#ifndef CONF_DMAC_SRCINC_19 +#define CONF_DMAC_SRCINC_19 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_19 +#ifndef CONF_DMAC_DSTINC_19 +#define CONF_DMAC_DSTINC_19 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_19 +#ifndef CONF_DMAC_BEATSIZE_19 +#define CONF_DMAC_BEATSIZE_19 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_19 +#ifndef CONF_DMAC_BLOCKACT_19 +#define CONF_DMAC_BLOCKACT_19 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_19 +#ifndef CONF_DMAC_EVOSEL_19 +#define CONF_DMAC_EVOSEL_19 0 +#endif +// + +// Channel 20 settings +// dmac_channel_20_settings +#ifndef CONF_DMAC_CHANNEL_20_SETTINGS +#define CONF_DMAC_CHANNEL_20_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 20 is running in standby mode or not +// dmac_runstdby_20 +#ifndef CONF_DMAC_RUNSTDBY_20 +#define CONF_DMAC_RUNSTDBY_20 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_20 +#ifndef CONF_DMAC_TRIGACT_20 +#define CONF_DMAC_TRIGACT_20 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_20 +#ifndef CONF_DMAC_TRIGSRC_20 +#define CONF_DMAC_TRIGSRC_20 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_20 +#ifndef CONF_DMAC_LVL_20 +#define CONF_DMAC_LVL_20 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_20 +#ifndef CONF_DMAC_EVOE_20 +#define CONF_DMAC_EVOE_20 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_20 +#ifndef CONF_DMAC_EVIE_20 +#define CONF_DMAC_EVIE_20 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_20 +#ifndef CONF_DMAC_EVACT_20 +#define CONF_DMAC_EVACT_20 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_20 +#ifndef CONF_DMAC_STEPSIZE_20 +#define CONF_DMAC_STEPSIZE_20 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_20 +#ifndef CONF_DMAC_STEPSEL_20 +#define CONF_DMAC_STEPSEL_20 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_20 +#ifndef CONF_DMAC_SRCINC_20 +#define CONF_DMAC_SRCINC_20 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_20 +#ifndef CONF_DMAC_DSTINC_20 +#define CONF_DMAC_DSTINC_20 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_20 +#ifndef CONF_DMAC_BEATSIZE_20 +#define CONF_DMAC_BEATSIZE_20 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_20 +#ifndef CONF_DMAC_BLOCKACT_20 +#define CONF_DMAC_BLOCKACT_20 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_20 +#ifndef CONF_DMAC_EVOSEL_20 +#define CONF_DMAC_EVOSEL_20 0 +#endif +// + +// Channel 21 settings +// dmac_channel_21_settings +#ifndef CONF_DMAC_CHANNEL_21_SETTINGS +#define CONF_DMAC_CHANNEL_21_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 21 is running in standby mode or not +// dmac_runstdby_21 +#ifndef CONF_DMAC_RUNSTDBY_21 +#define CONF_DMAC_RUNSTDBY_21 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_21 +#ifndef CONF_DMAC_TRIGACT_21 +#define CONF_DMAC_TRIGACT_21 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_21 +#ifndef CONF_DMAC_TRIGSRC_21 +#define CONF_DMAC_TRIGSRC_21 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_21 +#ifndef CONF_DMAC_LVL_21 +#define CONF_DMAC_LVL_21 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_21 +#ifndef CONF_DMAC_EVOE_21 +#define CONF_DMAC_EVOE_21 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_21 +#ifndef CONF_DMAC_EVIE_21 +#define CONF_DMAC_EVIE_21 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_21 +#ifndef CONF_DMAC_EVACT_21 +#define CONF_DMAC_EVACT_21 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_21 +#ifndef CONF_DMAC_STEPSIZE_21 +#define CONF_DMAC_STEPSIZE_21 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_21 +#ifndef CONF_DMAC_STEPSEL_21 +#define CONF_DMAC_STEPSEL_21 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_21 +#ifndef CONF_DMAC_SRCINC_21 +#define CONF_DMAC_SRCINC_21 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_21 +#ifndef CONF_DMAC_DSTINC_21 +#define CONF_DMAC_DSTINC_21 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_21 +#ifndef CONF_DMAC_BEATSIZE_21 +#define CONF_DMAC_BEATSIZE_21 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_21 +#ifndef CONF_DMAC_BLOCKACT_21 +#define CONF_DMAC_BLOCKACT_21 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_21 +#ifndef CONF_DMAC_EVOSEL_21 +#define CONF_DMAC_EVOSEL_21 0 +#endif +// + +// Channel 22 settings +// dmac_channel_22_settings +#ifndef CONF_DMAC_CHANNEL_22_SETTINGS +#define CONF_DMAC_CHANNEL_22_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 22 is running in standby mode or not +// dmac_runstdby_22 +#ifndef CONF_DMAC_RUNSTDBY_22 +#define CONF_DMAC_RUNSTDBY_22 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_22 +#ifndef CONF_DMAC_TRIGACT_22 +#define CONF_DMAC_TRIGACT_22 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_22 +#ifndef CONF_DMAC_TRIGSRC_22 +#define CONF_DMAC_TRIGSRC_22 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_22 +#ifndef CONF_DMAC_LVL_22 +#define CONF_DMAC_LVL_22 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_22 +#ifndef CONF_DMAC_EVOE_22 +#define CONF_DMAC_EVOE_22 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_22 +#ifndef CONF_DMAC_EVIE_22 +#define CONF_DMAC_EVIE_22 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_22 +#ifndef CONF_DMAC_EVACT_22 +#define CONF_DMAC_EVACT_22 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_22 +#ifndef CONF_DMAC_STEPSIZE_22 +#define CONF_DMAC_STEPSIZE_22 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_22 +#ifndef CONF_DMAC_STEPSEL_22 +#define CONF_DMAC_STEPSEL_22 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_22 +#ifndef CONF_DMAC_SRCINC_22 +#define CONF_DMAC_SRCINC_22 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_22 +#ifndef CONF_DMAC_DSTINC_22 +#define CONF_DMAC_DSTINC_22 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_22 +#ifndef CONF_DMAC_BEATSIZE_22 +#define CONF_DMAC_BEATSIZE_22 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_22 +#ifndef CONF_DMAC_BLOCKACT_22 +#define CONF_DMAC_BLOCKACT_22 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_22 +#ifndef CONF_DMAC_EVOSEL_22 +#define CONF_DMAC_EVOSEL_22 0 +#endif +// + +// Channel 23 settings +// dmac_channel_23_settings +#ifndef CONF_DMAC_CHANNEL_23_SETTINGS +#define CONF_DMAC_CHANNEL_23_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 23 is running in standby mode or not +// dmac_runstdby_23 +#ifndef CONF_DMAC_RUNSTDBY_23 +#define CONF_DMAC_RUNSTDBY_23 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_23 +#ifndef CONF_DMAC_TRIGACT_23 +#define CONF_DMAC_TRIGACT_23 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_23 +#ifndef CONF_DMAC_TRIGSRC_23 +#define CONF_DMAC_TRIGSRC_23 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_23 +#ifndef CONF_DMAC_LVL_23 +#define CONF_DMAC_LVL_23 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_23 +#ifndef CONF_DMAC_EVOE_23 +#define CONF_DMAC_EVOE_23 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_23 +#ifndef CONF_DMAC_EVIE_23 +#define CONF_DMAC_EVIE_23 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_23 +#ifndef CONF_DMAC_EVACT_23 +#define CONF_DMAC_EVACT_23 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_23 +#ifndef CONF_DMAC_STEPSIZE_23 +#define CONF_DMAC_STEPSIZE_23 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_23 +#ifndef CONF_DMAC_STEPSEL_23 +#define CONF_DMAC_STEPSEL_23 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_23 +#ifndef CONF_DMAC_SRCINC_23 +#define CONF_DMAC_SRCINC_23 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_23 +#ifndef CONF_DMAC_DSTINC_23 +#define CONF_DMAC_DSTINC_23 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_23 +#ifndef CONF_DMAC_BEATSIZE_23 +#define CONF_DMAC_BEATSIZE_23 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_23 +#ifndef CONF_DMAC_BLOCKACT_23 +#define CONF_DMAC_BLOCKACT_23 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_23 +#ifndef CONF_DMAC_EVOSEL_23 +#define CONF_DMAC_EVOSEL_23 0 +#endif +// + +// Channel 24 settings +// dmac_channel_24_settings +#ifndef CONF_DMAC_CHANNEL_24_SETTINGS +#define CONF_DMAC_CHANNEL_24_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 24 is running in standby mode or not +// dmac_runstdby_24 +#ifndef CONF_DMAC_RUNSTDBY_24 +#define CONF_DMAC_RUNSTDBY_24 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_24 +#ifndef CONF_DMAC_TRIGACT_24 +#define CONF_DMAC_TRIGACT_24 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_24 +#ifndef CONF_DMAC_TRIGSRC_24 +#define CONF_DMAC_TRIGSRC_24 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_24 +#ifndef CONF_DMAC_LVL_24 +#define CONF_DMAC_LVL_24 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_24 +#ifndef CONF_DMAC_EVOE_24 +#define CONF_DMAC_EVOE_24 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_24 +#ifndef CONF_DMAC_EVIE_24 +#define CONF_DMAC_EVIE_24 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_24 +#ifndef CONF_DMAC_EVACT_24 +#define CONF_DMAC_EVACT_24 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_24 +#ifndef CONF_DMAC_STEPSIZE_24 +#define CONF_DMAC_STEPSIZE_24 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_24 +#ifndef CONF_DMAC_STEPSEL_24 +#define CONF_DMAC_STEPSEL_24 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_24 +#ifndef CONF_DMAC_SRCINC_24 +#define CONF_DMAC_SRCINC_24 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_24 +#ifndef CONF_DMAC_DSTINC_24 +#define CONF_DMAC_DSTINC_24 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_24 +#ifndef CONF_DMAC_BEATSIZE_24 +#define CONF_DMAC_BEATSIZE_24 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_24 +#ifndef CONF_DMAC_BLOCKACT_24 +#define CONF_DMAC_BLOCKACT_24 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_24 +#ifndef CONF_DMAC_EVOSEL_24 +#define CONF_DMAC_EVOSEL_24 0 +#endif +// + +// Channel 25 settings +// dmac_channel_25_settings +#ifndef CONF_DMAC_CHANNEL_25_SETTINGS +#define CONF_DMAC_CHANNEL_25_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 25 is running in standby mode or not +// dmac_runstdby_25 +#ifndef CONF_DMAC_RUNSTDBY_25 +#define CONF_DMAC_RUNSTDBY_25 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_25 +#ifndef CONF_DMAC_TRIGACT_25 +#define CONF_DMAC_TRIGACT_25 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_25 +#ifndef CONF_DMAC_TRIGSRC_25 +#define CONF_DMAC_TRIGSRC_25 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_25 +#ifndef CONF_DMAC_LVL_25 +#define CONF_DMAC_LVL_25 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_25 +#ifndef CONF_DMAC_EVOE_25 +#define CONF_DMAC_EVOE_25 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_25 +#ifndef CONF_DMAC_EVIE_25 +#define CONF_DMAC_EVIE_25 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_25 +#ifndef CONF_DMAC_EVACT_25 +#define CONF_DMAC_EVACT_25 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_25 +#ifndef CONF_DMAC_STEPSIZE_25 +#define CONF_DMAC_STEPSIZE_25 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_25 +#ifndef CONF_DMAC_STEPSEL_25 +#define CONF_DMAC_STEPSEL_25 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_25 +#ifndef CONF_DMAC_SRCINC_25 +#define CONF_DMAC_SRCINC_25 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_25 +#ifndef CONF_DMAC_DSTINC_25 +#define CONF_DMAC_DSTINC_25 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_25 +#ifndef CONF_DMAC_BEATSIZE_25 +#define CONF_DMAC_BEATSIZE_25 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_25 +#ifndef CONF_DMAC_BLOCKACT_25 +#define CONF_DMAC_BLOCKACT_25 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_25 +#ifndef CONF_DMAC_EVOSEL_25 +#define CONF_DMAC_EVOSEL_25 0 +#endif +// + +// Channel 26 settings +// dmac_channel_26_settings +#ifndef CONF_DMAC_CHANNEL_26_SETTINGS +#define CONF_DMAC_CHANNEL_26_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 26 is running in standby mode or not +// dmac_runstdby_26 +#ifndef CONF_DMAC_RUNSTDBY_26 +#define CONF_DMAC_RUNSTDBY_26 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_26 +#ifndef CONF_DMAC_TRIGACT_26 +#define CONF_DMAC_TRIGACT_26 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_26 +#ifndef CONF_DMAC_TRIGSRC_26 +#define CONF_DMAC_TRIGSRC_26 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_26 +#ifndef CONF_DMAC_LVL_26 +#define CONF_DMAC_LVL_26 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_26 +#ifndef CONF_DMAC_EVOE_26 +#define CONF_DMAC_EVOE_26 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_26 +#ifndef CONF_DMAC_EVIE_26 +#define CONF_DMAC_EVIE_26 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_26 +#ifndef CONF_DMAC_EVACT_26 +#define CONF_DMAC_EVACT_26 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_26 +#ifndef CONF_DMAC_STEPSIZE_26 +#define CONF_DMAC_STEPSIZE_26 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_26 +#ifndef CONF_DMAC_STEPSEL_26 +#define CONF_DMAC_STEPSEL_26 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_26 +#ifndef CONF_DMAC_SRCINC_26 +#define CONF_DMAC_SRCINC_26 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_26 +#ifndef CONF_DMAC_DSTINC_26 +#define CONF_DMAC_DSTINC_26 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_26 +#ifndef CONF_DMAC_BEATSIZE_26 +#define CONF_DMAC_BEATSIZE_26 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_26 +#ifndef CONF_DMAC_BLOCKACT_26 +#define CONF_DMAC_BLOCKACT_26 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_26 +#ifndef CONF_DMAC_EVOSEL_26 +#define CONF_DMAC_EVOSEL_26 0 +#endif +// + +// Channel 27 settings +// dmac_channel_27_settings +#ifndef CONF_DMAC_CHANNEL_27_SETTINGS +#define CONF_DMAC_CHANNEL_27_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 27 is running in standby mode or not +// dmac_runstdby_27 +#ifndef CONF_DMAC_RUNSTDBY_27 +#define CONF_DMAC_RUNSTDBY_27 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_27 +#ifndef CONF_DMAC_TRIGACT_27 +#define CONF_DMAC_TRIGACT_27 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_27 +#ifndef CONF_DMAC_TRIGSRC_27 +#define CONF_DMAC_TRIGSRC_27 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_27 +#ifndef CONF_DMAC_LVL_27 +#define CONF_DMAC_LVL_27 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_27 +#ifndef CONF_DMAC_EVOE_27 +#define CONF_DMAC_EVOE_27 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_27 +#ifndef CONF_DMAC_EVIE_27 +#define CONF_DMAC_EVIE_27 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_27 +#ifndef CONF_DMAC_EVACT_27 +#define CONF_DMAC_EVACT_27 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_27 +#ifndef CONF_DMAC_STEPSIZE_27 +#define CONF_DMAC_STEPSIZE_27 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_27 +#ifndef CONF_DMAC_STEPSEL_27 +#define CONF_DMAC_STEPSEL_27 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_27 +#ifndef CONF_DMAC_SRCINC_27 +#define CONF_DMAC_SRCINC_27 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_27 +#ifndef CONF_DMAC_DSTINC_27 +#define CONF_DMAC_DSTINC_27 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_27 +#ifndef CONF_DMAC_BEATSIZE_27 +#define CONF_DMAC_BEATSIZE_27 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_27 +#ifndef CONF_DMAC_BLOCKACT_27 +#define CONF_DMAC_BLOCKACT_27 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_27 +#ifndef CONF_DMAC_EVOSEL_27 +#define CONF_DMAC_EVOSEL_27 0 +#endif +// + +// Channel 28 settings +// dmac_channel_28_settings +#ifndef CONF_DMAC_CHANNEL_28_SETTINGS +#define CONF_DMAC_CHANNEL_28_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 28 is running in standby mode or not +// dmac_runstdby_28 +#ifndef CONF_DMAC_RUNSTDBY_28 +#define CONF_DMAC_RUNSTDBY_28 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_28 +#ifndef CONF_DMAC_TRIGACT_28 +#define CONF_DMAC_TRIGACT_28 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_28 +#ifndef CONF_DMAC_TRIGSRC_28 +#define CONF_DMAC_TRIGSRC_28 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_28 +#ifndef CONF_DMAC_LVL_28 +#define CONF_DMAC_LVL_28 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_28 +#ifndef CONF_DMAC_EVOE_28 +#define CONF_DMAC_EVOE_28 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_28 +#ifndef CONF_DMAC_EVIE_28 +#define CONF_DMAC_EVIE_28 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_28 +#ifndef CONF_DMAC_EVACT_28 +#define CONF_DMAC_EVACT_28 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_28 +#ifndef CONF_DMAC_STEPSIZE_28 +#define CONF_DMAC_STEPSIZE_28 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_28 +#ifndef CONF_DMAC_STEPSEL_28 +#define CONF_DMAC_STEPSEL_28 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_28 +#ifndef CONF_DMAC_SRCINC_28 +#define CONF_DMAC_SRCINC_28 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_28 +#ifndef CONF_DMAC_DSTINC_28 +#define CONF_DMAC_DSTINC_28 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_28 +#ifndef CONF_DMAC_BEATSIZE_28 +#define CONF_DMAC_BEATSIZE_28 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_28 +#ifndef CONF_DMAC_BLOCKACT_28 +#define CONF_DMAC_BLOCKACT_28 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_28 +#ifndef CONF_DMAC_EVOSEL_28 +#define CONF_DMAC_EVOSEL_28 0 +#endif +// + +// Channel 29 settings +// dmac_channel_29_settings +#ifndef CONF_DMAC_CHANNEL_29_SETTINGS +#define CONF_DMAC_CHANNEL_29_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 29 is running in standby mode or not +// dmac_runstdby_29 +#ifndef CONF_DMAC_RUNSTDBY_29 +#define CONF_DMAC_RUNSTDBY_29 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_29 +#ifndef CONF_DMAC_TRIGACT_29 +#define CONF_DMAC_TRIGACT_29 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_29 +#ifndef CONF_DMAC_TRIGSRC_29 +#define CONF_DMAC_TRIGSRC_29 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_29 +#ifndef CONF_DMAC_LVL_29 +#define CONF_DMAC_LVL_29 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_29 +#ifndef CONF_DMAC_EVOE_29 +#define CONF_DMAC_EVOE_29 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_29 +#ifndef CONF_DMAC_EVIE_29 +#define CONF_DMAC_EVIE_29 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_29 +#ifndef CONF_DMAC_EVACT_29 +#define CONF_DMAC_EVACT_29 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_29 +#ifndef CONF_DMAC_STEPSIZE_29 +#define CONF_DMAC_STEPSIZE_29 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_29 +#ifndef CONF_DMAC_STEPSEL_29 +#define CONF_DMAC_STEPSEL_29 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_29 +#ifndef CONF_DMAC_SRCINC_29 +#define CONF_DMAC_SRCINC_29 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_29 +#ifndef CONF_DMAC_DSTINC_29 +#define CONF_DMAC_DSTINC_29 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_29 +#ifndef CONF_DMAC_BEATSIZE_29 +#define CONF_DMAC_BEATSIZE_29 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_29 +#ifndef CONF_DMAC_BLOCKACT_29 +#define CONF_DMAC_BLOCKACT_29 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_29 +#ifndef CONF_DMAC_EVOSEL_29 +#define CONF_DMAC_EVOSEL_29 0 +#endif +// + +// Channel 30 settings +// dmac_channel_30_settings +#ifndef CONF_DMAC_CHANNEL_30_SETTINGS +#define CONF_DMAC_CHANNEL_30_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 30 is running in standby mode or not +// dmac_runstdby_30 +#ifndef CONF_DMAC_RUNSTDBY_30 +#define CONF_DMAC_RUNSTDBY_30 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_30 +#ifndef CONF_DMAC_TRIGACT_30 +#define CONF_DMAC_TRIGACT_30 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_30 +#ifndef CONF_DMAC_TRIGSRC_30 +#define CONF_DMAC_TRIGSRC_30 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_30 +#ifndef CONF_DMAC_LVL_30 +#define CONF_DMAC_LVL_30 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_30 +#ifndef CONF_DMAC_EVOE_30 +#define CONF_DMAC_EVOE_30 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_30 +#ifndef CONF_DMAC_EVIE_30 +#define CONF_DMAC_EVIE_30 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_30 +#ifndef CONF_DMAC_EVACT_30 +#define CONF_DMAC_EVACT_30 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_30 +#ifndef CONF_DMAC_STEPSIZE_30 +#define CONF_DMAC_STEPSIZE_30 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_30 +#ifndef CONF_DMAC_STEPSEL_30 +#define CONF_DMAC_STEPSEL_30 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_30 +#ifndef CONF_DMAC_SRCINC_30 +#define CONF_DMAC_SRCINC_30 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_30 +#ifndef CONF_DMAC_DSTINC_30 +#define CONF_DMAC_DSTINC_30 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_30 +#ifndef CONF_DMAC_BEATSIZE_30 +#define CONF_DMAC_BEATSIZE_30 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_30 +#ifndef CONF_DMAC_BLOCKACT_30 +#define CONF_DMAC_BLOCKACT_30 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_30 +#ifndef CONF_DMAC_EVOSEL_30 +#define CONF_DMAC_EVOSEL_30 0 +#endif +// + +// Channel 31 settings +// dmac_channel_31_settings +#ifndef CONF_DMAC_CHANNEL_31_SETTINGS +#define CONF_DMAC_CHANNEL_31_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 31 is running in standby mode or not +// dmac_runstdby_31 +#ifndef CONF_DMAC_RUNSTDBY_31 +#define CONF_DMAC_RUNSTDBY_31 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_31 +#ifndef CONF_DMAC_TRIGACT_31 +#define CONF_DMAC_TRIGACT_31 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_31 +#ifndef CONF_DMAC_TRIGSRC_31 +#define CONF_DMAC_TRIGSRC_31 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_31 +#ifndef CONF_DMAC_LVL_31 +#define CONF_DMAC_LVL_31 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_31 +#ifndef CONF_DMAC_EVOE_31 +#define CONF_DMAC_EVOE_31 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_31 +#ifndef CONF_DMAC_EVIE_31 +#define CONF_DMAC_EVIE_31 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_31 +#ifndef CONF_DMAC_EVACT_31 +#define CONF_DMAC_EVACT_31 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_31 +#ifndef CONF_DMAC_STEPSIZE_31 +#define CONF_DMAC_STEPSIZE_31 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_31 +#ifndef CONF_DMAC_STEPSEL_31 +#define CONF_DMAC_STEPSEL_31 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_31 +#ifndef CONF_DMAC_SRCINC_31 +#define CONF_DMAC_SRCINC_31 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_31 +#ifndef CONF_DMAC_DSTINC_31 +#define CONF_DMAC_DSTINC_31 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_31 +#ifndef CONF_DMAC_BEATSIZE_31 +#define CONF_DMAC_BEATSIZE_31 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_31 +#ifndef CONF_DMAC_BLOCKACT_31 +#define CONF_DMAC_BLOCKACT_31 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_31 +#ifndef CONF_DMAC_EVOSEL_31 +#define CONF_DMAC_EVOSEL_31 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_evsys_config.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_evsys_config.h new file mode 100644 index 0000000..84b0080 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_evsys_config.h @@ -0,0 +1,8363 @@ +/* Auto-generated config file hpl_evsys_config.h */ +#ifndef HPL_EVSYS_CONFIG_H +#define HPL_EVSYS_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Channel 0 settings +// evsys_channel_setting_0 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_0 +#define CONF_EVSYS_CHANNEL_SETTINGS_0 1 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_0 +#ifndef CONF_EDGSEL_0 +#define CONF_EDGSEL_0 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_0 +#ifndef CONF_PATH_0 +#define CONF_PATH_0 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_0 +#ifndef CONF_EVGEN_0 +#define CONF_EVGEN_0 73 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_0 +#ifndef CONF_OVR_0 +#define CONF_OVR_0 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_0 +#ifndef CONF_EVD_0 +#define CONF_EVD_0 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_0 +#ifndef CONF_ONDEMAND_0 +#define CONF_ONDEMAND_0 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_0 +#ifndef CONF_RUNSTDBY_0 +#define CONF_RUNSTDBY_0 0 +#endif + +// + +// Channel 1 settings +// evsys_channel_setting_1 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_1 +#define CONF_EVSYS_CHANNEL_SETTINGS_1 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_1 +#ifndef CONF_EDGSEL_1 +#define CONF_EDGSEL_1 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_1 +#ifndef CONF_PATH_1 +#define CONF_PATH_1 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_1 +#ifndef CONF_EVGEN_1 +#define CONF_EVGEN_1 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_1 +#ifndef CONF_OVR_1 +#define CONF_OVR_1 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_1 +#ifndef CONF_EVD_1 +#define CONF_EVD_1 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_1 +#ifndef CONF_ONDEMAND_1 +#define CONF_ONDEMAND_1 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_1 +#ifndef CONF_RUNSTDBY_1 +#define CONF_RUNSTDBY_1 0 +#endif + +// + +// Channel 2 settings +// evsys_channel_setting_2 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_2 +#define CONF_EVSYS_CHANNEL_SETTINGS_2 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_2 +#ifndef CONF_EDGSEL_2 +#define CONF_EDGSEL_2 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_2 +#ifndef CONF_PATH_2 +#define CONF_PATH_2 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_2 +#ifndef CONF_EVGEN_2 +#define CONF_EVGEN_2 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_2 +#ifndef CONF_OVR_2 +#define CONF_OVR_2 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_2 +#ifndef CONF_EVD_2 +#define CONF_EVD_2 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_2 +#ifndef CONF_ONDEMAND_2 +#define CONF_ONDEMAND_2 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_2 +#ifndef CONF_RUNSTDBY_2 +#define CONF_RUNSTDBY_2 0 +#endif + +// + +// Channel 3 settings +// evsys_channel_setting_3 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_3 +#define CONF_EVSYS_CHANNEL_SETTINGS_3 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_3 +#ifndef CONF_EDGSEL_3 +#define CONF_EDGSEL_3 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_3 +#ifndef CONF_PATH_3 +#define CONF_PATH_3 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_3 +#ifndef CONF_EVGEN_3 +#define CONF_EVGEN_3 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_3 +#ifndef CONF_OVR_3 +#define CONF_OVR_3 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_3 +#ifndef CONF_EVD_3 +#define CONF_EVD_3 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_3 +#ifndef CONF_ONDEMAND_3 +#define CONF_ONDEMAND_3 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_3 +#ifndef CONF_RUNSTDBY_3 +#define CONF_RUNSTDBY_3 0 +#endif + +// + +// Channel 4 settings +// evsys_channel_setting_4 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_4 +#define CONF_EVSYS_CHANNEL_SETTINGS_4 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_4 +#ifndef CONF_EDGSEL_4 +#define CONF_EDGSEL_4 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_4 +#ifndef CONF_PATH_4 +#define CONF_PATH_4 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_4 +#ifndef CONF_EVGEN_4 +#define CONF_EVGEN_4 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_4 +#ifndef CONF_OVR_4 +#define CONF_OVR_4 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_4 +#ifndef CONF_EVD_4 +#define CONF_EVD_4 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_4 +#ifndef CONF_ONDEMAND_4 +#define CONF_ONDEMAND_4 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_4 +#ifndef CONF_RUNSTDBY_4 +#define CONF_RUNSTDBY_4 0 +#endif + +// + +// Channel 5 settings +// evsys_channel_setting_5 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_5 +#define CONF_EVSYS_CHANNEL_SETTINGS_5 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_5 +#ifndef CONF_EDGSEL_5 +#define CONF_EDGSEL_5 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_5 +#ifndef CONF_PATH_5 +#define CONF_PATH_5 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_5 +#ifndef CONF_EVGEN_5 +#define CONF_EVGEN_5 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_5 +#ifndef CONF_OVR_5 +#define CONF_OVR_5 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_5 +#ifndef CONF_EVD_5 +#define CONF_EVD_5 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_5 +#ifndef CONF_ONDEMAND_5 +#define CONF_ONDEMAND_5 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_5 +#ifndef CONF_RUNSTDBY_5 +#define CONF_RUNSTDBY_5 0 +#endif + +// + +// Channel 6 settings +// evsys_channel_setting_6 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_6 +#define CONF_EVSYS_CHANNEL_SETTINGS_6 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_6 +#ifndef CONF_EDGSEL_6 +#define CONF_EDGSEL_6 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_6 +#ifndef CONF_PATH_6 +#define CONF_PATH_6 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_6 +#ifndef CONF_EVGEN_6 +#define CONF_EVGEN_6 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_6 +#ifndef CONF_OVR_6 +#define CONF_OVR_6 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_6 +#ifndef CONF_EVD_6 +#define CONF_EVD_6 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_6 +#ifndef CONF_ONDEMAND_6 +#define CONF_ONDEMAND_6 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_6 +#ifndef CONF_RUNSTDBY_6 +#define CONF_RUNSTDBY_6 0 +#endif + +// + +// Channel 7 settings +// evsys_channel_setting_7 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_7 +#define CONF_EVSYS_CHANNEL_SETTINGS_7 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_7 +#ifndef CONF_EDGSEL_7 +#define CONF_EDGSEL_7 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_7 +#ifndef CONF_PATH_7 +#define CONF_PATH_7 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_7 +#ifndef CONF_EVGEN_7 +#define CONF_EVGEN_7 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_7 +#ifndef CONF_OVR_7 +#define CONF_OVR_7 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_7 +#ifndef CONF_EVD_7 +#define CONF_EVD_7 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_7 +#ifndef CONF_ONDEMAND_7 +#define CONF_ONDEMAND_7 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_7 +#ifndef CONF_RUNSTDBY_7 +#define CONF_RUNSTDBY_7 0 +#endif + +// + +// Channel 8 settings +// evsys_channel_setting_8 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_8 +#define CONF_EVSYS_CHANNEL_SETTINGS_8 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_8 +#ifndef CONF_EDGSEL_8 +#define CONF_EDGSEL_8 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_8 +#ifndef CONF_PATH_8 +#define CONF_PATH_8 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_8 +#ifndef CONF_EVGEN_8 +#define CONF_EVGEN_8 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_8 +#ifndef CONF_OVR_8 +#define CONF_OVR_8 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_8 +#ifndef CONF_EVD_8 +#define CONF_EVD_8 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_8 +#ifndef CONF_ONDEMAND_8 +#define CONF_ONDEMAND_8 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_8 +#ifndef CONF_RUNSTDBY_8 +#define CONF_RUNSTDBY_8 0 +#endif + +// + +// Channel 9 settings +// evsys_channel_setting_9 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_9 +#define CONF_EVSYS_CHANNEL_SETTINGS_9 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_9 +#ifndef CONF_EDGSEL_9 +#define CONF_EDGSEL_9 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_9 +#ifndef CONF_PATH_9 +#define CONF_PATH_9 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_9 +#ifndef CONF_EVGEN_9 +#define CONF_EVGEN_9 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_9 +#ifndef CONF_OVR_9 +#define CONF_OVR_9 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_9 +#ifndef CONF_EVD_9 +#define CONF_EVD_9 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_9 +#ifndef CONF_ONDEMAND_9 +#define CONF_ONDEMAND_9 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_9 +#ifndef CONF_RUNSTDBY_9 +#define CONF_RUNSTDBY_9 0 +#endif + +// + +// Channel 10 settings +// evsys_channel_setting_10 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_10 +#define CONF_EVSYS_CHANNEL_SETTINGS_10 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_10 +#ifndef CONF_EDGSEL_10 +#define CONF_EDGSEL_10 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_10 +#ifndef CONF_PATH_10 +#define CONF_PATH_10 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_10 +#ifndef CONF_EVGEN_10 +#define CONF_EVGEN_10 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_10 +#ifndef CONF_OVR_10 +#define CONF_OVR_10 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_10 +#ifndef CONF_EVD_10 +#define CONF_EVD_10 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_10 +#ifndef CONF_ONDEMAND_10 +#define CONF_ONDEMAND_10 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_10 +#ifndef CONF_RUNSTDBY_10 +#define CONF_RUNSTDBY_10 0 +#endif + +// + +// Channel 11 settings +// evsys_channel_setting_11 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_11 +#define CONF_EVSYS_CHANNEL_SETTINGS_11 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_11 +#ifndef CONF_EDGSEL_11 +#define CONF_EDGSEL_11 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_11 +#ifndef CONF_PATH_11 +#define CONF_PATH_11 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_11 +#ifndef CONF_EVGEN_11 +#define CONF_EVGEN_11 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_11 +#ifndef CONF_OVR_11 +#define CONF_OVR_11 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_11 +#ifndef CONF_EVD_11 +#define CONF_EVD_11 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_11 +#ifndef CONF_ONDEMAND_11 +#define CONF_ONDEMAND_11 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_11 +#ifndef CONF_RUNSTDBY_11 +#define CONF_RUNSTDBY_11 0 +#endif + +// + +// Channel 12 settings +// evsys_channel_setting_12 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_12 +#define CONF_EVSYS_CHANNEL_SETTINGS_12 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_12 +#ifndef CONF_EDGSEL_12 +#define CONF_EDGSEL_12 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_12 +#ifndef CONF_PATH_12 +#define CONF_PATH_12 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_12 +#ifndef CONF_EVGEN_12 +#define CONF_EVGEN_12 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_12 +#ifndef CONF_OVR_12 +#define CONF_OVR_12 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_12 +#ifndef CONF_EVD_12 +#define CONF_EVD_12 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_12 +#ifndef CONF_ONDEMAND_12 +#define CONF_ONDEMAND_12 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_12 +#ifndef CONF_RUNSTDBY_12 +#define CONF_RUNSTDBY_12 0 +#endif + +// + +// Channel 13 settings +// evsys_channel_setting_13 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_13 +#define CONF_EVSYS_CHANNEL_SETTINGS_13 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_13 +#ifndef CONF_EDGSEL_13 +#define CONF_EDGSEL_13 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_13 +#ifndef CONF_PATH_13 +#define CONF_PATH_13 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_13 +#ifndef CONF_EVGEN_13 +#define CONF_EVGEN_13 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_13 +#ifndef CONF_OVR_13 +#define CONF_OVR_13 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_13 +#ifndef CONF_EVD_13 +#define CONF_EVD_13 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_13 +#ifndef CONF_ONDEMAND_13 +#define CONF_ONDEMAND_13 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_13 +#ifndef CONF_RUNSTDBY_13 +#define CONF_RUNSTDBY_13 0 +#endif + +// + +// Channel 14 settings +// evsys_channel_setting_14 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_14 +#define CONF_EVSYS_CHANNEL_SETTINGS_14 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_14 +#ifndef CONF_EDGSEL_14 +#define CONF_EDGSEL_14 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_14 +#ifndef CONF_PATH_14 +#define CONF_PATH_14 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_14 +#ifndef CONF_EVGEN_14 +#define CONF_EVGEN_14 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_14 +#ifndef CONF_OVR_14 +#define CONF_OVR_14 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_14 +#ifndef CONF_EVD_14 +#define CONF_EVD_14 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_14 +#ifndef CONF_ONDEMAND_14 +#define CONF_ONDEMAND_14 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_14 +#ifndef CONF_RUNSTDBY_14 +#define CONF_RUNSTDBY_14 0 +#endif + +// + +// Channel 15 settings +// evsys_channel_setting_15 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_15 +#define CONF_EVSYS_CHANNEL_SETTINGS_15 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_15 +#ifndef CONF_EDGSEL_15 +#define CONF_EDGSEL_15 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_15 +#ifndef CONF_PATH_15 +#define CONF_PATH_15 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_15 +#ifndef CONF_EVGEN_15 +#define CONF_EVGEN_15 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_15 +#ifndef CONF_OVR_15 +#define CONF_OVR_15 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_15 +#ifndef CONF_EVD_15 +#define CONF_EVD_15 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_15 +#ifndef CONF_ONDEMAND_15 +#define CONF_ONDEMAND_15 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_15 +#ifndef CONF_RUNSTDBY_15 +#define CONF_RUNSTDBY_15 0 +#endif + +// + +// Channel 16 settings +// evsys_channel_setting_16 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_16 +#define CONF_EVSYS_CHANNEL_SETTINGS_16 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_16 +#ifndef CONF_EDGSEL_16 +#define CONF_EDGSEL_16 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_16 +#ifndef CONF_PATH_16 +#define CONF_PATH_16 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_16 +#ifndef CONF_EVGEN_16 +#define CONF_EVGEN_16 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_16 +#ifndef CONF_OVR_16 +#define CONF_OVR_16 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_16 +#ifndef CONF_EVD_16 +#define CONF_EVD_16 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_16 +#ifndef CONF_ONDEMAND_16 +#define CONF_ONDEMAND_16 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_16 +#ifndef CONF_RUNSTDBY_16 +#define CONF_RUNSTDBY_16 0 +#endif + +// + +// Channel 17 settings +// evsys_channel_setting_17 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_17 +#define CONF_EVSYS_CHANNEL_SETTINGS_17 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_17 +#ifndef CONF_EDGSEL_17 +#define CONF_EDGSEL_17 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_17 +#ifndef CONF_PATH_17 +#define CONF_PATH_17 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_17 +#ifndef CONF_EVGEN_17 +#define CONF_EVGEN_17 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_17 +#ifndef CONF_OVR_17 +#define CONF_OVR_17 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_17 +#ifndef CONF_EVD_17 +#define CONF_EVD_17 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_17 +#ifndef CONF_ONDEMAND_17 +#define CONF_ONDEMAND_17 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_17 +#ifndef CONF_RUNSTDBY_17 +#define CONF_RUNSTDBY_17 0 +#endif + +// + +// Channel 18 settings +// evsys_channel_setting_18 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_18 +#define CONF_EVSYS_CHANNEL_SETTINGS_18 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_18 +#ifndef CONF_EDGSEL_18 +#define CONF_EDGSEL_18 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_18 +#ifndef CONF_PATH_18 +#define CONF_PATH_18 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_18 +#ifndef CONF_EVGEN_18 +#define CONF_EVGEN_18 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_18 +#ifndef CONF_OVR_18 +#define CONF_OVR_18 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_18 +#ifndef CONF_EVD_18 +#define CONF_EVD_18 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_18 +#ifndef CONF_ONDEMAND_18 +#define CONF_ONDEMAND_18 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_18 +#ifndef CONF_RUNSTDBY_18 +#define CONF_RUNSTDBY_18 0 +#endif + +// + +// Channel 19 settings +// evsys_channel_setting_19 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_19 +#define CONF_EVSYS_CHANNEL_SETTINGS_19 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_19 +#ifndef CONF_EDGSEL_19 +#define CONF_EDGSEL_19 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_19 +#ifndef CONF_PATH_19 +#define CONF_PATH_19 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_19 +#ifndef CONF_EVGEN_19 +#define CONF_EVGEN_19 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_19 +#ifndef CONF_OVR_19 +#define CONF_OVR_19 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_19 +#ifndef CONF_EVD_19 +#define CONF_EVD_19 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_19 +#ifndef CONF_ONDEMAND_19 +#define CONF_ONDEMAND_19 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_19 +#ifndef CONF_RUNSTDBY_19 +#define CONF_RUNSTDBY_19 0 +#endif + +// + +// Channel 20 settings +// evsys_channel_setting_20 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_20 +#define CONF_EVSYS_CHANNEL_SETTINGS_20 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_20 +#ifndef CONF_EDGSEL_20 +#define CONF_EDGSEL_20 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_20 +#ifndef CONF_PATH_20 +#define CONF_PATH_20 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_20 +#ifndef CONF_EVGEN_20 +#define CONF_EVGEN_20 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_20 +#ifndef CONF_OVR_20 +#define CONF_OVR_20 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_20 +#ifndef CONF_EVD_20 +#define CONF_EVD_20 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_20 +#ifndef CONF_ONDEMAND_20 +#define CONF_ONDEMAND_20 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_20 +#ifndef CONF_RUNSTDBY_20 +#define CONF_RUNSTDBY_20 0 +#endif + +// + +// Channel 21 settings +// evsys_channel_setting_21 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_21 +#define CONF_EVSYS_CHANNEL_SETTINGS_21 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_21 +#ifndef CONF_EDGSEL_21 +#define CONF_EDGSEL_21 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_21 +#ifndef CONF_PATH_21 +#define CONF_PATH_21 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_21 +#ifndef CONF_EVGEN_21 +#define CONF_EVGEN_21 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_21 +#ifndef CONF_OVR_21 +#define CONF_OVR_21 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_21 +#ifndef CONF_EVD_21 +#define CONF_EVD_21 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_21 +#ifndef CONF_ONDEMAND_21 +#define CONF_ONDEMAND_21 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_21 +#ifndef CONF_RUNSTDBY_21 +#define CONF_RUNSTDBY_21 0 +#endif + +// + +// Channel 22 settings +// evsys_channel_setting_22 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_22 +#define CONF_EVSYS_CHANNEL_SETTINGS_22 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_22 +#ifndef CONF_EDGSEL_22 +#define CONF_EDGSEL_22 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_22 +#ifndef CONF_PATH_22 +#define CONF_PATH_22 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_22 +#ifndef CONF_EVGEN_22 +#define CONF_EVGEN_22 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_22 +#ifndef CONF_OVR_22 +#define CONF_OVR_22 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_22 +#ifndef CONF_EVD_22 +#define CONF_EVD_22 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_22 +#ifndef CONF_ONDEMAND_22 +#define CONF_ONDEMAND_22 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_22 +#ifndef CONF_RUNSTDBY_22 +#define CONF_RUNSTDBY_22 0 +#endif + +// + +// Channel 23 settings +// evsys_channel_setting_23 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_23 +#define CONF_EVSYS_CHANNEL_SETTINGS_23 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_23 +#ifndef CONF_EDGSEL_23 +#define CONF_EDGSEL_23 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_23 +#ifndef CONF_PATH_23 +#define CONF_PATH_23 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_23 +#ifndef CONF_EVGEN_23 +#define CONF_EVGEN_23 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_23 +#ifndef CONF_OVR_23 +#define CONF_OVR_23 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_23 +#ifndef CONF_EVD_23 +#define CONF_EVD_23 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_23 +#ifndef CONF_ONDEMAND_23 +#define CONF_ONDEMAND_23 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_23 +#ifndef CONF_RUNSTDBY_23 +#define CONF_RUNSTDBY_23 0 +#endif + +// + +// Channel 24 settings +// evsys_channel_setting_24 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_24 +#define CONF_EVSYS_CHANNEL_SETTINGS_24 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_24 +#ifndef CONF_EDGSEL_24 +#define CONF_EDGSEL_24 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_24 +#ifndef CONF_PATH_24 +#define CONF_PATH_24 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_24 +#ifndef CONF_EVGEN_24 +#define CONF_EVGEN_24 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_24 +#ifndef CONF_OVR_24 +#define CONF_OVR_24 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_24 +#ifndef CONF_EVD_24 +#define CONF_EVD_24 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_24 +#ifndef CONF_ONDEMAND_24 +#define CONF_ONDEMAND_24 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_24 +#ifndef CONF_RUNSTDBY_24 +#define CONF_RUNSTDBY_24 0 +#endif + +// + +// Channel 25 settings +// evsys_channel_setting_25 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_25 +#define CONF_EVSYS_CHANNEL_SETTINGS_25 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_25 +#ifndef CONF_EDGSEL_25 +#define CONF_EDGSEL_25 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_25 +#ifndef CONF_PATH_25 +#define CONF_PATH_25 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_25 +#ifndef CONF_EVGEN_25 +#define CONF_EVGEN_25 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_25 +#ifndef CONF_OVR_25 +#define CONF_OVR_25 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_25 +#ifndef CONF_EVD_25 +#define CONF_EVD_25 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_25 +#ifndef CONF_ONDEMAND_25 +#define CONF_ONDEMAND_25 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_25 +#ifndef CONF_RUNSTDBY_25 +#define CONF_RUNSTDBY_25 0 +#endif + +// + +// Channel 26 settings +// evsys_channel_setting_26 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_26 +#define CONF_EVSYS_CHANNEL_SETTINGS_26 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_26 +#ifndef CONF_EDGSEL_26 +#define CONF_EDGSEL_26 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_26 +#ifndef CONF_PATH_26 +#define CONF_PATH_26 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_26 +#ifndef CONF_EVGEN_26 +#define CONF_EVGEN_26 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_26 +#ifndef CONF_OVR_26 +#define CONF_OVR_26 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_26 +#ifndef CONF_EVD_26 +#define CONF_EVD_26 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_26 +#ifndef CONF_ONDEMAND_26 +#define CONF_ONDEMAND_26 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_26 +#ifndef CONF_RUNSTDBY_26 +#define CONF_RUNSTDBY_26 0 +#endif + +// + +// Channel 27 settings +// evsys_channel_setting_27 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_27 +#define CONF_EVSYS_CHANNEL_SETTINGS_27 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_27 +#ifndef CONF_EDGSEL_27 +#define CONF_EDGSEL_27 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_27 +#ifndef CONF_PATH_27 +#define CONF_PATH_27 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_27 +#ifndef CONF_EVGEN_27 +#define CONF_EVGEN_27 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_27 +#ifndef CONF_OVR_27 +#define CONF_OVR_27 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_27 +#ifndef CONF_EVD_27 +#define CONF_EVD_27 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_27 +#ifndef CONF_ONDEMAND_27 +#define CONF_ONDEMAND_27 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_27 +#ifndef CONF_RUNSTDBY_27 +#define CONF_RUNSTDBY_27 0 +#endif + +// + +// Channel 28 settings +// evsys_channel_setting_28 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_28 +#define CONF_EVSYS_CHANNEL_SETTINGS_28 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_28 +#ifndef CONF_EDGSEL_28 +#define CONF_EDGSEL_28 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_28 +#ifndef CONF_PATH_28 +#define CONF_PATH_28 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_28 +#ifndef CONF_EVGEN_28 +#define CONF_EVGEN_28 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_28 +#ifndef CONF_OVR_28 +#define CONF_OVR_28 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_28 +#ifndef CONF_EVD_28 +#define CONF_EVD_28 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_28 +#ifndef CONF_ONDEMAND_28 +#define CONF_ONDEMAND_28 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_28 +#ifndef CONF_RUNSTDBY_28 +#define CONF_RUNSTDBY_28 0 +#endif + +// + +// Channel 29 settings +// evsys_channel_setting_29 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_29 +#define CONF_EVSYS_CHANNEL_SETTINGS_29 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_29 +#ifndef CONF_EDGSEL_29 +#define CONF_EDGSEL_29 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_29 +#ifndef CONF_PATH_29 +#define CONF_PATH_29 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_29 +#ifndef CONF_EVGEN_29 +#define CONF_EVGEN_29 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_29 +#ifndef CONF_OVR_29 +#define CONF_OVR_29 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_29 +#ifndef CONF_EVD_29 +#define CONF_EVD_29 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_29 +#ifndef CONF_ONDEMAND_29 +#define CONF_ONDEMAND_29 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_29 +#ifndef CONF_RUNSTDBY_29 +#define CONF_RUNSTDBY_29 0 +#endif + +// + +// Channel 30 settings +// evsys_channel_setting_30 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_30 +#define CONF_EVSYS_CHANNEL_SETTINGS_30 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_30 +#ifndef CONF_EDGSEL_30 +#define CONF_EDGSEL_30 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_30 +#ifndef CONF_PATH_30 +#define CONF_PATH_30 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_30 +#ifndef CONF_EVGEN_30 +#define CONF_EVGEN_30 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_30 +#ifndef CONF_OVR_30 +#define CONF_OVR_30 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_30 +#ifndef CONF_EVD_30 +#define CONF_EVD_30 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_30 +#ifndef CONF_ONDEMAND_30 +#define CONF_ONDEMAND_30 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_30 +#ifndef CONF_RUNSTDBY_30 +#define CONF_RUNSTDBY_30 0 +#endif + +// + +// Channel 31 settings +// evsys_channel_setting_31 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_31 +#define CONF_EVSYS_CHANNEL_SETTINGS_31 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_31 +#ifndef CONF_EDGSEL_31 +#define CONF_EDGSEL_31 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_31 +#ifndef CONF_PATH_31 +#define CONF_PATH_31 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_31 +#ifndef CONF_EVGEN_31 +#define CONF_EVGEN_31 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_31 +#ifndef CONF_OVR_31 +#define CONF_OVR_31 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_31 +#ifndef CONF_EVD_31 +#define CONF_EVD_31 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_31 +#ifndef CONF_ONDEMAND_31 +#define CONF_ONDEMAND_31 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_31 +#ifndef CONF_RUNSTDBY_31 +#define CONF_RUNSTDBY_31 0 +#endif + +// + +// Event User Security Attribution Settings + +// + +// RTC events +// Channel selection for RTC Tamper Event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_0 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_0 +#define CONF_CHANNEL_0 0 +#endif +// + +// PORT events +// Channel selection for PORT event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_1 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_1 +#define CONF_CHANNEL_1 0 +#endif + +// Channel selection for PORT event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_2 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_2 +#define CONF_CHANNEL_2 0 +#endif + +// Channel selection for PORT event 2 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_3 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_3 +#define CONF_CHANNEL_3 0 +#endif + +// Channel selection for PORT event 3 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_4 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_4 +#define CONF_CHANNEL_4 0 +#endif +// + +// DMAC events +// Channel selection for DMAC channel 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_5 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_5 +#define CONF_CHANNEL_5 1 +#endif + +// Channel selection for DMAC channel 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_6 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_6 +#define CONF_CHANNEL_6 1 +#endif + +// Channel selection for DMAC channel 2 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_7 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_7 +#define CONF_CHANNEL_7 1 +#endif + +// Channel selection for DMAC channel 3 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_8 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_8 +#define CONF_CHANNEL_8 1 +#endif + +// Channel selection for DMAC channel 4 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_9 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_9 +#define CONF_CHANNEL_9 1 +#endif + +// Channel selection for DMAC channel 5 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_10 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_10 +#define CONF_CHANNEL_10 1 +#endif + +// Channel selection for DMAC channel 6 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_11 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_11 +#define CONF_CHANNEL_11 1 +#endif + +// Channel selection for DMAC channel 7 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_12 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_12 +#define CONF_CHANNEL_12 1 +#endif +// + +// Reserved +#ifndef CONF_CHANNEL_13 +#define CONF_CHANNEL_13 0 +#endif + +#ifndef CONF_CHANNEL_14 +#define CONF_CHANNEL_14 0 +#endif + +#ifndef CONF_CHANNEL_15 +#define CONF_CHANNEL_15 0 +#endif + +#ifndef CONF_CHANNEL_16 +#define CONF_CHANNEL_16 0 +#endif +// + +// TCC events +// Channel selection for TCC0 Event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_17 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_17 +#define CONF_CHANNEL_17 0 +#endif + +// Channel selection for TCC0 Event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_18 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_18 +#define CONF_CHANNEL_18 0 +#endif + +// Channel selection for TCC0 match/capture 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_19 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_19 +#define CONF_CHANNEL_19 0 +#endif + +// Channel selection for TCC0 match/capture 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_20 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_20 +#define CONF_CHANNEL_20 0 +#endif + +// Channel selection for TCC0 match/capture 2 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_21 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_21 +#define CONF_CHANNEL_21 0 +#endif + +// Channel selection for TCC0 match/capture 3 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_22 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_22 +#define CONF_CHANNEL_22 0 +#endif + +// Channel selection for TCC0 match/capture 4 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_23 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_23 +#define CONF_CHANNEL_23 0 +#endif + +// Channel selection for TCC0 match/capture 5 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_24 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_24 +#define CONF_CHANNEL_24 0 +#endif + +// Channel selection for TCC1 Event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_25 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_25 +#define CONF_CHANNEL_25 0 +#endif + +// Channel selection for TCC1 Event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_26 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_26 +#define CONF_CHANNEL_26 0 +#endif + +// Channel selection for TCC1 match/capture 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_27 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_27 +#define CONF_CHANNEL_27 0 +#endif + +// Channel selection for TCC1 match/capture 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_28 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_28 +#define CONF_CHANNEL_28 0 +#endif + +// Channel selection for TCC1 match/capture 2 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_29 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_29 +#define CONF_CHANNEL_29 0 +#endif + +// Channel selection for TCC1 match/capture 3 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_30 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_30 +#define CONF_CHANNEL_30 0 +#endif + +// Channel selection for TCC2 Event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_31 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_31 +#define CONF_CHANNEL_31 0 +#endif + +// Channel selection for TCC2 Event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_32 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_32 +#define CONF_CHANNEL_32 0 +#endif + +// Channel selection for TCC2 match/capture 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_33 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_33 +#define CONF_CHANNEL_33 0 +#endif + +// Channel selection for TCC2 match/capture 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_34 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_34 +#define CONF_CHANNEL_34 0 +#endif + +// Channel selection for TCC2 match/capture 2 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_35 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_35 +#define CONF_CHANNEL_35 0 +#endif + +// Channel selection for TCC3 Event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_36 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_36 +#define CONF_CHANNEL_36 0 +#endif + +// Channel selection for TCC3 Event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_37 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_37 +#define CONF_CHANNEL_37 0 +#endif + +// Channel selection for TCC3 match/capture 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_38 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_38 +#define CONF_CHANNEL_38 0 +#endif + +// Channel selection for TCC3 match/capture 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_39 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_39 +#define CONF_CHANNEL_39 0 +#endif + +// Channel selection for TCC4 Event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_40 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_40 +#define CONF_CHANNEL_40 0 +#endif + +// Channel selection for TCC4 Event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_41 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_41 +#define CONF_CHANNEL_41 0 +#endif + +// Channel selection for TCC4 match/capture 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_42 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_42 +#define CONF_CHANNEL_42 0 +#endif + +// Channel selection for TCC4 match/capture 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_43 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_43 +#define CONF_CHANNEL_43 0 +#endif +// + +// TC events +// Channel selection for TC0 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_44 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_44 +#define CONF_CHANNEL_44 0 +#endif + +// Channel selection for TC1 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_45 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_45 +#define CONF_CHANNEL_45 0 +#endif + +// Channel selection for TC2 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_46 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_46 +#define CONF_CHANNEL_46 0 +#endif + +// Channel selection for TC3 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_47 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_47 +#define CONF_CHANNEL_47 0 +#endif + +// Channel selection for TC4 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_48 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_48 +#define CONF_CHANNEL_48 0 +#endif + +// Channel selection for TC5 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_49 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_49 +#define CONF_CHANNEL_49 0 +#endif + +// Channel selection for TC6 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_50 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_50 +#define CONF_CHANNEL_50 0 +#endif + +// Channel selection for TC7 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_51 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_51 +#define CONF_CHANNEL_51 0 +#endif +// + +// PDEC events +// Channel selection for PDEC event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_52 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_52 +#define CONF_CHANNEL_52 0 +#endif + +// Channel selection for PDEC event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_53 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_53 +#define CONF_CHANNEL_53 0 +#endif + +// Channel selection for PDEC event 2 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_54 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_54 +#define CONF_CHANNEL_54 0 +#endif +// + +// ADC events +// Channel selection for ADC0 start conversion event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_55 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_55 +#define CONF_CHANNEL_55 0 +#endif + +// Channel selection for ADC0 flush event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_56 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_56 +#define CONF_CHANNEL_56 0 +#endif + +// Channel selection for ADC1 start conversion event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_57 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_57 +#define CONF_CHANNEL_57 0 +#endif + +// Channel selection for ADC1 flush event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_58 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_58 +#define CONF_CHANNEL_58 0 +#endif +// + +// AC events +// Channel selection for Start comparator event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_59 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_59 +#define CONF_CHANNEL_59 0 +#endif + +// Channel selection for Start comparator event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_60 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_60 +#define CONF_CHANNEL_60 0 +#endif +// + +// DAC events +// Channel selection for DAC Start event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_61 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_61 +#define CONF_CHANNEL_61 0 +#endif + +// Channel selection for DAC Start event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_62 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_62 +#define CONF_CHANNEL_62 0 +#endif +// + +// CCL events +// Channel selection for CCL input event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_63 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_63 +#define CONF_CHANNEL_63 0 +#endif + +// Channel selection for CCL input event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_64 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_64 +#define CONF_CHANNEL_64 0 +#endif + +// Channel selection for CCL input event 2 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_65 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_65 +#define CONF_CHANNEL_65 0 +#endif + +// Channel selection for CCL input event 3 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_66 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_66 +#define CONF_CHANNEL_66 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_EVSYS_CONFIG_H diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_gclk_config.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_gclk_config.h new file mode 100644 index 0000000..85a5631 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_gclk_config.h @@ -0,0 +1,920 @@ +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 0 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SOURCE +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_runstdby +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif +// +// + +// Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 1 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SOURCE +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_runstdby +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif +// +// + +// Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 2 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SOURCE +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_runstdby +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 1 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 1 +#endif +// +// + +// Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 3 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SOURCE +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_runstdby +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif +// +// + +// Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 4 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SOURCE +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_runstdby +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif +// +// + +// Generic clock generator 5 configuration +// Indicates whether generic clock 5 configuration is enabled or not +// enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 5 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 5 +// gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SOURCE +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_5_runstdby +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> +// gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 1 +#endif +// +// + +// Generic clock generator 6 configuration +// Indicates whether generic clock 6 configuration is enabled or not +// enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 6 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 6 +// gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SOURCE +#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_6_runstdby +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> +// gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 1 +#endif +// +// + +// Generic clock generator 7 configuration +// Indicates whether generic clock 7 configuration is enabled or not +// enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 7 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 7 +// gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SOURCE +#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_7_runstdby +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> +// gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif +// +// + +// Generic clock generator 8 configuration +// Indicates whether generic clock 8 configuration is enabled or not +// enable_gclk_gen_8 +#ifndef CONF_GCLK_GENERATOR_8_CONFIG +#define CONF_GCLK_GENERATOR_8_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 8 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 8 +// gclk_gen_8_oscillator +#ifndef CONF_GCLK_GEN_8_SOURCE +#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_8_runstdby +#ifndef CONF_GCLK_GEN_8_RUNSTDBY +#define CONF_GCLK_GEN_8_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_8_div_sel +#ifndef CONF_GCLK_GEN_8_DIVSEL +#define CONF_GCLK_GEN_8_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_8_oe +#ifndef CONF_GCLK_GEN_8_OE +#define CONF_GCLK_GEN_8_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_8_oov +#ifndef CONF_GCLK_GEN_8_OOV +#define CONF_GCLK_GEN_8_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_8_idc +#ifndef CONF_GCLK_GEN_8_IDC +#define CONF_GCLK_GEN_8_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_8_enable +#ifndef CONF_GCLK_GEN_8_GENEN +#define CONF_GCLK_GEN_8_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 8 division <0x0000-0xFFFF> +// gclk_gen_8_div +#ifndef CONF_GCLK_GEN_8_DIV +#define CONF_GCLK_GEN_8_DIV 1 +#endif +// +// + +// Generic clock generator 9 configuration +// Indicates whether generic clock 9 configuration is enabled or not +// enable_gclk_gen_9 +#ifndef CONF_GCLK_GENERATOR_9_CONFIG +#define CONF_GCLK_GENERATOR_9_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 9 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 9 +// gclk_gen_9_oscillator +#ifndef CONF_GCLK_GEN_9_SOURCE +#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_9_runstdby +#ifndef CONF_GCLK_GEN_9_RUNSTDBY +#define CONF_GCLK_GEN_9_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_9_div_sel +#ifndef CONF_GCLK_GEN_9_DIVSEL +#define CONF_GCLK_GEN_9_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_9_oe +#ifndef CONF_GCLK_GEN_9_OE +#define CONF_GCLK_GEN_9_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_9_oov +#ifndef CONF_GCLK_GEN_9_OOV +#define CONF_GCLK_GEN_9_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_9_idc +#ifndef CONF_GCLK_GEN_9_IDC +#define CONF_GCLK_GEN_9_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_9_enable +#ifndef CONF_GCLK_GEN_9_GENEN +#define CONF_GCLK_GEN_9_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 9 division <0x0000-0xFFFF> +// gclk_gen_9_div +#ifndef CONF_GCLK_GEN_9_DIV +#define CONF_GCLK_GEN_9_DIV 1 +#endif +// +// + +// Generic clock generator 10 configuration +// Indicates whether generic clock 10 configuration is enabled or not +// enable_gclk_gen_10 +#ifndef CONF_GCLK_GENERATOR_10_CONFIG +#define CONF_GCLK_GENERATOR_10_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 10 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 10 +// gclk_gen_10_oscillator +#ifndef CONF_GCLK_GEN_10_SOURCE +#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_10_runstdby +#ifndef CONF_GCLK_GEN_10_RUNSTDBY +#define CONF_GCLK_GEN_10_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_10_div_sel +#ifndef CONF_GCLK_GEN_10_DIVSEL +#define CONF_GCLK_GEN_10_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_10_oe +#ifndef CONF_GCLK_GEN_10_OE +#define CONF_GCLK_GEN_10_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_10_oov +#ifndef CONF_GCLK_GEN_10_OOV +#define CONF_GCLK_GEN_10_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_10_idc +#ifndef CONF_GCLK_GEN_10_IDC +#define CONF_GCLK_GEN_10_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_10_enable +#ifndef CONF_GCLK_GEN_10_GENEN +#define CONF_GCLK_GEN_10_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 10 division <0x0000-0xFFFF> +// gclk_gen_10_div +#ifndef CONF_GCLK_GEN_10_DIV +#define CONF_GCLK_GEN_10_DIV 1 +#endif +// +// + +// Generic clock generator 11 configuration +// Indicates whether generic clock 11 configuration is enabled or not +// enable_gclk_gen_11 +#ifndef CONF_GCLK_GENERATOR_11_CONFIG +#define CONF_GCLK_GENERATOR_11_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 11 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 11 +// gclk_gen_11_oscillator +#ifndef CONF_GCLK_GEN_11_SOURCE +#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_11_runstdby +#ifndef CONF_GCLK_GEN_11_RUNSTDBY +#define CONF_GCLK_GEN_11_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_11_div_sel +#ifndef CONF_GCLK_GEN_11_DIVSEL +#define CONF_GCLK_GEN_11_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_11_oe +#ifndef CONF_GCLK_GEN_11_OE +#define CONF_GCLK_GEN_11_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_11_oov +#ifndef CONF_GCLK_GEN_11_OOV +#define CONF_GCLK_GEN_11_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_11_idc +#ifndef CONF_GCLK_GEN_11_IDC +#define CONF_GCLK_GEN_11_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_11_enable +#ifndef CONF_GCLK_GEN_11_GENEN +#define CONF_GCLK_GEN_11_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 11 division <0x0000-0xFFFF> +// gclk_gen_11_div +#ifndef CONF_GCLK_GEN_11_DIV +#define CONF_GCLK_GEN_11_DIV 1 +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_mclk_config.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_mclk_config.h new file mode 100644 index 0000000..a5a7de5 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_mclk_config.h @@ -0,0 +1,104 @@ +/* Auto-generated config file hpl_mclk_config.h */ +#ifndef HPL_MCLK_CONFIG_H +#define HPL_MCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Basic settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// CPU Clock Division Factor +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for CPU clock +// cpu_div +#ifndef CONF_MCLK_CPUDIV +#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val +#endif +// Low Power Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_lpdiv +#ifndef CONF_MCLK_LPDIV +#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val +#endif + +// Backup Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_bupdiv +#ifndef CONF_MCLK_BUPDIV +#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val +#endif +// High-Speed Clock Division +// Divide by 1 +// mclk_arch_hsdiv +#ifndef CONF_MCLK_HSDIV +#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val +#endif +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 0 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_MCLK_CONFIG_H diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_osc32kctrl_config.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_osc32kctrl_config.h new file mode 100644 index 0000000..e7fddd2 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_osc32kctrl_config.h @@ -0,0 +1,165 @@ +/* Auto-generated config file hpl_osc32kctrl_config.h */ +#ifndef HPL_OSC32KCTRL_CONFIG_H +#define HPL_OSC32KCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RTC Source configuration +// enable_rtc_source +#ifndef CONF_RTCCTRL_CONFIG +#define CONF_RTCCTRL_CONFIG 0 +#endif + +// RTC source control +// RTC Clock Source Selection +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// This defines the clock source for RTC +// rtc_source_oscillator +#ifndef CONF_RTCCTRL_SRC +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// Use 1 kHz output +// rtc_1khz_selection +#ifndef CONF_RTCCTRL_1KHZ + +#define CONF_RTCCTRL_1KHZ 0 + +#endif + +#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) +#else +#error unexpected CONF_RTCCTRL_SRC +#endif + +// +// + +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 0 +#endif + +// 32kHz External Crystal Oscillator Control +// Oscillator enable +// Indicates whether 32kHz External Crystal Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>62592us +// <0x1=>125092us +// <0x2=>500092us +// <0x3=>1000092us +// <0x4=>2000092us +// <0x5=>4000092us +// <0x6=>8000092us +// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc32k_arch_swben +#ifndef CONF_XOSC32K_SWBEN +#define CONF_XOSC32K_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc32k_arch_cfden +#ifndef CONF_XOSC32K_CFDEN +#define CONF_XOSC32K_CFDEN 0 +#endif + +// Clock Failure Detector Event Out +// Indicates whether Clock Failure Detector Event Out is enabled or not +// xosc32k_arch_cfdeo +#ifndef CONF_XOSC32K_CFDEO +#define CONF_XOSC32K_CFDEO 0 +#endif + +// Crystal connected to XIN32/XOUT32 Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 1 +#endif + +// Control Gain Mode +// <0x0=>Low Power mode +// <0x1=>Standard mode +// <0x2=>High Speed mode +// xosc32k_arch_cgm +#ifndef CONF_XOSC32K_CGM +#define CONF_XOSC32K_CGM 0x1 +#endif + +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator Control + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osculp32k_calib_enable +#ifndef CONF_OSCULP32K_CALIB_ENABLE +#define CONF_OSCULP32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x3F> +// osculp32k_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_oscctrl_config.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_oscctrl_config.h new file mode 100644 index 0000000..bb1a5dc --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_oscctrl_config.h @@ -0,0 +1,640 @@ +/* Auto-generated config file hpl_oscctrl_config.h */ +#ifndef HPL_OSCCTRL_CONFIG_H +#define HPL_OSCCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC0 is enabled or not +// enable_xosc0 +#ifndef CONF_XOSC0_CONFIG +#define CONF_XOSC0_CONFIG 0 +#endif + +// Frequency <8000000-48000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc0_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC0_FREQUENCY 12000000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc0_arch_enable +#ifndef CONF_XOSC0_ENABLE +#define CONF_XOSC0_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc0_arch_startup +#ifndef CONF_XOSC0_STARTUP +#define CONF_XOSC0_STARTUP 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc0_arch_swben +#ifndef CONF_XOSC0_SWBEN +#define CONF_XOSC0_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc0_arch_cfden +#ifndef CONF_XOSC0_CFDEN +#define CONF_XOSC0_CFDEN 0 +#endif + +// Automatic Loop Control Enable +// Indicates whether Automatic Loop Control is enabled or not +// xosc0_arch_enalc +#ifndef CONF_XOSC0_ENALC +#define CONF_XOSC0_ENALC 0 +#endif + +// Low Buffer Gain Enable +// Indicates whether Low Buffer Gain is enabled or not +// xosc0_arch_lowbufgain +#ifndef CONF_XOSC0_LOWBUFGAIN +#define CONF_XOSC0_LOWBUFGAIN 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc0_arch_ondemand +#ifndef CONF_XOSC0_ONDEMAND +#define CONF_XOSC0_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc0_arch_runstdby +#ifndef CONF_XOSC0_RUNSTDBY +#define CONF_XOSC0_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc0_arch_xtalen +#ifndef CONF_XOSC0_XTALEN +#define CONF_XOSC0_XTALEN 0 +#endif +// +// + +#if CONF_XOSC0_FREQUENCY >= 32000000 +#define CONF_XOSC0_CFDPRESC 0x0 +#define CONF_XOSC0_IMULT 0x7 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 24000000 +#define CONF_XOSC0_CFDPRESC 0x1 +#define CONF_XOSC0_IMULT 0x6 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 16000000 +#define CONF_XOSC0_CFDPRESC 0x2 +#define CONF_XOSC0_IMULT 0x5 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 8000000 +#define CONF_XOSC0_CFDPRESC 0x3 +#define CONF_XOSC0_IMULT 0x4 +#define CONF_XOSC0_IPTAT 0x3 +#endif + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC1 is enabled or not +// enable_xosc1 +#ifndef CONF_XOSC1_CONFIG +#define CONF_XOSC1_CONFIG 1 +#endif + +// Frequency <8000000-48000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc1_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC1_FREQUENCY 12000000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc1_arch_enable +#ifndef CONF_XOSC1_ENABLE +#define CONF_XOSC1_ENABLE 1 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc1_arch_startup +#ifndef CONF_XOSC1_STARTUP +#define CONF_XOSC1_STARTUP 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc1_arch_swben +#ifndef CONF_XOSC1_SWBEN +#define CONF_XOSC1_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc1_arch_cfden +#ifndef CONF_XOSC1_CFDEN +#define CONF_XOSC1_CFDEN 0 +#endif + +// Automatic Loop Control Enable +// Indicates whether Automatic Loop Control is enabled or not +// xosc1_arch_enalc +#ifndef CONF_XOSC1_ENALC +#define CONF_XOSC1_ENALC 0 +#endif + +// Low Buffer Gain Enable +// Indicates whether Low Buffer Gain is enabled or not +// xosc1_arch_lowbufgain +#ifndef CONF_XOSC1_LOWBUFGAIN +#define CONF_XOSC1_LOWBUFGAIN 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc1_arch_ondemand +#ifndef CONF_XOSC1_ONDEMAND +#define CONF_XOSC1_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc1_arch_runstdby +#ifndef CONF_XOSC1_RUNSTDBY +#define CONF_XOSC1_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc1_arch_xtalen +#ifndef CONF_XOSC1_XTALEN +#define CONF_XOSC1_XTALEN 1 +#endif +// +// + +#if CONF_XOSC1_FREQUENCY >= 32000000 +#define CONF_XOSC1_CFDPRESC 0x0 +#define CONF_XOSC1_IMULT 0x7 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 24000000 +#define CONF_XOSC1_CFDPRESC 0x1 +#define CONF_XOSC1_IMULT 0x6 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 16000000 +#define CONF_XOSC1_CFDPRESC 0x2 +#define CONF_XOSC1_IMULT 0x5 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 8000000 +#define CONF_XOSC1_CFDPRESC 0x3 +#define CONF_XOSC1_IMULT 0x4 +#define CONF_XOSC1_IPTAT 0x3 +#endif + +// DFLL Configuration +// Indicates whether configuration for DFLL is enabled or not +// enable_dfll +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 0 +#endif + +// Reference Clock Source +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source +// dfll_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +// Digital Frequency Locked Loop Control +// DFLL Enable +// Indicates whether DFLL is enabled or not +// dfll_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// dfll_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// dfll_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// USB Clock Recovery Mode +// Indicates whether USB Clock Recovery Mode is enabled or not +// dfll_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 0 +#endif + +// Wait Lock +// Indicates whether Wait Lock is enabled or not +// dfll_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 1 +#endif + +// Bypass Coarse Lock +// Indicates whether Bypass Coarse Lock is enabled or not +// dfll_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// Quick Lock Disable +// Indicates whether Quick Lock Disable is enabled or not +// dfll_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// Chill Cycle Disable +// Indicates whether Chill Cycle Disable is enabled or not +// dfll_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 0 +#endif + +// Lose Lock After Wake +// Indicates whether Lose Lock After Wake is enabled or not +// dfll_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// Stable DFLL Frequency +// Indicates whether Stable DFLL Frequency is enabled or not +// dfll_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// Operating Mode Selection +// <0=>Open Loop Mode +// <1=>Closed Loop Mode +// dfll_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE 0x0 +#endif + +// Coarse Maximum Step <0x0-0x1F> +// dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 0x1 +#endif + +// Fine Maximum Step <0x0-0xFF> +// dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 0x1 +#endif + +// DFLL Multiply Factor <0x0-0xFFFF> +// dfll_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 0x0 +#endif + +// DFLL Calibration Overwrite +// Indicates whether Overwrite Calibration value of DFLL +// dfll_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 0 +#endif + +// Coarse Value <0x0-0x3F> +// dfll_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0x1f / 4) +#endif + +// Fine Value <0x0-0xFF> +// dfll_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x80) +#endif + +// + +// + +// + +// FDPLL0 Configuration +// Indicates whether configuration for FDPLL0 is enabled or not +// enable_fdpll0 +#ifndef CONF_FDPLL0_CONFIG +#define CONF_FDPLL0_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source. +// fdpll0_ref_clock +#ifndef CONF_FDPLL0_GCLK +#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll0_arch_enable +#ifndef CONF_FDPLL0_ENABLE +#define CONF_FDPLL0_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll0_arch_ondemand +#ifndef CONF_FDPLL0_ONDEMAND +#define CONF_FDPLL0_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll0_arch_runstdby +#ifndef CONF_FDPLL0_RUNSTDBY +#define CONF_FDPLL0_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0x1F> +// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll0_ldrfrac +#ifndef CONF_FDPLL0_LDRFRAC +#define CONF_FDPLL0_LDRFRAC 0xd +#endif + +// Loop Divider Ratio Integer Part <0x0-0x1FFF> +// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll0_ldr +#ifndef CONF_FDPLL0_LDR +#define CONF_FDPLL0_LDR 0x5b7 +#endif + +// Clock Divider <0x0-0x7FF> +// This Clock divider is only for XOSC clock input to DPLL +// fdpll0_clock_div +#ifndef CONF_FDPLL0_DIV +#define CONF_FDPLL0_DIV 0x0 +#endif + +// DCO Filter Enable +// Indicates whether DCO Filter Enable is enabled or not +// fdpll0_arch_dcoen +#ifndef CONF_FDPLL0_DCOEN +#define CONF_FDPLL0_DCOEN 0 +#endif + +// Sigma-Delta DCO Filter Selection <0x0-0x7> +// fdpll0_clock_dcofilter +#ifndef CONF_FDPLL0_DCOFILTER +#define CONF_FDPLL0_DCOFILTER 0x0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll0_arch_lbypass +#ifndef CONF_FDPLL0_LBYPASS +#define CONF_FDPLL0_LBYPASS 0 +#endif + +// Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// fdpll0_arch_ltime +#ifndef CONF_FDPLL0_LTIME +#define CONF_FDPLL0_LTIME 0x0 +#endif + +// Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// fdpll0_arch_refclk +#ifndef CONF_FDPLL0_REFCLK +#define CONF_FDPLL0_REFCLK 0x1 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll0_arch_wuf +#ifndef CONF_FDPLL0_WUF +#define CONF_FDPLL0_WUF 0 +#endif + +// Proportional Integral Filter Selection <0x0-0xF> +// fdpll0_arch_filter +#ifndef CONF_FDPLL0_FILTER +#define CONF_FDPLL0_FILTER 0x0 +#endif + +// +// +// FDPLL1 Configuration +// Indicates whether configuration for FDPLL1 is enabled or not +// enable_fdpll1 +#ifndef CONF_FDPLL1_CONFIG +#define CONF_FDPLL1_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source. +// fdpll1_ref_clock +#ifndef CONF_FDPLL1_GCLK +#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll1_arch_enable +#ifndef CONF_FDPLL1_ENABLE +#define CONF_FDPLL1_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll1_arch_ondemand +#ifndef CONF_FDPLL1_ONDEMAND +#define CONF_FDPLL1_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll1_arch_runstdby +#ifndef CONF_FDPLL1_RUNSTDBY +#define CONF_FDPLL1_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0x1F> +// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll1_ldrfrac +#ifndef CONF_FDPLL1_LDRFRAC +#define CONF_FDPLL1_LDRFRAC 0xd +#endif + +// Loop Divider Ratio Integer Part <0x0-0x1FFF> +// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll1_ldr +#ifndef CONF_FDPLL1_LDR +#define CONF_FDPLL1_LDR 0x5b7 +#endif + +// Clock Divider <0x0-0x7FF> +// This Clock divider is only for XOSC clock input to DPLL +// fdpll1_clock_div +#ifndef CONF_FDPLL1_DIV +#define CONF_FDPLL1_DIV 0x0 +#endif + +// DCO Filter Enable +// Indicates whether DCO Filter Enable is enabled or not +// fdpll1_arch_dcoen +#ifndef CONF_FDPLL1_DCOEN +#define CONF_FDPLL1_DCOEN 0 +#endif + +// Sigma-Delta DCO Filter Selection <0x0-0x7> +// fdpll1_clock_dcofilter +#ifndef CONF_FDPLL1_DCOFILTER +#define CONF_FDPLL1_DCOFILTER 0x0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll1_arch_lbypass +#ifndef CONF_FDPLL1_LBYPASS +#define CONF_FDPLL1_LBYPASS 0 +#endif + +// Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// fdpll1_arch_ltime +#ifndef CONF_FDPLL1_LTIME +#define CONF_FDPLL1_LTIME 0x0 +#endif + +// Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// fdpll1_arch_refclk +#ifndef CONF_FDPLL1_REFCLK +#define CONF_FDPLL1_REFCLK 0x1 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll1_arch_wuf +#ifndef CONF_FDPLL1_WUF +#define CONF_FDPLL1_WUF 0 +#endif + +// Proportional Integral Filter Selection <0x0-0xF> +// fdpll1_arch_filter +#ifndef CONF_FDPLL1_FILTER +#define CONF_FDPLL1_FILTER 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSCCTRL_CONFIG_H diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_port_config.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_port_config.h new file mode 100644 index 0000000..b5315f0 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_port_config.h @@ -0,0 +1,522 @@ +/* Auto-generated config file hpl_port_config.h */ +#ifndef HPL_PORT_CONFIG_H +#define HPL_PORT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// PORT Input Event 0 configuration +// enable_port_input_event_0 +#ifndef CONF_PORT_EVCTRL_PORT_0 +#define CONF_PORT_EVCTRL_PORT_0 0 +#endif + +// PORT Input Event 0 configuration on PORT A + +// PORTA Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled +// porta_input_event_enable_0 +#ifndef CONF_PORTA_EVCTRL_PORTEI_0 +#define CONF_PORTA_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTA Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_0 +#ifndef CONF_PORTA_EVCTRL_PID_0 +#define CONF_PORTA_EVCTRL_PID_0 0x0 +#endif + +// PORTA Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 0 +// porta_event_action_0 +#ifndef CONF_PORTA_EVCTRL_EVACT_0 +#define CONF_PORTA_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT B + +// PORTB Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled +// portb_input_event_enable_0 +#ifndef CONF_PORTB_EVCTRL_PORTEI_0 +#define CONF_PORTB_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTB Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_0 +#ifndef CONF_PORTB_EVCTRL_PID_0 +#define CONF_PORTB_EVCTRL_PID_0 0x0 +#endif + +// PORTB Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 0 +// portb_event_action_0 +#ifndef CONF_PORTB_EVCTRL_EVACT_0 +#define CONF_PORTB_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT C + +// PORTC Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 0 configuration is enabled +// portc_input_event_enable_0 +#ifndef CONF_PORTC_EVCTRL_PORTEI_0 +#define CONF_PORTC_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTC Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_0 +#ifndef CONF_PORTC_EVCTRL_PID_0 +#define CONF_PORTC_EVCTRL_PID_0 0x0 +#endif + +// PORTC Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 0 +// portc_event_action_0 +#ifndef CONF_PORTC_EVCTRL_EVACT_0 +#define CONF_PORTC_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT D + +// PORTD Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT D Input Event 0 configuration is enabled +// portd_input_event_enable_0 +#ifndef CONF_PORTD_EVCTRL_PORTEI_0 +#define CONF_PORTD_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTD Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port D on which the event action will be performed +// portd_event_pin_identifier_0 +#ifndef CONF_PORTD_EVCTRL_PID_0 +#define CONF_PORTD_EVCTRL_PID_0 0x0 +#endif + +// PORTD Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT D will perform on event input 0 +// portd_event_action_0 +#ifndef CONF_PORTD_EVCTRL_EVACT_0 +#define CONF_PORTD_EVCTRL_EVACT_0 0 +#endif + +// + +// + +// PORT Input Event 1 configuration +// enable_port_input_event_1 +#ifndef CONF_PORT_EVCTRL_PORT_1 +#define CONF_PORT_EVCTRL_PORT_1 0 +#endif + +// PORT Input Event 1 configuration on PORT A + +// PORTA Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled +// porta_input_event_enable_1 +#ifndef CONF_PORTA_EVCTRL_PORTEI_1 +#define CONF_PORTA_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTA Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_1 +#ifndef CONF_PORTA_EVCTRL_PID_1 +#define CONF_PORTA_EVCTRL_PID_1 0x0 +#endif + +// PORTA Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 1 +// porta_event_action_1 +#ifndef CONF_PORTA_EVCTRL_EVACT_1 +#define CONF_PORTA_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT B + +// PORTB Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled +// portb_input_event_enable_1 +#ifndef CONF_PORTB_EVCTRL_PORTEI_1 +#define CONF_PORTB_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTB Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_1 +#ifndef CONF_PORTB_EVCTRL_PID_1 +#define CONF_PORTB_EVCTRL_PID_1 0x0 +#endif + +// PORTB Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 1 +// portb_event_action_1 +#ifndef CONF_PORTB_EVCTRL_EVACT_1 +#define CONF_PORTB_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT C + +// PORTC Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 1 configuration is enabled +// portc_input_event_enable_1 +#ifndef CONF_PORTC_EVCTRL_PORTEI_1 +#define CONF_PORTC_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTC Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_1 +#ifndef CONF_PORTC_EVCTRL_PID_1 +#define CONF_PORTC_EVCTRL_PID_1 0x0 +#endif + +// PORTC Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 1 +// portc_event_action_1 +#ifndef CONF_PORTC_EVCTRL_EVACT_1 +#define CONF_PORTC_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT D + +// PORTD Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT D Input Event 1 configuration is enabled +// portd_input_event_enable_1 +#ifndef CONF_PORTD_EVCTRL_PORTEI_1 +#define CONF_PORTD_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTD Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port D on which the event action will be performed +// portd_event_pin_identifier_1 +#ifndef CONF_PORTD_EVCTRL_PID_1 +#define CONF_PORTD_EVCTRL_PID_1 0x0 +#endif + +// PORTD Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT D will perform on event input 1 +// portd_event_action_1 +#ifndef CONF_PORTD_EVCTRL_EVACT_1 +#define CONF_PORTD_EVCTRL_EVACT_1 0 +#endif + +// + +// + +// PORT Input Event 2 configuration +// enable_port_input_event_2 +#ifndef CONF_PORT_EVCTRL_PORT_2 +#define CONF_PORT_EVCTRL_PORT_2 0 +#endif + +// PORT Input Event 2 configuration on PORT A + +// PORTA Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled +// porta_input_event_enable_2 +#ifndef CONF_PORTA_EVCTRL_PORTEI_2 +#define CONF_PORTA_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTA Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_2 +#ifndef CONF_PORTA_EVCTRL_PID_2 +#define CONF_PORTA_EVCTRL_PID_2 0x0 +#endif + +// PORTA Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 2 +// porta_event_action_2 +#ifndef CONF_PORTA_EVCTRL_EVACT_2 +#define CONF_PORTA_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT B + +// PORTB Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled +// portb_input_event_enable_2 +#ifndef CONF_PORTB_EVCTRL_PORTEI_2 +#define CONF_PORTB_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTB Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_2 +#ifndef CONF_PORTB_EVCTRL_PID_2 +#define CONF_PORTB_EVCTRL_PID_2 0x0 +#endif + +// PORTB Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 2 +// portb_event_action_2 +#ifndef CONF_PORTB_EVCTRL_EVACT_2 +#define CONF_PORTB_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT C + +// PORTC Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 2 configuration is enabled +// portc_input_event_enable_2 +#ifndef CONF_PORTC_EVCTRL_PORTEI_2 +#define CONF_PORTC_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTC Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_2 +#ifndef CONF_PORTC_EVCTRL_PID_2 +#define CONF_PORTC_EVCTRL_PID_2 0x0 +#endif + +// PORTC Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 2 +// portc_event_action_2 +#ifndef CONF_PORTC_EVCTRL_EVACT_2 +#define CONF_PORTC_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT D + +// PORTD Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT D Input Event 2 configuration is enabled +// portd_input_event_enable_2 +#ifndef CONF_PORTD_EVCTRL_PORTEI_2 +#define CONF_PORTD_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTD Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port D on which the event action will be performed +// portd_event_pin_identifier_2 +#ifndef CONF_PORTD_EVCTRL_PID_2 +#define CONF_PORTD_EVCTRL_PID_2 0x0 +#endif + +// PORTD Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT D will perform on event input 2 +// portd_event_action_2 +#ifndef CONF_PORTD_EVCTRL_EVACT_2 +#define CONF_PORTD_EVCTRL_EVACT_2 0 +#endif + +// + +// + +// PORT Input Event 3 configuration +// enable_port_input_event_3 +#ifndef CONF_PORT_EVCTRL_PORT_3 +#define CONF_PORT_EVCTRL_PORT_3 0 +#endif + +// PORT Input Event 3 configuration on PORT A + +// PORTA Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled +// porta_input_event_enable_3 +#ifndef CONF_PORTA_EVCTRL_PORTEI_3 +#define CONF_PORTA_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTA Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_3 +#ifndef CONF_PORTA_EVCTRL_PID_3 +#define CONF_PORTA_EVCTRL_PID_3 0x0 +#endif + +// PORTA Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 3 +// porta_event_action_3 +#ifndef CONF_PORTA_EVCTRL_EVACT_3 +#define CONF_PORTA_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT B + +// PORTB Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled +// portb_input_event_enable_3 +#ifndef CONF_PORTB_EVCTRL_PORTEI_3 +#define CONF_PORTB_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTB Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_3 +#ifndef CONF_PORTB_EVCTRL_PID_3 +#define CONF_PORTB_EVCTRL_PID_3 0x0 +#endif + +// PORTB Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 3 +// portb_event_action_3 +#ifndef CONF_PORTB_EVCTRL_EVACT_3 +#define CONF_PORTB_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT C + +// PORTC Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 3 configuration is enabled +// portc_input_event_enable_3 +#ifndef CONF_PORTC_EVCTRL_PORTEI_3 +#define CONF_PORTC_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTC Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_3 +#ifndef CONF_PORTC_EVCTRL_PID_3 +#define CONF_PORTC_EVCTRL_PID_3 0x0 +#endif + +// PORTC Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 3 +// portc_event_action_3 +#ifndef CONF_PORTC_EVCTRL_EVACT_3 +#define CONF_PORTC_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT D + +// PORTD Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT D Input Event 3 configuration is enabled +// portd_input_event_enable_3 +#ifndef CONF_PORTD_EVCTRL_PORTEI_3 +#define CONF_PORTD_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTD Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port D on which the event action will be performed +// portd_event_pin_identifier_3 +#ifndef CONF_PORTD_EVCTRL_PID_3 +#define CONF_PORTD_EVCTRL_PID_3 0x0 +#endif + +// PORTD Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT D will perform on event input 3 +// portd_event_action_3 +#ifndef CONF_PORTD_EVCTRL_EVACT_3 +#define CONF_PORTD_EVCTRL_EVACT_3 0 +#endif + +// + +// + +#define CONF_PORTA_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ + | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ + | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) +#define CONF_PORTB_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ + | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ + | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) +#define CONF_PORTC_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1) \ + | CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \ + | CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3)) +#define CONF_PORTD_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTD_EVCTRL_EVACT_0) | CONF_PORTD_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTD_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTD_EVCTRL_EVACT_1) \ + | CONF_PORTD_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTD_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTD_EVCTRL_EVACT_2) | CONF_PORTD_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTD_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTD_EVCTRL_EVACT_3) \ + | CONF_PORTD_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTD_EVCTRL_PID_3)) + +// <<< end of configuration section >>> + +#endif // HPL_PORT_CONFIG_H diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_sercom_config.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_sercom_config.h new file mode 100644 index 0000000..d026384 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_sercom_config.h @@ -0,0 +1,618 @@ +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 1 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable input buffer in SERCOM module +// usart_rx_enable +#ifndef CONF_SERCOM_2_USART_RXEN +#define CONF_SERCOM_2_USART_RXEN 1 +#endif + +// Transmitt buffer enable +// Enable output buffer in SERCOM module +// usart_tx_enable +#ifndef CONF_SERCOM_2_USART_TXEN +#define CONF_SERCOM_2_USART_TXEN 1 +#endif + +// Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_SERCOM_2_USART_PARITY +#define CONF_SERCOM_2_USART_PARITY 0x0 +#endif + +// Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_SERCOM_2_USART_CHSIZE +#define CONF_SERCOM_2_USART_CHSIZE 0x0 +#endif + +// Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_SERCOM_2_USART_SBMODE +#define CONF_SERCOM_2_USART_SBMODE 0 +#endif + +// Baud rate <1-6250000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_SERCOM_2_USART_BAUD +#define CONF_SERCOM_2_USART_BAUD 9600 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG +#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0 +#endif + +// Run in stand-by +// Keep the module running in standby sleep mode +// usart_arch_runstdby +#ifndef CONF_SERCOM_2_USART_RUNSTDBY +#define CONF_SERCOM_2_USART_RUNSTDBY 0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when the BUFOVF status bit is asserted +// usart_arch_ibon +#ifndef CONF_SERCOM_2_USART_IBON +#define CONF_SERCOM_2_USART_IBON 0 +#endif + +// Start of Frame Detection Enable +// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// usart_arch_sfde +#ifndef CONF_SERCOM_2_USART_SFDE +#define CONF_SERCOM_2_USART_SFDE 0 +#endif + +// Collision Detection Enable +// Collision detection enable +// usart_arch_cloden +#ifndef CONF_SERCOM_2_USART_CLODEN +#define CONF_SERCOM_2_USART_CLODEN 0 +#endif + +// Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// usart_arch_clock_mode +#ifndef CONF_SERCOM_2_USART_MODE +#define CONF_SERCOM_2_USART_MODE 0x1 +#endif + +// Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x4=>3x arithmetic +// How many over-sampling bits used when sampling data state +// usart_arch_sampr +#ifndef CONF_SERCOM_2_USART_SAMPR +#define CONF_SERCOM_2_USART_SAMPR 0x0 +#endif + +// Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// Adjust which samples to use for data sampling in asynchronous mode +// usart_arch_sampa +#ifndef CONF_SERCOM_2_USART_SAMPA +#define CONF_SERCOM_2_USART_SAMPA 0x0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_SERCOM_2_USART_FRACTIONAL +#define CONF_SERCOM_2_USART_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_dord +#ifndef CONF_SERCOM_2_USART_DORD +#define CONF_SERCOM_2_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_2_USART_CPOL 0 + +// Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// usart_arch_enc +#ifndef CONF_SERCOM_2_USART_ENC +#define CONF_SERCOM_2_USART_ENC 0 +#endif + +// LIN Slave Enable +// Break Character Detection and Auto-Baud/LIN Slave Enable. +// Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). +// <0=>Disable +// <1=>Enable +// usart_arch_lin_slave_enable +#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE +#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// usart_arch_dbgstop +#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_2_USART_INACK +#define CONF_SERCOM_2_USART_INACK 0x0 +#endif + +#ifndef CONF_SERCOM_2_USART_DSNACK +#define CONF_SERCOM_2_USART_DSNACK 0x0 +#endif + +#ifndef CONF_SERCOM_2_USART_MAXITER +#define CONF_SERCOM_2_USART_MAXITER 0x7 +#endif + +#ifndef CONF_SERCOM_2_USART_GTIME +#define CONF_SERCOM_2_USART_GTIME 0x2 +#endif + +#define CONF_SERCOM_2_USART_RXINV 0x0 +#define CONF_SERCOM_2_USART_TXINV 0x0 + +#ifndef CONF_SERCOM_2_USART_CMODE +#define CONF_SERCOM_2_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_2_USART_RXPO +#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */ +#endif + +#ifndef CONF_SERCOM_2_USART_TXPO +#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1 +#if CONF_SERCOM_2_USART_PARITY == 0 +#define CONF_SERCOM_2_USART_PMODE 0 +#define CONF_SERCOM_2_USART_FORM 4 +#else +#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 +#define CONF_SERCOM_2_USART_FORM 5 +#endif +#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */ +#if CONF_SERCOM_2_USART_PARITY == 0 +#define CONF_SERCOM_2_USART_PMODE 0 +#define CONF_SERCOM_2_USART_FORM 0 +#else +#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 +#define CONF_SERCOM_2_USART_FORM 1 +#endif +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_2_USART_SAMPR == 0 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 1 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 2 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 3 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 4 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +#include + +// Enable configuration of module +#ifndef CONF_SERCOM_4_SPI_ENABLE +#define CONF_SERCOM_4_SPI_ENABLE 1 +#endif + +// SPI DMA TX Channel <0-32> +// This defines DMA channel to be used +// spi_master_dma_tx_channel +#ifndef CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL +#define CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL 2 +#endif + +// SPI RX Channel Enable +// spi_master_rx_channel +#ifndef CONF_SERCOM_4_SPI_RX_CHANNEL +#define CONF_SERCOM_4_SPI_RX_CHANNEL 1 +#endif + +// DMA Channel <0-32> +// This defines DMA channel to be used +// spi_master_dma_rx_channel +#ifndef CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL +#define CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL 3 +#endif + +// + +// Set module in SPI Master mode +#ifndef CONF_SERCOM_4_SPI_MODE +#define CONF_SERCOM_4_SPI_MODE 0x03 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable receive buffer to receive data from slave (RXEN) +// spi_master_rx_enable +#ifndef CONF_SERCOM_4_SPI_RXEN +#define CONF_SERCOM_4_SPI_RXEN 0x1 +#endif + +// Character Size +// Bit size for all characters sent over the SPI bus (CHSIZE) +// <0x0=>8 bits +// <0x1=>9 bits +// spi_master_character_size +#ifndef CONF_SERCOM_4_SPI_CHSIZE +#define CONF_SERCOM_4_SPI_CHSIZE 0x0 +#endif +// Baud rate <1-18000000> +// The SPI data transfer rate +// spi_master_baud_rate +#ifndef CONF_SERCOM_4_SPI_BAUD +#define CONF_SERCOM_4_SPI_BAUD 1000000 +#endif + +// + +// Advanced Configuration +// spi_master_advanced +#ifndef CONF_SERCOM_4_SPI_ADVANCED +#define CONF_SERCOM_4_SPI_ADVANCED 0 +#endif + +// Dummy byte <0x00-0x1ff> +// spi_master_dummybyte +// Dummy byte used when reading data from the slave without sending any data +#ifndef CONF_SERCOM_4_SPI_DUMMYBYTE +#define CONF_SERCOM_4_SPI_DUMMYBYTE 0x1ff +#endif + +// Data Order +// <0=>MSB first +// <1=>LSB first +// I least significant or most significant bit is shifted out first (DORD) +// spi_master_arch_dord +#ifndef CONF_SERCOM_4_SPI_DORD +#define CONF_SERCOM_4_SPI_DORD 0x0 +#endif + +// Clock Polarity +// <0=>SCK is low when idle +// <1=>SCK is high when idle +// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) +// spi_master_arch_cpol +#ifndef CONF_SERCOM_4_SPI_CPOL +#define CONF_SERCOM_4_SPI_CPOL 0x0 +#endif + +// Clock Phase +// <0x0=>Sample input on leading edge +// <0x1=>Sample input on trailing edge +// Determines if input data is sampled on leading or trailing SCK edge. (CPHA) +// spi_master_arch_cpha +#ifndef CONF_SERCOM_4_SPI_CPHA +#define CONF_SERCOM_4_SPI_CPHA 0x0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when OVF is asserted (IBON) +// <0x0=>In data stream +// <0x1=>On buffer overflow +// spi_master_arch_ibon +#ifndef CONF_SERCOM_4_SPI_IBON +#define CONF_SERCOM_4_SPI_IBON 0x0 +#endif + +// Run in stand-by +// Module stays active in stand-by sleep mode. (RUNSTDBY) +// spi_master_arch_runstdby +#ifndef CONF_SERCOM_4_SPI_RUNSTDBY +#define CONF_SERCOM_4_SPI_RUNSTDBY 0x0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) +// <0=>Keep running +// <1=>Halt +// spi_master_arch_dbgstop +#ifndef CONF_SERCOM_4_SPI_DBGSTOP +#define CONF_SERCOM_4_SPI_DBGSTOP 0 +#endif + +// + +// Address mode disabled in master mode +#ifndef CONF_SERCOM_4_SPI_AMODE_EN +#define CONF_SERCOM_4_SPI_AMODE_EN 0 +#endif + +#ifndef CONF_SERCOM_4_SPI_AMODE +#define CONF_SERCOM_4_SPI_AMODE 0 +#endif + +#ifndef CONF_SERCOM_4_SPI_ADDR +#define CONF_SERCOM_4_SPI_ADDR 0 +#endif + +#ifndef CONF_SERCOM_4_SPI_ADDRMASK +#define CONF_SERCOM_4_SPI_ADDRMASK 0 +#endif + +#ifndef CONF_SERCOM_4_SPI_SSDE +#define CONF_SERCOM_4_SPI_SSDE 0 +#endif + +#ifndef CONF_SERCOM_4_SPI_MSSEN +#define CONF_SERCOM_4_SPI_MSSEN 0x0 +#endif + +#ifndef CONF_SERCOM_4_SPI_PLOADEN +#define CONF_SERCOM_4_SPI_PLOADEN 0 +#endif + +// Receive Data Pinout +// <0x0=>PAD[0] +// <0x1=>PAD[1] +// <0x2=>PAD[2] +// <0x3=>PAD[3] +// spi_master_rxpo +#ifndef CONF_SERCOM_4_SPI_RXPO +#define CONF_SERCOM_4_SPI_RXPO 3 +#endif + +// Transmit Data Pinout +// <0x0=>PAD[0,1]_DO_SCK +// <0x1=>PAD[2,3]_DO_SCK +// <0x2=>PAD[3,1]_DO_SCK +// <0x3=>PAD[0,3]_DO_SCK +// spi_master_txpo +#ifndef CONF_SERCOM_4_SPI_TXPO +#define CONF_SERCOM_4_SPI_TXPO 0 +#endif + +// Calculate baud register value from requested baudrate value +#ifndef CONF_SERCOM_4_SPI_BAUD_RATE +#define CONF_SERCOM_4_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM4_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_4_SPI_BAUD)) - 1 +#endif + +#include + +// Enable configuration of module +#ifndef CONF_SERCOM_6_SPI_ENABLE +#define CONF_SERCOM_6_SPI_ENABLE 1 +#endif + +// Set module in SPI Master mode +#ifndef CONF_SERCOM_6_SPI_MODE +#define CONF_SERCOM_6_SPI_MODE 0x03 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable receive buffer to receive data from slave (RXEN) +// spi_master_rx_enable +#ifndef CONF_SERCOM_6_SPI_RXEN +#define CONF_SERCOM_6_SPI_RXEN 0x1 +#endif + +// Character Size +// Bit size for all characters sent over the SPI bus (CHSIZE) +// <0x0=>8 bits +// <0x1=>9 bits +// spi_master_character_size +#ifndef CONF_SERCOM_6_SPI_CHSIZE +#define CONF_SERCOM_6_SPI_CHSIZE 0x0 +#endif +// Baud rate <1-18000000> +// The SPI data transfer rate +// spi_master_baud_rate +#ifndef CONF_SERCOM_6_SPI_BAUD +#define CONF_SERCOM_6_SPI_BAUD 1000000 +#endif + +// + +// Advanced Configuration +// spi_master_advanced +#ifndef CONF_SERCOM_6_SPI_ADVANCED +#define CONF_SERCOM_6_SPI_ADVANCED 1 +#endif + +// Dummy byte <0x00-0x1ff> +// spi_master_dummybyte +// Dummy byte used when reading data from the slave without sending any data +#ifndef CONF_SERCOM_6_SPI_DUMMYBYTE +#define CONF_SERCOM_6_SPI_DUMMYBYTE 0x1ff +#endif + +// Data Order +// <0=>MSB first +// <1=>LSB first +// I least significant or most significant bit is shifted out first (DORD) +// spi_master_arch_dord +#ifndef CONF_SERCOM_6_SPI_DORD +#define CONF_SERCOM_6_SPI_DORD 0x0 +#endif + +// Clock Polarity +// <0=>SCK is low when idle +// <1=>SCK is high when idle +// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) +// spi_master_arch_cpol +#ifndef CONF_SERCOM_6_SPI_CPOL +#define CONF_SERCOM_6_SPI_CPOL 0x1 +#endif + +// Clock Phase +// <0x0=>Sample input on leading edge +// <0x1=>Sample input on trailing edge +// Determines if input data is sampled on leading or trailing SCK edge. (CPHA) +// spi_master_arch_cpha +#ifndef CONF_SERCOM_6_SPI_CPHA +#define CONF_SERCOM_6_SPI_CPHA 0x1 +#endif + +// Immediate Buffer Overflow Notification +// Controls when OVF is asserted (IBON) +// <0x0=>In data stream +// <0x1=>On buffer overflow +// spi_master_arch_ibon +#ifndef CONF_SERCOM_6_SPI_IBON +#define CONF_SERCOM_6_SPI_IBON 0x0 +#endif + +// Run in stand-by +// Module stays active in stand-by sleep mode. (RUNSTDBY) +// spi_master_arch_runstdby +#ifndef CONF_SERCOM_6_SPI_RUNSTDBY +#define CONF_SERCOM_6_SPI_RUNSTDBY 0x0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) +// <0=>Keep running +// <1=>Halt +// spi_master_arch_dbgstop +#ifndef CONF_SERCOM_6_SPI_DBGSTOP +#define CONF_SERCOM_6_SPI_DBGSTOP 0 +#endif + +// + +// Address mode disabled in master mode +#ifndef CONF_SERCOM_6_SPI_AMODE_EN +#define CONF_SERCOM_6_SPI_AMODE_EN 0 +#endif + +#ifndef CONF_SERCOM_6_SPI_AMODE +#define CONF_SERCOM_6_SPI_AMODE 0 +#endif + +#ifndef CONF_SERCOM_6_SPI_ADDR +#define CONF_SERCOM_6_SPI_ADDR 0 +#endif + +#ifndef CONF_SERCOM_6_SPI_ADDRMASK +#define CONF_SERCOM_6_SPI_ADDRMASK 0 +#endif + +#ifndef CONF_SERCOM_6_SPI_SSDE +#define CONF_SERCOM_6_SPI_SSDE 0 +#endif + +#ifndef CONF_SERCOM_6_SPI_MSSEN +#define CONF_SERCOM_6_SPI_MSSEN 0x0 +#endif + +#ifndef CONF_SERCOM_6_SPI_PLOADEN +#define CONF_SERCOM_6_SPI_PLOADEN 0 +#endif + +// Receive Data Pinout +// <0x0=>PAD[0] +// <0x1=>PAD[1] +// <0x2=>PAD[2] +// <0x3=>PAD[3] +// spi_master_rxpo +#ifndef CONF_SERCOM_6_SPI_RXPO +#define CONF_SERCOM_6_SPI_RXPO 3 +#endif + +// Transmit Data Pinout +// <0x0=>PAD[0,1]_DO_SCK +// <0x1=>PAD[2,3]_DO_SCK +// <0x2=>PAD[3,1]_DO_SCK +// <0x3=>PAD[0,3]_DO_SCK +// spi_master_txpo +#ifndef CONF_SERCOM_6_SPI_TXPO +#define CONF_SERCOM_6_SPI_TXPO 0 +#endif + +// Calculate baud register value from requested baudrate value +#ifndef CONF_SERCOM_6_SPI_BAUD_RATE +#define CONF_SERCOM_6_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM6_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_6_SPI_BAUD)) - 1 +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_tc_config.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_tc_config.h new file mode 100644 index 0000000..6003f1f --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_tc_config.h @@ -0,0 +1,180 @@ +/* Auto-generated config file hpl_tc_config.h */ +#ifndef HPL_TC_CONFIG_H +#define HPL_TC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef CONF_TC0_ENABLE +#define CONF_TC0_ENABLE 1 +#endif + +#include "peripheral_clk_config.h" + +// Basic configuration + +// Prescaler +// <0x0=> No division +// <0x1=> Divide by 2 +// <0x2=> Divide by 4 +// <0x3=> Divide by 8 +// <0x4=> Divide by 16 +// <0x5=> Divide by 64 +// <0x6=> Divide by 256 +// <0x7=> Divide by 1024 +// This defines the prescaler value +// timer_prescaler +#ifndef CONF_TC0_PRESCALER +#define CONF_TC0_PRESCALER 0x3 +#endif + +// Length of one timer tick in uS <0-4294967295> +// timer_tick +#ifndef CONF_TC0_TIMER_TICK +#define CONF_TC0_TIMER_TICK 1000 +#endif +// + +// Advanced configuration +// timer_advanced_configuration +#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE +#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 0 +#endif + +// Prescaler and Counter Synchronization Selection +// Reload or reset counter on next GCLK +// Reload or reset counter on next prescaler clock +// Reload or reset counter on next GCLK and reset prescaler counter +// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. +// tc_arch_presync +#ifndef CONF_TC0_PRESCSYNC +#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +// Run in standby +// Indicates whether the module will continue to run in standby sleep mode +// tc_arch_runstdby +#ifndef CONF_TC0_RUNSTDBY +#define CONF_TC0_RUNSTDBY 0 +#endif + +// Run in debug mode +// Indicates whether the module will run in debug mode +// tc_arch_dbgrun +#ifndef CONF_TC0_DBGRUN +#define CONF_TC0_DBGRUN 0 +#endif + +// Run on demand +// Run if requested by some other peripheral in the device +// tc_arch_ondemand +#ifndef CONF_TC0_ONDEMAND +#define CONF_TC0_ONDEMAND 0 +#endif + +// + +// Event control +// timer_event_control +#ifndef CONF_TC0_EVENT_CONTROL_ENABLE +#define CONF_TC0_EVENT_CONTROL_ENABLE 1 +#endif + +// Output Event On Match or Capture on Channel 0 +// Enable output of event on timer tick +// tc_arch_mceo0 +#ifndef CONF_TC0_MCEO0 +#define CONF_TC0_MCEO0 0 +#endif + +// Output Event On Match or Capture on Channel 1 +// Enable output of event on timer tick +// tc_arch_mceo1 +#ifndef CONF_TC0_MCEO1 +#define CONF_TC0_MCEO1 0 +#endif + +// Output Event On Timer Tick +// Enable output of event on timer tick +// tc_arch_ovfeo +#ifndef CONF_TC0_OVFEO +#define CONF_TC0_OVFEO 0 +#endif + +// Event Input +// Enable asynchronous input events +// tc_arch_tcei +#ifndef CONF_TC0_TCEI +#define CONF_TC0_TCEI 0 +#endif + +// Inverted Event Input +// Invert the asynchronous input events +// tc_arch_tcinv +#ifndef CONF_TC0_TCINV +#define CONF_TC0_TCINV 0 +#endif + +// Event action +// <0=> Event action disabled +// <1=> Start, restart or re-trigger TC on event +// <2=> Count on event +// <3=> Start on event +// <4=> Time stamp capture +// <5=> Period captured in CC0, pulse width in CC1 +// <6=> Period captured in CC1, pulse width in CC0 +// <7=> Pulse width capture +// Event which will be performed on an event +// tc_arch_evact +#ifndef CONF_TC0_EVACT +#define CONF_TC0_EVACT 0 +#endif +// + +// Default values which the driver needs in order to work correctly + +// Mode set to 32-bit +#ifndef CONF_TC0_MODE +#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val +#endif + +// CC 1 register set to 0 +#ifndef CONF_TC0_CC1 +#define CONF_TC0_CC1 0 +#endif + +#ifndef CONF_TC0_ALOCK +#define CONF_TC0_ALOCK 0 +#endif + +// Not used in 32-bit mode +#define CONF_TC0_PER 0 + +// Calculating correct top value based on requested tick interval. +#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER) + +// Prescaler set to 64 +#if CONF_TC0_PRESCALER > 0x4 +#undef CONF_TC0_PRESCALE +#define CONF_TC0_PRESCALE 64 +#endif + +// Prescaler set to 256 +#if CONF_TC0_PRESCALER > 0x5 +#undef CONF_TC0_PRESCALE +#define CONF_TC0_PRESCALE 256 +#endif + +// Prescaler set to 1024 +#if CONF_TC0_PRESCALER > 0x6 +#undef CONF_TC0_PRESCALE +#define CONF_TC0_PRESCALE 1024 +#endif + +#ifndef CONF_TC0_CC0 +#define CONF_TC0_CC0 \ + (uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE))) +#endif + +// <<< end of configuration section >>> + +#endif // HPL_TC_CONFIG_H diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/peripheral_clk_config.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/peripheral_clk_config.h new file mode 100644 index 0000000..07e2e11 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/peripheral_clk_config.h @@ -0,0 +1,789 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EVSYS Channel 0 Clock Source +// evsys_clk_selection_0 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 0. +#ifndef CONF_GCLK_EVSYS_CHANNEL_0_SRC +#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 12000000 +#endif + +// EVSYS Channel 1 Clock Source +// evsys_clk_selection_1 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 1. +#ifndef CONF_GCLK_EVSYS_CHANNEL_1_SRC +#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 12000000 +#endif + +// EVSYS Channel 2 Clock Source +// evsys_clk_selection_2 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 2. +#ifndef CONF_GCLK_EVSYS_CHANNEL_2_SRC +#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 12000000 +#endif + +// EVSYS Channel 3 Clock Source +// evsys_clk_selection_3 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 3. +#ifndef CONF_GCLK_EVSYS_CHANNEL_3_SRC +#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 12000000 +#endif + +// EVSYS Channel 4 Clock Source +// evsys_clk_selection_4 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 4. +#ifndef CONF_GCLK_EVSYS_CHANNEL_4_SRC +#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 12000000 +#endif + +// EVSYS Channel 5 Clock Source +// evsys_clk_selection_5 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 5. +#ifndef CONF_GCLK_EVSYS_CHANNEL_5_SRC +#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 12000000 +#endif + +// EVSYS Channel 6 Clock Source +// evsys_clk_selection_6 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 6. +#ifndef CONF_GCLK_EVSYS_CHANNEL_6_SRC +#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 12000000 +#endif + +// EVSYS Channel 7 Clock Source +// evsys_clk_selection_7 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 7. +#ifndef CONF_GCLK_EVSYS_CHANNEL_7_SRC +#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 12000000 +#endif + +// EVSYS Channel 8 Clock Source +// evsys_clk_selection_8 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 8. +#ifndef CONF_GCLK_EVSYS_CHANNEL_8_SRC +#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 12000000 +#endif + +// EVSYS Channel 9 Clock Source +// evsys_clk_selection_9 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 9. +#ifndef CONF_GCLK_EVSYS_CHANNEL_9_SRC +#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 12000000 +#endif + +// EVSYS Channel 10 Clock Source +// evsys_clk_selection_10 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 10. +#ifndef CONF_GCLK_EVSYS_CHANNEL_10_SRC +#define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 12000000 +#endif + +// EVSYS Channel 11 Clock Source +// evsys_clk_selection_11 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 11. +#ifndef CONF_GCLK_EVSYS_CHANNEL_11_SRC +#define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 12000000 +#endif + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 12000000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM2_CORE_SRC +#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM2_SLOW_SRC +#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY + * \brief SERCOM2's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY +#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 12000000 +#endif + +/** + * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY + * \brief SERCOM2's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM4_CORE_SRC +#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM4_SLOW_SRC +#define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM4_CORE_FREQUENCY + * \brief SERCOM4's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY +#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 12000000 +#endif + +/** + * \def CONF_GCLK_SERCOM4_SLOW_FREQUENCY + * \brief SERCOM4's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM4_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM6_CORE_SRC +#define CONF_GCLK_SERCOM6_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM6_SLOW_SRC +#define CONF_GCLK_SERCOM6_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM6_CORE_FREQUENCY + * \brief SERCOM6's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM6_CORE_FREQUENCY +#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 12000000 +#endif + +/** + * \def CONF_GCLK_SERCOM6_SLOW_FREQUENCY + * \brief SERCOM6's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM6_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM6_SLOW_FREQUENCY 32768 +#endif + +// TC Clock Source +// tc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for TC. +#ifndef CONF_GCLK_TC0_SRC +#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_TC0_FREQUENCY + * \brief TC0's Clock frequency + */ +#ifndef CONF_GCLK_TC0_FREQUENCY +#define CONF_GCLK_TC0_FREQUENCY 12000000 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/spi_slave_dma_config.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/spi_slave_dma_config.h new file mode 100644 index 0000000..0be2677 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/spi_slave_dma_config.h @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief Application implement + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef SPI_SLAVE_DMA_CONFIG_H +#define SPI_SLAVE_DMA_CONFIG_H + +// Delay in Micro Seconds <1-1000> +// Delay in microseconds to hold CS low after data transfer completion by DMA +// delay_in_us_cs_low +#ifndef CONF_DELAY_US +#define CONF_DELAY_US 5 +#endif + +#endif diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/stdio_redirect_config.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/stdio_redirect_config.h new file mode 100644 index 0000000..3515c0c --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/stdio_redirect_config.h @@ -0,0 +1,9 @@ +/* Auto-generated config file stdio_redirect_config.h */ +#ifndef STDIO_REDIRECT_CONFIG_H +#define STDIO_REDIRECT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <<< end of configuration section >>> + +#endif // STDIO_REDIRECT_CONFIG_H diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Default.xml b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Default.xml new file mode 100644 index 0000000..8b9dc9c --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Default.xml @@ -0,0 +1,475 @@ + + + + + + + DebugLevel + None + + + IncludePaths + NDEBUG + + + MiscellaneousSettings + -std=gnu99 + + + OptimizationLevel + Optimize for size (-Os) + + + SymbolDefines + NDEBUG + + + SymbolUndefines + + + + Verbose + False + + + WarningsAsErrors + False + + + armgcc.compiler.general.CLanguageExp + True + + + armgcc.compiler.general.ChangeDefaultCharTypeUnsigned + False + + + armgcc.compiler.general.ChangeDefaultBitFieldUnsigned + False + + + armgcc.compiler.general.processormode + + + + armgcc.compiler.preprocessor.DoNotSearchSystemDirectories + False + + + armgcc.compiler.preprocessor.PreprocessOnly + False + + + armgcc.compiler.symbols.Default + + + + armgcc.compiler.directories.DefaultIncludePath + True + + + armgcc.compiler.optimization.OtherFlags + + + + armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection + True + + + armgcc.compiler.optimization.PrepareDataForGarbageCollection + False + + + armgcc.compiler.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.compiler.optimization.EnableFastMath + False + + + armgcc.compiler.optimization.GeneratePositionIndependentCode + False + + + armgcc.compiler.optimization.EnableLongCalls + True + + + armgcc.compiler.optimization.OtherDebuggingFlags + + + + armgcc.compiler.optimization.GenerateGprofInformation + False + + + armgcc.compiler.optimization.GenerateProfInformation + False + + + armgcc.compiler.warnings.AllWarnings + True + + + armgcc.compiler.warnings.ExtraWarnings + False + + + armgcc.compiler.warnings.Undefined + False + + + armgcc.compiler.warnings.CheckSyntaxOnly + False + + + armgcc.compiler.warnings.Pedantic + False + + + armgcc.compiler.warnings.PedanticWarningsAsErrors + False + + + armgcc.compiler.warnings.InhibitAllWarnings + False + + + armgcc.compiler.miscellaneous.Device + True + + + armgcc.compiler.miscellaneous.CompileOnly + True + + + armgcc.compiler.miscellaneous.SupportAnsiPrograms + False + + + armgcc.compiler.miscellaneous.MakeFileDependent + True + + + + + Libraries + libm + + + LibrarySearchPath + $(ProjectDir)\Device_Startup + + + MiscellaneousSettings + -Tsame54p20a_flash.ld + + + armgcc.linker.general.DoNotUseStandardStartFiles + False + + + armgcc.linker.general.DoNotUseDefaultLibraries + False + + + armgcc.linker.general.NoStartupOrDefaultLibs + False + + + armgcc.linker.general.OmitAllSymbolInformation + False + + + armgcc.linker.general.NoSharedLibraries + False + + + armgcc.linker.general.GenerateMAPFile + True + + + armgcc.linker.general.UseNewlibNano + False + + + armgcc.linker.general.AdditionalSpecs + None + + + armgcc.linker.optimization.GarbageCollectUnusedSections + True + + + armgcc.linker.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.linker.optimization.EnableFastMath + False + + + armgcc.linker.optimization.GeneratePositionIndependentCode + False + + + armgcc.linker.memorysettings.Flash + + + + armgcc.linker.memorysettings.Sram + + + + armgcc.linker.memorysettings.ExternalRAM + + + + armgcc.linker.miscellaneous.OtherOptions + + + + armgcc.linker.miscellaneous.OtherObjects + + + + Release + + + + + DebugLevel + Maximum (-g3) + + + IncludePaths + DEBUG + + + MiscellaneousSettings + -std=gnu99 + + + OptimizationLevel + Optimize debugging experience (-Og) + + + SymbolDefines + DEBUG + + + SymbolUndefines + + + + Verbose + False + + + WarningsAsErrors + False + + + armgcc.compiler.general.CLanguageExp + True + + + armgcc.compiler.general.ChangeDefaultCharTypeUnsigned + False + + + armgcc.compiler.general.ChangeDefaultBitFieldUnsigned + False + + + armgcc.compiler.general.processormode + + + + armgcc.compiler.preprocessor.DoNotSearchSystemDirectories + False + + + armgcc.compiler.preprocessor.PreprocessOnly + False + + + armgcc.compiler.symbols.Default + + + + armgcc.compiler.directories.DefaultIncludePath + True + + + armgcc.compiler.optimization.OtherFlags + + + + armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection + True + + + armgcc.compiler.optimization.PrepareDataForGarbageCollection + False + + + armgcc.compiler.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.compiler.optimization.EnableFastMath + False + + + armgcc.compiler.optimization.GeneratePositionIndependentCode + False + + + armgcc.compiler.optimization.EnableLongCalls + True + + + armgcc.compiler.optimization.OtherDebuggingFlags + + + + armgcc.compiler.optimization.GenerateGprofInformation + False + + + armgcc.compiler.optimization.GenerateProfInformation + False + + + armgcc.compiler.warnings.AllWarnings + True + + + armgcc.compiler.warnings.ExtraWarnings + False + + + armgcc.compiler.warnings.Undefined + False + + + armgcc.compiler.warnings.CheckSyntaxOnly + False + + + armgcc.compiler.warnings.Pedantic + False + + + armgcc.compiler.warnings.PedanticWarningsAsErrors + False + + + armgcc.compiler.warnings.InhibitAllWarnings + False + + + armgcc.compiler.miscellaneous.Device + True + + + armgcc.compiler.miscellaneous.CompileOnly + True + + + armgcc.compiler.miscellaneous.SupportAnsiPrograms + False + + + armgcc.compiler.miscellaneous.MakeFileDependent + True + + + + + Libraries + libm + + + LibrarySearchPath + $(ProjectDir)\Device_Startup + + + MiscellaneousSettings + -Tsame54p20a_flash.ld + + + armgcc.linker.general.DoNotUseStandardStartFiles + False + + + armgcc.linker.general.DoNotUseDefaultLibraries + False + + + armgcc.linker.general.NoStartupOrDefaultLibs + False + + + armgcc.linker.general.OmitAllSymbolInformation + False + + + armgcc.linker.general.NoSharedLibraries + False + + + armgcc.linker.general.GenerateMAPFile + True + + + armgcc.linker.general.UseNewlibNano + False + + + armgcc.linker.general.AdditionalSpecs + None + + + armgcc.linker.optimization.GarbageCollectUnusedSections + True + + + armgcc.linker.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.linker.optimization.EnableFastMath + False + + + armgcc.linker.optimization.GeneratePositionIndependentCode + False + + + armgcc.linker.memorysettings.Flash + + + + armgcc.linker.memorysettings.Sram + + + + armgcc.linker.memorysettings.ExternalRAM + + + + armgcc.linker.miscellaneous.OtherOptions + + + + armgcc.linker.miscellaneous.OtherObjects + + + + Debug + + + \ No newline at end of file diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_flash.ld b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_flash.ld new file mode 100644 index 0000000..97072bf --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAME54P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_sram.ld b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_sram.ld new file mode 100644 index 0000000..6219f4a --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAME54P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/startup_same54.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/startup_same54.c new file mode 100644 index 0000000..32efc2c --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/startup_same54.c @@ -0,0 +1,546 @@ +/** + * \file + * + * \brief gcc starttup file for SAME54 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "same54.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ +void OSCCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ +void OSCCTRL_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ +void OSCCTRL_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ +void OSCCTRL_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ +void SUPC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */ +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */ +void EIC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */ +void EIC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */ +void EIC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */ +void EIC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */ +void EIC_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */ +void EIC_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */ +void EIC_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */ +void EIC_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */ +void EIC_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */ +void EIC_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */ +void EIC_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */ +void EIC_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */ +void EIC_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */ +void EIC_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */ +void EIC_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */ +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ +void DMAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */ +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */ +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */ +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */ +void EVSYS_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */ +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */ +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */ +void SERCOM0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */ +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */ +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */ +void SERCOM1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */ +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */ +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */ +void SERCOM2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */ +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */ +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */ +void SERCOM3_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ +#ifdef ID_SERCOM4 +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */ +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */ +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */ +void SERCOM4_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ +#endif +#ifdef ID_SERCOM5 +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */ +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */ +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */ +void SERCOM5_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ +#endif +#ifdef ID_SERCOM6 +void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */ +void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */ +void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */ +void SERCOM6_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ +#endif +#ifdef ID_SERCOM7 +void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */ +void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */ +void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */ +void SERCOM7_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ +#endif +#ifdef ID_CAN0 +void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_CAN1 +void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_USB +void USB_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ +void USB_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */ +void USB_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ +void USB_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ +#endif +#ifdef ID_GMAC +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void TCC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ +void TCC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */ +void TCC0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */ +void TCC0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */ +void TCC0_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */ +void TCC0_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */ +void TCC0_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */ +void TCC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ +void TCC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */ +void TCC1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */ +void TCC1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */ +void TCC1_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */ +void TCC2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ +void TCC2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */ +void TCC2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */ +void TCC2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */ +#ifdef ID_TCC3 +void TCC3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ +void TCC3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */ +void TCC3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */ +#endif +#ifdef ID_TCC4 +void TCC4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ +void TCC4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */ +void TCC4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */ +#endif +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_TC4 +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC5 +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC6 +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC7 +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void PDEC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ +void PDEC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */ +void PDEC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */ +void ADC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */ +void ADC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */ +void ADC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */ +void ADC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */ +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ +void DAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */ +void DAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */ +void DAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */ +void DAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */ +#ifdef ID_I2S +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_ICM +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_PUKCC +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_SDHC0 +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SDHC1 +void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemManagement_Handler = (void*) MemManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedM9 = (void*) (0UL), /* Reserved */ + .pvReservedM8 = (void*) (0UL), /* Reserved */ + .pvReservedM7 = (void*) (0UL), /* Reserved */ + .pvReservedM6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedM3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_0_Handler = (void*) OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + .pfnOSCCTRL_1_Handler = (void*) OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + .pfnOSCCTRL_2_Handler = (void*) OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + .pfnOSCCTRL_3_Handler = (void*) OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + .pfnOSCCTRL_4_Handler = (void*) OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_0_Handler = (void*) SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + .pfnSUPC_1_Handler = (void*) SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_0_Handler = (void*) EIC_0_Handler, /* 12 EIC_EXTINT_0 */ + .pfnEIC_1_Handler = (void*) EIC_1_Handler, /* 13 EIC_EXTINT_1 */ + .pfnEIC_2_Handler = (void*) EIC_2_Handler, /* 14 EIC_EXTINT_2 */ + .pfnEIC_3_Handler = (void*) EIC_3_Handler, /* 15 EIC_EXTINT_3 */ + .pfnEIC_4_Handler = (void*) EIC_4_Handler, /* 16 EIC_EXTINT_4 */ + .pfnEIC_5_Handler = (void*) EIC_5_Handler, /* 17 EIC_EXTINT_5 */ + .pfnEIC_6_Handler = (void*) EIC_6_Handler, /* 18 EIC_EXTINT_6 */ + .pfnEIC_7_Handler = (void*) EIC_7_Handler, /* 19 EIC_EXTINT_7 */ + .pfnEIC_8_Handler = (void*) EIC_8_Handler, /* 20 EIC_EXTINT_8 */ + .pfnEIC_9_Handler = (void*) EIC_9_Handler, /* 21 EIC_EXTINT_9 */ + .pfnEIC_10_Handler = (void*) EIC_10_Handler, /* 22 EIC_EXTINT_10 */ + .pfnEIC_11_Handler = (void*) EIC_11_Handler, /* 23 EIC_EXTINT_11 */ + .pfnEIC_12_Handler = (void*) EIC_12_Handler, /* 24 EIC_EXTINT_12 */ + .pfnEIC_13_Handler = (void*) EIC_13_Handler, /* 25 EIC_EXTINT_13 */ + .pfnEIC_14_Handler = (void*) EIC_14_Handler, /* 26 EIC_EXTINT_14 */ + .pfnEIC_15_Handler = (void*) EIC_15_Handler, /* 27 EIC_EXTINT_15 */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + .pfnDMAC_4_Handler = (void*) DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */ + .pfnEVSYS_4_Handler = (void*) EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 SERCOM0_0 */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 SERCOM0_1 */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 SERCOM0_2 */ + .pfnSERCOM0_3_Handler = (void*) SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 SERCOM1_0 */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 SERCOM1_1 */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 SERCOM1_2 */ + .pfnSERCOM1_3_Handler = (void*) SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 SERCOM2_0 */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 SERCOM2_1 */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 SERCOM2_2 */ + .pfnSERCOM2_3_Handler = (void*) SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 SERCOM3_0 */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 SERCOM3_1 */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 SERCOM3_2 */ + .pfnSERCOM3_3_Handler = (void*) SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ +#ifdef ID_SERCOM4 + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 SERCOM4_0 */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 SERCOM4_1 */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 SERCOM4_2 */ + .pfnSERCOM4_3_Handler = (void*) SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ +#else + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pvReserved63 = (void*) (0UL), /* 63 Reserved */ + .pvReserved64 = (void*) (0UL), /* 64 Reserved */ + .pvReserved65 = (void*) (0UL), /* 65 Reserved */ +#endif +#ifdef ID_SERCOM5 + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 SERCOM5_0 */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 SERCOM5_1 */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 SERCOM5_2 */ + .pfnSERCOM5_3_Handler = (void*) SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ +#else + .pvReserved66 = (void*) (0UL), /* 66 Reserved */ + .pvReserved67 = (void*) (0UL), /* 67 Reserved */ + .pvReserved68 = (void*) (0UL), /* 68 Reserved */ + .pvReserved69 = (void*) (0UL), /* 69 Reserved */ +#endif +#ifdef ID_SERCOM6 + .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 SERCOM6_0 */ + .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 SERCOM6_1 */ + .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 SERCOM6_2 */ + .pfnSERCOM6_3_Handler = (void*) SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ +#else + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ + .pvReserved71 = (void*) (0UL), /* 71 Reserved */ + .pvReserved72 = (void*) (0UL), /* 72 Reserved */ + .pvReserved73 = (void*) (0UL), /* 73 Reserved */ +#endif +#ifdef ID_SERCOM7 + .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 SERCOM7_0 */ + .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 SERCOM7_1 */ + .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 SERCOM7_2 */ + .pfnSERCOM7_3_Handler = (void*) SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ +#else + .pvReserved74 = (void*) (0UL), /* 74 Reserved */ + .pvReserved75 = (void*) (0UL), /* 75 Reserved */ + .pvReserved76 = (void*) (0UL), /* 76 Reserved */ + .pvReserved77 = (void*) (0UL), /* 77 Reserved */ +#endif +#ifdef ID_CAN0 + .pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network 0 */ +#else + .pvReserved78 = (void*) (0UL), /* 78 Reserved */ +#endif +#ifdef ID_CAN1 + .pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network 1 */ +#else + .pvReserved79 = (void*) (0UL), /* 79 Reserved */ +#endif +#ifdef ID_USB + .pfnUSB_0_Handler = (void*) USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + .pfnUSB_1_Handler = (void*) USB_1_Handler, /* 81 USB_SOF_HSOF */ + .pfnUSB_2_Handler = (void*) USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + .pfnUSB_3_Handler = (void*) USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ +#else + .pvReserved80 = (void*) (0UL), /* 80 Reserved */ + .pvReserved81 = (void*) (0UL), /* 81 Reserved */ + .pvReserved82 = (void*) (0UL), /* 82 Reserved */ + .pvReserved83 = (void*) (0UL), /* 83 Reserved */ +#endif +#ifdef ID_GMAC + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */ +#else + .pvReserved84 = (void*) (0UL), /* 84 Reserved */ +#endif + .pfnTCC0_0_Handler = (void*) TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + .pfnTCC0_1_Handler = (void*) TCC0_1_Handler, /* 86 TCC0_MC_0 */ + .pfnTCC0_2_Handler = (void*) TCC0_2_Handler, /* 87 TCC0_MC_1 */ + .pfnTCC0_3_Handler = (void*) TCC0_3_Handler, /* 88 TCC0_MC_2 */ + .pfnTCC0_4_Handler = (void*) TCC0_4_Handler, /* 89 TCC0_MC_3 */ + .pfnTCC0_5_Handler = (void*) TCC0_5_Handler, /* 90 TCC0_MC_4 */ + .pfnTCC0_6_Handler = (void*) TCC0_6_Handler, /* 91 TCC0_MC_5 */ + .pfnTCC1_0_Handler = (void*) TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + .pfnTCC1_1_Handler = (void*) TCC1_1_Handler, /* 93 TCC1_MC_0 */ + .pfnTCC1_2_Handler = (void*) TCC1_2_Handler, /* 94 TCC1_MC_1 */ + .pfnTCC1_3_Handler = (void*) TCC1_3_Handler, /* 95 TCC1_MC_2 */ + .pfnTCC1_4_Handler = (void*) TCC1_4_Handler, /* 96 TCC1_MC_3 */ + .pfnTCC2_0_Handler = (void*) TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + .pfnTCC2_1_Handler = (void*) TCC2_1_Handler, /* 98 TCC2_MC_0 */ + .pfnTCC2_2_Handler = (void*) TCC2_2_Handler, /* 99 TCC2_MC_1 */ + .pfnTCC2_3_Handler = (void*) TCC2_3_Handler, /* 100 TCC2_MC_2 */ +#ifdef ID_TCC3 + .pfnTCC3_0_Handler = (void*) TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + .pfnTCC3_1_Handler = (void*) TCC3_1_Handler, /* 102 TCC3_MC_0 */ + .pfnTCC3_2_Handler = (void*) TCC3_2_Handler, /* 103 TCC3_MC_1 */ +#else + .pvReserved101 = (void*) (0UL), /* 101 Reserved */ + .pvReserved102 = (void*) (0UL), /* 102 Reserved */ + .pvReserved103 = (void*) (0UL), /* 103 Reserved */ +#endif +#ifdef ID_TCC4 + .pfnTCC4_0_Handler = (void*) TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + .pfnTCC4_1_Handler = (void*) TCC4_1_Handler, /* 105 TCC4_MC_0 */ + .pfnTCC4_2_Handler = (void*) TCC4_2_Handler, /* 106 TCC4_MC_1 */ +#else + .pvReserved104 = (void*) (0UL), /* 104 Reserved */ + .pvReserved105 = (void*) (0UL), /* 105 Reserved */ + .pvReserved106 = (void*) (0UL), /* 106 Reserved */ +#endif + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter 0 */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter 1 */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter 2 */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter 3 */ +#ifdef ID_TC4 + .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter 4 */ +#else + .pvReserved111 = (void*) (0UL), /* 111 Reserved */ +#endif +#ifdef ID_TC5 + .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter 5 */ +#else + .pvReserved112 = (void*) (0UL), /* 112 Reserved */ +#endif +#ifdef ID_TC6 + .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter 6 */ +#else + .pvReserved113 = (void*) (0UL), /* 113 Reserved */ +#endif +#ifdef ID_TC7 + .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter 7 */ +#else + .pvReserved114 = (void*) (0UL), /* 114 Reserved */ +#endif + .pfnPDEC_0_Handler = (void*) PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + .pfnPDEC_1_Handler = (void*) PDEC_1_Handler, /* 116 PDEC_MC_0 */ + .pfnPDEC_2_Handler = (void*) PDEC_2_Handler, /* 117 PDEC_MC_1 */ + .pfnADC0_0_Handler = (void*) ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */ + .pfnADC0_1_Handler = (void*) ADC0_1_Handler, /* 119 ADC0_RESRDY */ + .pfnADC1_0_Handler = (void*) ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */ + .pfnADC1_1_Handler = (void*) ADC1_1_Handler, /* 121 ADC1_RESRDY */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_0_Handler = (void*) DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + .pfnDAC_1_Handler = (void*) DAC_1_Handler, /* 124 DAC_EMPTY_0 */ + .pfnDAC_2_Handler = (void*) DAC_2_Handler, /* 125 DAC_EMPTY_1 */ + .pfnDAC_3_Handler = (void*) DAC_3_Handler, /* 126 DAC_RESRDY_0 */ + .pfnDAC_4_Handler = (void*) DAC_4_Handler, /* 127 DAC_RESRDY_1 */ +#ifdef ID_I2S + .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ +#else + .pvReserved128 = (void*) (0UL), /* 128 Reserved */ +#endif + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ +#ifdef ID_ICM + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ +#else + .pvReserved132 = (void*) (0UL), /* 132 Reserved */ +#endif +#ifdef ID_PUKCC + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ +#else + .pvReserved133 = (void*) (0UL), /* 133 Reserved */ +#endif + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ +#ifdef ID_SDHC0 + .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */ +#else + .pvReserved135 = (void*) (0UL), /* 135 Reserved */ +#endif +#ifdef ID_SDHC1 + .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller 1 */ +#else + .pvReserved136 = (void*) (0UL) /* 136 Reserved */ +#endif +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + +#if __FPU_USED + /* Enable FPU */ + SCB->CPACR |= (0xFu << 20); + __DSB(); + __ISB(); +#endif + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/system_same54.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/system_same54.c new file mode 100644 index 0000000..d3d5c22 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/system_same54.c @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "same54.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.componentinfo.xml b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.componentinfo.xml new file mode 100644 index 0000000..7a19096 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.componentinfo.xml @@ -0,0 +1,169 @@ + + + + + + + CMSIS + CORE + + + ARM + 5.1.2 + C:/Program Files (x86)\Atmel\Studio\7.0\Packs + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Documentation\Core\html\index.html + + doc + + + + CMSIS/Documentation/Core/html/index.html + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + + include + + + + CMSIS/Core/Include/ + + + + + CMSIS + C:/Program Files (x86)/Atmel/Studio/7.0/Packs/arm/CMSIS/5.4.0/ARM.CMSIS.pdsc + 5.4.0 + true + ARMv6_7_8-M Device + + + + Resolved + Fixed + true + + + + + Device + Startup + + + Atmel + 1.1.0 + C:/Program Files (x86)\Atmel\Studio\7.0\Packs + + + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include + + include + C + + + include + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include\sam.h + + header + C + 8A8bci0EePdi0b+8Lluv4A== + + include/sam.h + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\templates\main.c + template + source + C Exe + aXXhA2eDFVdIvf+beNWFeQ== + + templates/main.c + Main file (.c) + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\templates\main.cpp + template + source + C Exe + Wwcf/gxegRQ10+cCzYcFIw== + + templates/main.cpp + Main file (.cpp) + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\gcc\system_same54.c + config + source + GCC Exe + 13EKFJ9ZysfwBWEbJglN5Q== + + gcc/system_same54.c + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\gcc\gcc\startup_same54.c + config + source + GCC Exe + hvyBThCuEBmDbH8Yhxa2Jw== + + gcc/gcc/startup_same54.c + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\gcc\gcc\same54p20a_flash.ld + config + linkerScript + GCC Exe + KxZPrZpayTyit24vDXKm8w== + + gcc/gcc/same54p20a_flash.ld + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\gcc\gcc\same54p20a_sram.ld + config + other + GCC Exe + +7n8kxIwTIMsWzB2gEYtIg== + + gcc/gcc/same54p20a_sram.ld + + + + + SAME54_DFP + C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/SAME54_DFP/1.1.134/Atmel.SAME54_DFP.pdsc + 1.1.134 + true + ATSAME54P20A + + + + Resolved + Fixed + true + + + \ No newline at end of file diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj new file mode 100644 index 0000000..e4351ef --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj @@ -0,0 +1,971 @@ + + + + 2.0 + 7.0 + com.Atmel.ARMGCC.C + dce6c7e3-ee26-4d79-826b-08594b9ad897 + ATSAME54P20A + none + Executable + C + $(MSBuildProjectName) + .elf + $(MSBuildProjectDirectory)\$(Configuration) + Master_Slave_IF_TestMaster + Master_Slave_IF_TestMaster + Master_Slave_IF_TestMaster + Native + true + false + true + true + 0x20000000 + + true + exception_table + 2 + 0 + 0 + + + + + + + + + + + + + + gcc + .atmelstart\atmel_start_config.atstart + .atmelstart\AtmelStart.gpdsc + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + True + True + True + True + True + + + NDEBUG + + + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/cmcc + ../hpl/core + ../hpl/dmac + ../hpl/evsys + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/ramecc + ../hpl/sercom + ../hpl/tc + ../hri + ../stdio_redirect + %24(PackRepoDir)\atmel\SAME54_DFP\1.1.134\include + + + Optimize for size (-Os) + True + True + -std=gnu99 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 + True + + + libm + + + + + %24(ProjectDir)\Device_Startup + + + True + -Tsame54p20a_flash.ld + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/cmcc + ../hpl/core + ../hpl/dmac + ../hpl/evsys + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/ramecc + ../hpl/sercom + ../hpl/tc + ../hri + ../stdio_redirect + %24(PackRepoDir)\atmel\SAME54_DFP\1.1.134\include + + + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/cmcc + ../hpl/core + ../hpl/dmac + ../hpl/evsys + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/ramecc + ../hpl/sercom + ../hpl/tc + ../hri + ../stdio_redirect + %24(PackRepoDir)\atmel\SAME54_DFP\1.1.134\include + + + + + + + + + True + True + True + True + True + + + DEBUG + + + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/cmcc + ../hpl/core + ../hpl/dmac + ../hpl/evsys + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/ramecc + ../hpl/sercom + ../hpl/tc + ../hri + ../stdio_redirect + %24(PackRepoDir)\atmel\SAME54_DFP\1.1.134\include + + + Optimize debugging experience (-Og) + True + Maximum (-g3) + True + -std=gnu99 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 + + + libm + + + + + %24(ProjectDir)\Device_Startup + + + True + + -Tsame54p20a_flash.ld + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/cmcc + ../hpl/core + ../hpl/dmac + ../hpl/evsys + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/ramecc + ../hpl/sercom + ../hpl/tc + ../hri + ../stdio_redirect + %24(PackRepoDir)\atmel\SAME54_DFP\1.1.134\include + + + Default (-g) + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/cmcc + ../hpl/core + ../hpl/dmac + ../hpl/evsys + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/ramecc + ../hpl/sercom + ../hpl/tc + ../hri + ../stdio_redirect + %24(PackRepoDir)\atmel\SAME54_DFP\1.1.134\include + + + Default (-Wa,-g) + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + \ No newline at end of file diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.c new file mode 100644 index 0000000..12895d0 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.c @@ -0,0 +1,10 @@ +#include + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void) +{ + system_init(); + stdio_redirect_init(); +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.h new file mode 100644 index 0000000..ace35cf --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.h @@ -0,0 +1,19 @@ +#ifndef ATMEL_START_H_INCLUDED +#define ATMEL_START_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "driver_init.h" +#include "stdio_start.h" + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start_pins.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start_pins.h new file mode 100644 index 0000000..d905772 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start_pins.h @@ -0,0 +1,41 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef ATMEL_START_PINS_H_INCLUDED +#define ATMEL_START_PINS_H_INCLUDED + +#include + +// SAME54 has 14 pin functions + +#define GPIO_PIN_FUNCTION_A 0 +#define GPIO_PIN_FUNCTION_B 1 +#define GPIO_PIN_FUNCTION_C 2 +#define GPIO_PIN_FUNCTION_D 3 +#define GPIO_PIN_FUNCTION_E 4 +#define GPIO_PIN_FUNCTION_F 5 +#define GPIO_PIN_FUNCTION_G 6 +#define GPIO_PIN_FUNCTION_H 7 +#define GPIO_PIN_FUNCTION_I 8 +#define GPIO_PIN_FUNCTION_J 9 +#define GPIO_PIN_FUNCTION_K 10 +#define GPIO_PIN_FUNCTION_L 11 +#define GPIO_PIN_FUNCTION_M 12 +#define GPIO_PIN_FUNCTION_N 13 + +#define PB24 GPIO(GPIO_PORTB, 24) +#define PB25 GPIO(GPIO_PORTB, 25) +#define PB26 GPIO(GPIO_PORTB, 26) +#define PB27 GPIO(GPIO_PORTB, 27) +#define SPI_CS GPIO(GPIO_PORTB, 28) +#define PB29 GPIO(GPIO_PORTB, 29) +#define PC04 GPIO(GPIO_PORTC, 4) +#define PC05 GPIO(GPIO_PORTC, 5) +#define Angle_SS GPIO(GPIO_PORTC, 6) +#define PC07 GPIO(GPIO_PORTC, 7) + +#endif // ATMEL_START_PINS_H_INCLUDED diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/documentation/stdio.rst b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/documentation/stdio.rst new file mode 100644 index 0000000..2864b49 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/documentation/stdio.rst @@ -0,0 +1,34 @@ +STDIO redirection +================= + +The STDIO redirection provides means to redirect standard input/output to HAL +IO. + +On initialization, the HAL IO descriptor is assigned so that all input and +output is redirected to access it. The IO descriptor can also be changed +through stdio_io_set_io(). All stdin or stdout access is redirected to the +IO descriptor. When the IO descriptor is set to NULL, all input and output +are discarded. + +For GCC redirection, the stdout and stdin buffer are turned off, the +standard _read() and _write() are overridden. + +For IAR redirection, the __read() and __write() are overridden. + +For Keil redirection, the Retarget.c are modified to override fputc(), fgetc(), +etc. + +Features +-------- + +* Standard input/output redirection (e.g., printf to EDBG COM port) + +Dependencies +------------ + +* HAL IO driver + +Limitations +----------- + +* IO read/write operation should be synchronous diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.c new file mode 100644 index 0000000..ce686f6 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.c @@ -0,0 +1,219 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_init.h" +#include +#include +#include + +struct spi_m_sync_descriptor SPI_1; +struct timer_descriptor TIMER_0; + +struct usart_sync_descriptor TARGET_IO; + +struct spi_m_dma_descriptor SPI_0; + +void EVENT_SYSTEM_0_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_0, CONF_GCLK_EVSYS_CHANNEL_0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBBMASK_EVSYS_bit(MCLK); + + event_system_init(); +} + +void TARGET_IO_PORT_init(void) +{ + + gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0); + + gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1); +} + +void TARGET_IO_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); +} + +void TARGET_IO_init(void) +{ + TARGET_IO_CLOCK_init(); + usart_sync_init(&TARGET_IO, SERCOM2, (void *)NULL); + TARGET_IO_PORT_init(); +} + +void SPI_0_PORT_init(void) +{ + + gpio_set_pin_level(PB27, + // Initial level + // pad_initial_level + // Low + // High + false); + + // Set pin direction to output + gpio_set_pin_direction(PB27, GPIO_DIRECTION_OUT); + + gpio_set_pin_function(PB27, PINMUX_PB27D_SERCOM4_PAD0); + + gpio_set_pin_level(PB26, + // Initial level + // pad_initial_level + // Low + // High + false); + + // Set pin direction to output + gpio_set_pin_direction(PB26, GPIO_DIRECTION_OUT); + + gpio_set_pin_function(PB26, PINMUX_PB26D_SERCOM4_PAD1); + + // Set pin direction to input + gpio_set_pin_direction(PB29, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PB29, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PB29, PINMUX_PB29D_SERCOM4_PAD3); +} + +void SPI_0_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBDMASK_SERCOM4_bit(MCLK); +} + +void SPI_0_init(void) +{ + SPI_0_CLOCK_init(); + spi_m_dma_init(&SPI_0, SERCOM4); + SPI_0_PORT_init(); +} + +void SPI_1_PORT_init(void) +{ + + gpio_set_pin_level(PC04, + // Initial level + // pad_initial_level + // Low + // High + false); + + // Set pin direction to output + gpio_set_pin_direction(PC04, GPIO_DIRECTION_OUT); + + gpio_set_pin_function(PC04, PINMUX_PC04C_SERCOM6_PAD0); + + gpio_set_pin_level(PC05, + // Initial level + // pad_initial_level + // Low + // High + false); + + // Set pin direction to output + gpio_set_pin_direction(PC05, GPIO_DIRECTION_OUT); + + gpio_set_pin_function(PC05, PINMUX_PC05C_SERCOM6_PAD1); + + // Set pin direction to input + gpio_set_pin_direction(PC07, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PC07, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PC07, PINMUX_PC07C_SERCOM6_PAD3); +} + +void SPI_1_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM6_GCLK_ID_CORE, CONF_GCLK_SERCOM6_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM6_GCLK_ID_SLOW, CONF_GCLK_SERCOM6_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBDMASK_SERCOM6_bit(MCLK); +} + +void SPI_1_init(void) +{ + SPI_1_CLOCK_init(); + spi_m_sync_init(&SPI_1, SERCOM6); + SPI_1_PORT_init(); +} + +/** + * \brief Timer initialization function + * + * Enables Timer peripheral, clocks and initializes Timer driver + */ +static void TIMER_0_init(void) +{ + hri_mclk_set_APBAMASK_TC0_bit(MCLK); + hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + timer_init(&TIMER_0, TC0, _tc_get_timer()); +} + +void system_init(void) +{ + init_mcu(); + + // GPIO on PB28 + + gpio_set_pin_level(SPI_CS, + // Initial level + // pad_initial_level + // Low + // High + true); + + // Set pin direction to output + gpio_set_pin_direction(SPI_CS, GPIO_DIRECTION_OUT); + + gpio_set_pin_function(SPI_CS, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PC06 + + gpio_set_pin_level(Angle_SS, + // Initial level + // pad_initial_level + // Low + // High + true); + + // Set pin direction to output + gpio_set_pin_direction(Angle_SS, GPIO_DIRECTION_OUT); + + gpio_set_pin_function(Angle_SS, GPIO_PIN_FUNCTION_OFF); + + EVENT_SYSTEM_0_init(); + + TARGET_IO_init(); + + SPI_0_init(); + + SPI_1_init(); + + TIMER_0_init(); +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.h new file mode 100644 index 0000000..4129491 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.h @@ -0,0 +1,60 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_INIT_INCLUDED +#define DRIVER_INIT_INCLUDED + +#include "atmel_start_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include +#include + +extern struct usart_sync_descriptor TARGET_IO; + +extern struct spi_m_dma_descriptor SPI_0; +extern struct spi_m_sync_descriptor SPI_1; +extern struct timer_descriptor TIMER_0; + +void TARGET_IO_PORT_init(void); +void TARGET_IO_CLOCK_init(void); +void TARGET_IO_init(void); + +void SPI_0_PORT_init(void); +void SPI_0_CLOCK_init(void); +void SPI_0_init(void); + +void SPI_1_PORT_init(void); +void SPI_1_CLOCK_init(void); +void SPI_1_init(void); + +/** + * \brief Perform system initialization, initialize pins and clocks for + * peripherals + */ +void system_init(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_INIT_INCLUDED diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.c new file mode 100644 index 0000000..18519f3 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.c @@ -0,0 +1,90 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_examples.h" +#include "driver_init.h" +#include "utils.h" + +/** + * Example of using TARGET_IO to write "Hello World" using the IO abstraction. + */ +void TARGET_IO_example(void) +{ + struct io_descriptor *io; + usart_sync_get_io_descriptor(&TARGET_IO, &io); + usart_sync_enable(&TARGET_IO); + + io_write(io, (uint8_t *)"Hello World!", 12); +} + +/** + * Example of using SPI_0 to write "Hello World" using the IO abstraction. + * + * Since the driver is asynchronous we need to use statically allocated memory for string + * because driver initiates transfer and then returns before the transmission is completed. + * + * Once transfer has been completed the tx_cb function will be called. + */ + +static uint8_t example_SPI_0[12] = "Hello World!"; + +static void tx_complete_cb_SPI_0(struct _dma_resource *resource) +{ + /* Transfer completed */ +} + +void SPI_0_example(void) +{ + struct io_descriptor *io; + spi_m_dma_get_io_descriptor(&SPI_0, &io); + + spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_TX_DONE, tx_complete_cb_SPI_0); + spi_m_dma_enable(&SPI_0); + io_write(io, example_SPI_0, 12); +} + +/** + * Example of using SPI_1 to write "Hello World" using the IO abstraction. + */ +static uint8_t example_SPI_1[12] = "Hello World!"; + +void SPI_1_example(void) +{ + struct io_descriptor *io; + spi_m_sync_get_io_descriptor(&SPI_1, &io); + + spi_m_sync_enable(&SPI_1); + io_write(io, example_SPI_1, 12); +} + +static struct timer_task TIMER_0_task1, TIMER_0_task2; + +/** + * Example of using TIMER_0. + */ +static void TIMER_0_task1_cb(const struct timer_task *const timer_task) +{ +} + +static void TIMER_0_task2_cb(const struct timer_task *const timer_task) +{ +} + +void TIMER_0_example(void) +{ + TIMER_0_task1.interval = 100; + TIMER_0_task1.cb = TIMER_0_task1_cb; + TIMER_0_task1.mode = TIMER_TASK_REPEAT; + TIMER_0_task2.interval = 200; + TIMER_0_task2.cb = TIMER_0_task2_cb; + TIMER_0_task2.mode = TIMER_TASK_REPEAT; + + timer_add_task(&TIMER_0, &TIMER_0_task1); + timer_add_task(&TIMER_0, &TIMER_0_task2); + timer_start(&TIMER_0); +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.h new file mode 100644 index 0000000..a5075d5 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.h @@ -0,0 +1,24 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_EXAMPLES_H_INCLUDED +#define DRIVER_EXAMPLES_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void TARGET_IO_example(void); + +void SPI_0_example(void); + +void TIMER_0_example(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_EXAMPLES_H_INCLUDED diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/evsys.rst b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/evsys.rst new file mode 100644 index 0000000..01d40bc --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/evsys.rst @@ -0,0 +1,24 @@ +=================== +Event system driver +=================== + +Event system allows autonomous, low-latency and configurable communication between peripherals. + +Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition +to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that +respond to events are event users, peripherals that generate events are called event generators. A peripheral can have +one or more event generators and can have one or more event users. + +Communication is made without CPU intervention and without consuming system resources such as bus or RAM bandwidth. This +reduces the load on the CPU and system resources, compared to a traditional interrupt-based system. + +The Event System consists of several channels which route the internal events from generators +to users. Each event generator can be selected as source for multiple channels, but a channel cannot +be set to use multiple event generators at the same time. + +Event system driver allows to configure event system of an MCU. + +Limitations +----------- + + - Event channel configuration is static diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/spi_master_dma.rst b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/spi_master_dma.rst new file mode 100644 index 0000000..475b317 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/spi_master_dma.rst @@ -0,0 +1,56 @@ +The SPI Master DMA Driver +================================== + +The serial peripheral interface (SPI) is a DMA serial communication +interface. + +The SPI Master DMA driver uses DMA system to transfer data from +a memory buffer to SPI (Memory to Peripheral), and receive data +from SPI to a memory buffer (Peripheral to Memory).User must configure +DMA system driver accordingly. A callback is called when all the data +is transfered or all the data is received, if it is registered via +spi_m_dma_register_callback function. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * SPI mode + * Character size + * Data order +* Data transfer: transmission, reception and full-duplex +* Notifications about transfer completion and errors via callbacks + +Applications +------------ + +Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card, +LCD controller, etc. + +Dependencies +------------ + +SPI master capable hardware and DMA hardware, with data sent/received. + +Concurrency +----------- + +N/A + +Limitations +----------- + +When only uses DMA channel to receive data, the transfer channel must enable to +send dummy data to the slave. + +While read/write/transfer is in progress, the data buffer used must be kept +unchanged. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/spi_master_sync.rst b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/spi_master_sync.rst new file mode 100644 index 0000000..4fbe45e --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/spi_master_sync.rst @@ -0,0 +1,51 @@ +The SPI Master Synchronous Driver +================================= + +The serial peripheral interface (SPI) is a synchronous serial communication +interface. + +SPI devices communicate in full duplex mode using a master-slave +architecture with a single master. The master device originates the frame for +reading and writing. Multiple slave devices are supported through selection +with individual slave select (SS) lines. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * SPI mode + * Character size + * Data order +* Data transfer: transmission, reception and full-duplex + +Applications +------------ + +Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card, +LCD controller, etc. + +Dependencies +------------ + +SPI master capable hardware + +Concurrency +----------- + +N/A + +Limitations +----------- + +The slave select (SS) is not automatically inserted during read/write/transfer, +user must use I/O to control the devices' SS. + +Known issues and workarounds +---------------------------- + +N/A + diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/timer.rst b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/timer.rst new file mode 100644 index 0000000..c5ca63d --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/timer.rst @@ -0,0 +1,52 @@ +============================ +The Timer driver (bare-bone) +============================ + +The Timer driver provides means for delayed and periodical function invocation. + +A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has +been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a +configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically +changes execution delays and periods for all tasks in the timers task queue. + +A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue +and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on +the period set in the task configuration. +In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to +reuse the memory of expired task in the callback. + +Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available. + +Features +-------- +* Initialization and de-initialization +* Starting and stopping +* Timer tasks - periodical invocation of functions +* Changing and obtaining of the period of a timer + +Applications +------------ +* Delayed and periodical function execution for middle-ware stacks and applications. + +Dependencies +------------ +* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt. + +Concurrency +----------- +The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during +the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed +until the task adding or removing is complete. + +The task queue is not protected from the access by interrupts not used by the driver. Due to this +it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes +the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver. + +Limitations +----------- +* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts. +* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task. + +Knows issues and workarounds +---------------------------- +Not applicable diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/usart_sync.rst b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/usart_sync.rst new file mode 100644 index 0000000..15e4b13 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/usart_sync.rst @@ -0,0 +1,58 @@ +The USART Synchronous Driver +============================ + +The universal synchronous and asynchronous receiver and transmitter +(USART) is usually used to transfer data from one device to the other. + +User can set action for flow control pins by function usart_set_flow_control, +if the flow control is enabled. All the available states are defined in union +usart_flow_control_state. + +Note that user can set state of flow control pins only if automatic support of +the flow control is not supported by the hardware. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * UART or USRT communication mode + * Character size + * Data order + * Flow control +* Data transfer: transmission, reception + +Applications +------------ + +They are commonly used in a terminal application or low-speed communication +between devices. + +Dependencies +------------ + +USART capable hardware. + +Concurrency +----------- + +Write buffer should not be changed while data is being sent. + + +Limitations +----------- + +* The driver does not support 9-bit character size. +* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. + And the SCK pin can't be set directly. Application can use a GCLK output PIN + to generate SCK. For example to communicate with a SMARTCARD with ISO7816 + (F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be + config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_atomic.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_atomic.h new file mode 100644 index 0000000..82151fc --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_atomic.h @@ -0,0 +1,120 @@ +/** + * \file + * + * \brief Critical sections related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ATOMIC_H_INCLUDED +#define _HAL_ATOMIC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_atomic + * + *@{ + */ + +/** + * \brief Type for the register holding global interrupt enable flag + */ +typedef uint32_t hal_atomic_t; + +/** + * \brief Helper macro for entering critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_enterCritical() function to enter critical + * sections. No semicolon is required after the macro. + * + * \section atomic_usage Usage Example + * \code + * CRITICAL_SECTION_ENTER() + * Critical code + * CRITICAL_SECTION_LEAVE() + * \endcode + */ +#define CRITICAL_SECTION_ENTER() \ + { \ + volatile hal_atomic_t __atomic; \ + atomic_enter_critical(&__atomic); + +/** + * \brief Helper macro for leaving critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_leaveCritical() function to leave critical + * sections. No semicolon is required after the macro. + */ +#define CRITICAL_SECTION_LEAVE() \ + atomic_leave_critical(&__atomic); \ + } + +/** + * \brief Disable interrupts, enter critical section + * + * Disables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[out] atomic The pointer to a variable to store the value of global + * interrupt enable flag + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Exit atomic section + * + * Enables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[in] atomic The pointer to a variable, which stores the latest stored + * value of the global interrupt enable flag + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t atomic_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_cache.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_cache.h new file mode 100644 index 0000000..071486b --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_cache.h @@ -0,0 +1,96 @@ +/** + * \file + * + * \brief HAL cache functionality implementation. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef HAL_CACHE_H_ +#define HAL_CACHE_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Enable cache module + * + * \param[in] pointer pointing to the starting address of cache module + * + * \return status of operation + */ +int32_t cache_enable(const void *hw); + +/** + * \brief Disable cache module + * + * \param[in] pointer pointing to the starting address of cache module + * + * \return status of operation + */ +int32_t cache_disable(const void *hw); + +/** + * \brief Initialize cache module + * + * This function initialize cache module configuration. + * + * \return status of operation + */ +int32_t cache_init(void); + +/** + * \brief Configure cache module + * + * \param[in] pointer pointing to the starting address of cache module + * \param[in] cache configuration structure pointer + * + * \return status of operation + */ +int32_t cache_configure(const void *hw, struct _cache_cfg *cache); + +/** + * \brief Invalidate entire cache entries + * + * \param[in] pointer pointing to the starting address of cache module + * + * \return status of operation + */ +int32_t cache_invalidate_all(const void *hw); + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_CACHE_H_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_delay.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_delay.h new file mode 100644 index 0000000..9d4aa5c --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_delay.h @@ -0,0 +1,89 @@ +/** + * \file + * + * \brief HAL delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#ifndef _HAL_DELAY_H_INCLUDED +#define _HAL_DELAY_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_delay Delay Driver + * + *@{ + */ + +/** + * \brief Initialize Delay driver + * + * \param[in] hw The pointer to hardware instance + */ +void delay_init(void *const hw); + +/** + * \brief Perform delay in us + * + * This function performs delay for the given amount of microseconds. + * + * \param[in] us The amount delay in us + */ +void delay_us(const uint16_t us); + +/** + * \brief Perform delay in ms + * + * This function performs delay for the given amount of milliseconds. + * + * \param[in] ms The amount delay in ms + */ +void delay_ms(const uint16_t ms); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t delay_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_evsys.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_evsys.h new file mode 100644 index 0000000..3f68540 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_evsys.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief HAL event system related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include + +#ifndef _HAL_EVSYS_H_INCLUDED +#define _HAL_EVSYS_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_evsys + * + * @{ + */ + +/** + * \brief Initialize event system. + * + * \return Initialization status. + */ +int32_t event_system_init(void); + +/** + * \brief Deinitialize event system. + * + * \return De-initialization status. + */ +int32_t event_system_deinit(void); + +/** + * \brief Enable event reception by the given user from the given channel + * + * \param[in] user A user to enable + * \param[in] channel A channel the user is assigned to + * + * \return Status of operation. + */ +int32_t event_system_enable_user(const uint16_t user, const uint16_t channel); + +/** + * \brief Disable event reception by the given user from the given channel + * + * \param[in] user A user to disable + * \param[in] channel A channel the user is assigned to + * + * \return Status of operation. + */ +int32_t event_system_disable_user(const uint16_t user, const uint16_t channel); + +/** + * \brief Enable event generation by the given generator for the given channel + * + * \param[in] generator A generator to disable + * \param[in] channel A channel the generator is assigned to + * + * \return Status of operation. + */ +int32_t event_system_enable_generator(const uint16_t generator, const uint16_t channel); + +/** + * \brief Disable event generation by the given generator for the given channel + * + * \param[in] generator A generator to disable + * \param[in] channel A channel the generator is assigned to + * + * \return Status of operation. + */ +int32_t event_system_disable_generator(const uint16_t generator, const uint16_t channel); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t event_system_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_EVSYS_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_gpio.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_gpio.h new file mode 100644 index 0000000..fbfa2d4 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_gpio.h @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ +#ifndef _HAL_GPIO_INCLUDED_ +#define _HAL_GPIO_INCLUDED_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set gpio pull mode + * + * Set pin pull mode, non existing pull modes throws an fatal assert + * + * \param[in] pin The pin number for device + * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor + * GPIO_PULL_UP = Pull pin high with internal resistor + * GPIO_PULL_OFF = Disable pin pull mode + */ +static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) +{ + _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); +} + +/** + * \brief Set pin function + * + * Select which function a pin will be used for + * + * \param[in] pin The pin number for device + * \param[in] function The pin function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) +{ + _gpio_set_pin_function(pin, function); +} + +/** + * \brief Set port data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + _gpio_set_direction(port, mask, direction); +} + +/** + * \brief Set gpio data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] pin The pin number for device + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) +{ + _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); +} + +/** + * \brief Set port level + * + * Sets output level on the pins defined by the bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply port level to the corresponding + * pin + * \param[in] level true = Pin levels set to "high" state + * false = Pin levels set to "low" state + */ +static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + _gpio_set_level(port, mask, level); +} + +/** + * \brief Set gpio level + * + * Sets output level on a pin + * + * \param[in] pin The pin number for device + * \param[in] level true = Pin level set to "high" state + * false = Pin level set to "low" state + */ +static inline void gpio_set_pin_level(const uint8_t pin, const bool level) +{ + _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); +} + +/** + * \brief Toggle out level on pins + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding + * pin + */ +static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) +{ + _gpio_toggle_level(port, mask); +} + +/** + * \brief Toggle output level on pin + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] pin The pin number for device + */ +static inline void gpio_toggle_pin_level(const uint8_t pin) +{ + _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); +} + +/** + * \brief Get input level on pins + * + * Read the input level on pins connected to a port + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t gpio_get_port_level(const enum gpio_port port) +{ + return _gpio_get_level(port); +} + +/** + * \brief Get level on pin + * + * Reads the level on pins connected to a port + * + * \param[in] pin The pin number for device + */ +static inline bool gpio_get_pin_level(const uint8_t pin) +{ + return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); +} +/** + * \brief Get current driver version + */ +uint32_t gpio_get_version(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_init.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_init.h new file mode 100644 index 0000000..d7bc6fe --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_init.h @@ -0,0 +1,72 @@ +/** + * \file + * + * \brief HAL initialization related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_INIT_H_INCLUDED +#define _HAL_INIT_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_init Init Driver + * + *@{ + */ + +/** + * \brief Initialize the hardware abstraction layer + * + * This function calls the various initialization functions. + * Currently the following initialization functions are supported: + * - System clock initialization + */ +static inline void init_mcu(void) +{ + _init_chip(); +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t init_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_io.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_io.h new file mode 100644 index 0000000..f50401d --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_io.h @@ -0,0 +1,110 @@ +/** + * \file + * + * \brief I/O related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_IO_INCLUDED +#define _HAL_IO_INCLUDED + +/** + * \addtogroup doc_driver_hal_helper_io I/O Driver + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I/O descriptor + * + * The I/O descriptor forward declaration. + */ +struct io_descriptor; + +/** + * \brief I/O write function pointer type + */ +typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read function pointer type + */ +typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O descriptor + */ +struct io_descriptor { + io_write_t write; /*! The write function pointer. */ + io_read_t read; /*! The read function pointer. */ +}; + +/** + * \brief I/O write interface + * + * This function writes up to \p length of bytes to a given I/O descriptor. + * It returns the number of bytes actually write. + * + * \param[in] descr An I/O descriptor to write + * \param[in] buf The buffer pointer to story the write data + * \param[in] length The number of bytes to write + * + * \return The number of bytes written + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read interface + * + * This function reads up to \p length bytes from a given I/O descriptor, and + * stores it in the buffer pointed to by \p buf. It returns the number of bytes + * actually read. + * + * \param[in] descr An I/O descriptor to read + * \param[in] buf The buffer pointer to story the read data + * \param[in] length The number of bytes to read + * + * \return The number of bytes actually read. This number can be less than the + * requested length. E.g., in a driver that uses ring buffer for + * reception, it may depend on the availability of data in the + * ring buffer. + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_IO_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_sleep.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_sleep.h new file mode 100644 index 0000000..b90ef6a --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_sleep.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SLEEP_H_INCLUDED +#define _HAL_SLEEP_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_sleep + * + *@{ + */ + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t sleep_get_version(void); +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_spi_m_dma.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_spi_m_dma.h new file mode 100644 index 0000000..24e7b11 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_spi_m_dma.h @@ -0,0 +1,257 @@ +/** + * \file + * + * \brief SPI DMA related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SPI_M_DMA_H_INCLUDED +#define _HAL_SPI_M_DMA_H_INCLUDED + +#include +#include + +/** + * \addtogroup doc_driver_hal_spi_master_dma + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Forward declaration of spi_descriptor. */ +struct spi_m_dma_descriptor; + +/** The callback types */ +enum spi_m_dma_cb_type { + /** Callback type for DMA transfer buffer done */ + SPI_M_DMA_CB_TX_DONE, + /** Callback type for DMA receive buffer done */ + SPI_M_DMA_CB_RX_DONE, + /** Callback type for DMA errors */ + SPI_M_DMA_CB_ERROR, + SPI_M_DMA_CB_N +}; + +/** + * \brief SPI Master DMA callback type + */ +typedef void (*spi_m_dma_cb_t)(struct _dma_resource *resource); + +/** \brief SPI HAL driver struct for DMA access + */ +struct spi_m_dma_descriptor { + struct _spi_m_dma_hpl_interface *func; + /** Pointer to SPI device instance */ + struct _spi_m_dma_dev dev; + /** I/O read/write */ + struct io_descriptor io; + /** DMA resource */ + struct _dma_resource *resource; +}; + +/** \brief Set the SPI HAL instance function pointer for HPL APIs. + * + * Set SPI HAL instance function pointer for HPL APIs. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] func Pointer to the HPL api structure. + * + */ +void spi_m_dma_set_func_ptr(struct spi_m_dma_descriptor *spi, void *const func); + +/** \brief Initialize the SPI HAL instance and hardware for DMA mode + * + * Initialize SPI HAL with dma mode. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] hw Pointer to the hardware base. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_INVALID_DATA Error, initialized. + */ +int32_t spi_m_dma_init(struct spi_m_dma_descriptor *spi, void *const hw); + +/** \brief Deinitialize the SPI HAL instance + * + * Abort transfer, disable and reset SPI, de-init software. + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_dma_deinit(struct spi_m_dma_descriptor *spi); + +/** \brief Enable SPI + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_dma_enable(struct spi_m_dma_descriptor *spi); + +/** \brief Disable SPI + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_dma_disable(struct spi_m_dma_descriptor *spi); + +/** \brief Set SPI baudrate + * + * Works if SPI is initialized as master. + * In the function a sanity check is used to confirm it's called in the correct mode. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] baud_val The target baudrate value + * (See "baudrate calculation" for calculating the value). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy. + * + * note: This api should be used to write the baudrate register with the given baud_val + * paramter, the user has to calculate the baud_val for required baud rate and pass it as + * argument(baud_val) to this api + */ +int32_t spi_m_dma_set_baudrate(struct spi_m_dma_descriptor *spi, const uint32_t baud_val); + +/** \brief Set SPI mode + * + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase: + * - Mode 0: leading edge is rising edge, data sample on leading edge. + * - Mode 1: leading edge is rising edge, data sample on trailing edge. + * - Mode 2: leading edge is falling edge, data sample on leading edge. + * - Mode 3: leading edge is falling edge, data sample on trailing edge. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] mode The mode (\ref spi_transfer_mode). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy, CS activated. + */ +int32_t spi_m_dma_set_mode(struct spi_m_dma_descriptor *spi, const enum spi_transfer_mode mode); + +/** \brief Set the SPI transfer character size in number of bits + * + * The character size (\ref spi_char_size) influence the way the data is + * sent/received. + * For char size <= 8-bit, data is stored byte by byte. + * For char size between 9-bit ~ 16-bit, data is stored in 2-byte length. + * Note that the default and recommended char size is 8-bit since it's + * supported by all system. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] char_size The char size (\ref spi_char_size). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy, CS activated. + * \retval ERR_INVALID_ARG The char size is not supported. + */ +int32_t spi_m_dma_set_char_size(struct spi_m_dma_descriptor *spi, const enum spi_char_size char_size); + +/** \brief Set SPI transfer data order + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] dord The data order: send LSB/MSB first. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy, CS activated. + * \retval ERR_INVALID The data order is not supported. + */ +int32_t spi_m_dma_set_data_order(struct spi_m_dma_descriptor *spi, const enum spi_data_order dord); + +/** \brief Perform the SPI data transfer (TX and RX) with the DMA + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] txbuf Pointer to the transfer information. + * \param[out] rxbuf Pointer to the receiver information. + * \param[in] length SPI transfer data length. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy. + */ +int32_t spi_m_dma_transfer(struct spi_m_dma_descriptor *spi, uint8_t const *txbuf, uint8_t *const rxbuf, + const uint16_t length); + +/** \brief Register a function as an SPI transfer completion callback + * + * Register a callback function specified by its \c type. + * - SPI_CB_COMPLETE: set the function that will be called on the SPI transfer + * completion including deactivating the CS. + * - SPI_CB_XFER: set the function that will be called on the SPI buffer transfer + * completion. + * Register a NULL function to not use the callback. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] type Callback type (\ref spi_m_dma_cb_type). + * \param[in] func Pointer to callback function. + */ +void spi_m_dma_register_callback(struct spi_m_dma_descriptor *spi, const enum spi_m_dma_cb_type type, + spi_m_dma_cb_t func); + +/** + * \brief Return I/O descriptor for this SPI instance + * + * This function will return an I/O instance for this SPI driver instance + * + * \param[in] spi An SPI master descriptor, which is used to communicate through + * SPI + * \param[in, out] io A pointer to an I/O descriptor pointer type + * + * \retval ERR_NONE + */ +int32_t spi_m_dma_get_io_descriptor(struct spi_m_dma_descriptor *const spi, struct io_descriptor **io); + +/** \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t spi_m_dma_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* ifndef _HAL_SPI_M_DMA_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_spi_m_sync.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_spi_m_sync.h new file mode 100644 index 0000000..5d04055 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_spi_m_sync.h @@ -0,0 +1,221 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SPI_M_SYNC_H_INCLUDED +#define _HAL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup doc_driver_hal_spi_master_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** \brief SPI HAL driver struct for polling mode + * + */ +struct spi_m_sync_descriptor { + struct _spi_m_sync_hpl_interface *func; + /** SPI device instance */ + struct _spi_sync_dev dev; + /** I/O read/write */ + struct io_descriptor io; + /** Flags for HAL driver */ + uint16_t flags; +}; + +/** \brief Set the SPI HAL instance function pointer for HPL APIs. + * + * Set SPI HAL instance function pointer for HPL APIs. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] func Pointer to the HPL api structure. + * + */ +void spi_m_sync_set_func_ptr(struct spi_m_sync_descriptor *spi, void *const func); + +/** \brief Initialize SPI HAL instance and hardware for polling mode + * + * Initialize SPI HAL with polling mode. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] hw Pointer to the hardware base. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_INVALID_DATA Error, initialized. + */ +int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw); + +/** \brief Deinitialize the SPI HAL instance and hardware + * + * Abort transfer, disable and reset SPI, deinit software. + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi); + +/** \brief Enable SPI + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_enable(struct spi_m_sync_descriptor *spi); + +/** \brief Disable SPI + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_disable(struct spi_m_sync_descriptor *spi); + +/** \brief Set SPI baudrate + * + * Works if SPI is initialized as master, it sets the baudrate. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] baud_val The target baudrate value + * (see "baudrate calculation" for calculating the value). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The baudrate is not supported. + */ +int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val); + +/** \brief Set SPI mode + * + * Set the SPI transfer mode (\ref spi_transfer_mode), + * which controls the clock polarity and clock phase: + * - Mode 0: leading edge is rising edge, data sample on leading edge. + * - Mode 1: leading edge is rising edge, data sample on trailing edge. + * - Mode 2: leading edge is falling edge, data sample on leading edge. + * - Mode 3: leading edge is falling edge, data sample on trailing edge. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] mode The mode (0~3). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The mode is not supported. + */ +int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode); + +/** \brief Set SPI transfer character size in number of bits + * + * The character size (\ref spi_char_size) influence the way the data is + * sent/received. + * For char size <= 8-bit, data is stored byte by byte. + * For char size between 9-bit ~ 16-bit, data is stored in 2-byte length. + * Note that the default and recommended char size is 8-bit since it's + * supported by all system. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] char_size The char size (~16, recommended 8). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The char size is not supported. + */ +int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size); + +/** \brief Set SPI transfer data order + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] dord The data order: send LSB/MSB first. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The data order is not supported. + */ +int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord); + +/** \brief Perform the SPI data transfer (TX and RX) in polling way + * + * Activate CS, do TX and RX and deactivate CS. It blocks. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[in] xfer Pointer to the transfer information (\ref spi_xfer). + * + * \retval size Success. + * \retval >=0 Timeout, with number of characters transferred. + * \retval ERR_BUSY SPI is busy + */ +int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *xfer); + +/** + * \brief Return the I/O descriptor for this SPI instance + * + * This function will return an I/O instance for this SPI driver instance. + * + * \param[in] spi An SPI master descriptor, which is used to communicate through + * SPI + * \param[in, out] io A pointer to an I/O descriptor pointer type + * + * \retval ERR_NONE + */ +int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io); + +/** \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t spi_m_sync_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _HAL_SPI_M_SYNC_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_timer.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_timer.h new file mode 100644 index 0000000..43a1ff4 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_timer.h @@ -0,0 +1,206 @@ +/** + * \file + * + * \brief Timer task functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_TIMER_H_INCLUDED +#define _HAL_TIMER_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_timer + * + * @{ + */ + +/** + * \brief Timer mode type + */ +enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT }; + +/** + * \brief Timer task descriptor + * + * The timer task descriptor forward declaration. + */ +struct timer_task; + +/** + * \brief Timer task callback function type + */ +typedef void (*timer_cb_t)(const struct timer_task *const timer_task); + +/** + * \brief Timer task structure + */ +struct timer_task { + struct list_element elem; /*! List element. */ + uint32_t time_label; /*! Absolute timer start time. */ + + uint32_t interval; /*! Number of timer ticks before calling the task. */ + timer_cb_t cb; /*! Function pointer to the task. */ + enum timer_task_mode mode; /*! Task mode: one shot or repeat. */ +}; + +/** + * \brief Timer structure + */ +struct timer_descriptor { + struct _timer_device device; + uint32_t time; + struct list_descriptor tasks; /*! Timer tasks list. */ + volatile uint8_t flags; +}; + +/** + * \brief Initialize timer + * + * This function initializes the given timer. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[out] descr A timer descriptor to initialize + * \param[in] hw The pointer to the hardware instance + * \param[in] func The pointer to a set of function pointers + * + * \return Initialization status. + */ +int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func); + +/** + * \brief Deinitialize timer + * + * This function deinitializes the given timer. + * It checks if the given hardware is initialized and if the given hardware is + * permitted to be deinitialized. + * + * \param[in] descr A timer descriptor to deinitialize + * + * \return De-initialization status. + */ +int32_t timer_deinit(struct timer_descriptor *const descr); + +/** + * \brief Start timer + * + * This function starts the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to start + * + * \return Timer starting status. + */ +int32_t timer_start(struct timer_descriptor *const descr); + +/** + * \brief Stop timer + * + * This function stops the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to stop + * + * \return Timer stopping status. + */ +int32_t timer_stop(struct timer_descriptor *const descr); + +/** + * \brief Set amount of clock cycles per timer tick + * + * This function sets the amount of clock cycles per timer tick for the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to stop + * \param[in] clock_cycles The amount of clock cycles per tick to set + * + * \return Setting clock cycles amount status. + */ +int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles); + +/** + * \brief Retrieve the amount of clock cycles in a tick + * + * This function retrieves how many clock cycles there are in a single timer tick. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to convert ticks to + * clock cycles + * \param[out] cycles The amount of clock cycles + * + * \return The status of clock cycles retrieving. + */ +int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles); + +/** + * \brief Add timer task + * + * This function adds the given timer task to the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to add task to + * \param[in] task A task to add + * + * \return Timer's task adding status. + */ +int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task); + +/** + * \brief Remove timer task + * + * This function removes the given timer task from the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to remove task from + * \param[in] task A task to remove + * + * \return Timer's task removing status. + */ +int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t timer_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_TIMER_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_usart_sync.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_usart_sync.h new file mode 100644 index 0000000..1ef22fc --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_usart_sync.h @@ -0,0 +1,247 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SYNC_USART_H_INCLUDED +#define _HAL_SYNC_USART_H_INCLUDED + +#include "hal_io.h" +#include + +/** + * \addtogroup doc_driver_hal_usart_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Synchronous USART descriptor + */ +struct usart_sync_descriptor { + struct io_descriptor io; + struct _usart_sync_device device; +}; + +/** + * \brief Initialize USART interface + * + * This function initializes the given I/O descriptor to be used + * as USART interface descriptor. + * It checks if the given hardware is not initialized and + * if the given hardware is permitted to be initialized. + * + * \param[out] descr A USART descriptor which is used to communicate via USART + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to as set of functions pointers + * + * \return Initialization status. + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); + +/** + * \brief Deinitialize USART interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and + * if the given hardware is permitted to be deinitialized. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return De-initialization status. + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); + +/** + * \brief Enable USART interface + * + * Enables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Enabling status. + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); + +/** + * \brief Disable USART interface + * + * Disables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Disabling status. + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve I/O descriptor + * + * This function retrieves the I/O descriptor of the given USART descriptor. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] io An I/O descriptor to retrieve + * + * \return The status of the I/O descriptor retrieving. + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); + +/** + * \brief Specify action for flow control pins + * + * This function sets the action (or state) for the flow control pins + * if the flow control is enabled. + * It sets the state of flow control pins only if the automatic support of + * the flow control is not supported by the hardware. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] state A state to set the flow control pins + * + * \return The status of flow control action setup. + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state); + +/** + * \brief Set USART baud rate + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] baud_rate A baud rate to set + * + * \return The status of baud rate setting. + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); + +/** + * \brief Set USART data order + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] data_order A data order to set + * + * \return The status of data order setting. + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); + +/** + * \brief Set USART mode + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] mode A mode to set + * + * \return The status of mode setting. + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); + +/** + * \brief Set USART parity + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] parity A parity to set + * + * \return The status of parity setting. + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); + +/** + * \brief Set USART stop bits + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] stop_bits Stop bits to set + * + * \return The status of stop bits setting. + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); + +/** + * \brief Set USART character size + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] size A character size to set + * + * \return The status of character size setting. + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins + * if the flow control is enabled. + * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case + * if the flow control is done by the hardware + * and the pins state cannot be read out. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] state The state of flow control pins + * + * \return The status of flow control state reading. + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state); + +/** + * \brief Check if the USART transmitter is empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART TX empty checking. + * \retval 0 The USART transmitter is not empty + * \retval 1 The USART transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Check if the USART receiver is not empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART RX empty checking. + * \retval 1 The USART receiver is not empty + * \retval 0 The USART receiver is empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usart_sync_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_cmcc.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_cmcc.h new file mode 100644 index 0000000..cb26091 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_cmcc.h @@ -0,0 +1,277 @@ +/** + * \file + * + * \brief Generic CMCC(Cortex M Cache Controller) related functionality. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef HPL_CMCC_H_ +#define HPL_CMCC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * \Cache driver MACROS + */ +#define CMCC_DISABLE 0U +#define CMCC_ENABLE 1U +#define IS_CMCC_DISABLED 0U +#define IS_CMCC_ENABLED 1U +#define CMCC_WAY_NOS 4U +#define CMCC_LINE_NOS 64U +#define CMCC_MONITOR_DISABLE 0U + +/** + * \brief Cache size configurations + */ +enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB }; + +/** + * \brief Way Numbers + */ +enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 }; + +/** + * \brief Cache monitor configurations + */ +enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT }; + +/** + * \brief Cache configuration structure + */ +struct _cache_cfg { + enum conf_cache_size cache_size; + bool data_cache_disable; + bool inst_cache_disable; + bool gclk_gate_disable; +}; + +/** + * \brief Cache enable status + */ +static inline bool _is_cache_enabled(const void *hw) +{ + return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false); +} + +/** + * \brief Cache disable status + */ +static inline bool _is_cache_disabled(const void *hw) +{ + return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false); +} + +/** + * \brief Cache enable + */ +static inline int32_t _cmcc_enable(const void *hw) +{ + int32_t return_value; + + if (_is_cache_disabled(hw)) { + hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN); + return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE; + } else { + return_value = ERR_NO_CHANGE; + } + + return return_value; +} + +/** + * \brief Cache disable + */ +static inline int32_t _cmcc_disable(const void *hw) +{ + hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos)); + while (!(_is_cache_disabled(hw))) + ; + + return ERR_NONE; +} + +/** + * \brief Initialize Cache Module + * + * This function initialize low level cmcc module configuration. + * + * \return initialize status + */ +int32_t _cmcc_init(void); + +/** + * \brief Configure CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] cache configuration structure pointer + * + * \return status of operation + */ +int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl); + +/** + * \brief Enable data cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache + * + * \return status of operation + */ +int32_t _cmcc_enable_data_cache(const void *hw, bool value); + +/** + * \brief Enable instruction cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache + * + * \return status of operation + */ +int32_t _cmcc_enable_inst_cache(const void *hw, bool value); + +/** + * \brief Enable clock gating in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate + * + * \return status of operation + */ +int32_t _cmcc_enable_clock_gating(const void *hw, bool value); + +/** + * \brief Configure the cache size in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache size configuration enumerator + * 0->1K, 1->2K, 2->4K(default) + * + * \return status of operation + */ +int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size); + +/** + * \brief Lock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_lock_way(const void *hw, enum way_num_index); + +/** + * \brief Unlock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_unlock_way(const void *hw, enum way_num_index); + +/** + * \brief Invalidate the mentioned cache line in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num" enumerator (valid arg is 0-3) + * \param[in] line number (valid arg is 0-63 as each way will have 64 lines) + * + * \return status of operation + */ +int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num); + +/** + * \brief Invalidate entire cache entries in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_invalidate_all(const void *hw); + +/** + * \brief Configure cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache monitor configurations enumerator + * + * \return status of operation + */ +int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg); + +/** + * \brief Enable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_enable_monitor(const void *hw); + +/** + * \brief Disable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_disable_monitor(const void *hw); + +/** + * \brief Reset cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_reset_monitor(const void *hw); + +/** + * \brief Get cache monitor event counter value from CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return event counter value + */ +uint32_t _cmcc_get_monitor_event_count(const void *hw); + +#ifdef __cplusplus +} +#endif +#endif /* HPL_CMCC_H_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_core.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_core.h new file mode 100644 index 0000000..9324c43 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_core.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief CPU core related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_H_INCLUDED +#define _HPL_CORE_H_INCLUDED + +/** + * \addtogroup HPL Core + * + * \section hpl_core_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_core_port.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_delay.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_delay.h new file mode 100644 index 0000000..a0f1ac8 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_delay.h @@ -0,0 +1,97 @@ +/** + * \file + * + * \brief Delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DELAY_H_INCLUDED +#define _HPL_DELAY_H_INCLUDED + +/** + * \addtogroup HPL Delay + * + * \section hpl_delay_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Initialize delay functionality + * + * \param[in] hw The pointer to hardware instance + */ +void _delay_init(void *const hw); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + * + * \param[in] us The amount of us to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_us(const uint16_t us); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + * + * \param[in] ms The amount of ms to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_ms(const uint16_t ms); + +/** + * \brief Delay loop to delay n number of cycles + * + * \param[in] hw The pointer to hardware instance + * \param[in] cycles The amount of cycles to delay for + */ +void _delay_cycles(void *const hw, uint32_t cycles); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_dma.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_dma.h new file mode 100644 index 0000000..1e08434 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_dma.h @@ -0,0 +1,176 @@ +/** + * \file + * + * \brief DMA related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DMA_H_INCLUDED +#define _HPL_DMA_H_INCLUDED + +/** + * \addtogroup HPL DMA + * + * \section hpl_dma_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct _dma_resource; + +/** + * \brief DMA callback types + */ +enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; + +/** + * \brief DMA interrupt callbacks + */ +struct _dma_callbacks { + void (*transfer_done)(struct _dma_resource *resource); + void (*error)(struct _dma_resource *resource); +}; + +/** + * \brief DMA resource structure + */ +struct _dma_resource { + struct _dma_callbacks dma_cb; + void * back; +}; + +/** + * \brief Initialize DMA + * + * This function does low level DMA configuration. + * + * \return initialize status + */ +int32_t _dma_init(void); + +/** + * \brief Set destination address + * + * \param[in] channel DMA channel to set destination address for + * \param[in] dst Destination address + * + * \return setting status + */ +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); + +/** + * \brief Set source address + * + * \param[in] channel DMA channel to set source address for + * \param[in] src Source address + * + * \return setting status + */ +int32_t _dma_set_source_address(const uint8_t channel, const void *const src); + +/** + * \brief Set next descriptor address + * + * \param[in] current_channel Current DMA channel to set next descriptor address + * \param[in] next_channel Next DMA channel used as next descriptor + * + * \return setting status + */ +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel); + +/** + * \brief Enable/disable source address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set source address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); + +/** + * \brief Enable/disable Destination address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set destination address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable); +/** + * \brief Set the amount of data to be transfered per transaction + * + * \param[in] channel DMA channel to set data amount for + * \param[in] amount Data amount + * + * \return status of operation + */ +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); + +/** + * \brief Trigger DMA transaction on the given channel + * + * \param[in] channel DMA channel to trigger transaction on + * + * \return status of operation + */ +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); + +/** + * \brief Retrieves DMA resource structure + * + * \param[out] resource The resource to be retrieved + * \param[in] channel DMA channel to retrieve structure for + * + * \return status of operation + */ +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); + +/** + * \brief Enable/disable DMA interrupt + * + * \param[in] channel DMA channel to enable/disable interrupt for + * \param[in] type The type of interrupt to disable/enable if applicable + * \param[in] state Enable or disable + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_DMA_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_evsys.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_evsys.h new file mode 100644 index 0000000..e7fc7b4 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_evsys.h @@ -0,0 +1,94 @@ +/** + * \file + * + * \brief Event system related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_EVSYS_H_INCLUDED +#define _HPL_EVSYS_H_INCLUDED + +/** + * \addtogroup HPL EVSYS + * + * \section hpl_eveys_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Initialize event system. + * + * \return Status of operation. + */ +int32_t _event_system_init(void); + +/** + * \brief Deinitialize event system. + * + * \return Status of operation. + */ +int32_t _event_system_deinit(void); + +/** + * \brief Enable/disable event reception by the given user from the given + * channel + * + * \param[in] user A user to enable + * \param[in] channel A channel the user is assigned to + * \param[in] on true to enable, false to disable + * + * \return Status of operation. + */ +int32_t _event_system_enable_user(const uint16_t user, const uint16_t channel, const bool on); + +/** + * \brief Enable/disable event generation by the given generator for the given + * channel + * + * \param[in] generator A generator to enable + * \param[in] channel A channel the user is assigned to + * \param[in] on true to enable, false to disable + * + * \return Status of operation. + */ +int32_t _event_system_enable_generator(const uint16_t generator, const uint16_t channel, const bool on); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_EVSYS_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_gpio.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_gpio.h new file mode 100644 index 0000000..5cdd387 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_gpio.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief Port related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GPIO_H_INCLUDED +#define _HPL_GPIO_H_INCLUDED + +/** + * \addtogroup HPL Port + * + * \section hpl_port_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \brief Macros for the pin and port group, lower 5 + * bits stands for pin number in the group, higher 3 + * bits stands for port group + */ +#define GPIO_PIN(n) (((n)&0x1Fu) << 0) +#define GPIO_PORT(n) ((n) >> 5) +#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) +#define GPIO_PIN_FUNCTION_OFF 0xffffffff + +/** + * \brief PORT pull mode settings + */ +enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; + +/** + * \brief PORT direction settins + */ +enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; + +/** + * \brief PORT group abstraction + */ + +enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Port initialization function + * + * Port initialization function should setup the port module based + * on a static configuration file, this function should normally + * not be called directly, but is a part of hal_init() + */ +void _gpio_init(void); + +/** + * \brief Set direction on port with mask + * + * Set data direction for each pin, or disable the pin + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input + * and disable input buffer to disable the pin + * GPIO_DIRECTION_IN = set pin direction to input + * and enable input buffer to enable the pin + * GPIO_DIRECTION_OUT = set pin direction to output + * and disable input buffer + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction); + +/** + * \brief Set output level on port with mask + * + * Sets output state on pin to high or low with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + * \param[in] level true = pin level is set to 1 + * false = pin level is set to 0 + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); + +/** + * \brief Change output level to the opposite with mask + * + * Change pin output level to the opposite with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); + +/** + * \brief Get input levels on all port pins + * + * Get input level on all port pins, will read IN register if configured to + * input and OUT register if configured as output + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port); + +/** + * \brief Set pin pull mode + * + * Set pull mode on a single pin + * + * \notice This function will automatically change pin direction to input + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] pin The pin in the group that pull mode should be selected + * for + * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled + * GPIO_PULL_DOWN = pull resistor on pin will pull pin + * level to ground level + * GPIO_PULL_UP = pull resistor on pin will pull pin + * level to VCC + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode); + +/** + * \brief Set gpio function + * + * Select which function a gpio is used for + * + * \param[in] gpio The gpio to set function for + * \param[in] function The gpio function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); + +#include +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_async.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_async.h new file mode 100644 index 0000000..8a9491d --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_async.h @@ -0,0 +1,205 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED +#define _HPL_I2C_M_ASYNC_H_INCLUDED + +#include "hpl_i2c_m_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c master callback names + */ +enum _i2c_m_async_callback_type { + I2C_M_ASYNC_DEVICE_ERROR, + I2C_M_ASYNC_DEVICE_TX_COMPLETE, + I2C_M_ASYNC_DEVICE_RX_COMPLETE +}; + +struct _i2c_m_async_device; + +typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); +typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); + +/** + * \brief i2c callback pointers structure + */ +struct _i2c_m_async_callback { + _i2c_error_cb_t error; + _i2c_complete_cb_t tx_complete; + _i2c_complete_cb_t rx_complete; +}; + +/** + * \brief i2c device structure + */ +struct _i2c_m_async_device { + struct _i2c_m_service service; + void * hw; + struct _i2c_m_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C in interrupt mode + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c interrupt device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C in interrupt mode + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Register callback to I2C + * + * This function does low level I2C callback register. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] cb_type The callback type request + * \param[in] func The callback function pointer + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, + FUNC_PTR func); + +/** + * \brief Generate stop condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Operation status + * \retval 0 Operation executed successfully + * \retval <0 Operation failed + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Returns the number of bytes left or not used in the I2C message buffer + * + * This function will return the number of bytes left (not written to the bus) or still free + * (not received from the bus) in the message buffer, depending on direction of transmission. + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Number of bytes or error code + * \retval >0 Positive number indicating bytes left + * \retval 0 Buffer is full/empty depending on direction + * \retval <0 Error code + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable/disable I2C master interrupt + * + * param[in] device The pointer to I2C master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_sync.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_sync.h new file mode 100644 index 0000000..ce173ae --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_sync.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_SYNC_H_INCLUDED +#define _HPL_I2C_M_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c flags + */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_BUSY 0x0100 +#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ +#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ +#define I2C_M_FAIL 0x1000 +#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ + +/** + * \brief i2c Return codes + */ +#define I2C_OK 0 /* Operation successful */ +#define I2C_ACK -1 /* Received ACK from device on I2C bus */ +#define I2C_NACK -2 /* Received NACK from device on I2C bus */ +#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ +#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ +#define I2C_ERR_BUS -5 /* Bus error */ +#define I2C_ERR_BUSY -6 /* Device busy */ +#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ + +/** + * \brief i2c I2C Modes + */ +#define I2C_STANDARD_MODE 0x00 +#define I2C_FASTMODE 0x01 +#define I2C_HIGHSPEED_MODE 0x02 + +/** + * \brief i2c master message structure + */ +struct _i2c_m_msg { + uint16_t addr; + volatile uint16_t flags; + int32_t len; + uint8_t * buffer; +}; + +/** + * \brief i2c master service + */ +struct _i2c_m_service { + struct _i2c_m_msg msg; + uint16_t mode; + uint16_t trise; +}; + +/** + * \brief i2c sync master device structure + */ +struct _i2c_m_sync_device { + struct _i2c_m_service service; + void * hw; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Send send condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_dev The pointer to i2c device struct + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_async.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_async.h new file mode 100644 index 0000000..92a5765 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_async.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED +#define _HPL_I2C_S_ASYNC_H_INCLUDED + +#include "hpl_i2c_s_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c callback types + */ +enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; + +/** + * \brief Forward declaration of I2C Slave device + */ +struct _i2c_s_async_device; + +/** + * \brief i2c slave callback function type + */ +typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); + +/** + * \brief i2c slave callback pointers structure + */ +struct _i2c_s_async_callback { + void (*error)(struct _i2c_s_async_device *const device); + void (*tx)(struct _i2c_s_async_device *const device); + void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); +}; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_async_device { + void * hw; + struct _i2c_s_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize asynchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c interrupt device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); + +/** + * \brief Deinitialize asynchronous I2C in interrupt mode + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); + +/** + * \brief Abort data transmission + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); + +/** + * \brief Enable/disable I2C slave interrupt + * + * param[in] device The pointer to I2C slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool disable); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_sync.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_sync.h new file mode 100644 index 0000000..93b5934 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_sync.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_SYNC_H_INCLUDED +#define _HPL_I2C_S_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I2C Slave status type + */ +typedef uint32_t i2c_s_status_t; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_sync_device { + void *hw; +}; + +#include + +/** + * \name HPL functions + */ + +/** + * \brief Initialize synchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize synchronous I2C slave + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); + +/** + * \brief Clear the Data Ready interrupt flag + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device); + +/** + * \brief Read a byte from the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Data received via I2C interface. + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if I2C is ready to send next byte + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the ready check. + * \retval true if the I2C is ready to send next byte + * \retval false if the I2C is not ready to send next byte + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if there is data received by I2C + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the data received check. + * \retval true if the I2C has received a byte + * \retval false if the I2C has not received a byte + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_init.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_init.h new file mode 100644 index 0000000..71bf49c --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_init.h @@ -0,0 +1,124 @@ +/** + * \file + * + * \brief Init related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_INIT_H_INCLUDED +#define _HPL_INIT_H_INCLUDED + +/** + * \addtogroup HPL Init + * + * \section hpl_init_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initializes clock sources + */ +void _sysctrl_init_sources(void); + +/** + * \brief Initializes Power Manager + */ +void _pm_init(void); + +/** + * \brief Initialize generators + */ +void _gclk_init_generators(void); + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void); + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _sysctrl_init_referenced_generators(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _oscctrl_init_referenced_generators(void); + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void); + +/** + * \brief Initialize clock generator + */ +void _lpmcu_misc_regs_init(void); + +/** + * \brief Initialize clock generator + */ +void _pmc_init(void); + +/** + * \brief Set performance level + * + * \param[in] level The performance level to set + */ +void _set_performance_level(const uint8_t level); + +/** + * \brief Initialize the chip + */ +void _init_chip(void); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_irq.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_irq.h new file mode 100644 index 0000000..2894944 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_irq.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief IRQ related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_IRQ_H_INCLUDED +#define _HPL_IRQ_H_INCLUDED + +/** + * \addtogroup HPL IRQ + * + * \section hpl_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief IRQ descriptor + */ +struct _irq_descriptor { + void (*handler)(void *parameter); + void *parameter; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve current IRQ number + * + * \return The current IRQ number + */ +uint8_t _irq_get_current(void); + +/** + * \brief Disable the given IRQ + * + * \param[in] n The number of IRQ to disable + */ +void _irq_disable(uint8_t n); + +/** + * \brief Set the given IRQ + * + * \param[in] n The number of IRQ to set + */ +void _irq_set(uint8_t n); + +/** + * \brief Clear the given IRQ + * + * \param[in] n The number of IRQ to clear + */ +void _irq_clear(uint8_t n); + +/** + * \brief Enable the given IRQ + * + * \param[in] n The number of IRQ to enable + */ +void _irq_enable(uint8_t n); + +/** + * \brief Register IRQ handler + * + * \param[in] number The number registered IRQ + * \param[in] irq The pointer to irq handler to register + * + * \return The status of IRQ handler registering + * \retval -1 Passed parameters were invalid + * \retval 0 The registering is completed successfully + */ +void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_missing_features.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_missing_features.h new file mode 100644 index 0000000..7071db2 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_missing_features.h @@ -0,0 +1,37 @@ +/** + * \file + * + * \brief Family-dependent missing features expected by HAL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_MISSING_FEATURES +#define _HPL_MISSING_FEATURES + +#endif /* _HPL_MISSING_FEATURES */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_pwm.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_pwm.h new file mode 100644 index 0000000..ff87052 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_pwm.h @@ -0,0 +1,193 @@ +/** + * \file + * + * \brief PWM related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_PWM_H_INCLUDED +#define _HPL_PWM_H_INCLUDED + +/** + * \addtogroup HPL PWM + * + * \section hpl_pwm_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief PWM callback types + */ +enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB }; + +/** + * \brief PWM pulse-width period + */ +typedef uint32_t pwm_period_t; + +/** + * \brief PWM device structure + * + * The PWM device structure forward declaration. + */ +struct _pwm_device; + +/** + * \brief PWM interrupt callbacks + */ +struct _pwm_callback { + void (*pwm_period_cb)(struct _pwm_device *device); + void (*pwm_error_cb)(struct _pwm_device *device); +}; + +/** + * \brief PWM descriptor device structure + */ +struct _pwm_device { + struct _pwm_callback callback; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief PWM functions, pointers to low-level functions + */ +struct _pwm_hpl_interface { + int32_t (*init)(struct _pwm_device *const device, void *const hw); + void (*deinit)(struct _pwm_device *const device); + void (*start_pwm)(struct _pwm_device *const device); + void (*stop_pwm)(struct _pwm_device *const device); + void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); + bool (*is_pwm_enabled)(const struct _pwm_device *const device); + pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device); + uint32_t (*pwm_get_duty)(const struct _pwm_device *const device); + void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); +}; +/** + * \brief Initialize TC + * + * This function does low level TC configuration. + * + * \param[in] device The pointer to PWM device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _pwm_init(struct _pwm_device *const device, void *const hw); + +/** + * \brief Deinitialize TC + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_deinit(struct _pwm_device *const device); + +/** + * \brief Retrieve offset of the given tc hardware instance + * + * \param[in] device The pointer to PWM device instance + * + * \return The offset of the given tc hardware instance + */ +uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device); + +/** + * \brief Start hardware pwm + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_enable(struct _pwm_device *const device); + +/** + * \brief Stop hardware pwm + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_disable(struct _pwm_device *const device); + +/** + * \brief Set pwm parameter + * + * \param[in] device The pointer to PWM device instance + * \param[in] period Total period of one PWM cycle. + * \param[in] duty_cycle Period of PWM first half during one cycle. + */ +void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); + +/** + * \brief Check if pwm is working + * + * \param[in] device The pointer to PWM device instance + * + * \return Check status. + * \retval true The given pwm is working + * \retval false The given pwm is not working + */ +bool _pwm_is_enabled(const struct _pwm_device *const device); + +/** + * \brief Get pwm waveform period value + * + * \param[in] device The pointer to PWM device instance + * + * \return Period value. + */ +pwm_period_t _pwm_get_period(const struct _pwm_device *const device); + +/** + * \brief Get pwm waveform duty cycle value + * + * \param[in] device The pointer to PWM device instance + * + * \return Duty cycle value + */ +uint32_t _pwm_get_duty(const struct _pwm_device *const device); + +/** + * \brief Enable/disable PWM interrupt + * + * param[in] device The pointer to PWM device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_PWM_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_ramecc.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_ramecc.h new file mode 100644 index 0000000..d79d514 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_ramecc.h @@ -0,0 +1,100 @@ +/** + * \file + * + * \brief RAMECC related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RAMECC_H_INCLUDED +#define _HPL_RAMECC_H_INCLUDED + +/** + * \addtogroup HPL RAMECC + * + * \section hpl_ramecc_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief RAMECC callback type + */ +typedef void (*ramecc_cb_t)(const uint32_t data); + +/** + * \brief RAMECC callback types + */ +enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB }; + +/** + * \brief RAMECC interrupt callbacks + */ +struct _ramecc_callbacks { + ramecc_cb_t dual_bit_err; + ramecc_cb_t single_bit_err; +}; + +/** + * \brief RAMECC device structure + */ +struct _ramecc_device { + struct _ramecc_callbacks ramecc_cb; + struct _irq_descriptor irq; +}; + +/** + * \brief Initialize RAMECC + * + * This function does low level RAMECC configuration. + * + * \return initialize status + */ +int32_t _ramecc_init(void); + +/** + * \brief Register RAMECC callback + * + * \param[in] type The type of callback + * \param[in] cb A callback function + */ +void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_RAMECC_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_reset.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_reset.h new file mode 100644 index 0000000..d627ea6 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_reset.h @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief Reset related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RESET_H_INCLUDED +#define _HPL_RESET_H_INCLUDED + +/** + * \addtogroup HPL Reset + * + * \section hpl_reset_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Reset reason enumeration + * + * The list of possible reset reasons. + */ +enum reset_reason { + RESET_REASON_POR = 1, + RESET_REASON_BOD12 = 2, + RESET_REASON_BOD33 = 4, + RESET_REASON_NVM = 8, + RESET_REASON_EXT = 16, + RESET_REASON_WDT = 32, + RESET_REASON_SYST = 64, + RESET_REASON_BACKUP = 128 +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve the reset reason + * + * Retrieves the reset reason of the last MCU reset. + * + *\return An enum value indicating the reason of the last reset. + */ +enum reset_reason _get_reset_reason(void); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_sleep.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_sleep.h new file mode 100644 index 0000000..6731ec3 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_sleep.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SLEEP_H_INCLUDED +#define _HPL_SLEEP_H_INCLUDED + +/** + * \addtogroup HPL Sleep + * + * \section hpl_sleep_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Set the sleep mode for the device + * + * This function sets the sleep mode for the device. + * For an overview of which systems are disabled in sleep for the different + * sleep modes see datasheet. + * + * \param[in] mode Sleep mode to use + * + * \return the status of a sleep request + * \retval -1 The requested sleep mode was invalid + * \retval 0 The operation completed successfully, sleep mode is set + */ +int32_t _set_sleep_mode(const uint8_t mode); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi.h new file mode 100644 index 0000000..a5652e5 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi.h @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_H_INCLUDED +#define _HPL_SPI_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SPI Dummy char is used when reading data from the SPI slave + */ +#define SPI_DUMMY_CHAR 0x1ff + +/** + * \brief SPI message to let driver to process + */ +//@{ +struct spi_msg { + /** Pointer to the output data buffer */ + uint8_t *txbuf; + /** Pointer to the input data buffer */ + uint8_t *rxbuf; + /** Size of the message data in SPI characters */ + uint32_t size; +}; +//@} + +/** + * \brief SPI transfer modes + * SPI transfer mode controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + */ +enum spi_transfer_mode { + /** Leading edge is rising edge, data sample on leading edge. */ + SPI_MODE_0, + /** Leading edge is rising edge, data sample on trailing edge. */ + SPI_MODE_1, + /** Leading edge is falling edge, data sample on leading edge. */ + SPI_MODE_2, + /** Leading edge is falling edge, data sample on trailing edge. */ + SPI_MODE_3 +}; + +/** + * \brief SPI character sizes + * The character size influence the way the data is sent/received. + * For char size <= 8 data is stored byte by byte. + * For char size between 9 ~ 16 data is stored in 2-byte length. + * Note that the default and recommended char size is 8 bit since it's + * supported by all system. + */ +enum spi_char_size { + /** Character size is 8 bit. */ + SPI_CHAR_SIZE_8 = 0, + /** Character size is 9 bit. */ + SPI_CHAR_SIZE_9 = 1, + /** Character size is 10 bit. */ + SPI_CHAR_SIZE_10 = 2, + /** Character size is 11 bit. */ + SPI_CHAR_SIZE_11 = 3, + /** Character size is 12 bit. */ + SPI_CHAR_SIZE_12 = 4, + /** Character size is 13 bit. */ + SPI_CHAR_SIZE_13 = 5, + /** Character size is 14 bit. */ + SPI_CHAR_SIZE_14 = 6, + /** Character size is 15 bit. */ + SPI_CHAR_SIZE_15 = 7, + /** Character size is 16 bit. */ + SPI_CHAR_SIZE_16 = 8 +}; + +/** + * \brief SPI data order + */ +enum spi_data_order { + /** MSB goes first. */ + SPI_DATA_ORDER_MSB_1ST = 0, + /** LSB goes first. */ + SPI_DATA_ORDER_LSB_1ST = 1 +}; + +/** \brief Transfer descriptor for SPI + * Transfer descriptor holds TX and RX buffers + */ +struct spi_xfer { + /** Pointer to data buffer to TX */ + uint8_t *txbuf; + /** Pointer to data buffer to RX */ + uint8_t *rxbuf; + /** Size of data characters to TX & RX */ + uint32_t size; +}; + +/** SPI generic driver. */ +struct spi_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Reference start of sync/async variables */ + uint32_t sync_async_misc[1]; +}; + +/** + * \brief Calculate the baudrate value for hardware to use to set baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] clk Clock frequency (Hz) for baudrate generation. + * \param[in] baud Target baudrate (bps). + * \return Error or baudrate value. + * \retval >0 Baudrate value. + * \retval ERR_INVALID_ARG Calculation fail. + */ +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_async.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_async.h new file mode 100644 index 0000000..8e5a848 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_async.h @@ -0,0 +1,131 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_ASYNC_H_INCLUDED +#define _HPL_SPI_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Callbacks the SPI driver must offer in async mode + */ +//@{ +/** The callback types */ +enum _spi_async_dev_cb_type { + /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_TX, + /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_RX, + /** Callback type for \ref _spi_async_dev_cb_complete_t. */ + SPI_DEV_CB_COMPLETE, + /** Callback type for error */ + SPI_DEV_CB_ERROR, + /** Number of callbacks. */ + SPI_DEV_CB_N +}; + +struct _spi_async_dev; + +/** \brief The prototype for callback on SPI transfer error. + * If status code is zero, it indicates the normal completion, that is, + * SS deactivation. + * If status code belows zero, it indicates complete. + */ +typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status); + +/** \brief The prototype for callback on SPI transmit/receive event + * For TX, the callback is invoked when transmit is done or ready to start + * transmit. + * For RX, the callback is invoked when receive is done or ready to read data, + * see \ref _spi_async_dev_read_one_t on data reading. + * Without DMA enabled, the callback is invoked on each character event. + * With DMA enabled, the callback is invoked on DMA buffer done. + */ +typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_async_dev_callbacks { + /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t tx; + /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t rx; + /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ + _spi_async_dev_cb_xfer_t complete; + /** Error callback, see \ref */ + _spi_async_dev_cb_error_t err; +}; +//@} + +/** + * \brief SPI async driver + */ +//@{ + +/** SPI driver to support async HAL */ +struct _spi_async_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; + + /** \brief Pointer to callback functions, ignored for polling mode + * Pointer to the callback functions so that initialize the driver to + * handle interrupts. + */ + struct _spi_async_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; +}; +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_dma.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_dma.h new file mode 100644 index 0000000..04a3015 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_dma.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Common SPI DMA related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_DMA_H_INCLUDED +#define _HPL_SPI_DMA_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** The callback types */ +enum _spi_dma_dev_cb_type { + /** Callback type for DMA transmit. */ + SPI_DEV_CB_DMA_TX, + /** Callback type for DMA receive. */ + SPI_DEV_CB_DMA_RX, + /** Callback type for DMA error. */ + SPI_DEV_CB_DMA_ERROR, + /** Number of callbacks. */ + SPI_DEV_CB_DMA_N +}; + +struct _spi_dma_dev; + +/** + * \brief The prototype for callback on SPI DMA. + */ +typedef void (*_spi_dma_cb_t)(struct _dma_resource *resource); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_dma_dev_callbacks { + _spi_dma_cb_t tx; + _spi_dma_cb_t rx; + _spi_dma_cb_t error; +}; + +/** SPI driver to support DMA HAL */ +struct _spi_dma_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Pointer to callback functions */ + struct _spi_dma_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; + /** DMA resource */ + struct _dma_resource *resource; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _HPL_SPI_DMA_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_async.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_async.h new file mode 100644 index 0000000..8d3555e --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_async.h @@ -0,0 +1,243 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED +#define _HPL_SPI_M_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_m_async_dev _spi_async_dev + +#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on after data transmission complate + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_dma.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_dma.h new file mode 100644 index 0000000..2b48300 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_dma.h @@ -0,0 +1,182 @@ +/** + * \file + * + * \brief SPI Master DMA related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_DMA_H_INCLUDED +#define _HPL_SPI_M_DMA_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI dma device driver. */ +#define _spi_m_dma_dev _spi_dma_dev + +#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); + +/** + * \brief Register the SPI device callback + * \param[in] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); + +/** \brief Do SPI data transfer (TX & RX) with DMA + * Log the TX & RX buffers and transfer them in background. It never blocks. + * + * \param[in] dev Pointer to the SPI device instance. + * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). + * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). + * \param[in] length spi transfer data length. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy. + */ +int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, + const uint16_t length); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_sync.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_sync.h new file mode 100644 index 0000000..38df15b --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_sync.h @@ -0,0 +1,166 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_SYNC_H_INCLUDED +#define _HPL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_m_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); + +/** + * \brief Deinitialize SPI + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI char size + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Transfer the whole message without interrupt + * Transfer the message, it will keep waiting until the message finish or + * error. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] msg Pointer to the message instance to process. + * \return Error or number of characters transferred. + * \retval ERR_BUSY SPI hardware is not ready to start transfer (not + * enabled, busy applying settings, ...). + * \retval SPI_ERR_OVERFLOW Overflow error. + * \retval >=0 Number of characters transferred. + */ +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_async.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_async.h new file mode 100644 index 0000000..5647243 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_async.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED +#define _HPL_SPI_S_ASYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_s_async_dev _spi_async_dev + +#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on Slave Select (SS) rising + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_sync.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_sync.h new file mode 100644 index 0000000..ff4c811 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_sync.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_SYNC_H_INCLUDED +#define _HPL_SPI_S_SYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_s_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retval 0 OK Status + */ +int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); + +/** + * \brief Check if TX ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return TX ready state + * \retval true TX ready + * \retval false TX not ready + */ +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if RX character ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return RX character ready state + * \retval true RX character ready + * \retval false RX character not ready + */ +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if SS deactiviation detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return SS deactiviation state + * \retval true SS deactiviation detected + * \retval false SS deactiviation not detected + */ +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if error is detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return Error detection state + * \retval true Error detected + * \retval false Error not detected + */ +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_sync.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_sync.h new file mode 100644 index 0000000..dc88648 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_sync.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_SYNC_H_INCLUDED +#define _HPL_SPI_SYNC_H_INCLUDED + +#include +#include + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * \section hpl_spi_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI driver to support sync HAL */ +struct _spi_sync_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; +}; + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_timer.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_timer.h new file mode 100644 index 0000000..9bdfbb7 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_timer.h @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief Timer related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_TIMER_H_INCLUDED +#define _HPL_TIMER_H_INCLUDED + +/** + * \addtogroup HPL Timer + * + * \section hpl_timer_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Timer device structure + * + * The Timer device structure forward declaration. + */ +struct _timer_device; + +/** + * \brief Timer interrupt callbacks + */ +struct _timer_callbacks { + void (*period_expired)(struct _timer_device *device); +}; + +/** + * \brief Timer device structure + */ +struct _timer_device { + struct _timer_callbacks timer_cb; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief Timer functions, pointers to low-level functions + */ +struct _timer_hpl_interface { + int32_t (*init)(struct _timer_device *const device, void *const hw); + void (*deinit)(struct _timer_device *const device); + void (*start_timer)(struct _timer_device *const device); + void (*stop_timer)(struct _timer_device *const device); + void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles); + uint32_t (*get_period)(const struct _timer_device *const device); + bool (*is_timer_started)(const struct _timer_device *const device); + void (*set_timer_irq)(struct _timer_device *const device); +}; +/** + * \brief Initialize TCC + * + * This function does low level TCC configuration. + * + * \param[in] device The pointer to timer device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _timer_init(struct _timer_device *const device, void *const hw); + +/** + * \brief Deinitialize TCC + * + * \param[in] device The pointer to timer device instance + */ +void _timer_deinit(struct _timer_device *const device); + +/** + * \brief Start hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_start(struct _timer_device *const device); + +/** + * \brief Stop hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_stop(struct _timer_device *const device); + +/** + * \brief Set timer period + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles); + +/** + * \brief Retrieve timer period + * + * \param[in] device The pointer to timer device instance + * + * \return Timer period + */ +uint32_t _timer_get_period(const struct _timer_device *const device); + +/** + * \brief Check if timer is running + * + * \param[in] device The pointer to timer device instance + * + * \return Check status. + * \retval true The given timer is running + * \retval false The given timer is not running + */ +bool _timer_is_started(const struct _timer_device *const device); + +/** + * \brief Set timer IRQ + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_irq(struct _timer_device *const device); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_TIMER_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart.h new file mode 100644 index 0000000..0e09501 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart.h @@ -0,0 +1,113 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_H_INCLUDED +#define _HPL_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART flow control state + */ +union usart_flow_control_state { + struct { + uint8_t cts : 1; + uint8_t rts : 1; + uint8_t unavailable : 1; + uint8_t reserved : 5; + } bit; + uint8_t value; +}; + +/** + * \brief USART baud rate mode + */ +enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; + +/** + * \brief USART data order + */ +enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; + +/** + * \brief USART mode + */ +enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; + +/** + * \brief USART parity + */ +enum usart_parity { + USART_PARITY_EVEN = 0, + USART_PARITY_ODD = 1, + USART_PARITY_NONE = 2, + USART_PARITY_SPACE = 3, + USART_PARITY_MARK = 4 +}; + +/** + * \brief USART stop bits mode + */ +enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; + +/** + * \brief USART character size + */ +enum usart_character_size { + USART_CHARACTER_SIZE_8BITS = 0, + USART_CHARACTER_SIZE_9BITS = 1, + USART_CHARACTER_SIZE_5BITS = 5, + USART_CHARACTER_SIZE_6BITS = 6, + USART_CHARACTER_SIZE_7BITS = 7 +}; + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_async.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_async.h new file mode 100644 index 0000000..3f833d1 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_async.h @@ -0,0 +1,270 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_ASYNC_H_INCLUDED +#define _HPL_USART_ASYNC_H_INCLUDED + +/** + * \addtogroup HPL USART + * + * \section hpl_usart_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_usart.h" +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART callback types + */ +enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; + +/** + * \brief USART device structure + * + * The USART device structure forward declaration. + */ +struct _usart_async_device; + +/** + * \brief USART interrupt callbacks + */ +struct _usart_async_callbacks { + void (*tx_byte_sent)(struct _usart_async_device *device); + void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); + void (*tx_done_cb)(struct _usart_async_device *device); + void (*error_cb)(struct _usart_async_device *device); +}; + +/** + * \brief USART descriptor device structure + */ +struct _usart_async_device { + struct _usart_async_callbacks usart_cb; + struct _irq_descriptor irq; + void * hw; +}; +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize asynchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_deinit(struct _usart_async_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable(struct _usart_async_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_disable(struct _usart_async_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); + +/** + * \brief Enable data register empty interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); + +/** + * \brief Enable transmission complete interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); + +/** + * \brief Enable/disable USART interrupt + * + * param[in] device The pointer to USART device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_sync.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_sync.h new file mode 100644 index 0000000..abc7264 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_sync.h @@ -0,0 +1,254 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SYNC_USART_H_INCLUDED +#define _HPL_SYNC_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor device structure + */ +struct _usart_sync_device { + void *hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_deinit(struct _usart_sync_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_enable(struct _usart_sync_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_disable(struct _usart_sync_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); + +/** + * \brief Read a byte from the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + * + * \return Data received via USART interface. + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART transmitter has sent the byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART transmitter has sent the byte + * \retval false if the USART transmitter has not send the byte + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device); + +/** + * \brief Check if there is data received by USART + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the data received check. + * \retval true if the USART has received a byte + * \retval false if the USART has not received a byte + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_atomic.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_atomic.c new file mode 100644 index 0000000..f56418e --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_atomic.c @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief Critical sections related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_atomic.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Disable interrupts, enter critical section + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic) +{ + *atomic = __get_PRIMASK(); + __disable_irq(); + __DMB(); +} + +/** + * \brief Exit atomic section + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic) +{ + __DMB(); + __set_PRIMASK(*atomic); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t atomic_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_cache.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_cache.c new file mode 100644 index 0000000..b2e75aa --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_cache.c @@ -0,0 +1,78 @@ +/** + * \file + * + * \brief HAL cache functionality implementation. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include + +/** + * \brief Initialize cache module + */ +int32_t cache_init(void) +{ + return _cmcc_init(); +} + +/** + * \brief Enable cache module + */ +int32_t cache_enable(const void *hw) +{ + return _cmcc_enable(hw); +} + +/** + * \brief Disable cache module + */ +int32_t cache_disable(const void *hw) +{ + return _cmcc_disable(hw); +} + +/** + * \brief Configure cache module + */ +int32_t cache_configure(const void *hw, struct _cache_cfg *cache) +{ + return _cmcc_configure(hw, cache); +} + +/** + * \brief Invalidate entire cache entries + */ +int32_t cache_invalidate_all(const void *hw) +{ + return _cmcc_invalidate_all(hw); +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_delay.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_delay.c new file mode 100644 index 0000000..6f77cc7 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_delay.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief HAL delay related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include "hal_delay.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief The pointer to a hardware instance used by the driver. + */ +static void *hardware; + +/** + * \brief Initialize Delay driver + */ +void delay_init(void *const hw) +{ + _delay_init(hardware = hw); +} + +/** + * \brief Perform delay in us + */ +void delay_us(const uint16_t us) +{ + _delay_cycles(hardware, _get_cycles_for_us(us)); +} + +/** + * \brief Perform delay in ms + */ +void delay_ms(const uint16_t ms) +{ + _delay_cycles(hardware, _get_cycles_for_ms(ms)); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t delay_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_evsys.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_evsys.c new file mode 100644 index 0000000..0ce8ce5 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_evsys.c @@ -0,0 +1,98 @@ +/** + * \file + * + * \brief HAL event system related functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_evsys.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Initialize event system. + */ +int32_t event_system_init(void) +{ + return _event_system_init(); +} + +/** + * \brief Deinitialize event system. + */ +int32_t event_system_deinit(void) +{ + return _event_system_deinit(); +} + +/** + * \brief Enable event reception by the given user from the given channel + */ +int32_t event_system_enable_user(const uint16_t user, const uint16_t channel) +{ + return _event_system_enable_user(user, channel, true); +} + +/** + * \brief Enable event reception by the given user from the given channel + */ +int32_t event_system_disable_user(const uint16_t user, const uint16_t channel) +{ + return _event_system_enable_user(user, channel, false); +} + +/** + * \brief Enable event generation by the given generator for the given channel + */ +int32_t event_system_enable_generator(const uint16_t generator, const uint16_t channel) +{ + return _event_system_enable_generator(generator, channel, true); +} + +/** + * \brief Enable event generation by the given generator for the given channel + */ +int32_t event_system_disable_generator(const uint16_t generator, const uint16_t channel) +{ + return _event_system_enable_generator(generator, channel, false); +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version + */ +uint32_t event_system_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_gpio.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_gpio.c new file mode 100644 index 0000000..00dfea6 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_gpio.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_gpio.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t gpio_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_init.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_init.c new file mode 100644 index 0000000..fb65341 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_init.c @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief HAL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_init.h" + +/** + * \brief Driver version + */ +#define HAL_INIT_VERSION 0x00000001u + +/** + * \brief Retrieve the current driver version + */ +uint32_t init_get_version(void) +{ + return HAL_INIT_VERSION; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_io.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_io.c new file mode 100644 index 0000000..7e8feb0 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_io.c @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief I/O functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t io_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \brief I/O write interface + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->write(io_descr, buf, length); +} + +/** + * \brief I/O read interface + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->read(io_descr, buf, length); +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_sleep.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_sleep.c new file mode 100644 index 0000000..89472f1 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_sleep.c @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Sleep related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_sleep.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode) +{ + if (ERR_NONE != _set_sleep_mode(mode)) + return ERR_INVALID_ARG; + + _go_to_sleep(); + + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version + */ +uint32_t sleep_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_spi_m_dma.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_spi_m_dma.c new file mode 100644 index 0000000..976d0f8 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_spi_m_dma.c @@ -0,0 +1,183 @@ +/** + * \file + * + * \brief I/O SPI DMA related functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_atomic.h" +#include "hal_spi_m_dma.h" +#include +#include + +/** + * \brief Driver version + */ +#define SPI_DRIVER_VERSION 0x00000001u + +static int32_t _spi_m_dma_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length); +static int32_t _spi_m_dma_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t length); + +/** + * \brief Initialize the SPI HAL instance function pointer for HPL APIs. + */ +void spi_m_dma_set_func_ptr(struct spi_m_dma_descriptor *spi, void *const func) +{ + ASSERT(spi); + spi->func = (struct _spi_m_dma_hpl_interface *)func; +} + +int32_t spi_m_dma_init(struct spi_m_dma_descriptor *spi, void *const hw) +{ + int32_t rc = 0; + ASSERT(spi && hw); + spi->dev.prvt = (void *)hw; + rc = _spi_m_dma_init(&spi->dev, hw); + + if (rc) { + return rc; + } + + spi->io.read = _spi_m_dma_io_read; + spi->io.write = _spi_m_dma_io_write; + + return ERR_NONE; +} + +void spi_m_dma_deinit(struct spi_m_dma_descriptor *spi) +{ + ASSERT(spi); + _spi_m_dma_deinit(&spi->dev); +} + +void spi_m_dma_enable(struct spi_m_dma_descriptor *spi) +{ + ASSERT(spi); + _spi_m_dma_enable(&spi->dev); +} + +void spi_m_dma_disable(struct spi_m_dma_descriptor *spi) +{ + ASSERT(spi); + _spi_m_dma_disable(&spi->dev); +} + +int32_t spi_m_dma_set_baudrate(struct spi_m_dma_descriptor *spi, const uint32_t baud_val) +{ + ASSERT(spi); + return _spi_m_dma_set_baudrate(&spi->dev, baud_val); +} + +int32_t spi_m_dma_set_mode(struct spi_m_dma_descriptor *spi, const enum spi_transfer_mode mode) +{ + ASSERT(spi); + return _spi_m_dma_set_mode(&spi->dev, mode); +} + +int32_t spi_m_dma_set_char_size(struct spi_m_dma_descriptor *spi, const enum spi_char_size char_size) +{ + ASSERT(spi); + return _spi_m_dma_set_char_size(&spi->dev, char_size); +} + +int32_t spi_m_dma_set_data_order(struct spi_m_dma_descriptor *spi, const enum spi_data_order dord) +{ + ASSERT(spi); + return _spi_m_dma_set_data_order(&spi->dev, dord); +} + +/** \brief Do SPI read in background + * + * It never blocks and return quickly, user check status or set callback to + * know when data is ready to process. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[out] p_buf Pointer to the buffer to store read data. + * \param[in] size Size of the data in number of characters. + * \return ERR_NONE on success, or an error code on failure. + * \retval ERR_NONE Success, transfer started. + * \retval ERR_BUSY Busy. + */ +static int32_t _spi_m_dma_io_read(struct io_descriptor *io, uint8_t *const buf, const uint16_t length) +{ + ASSERT(io); + + struct spi_m_dma_descriptor *spi = CONTAINER_OF(io, struct spi_m_dma_descriptor, io); + return _spi_m_dma_transfer(&spi->dev, NULL, buf, length); +} + +/** \brief Do SPI data write in background + * + * The data read back is discarded. + * + * It never blocks and return quickly, user check status or set callback to + * know when data is sent. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[in] p_buf Pointer to the buffer to store data to write. + * \param[in] size Size of the data in number of characters. + * + * \return ERR_NONE on success, or an error code on failure. + * \retval ERR_NONE Success, transfer started. + * \retval ERR_BUSY Busy. + */ +static int32_t _spi_m_dma_io_write(struct io_descriptor *io, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io); + + struct spi_m_dma_descriptor *spi = CONTAINER_OF(io, struct spi_m_dma_descriptor, io); + return _spi_m_dma_transfer(&spi->dev, buf, NULL, length); +} + +int32_t spi_m_dma_transfer(struct spi_m_dma_descriptor *spi, uint8_t const *txbuf, uint8_t *const rxbuf, + const uint16_t length) +{ + ASSERT(spi); + return _spi_m_dma_transfer(&spi->dev, txbuf, rxbuf, length); +} + +void spi_m_dma_register_callback(struct spi_m_dma_descriptor *spi, const enum spi_m_dma_cb_type type, + spi_m_dma_cb_t func) +{ + ASSERT(spi); + _spi_m_dma_register_callback(&spi->dev, (enum _spi_dma_dev_cb_type)type, func); +} + +int32_t spi_m_dma_get_io_descriptor(struct spi_m_dma_descriptor *const spi, struct io_descriptor **io) +{ + ASSERT(spi && io); + *io = &spi->io; + + return 0; +} + +uint32_t spi_m_dma_get_version(void) +{ + return SPI_DRIVER_VERSION; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_spi_m_sync.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_spi_m_sync.c new file mode 100644 index 0000000..1a64296 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_spi_m_sync.c @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief I/O SPI related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_spi_m_sync.h" +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Driver version + */ +#define SPI_M_SYNC_DRIVER_VERSION 0x00000001u + +#define SPI_DEACTIVATE_NEXT 0x8000 + +static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length); +static int32_t _spi_m_sync_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t length); + +/** + * \brief Initialize the SPI HAL instance function pointer for HPL APIs. + */ +void spi_m_sync_set_func_ptr(struct spi_m_sync_descriptor *spi, void *const func) +{ + ASSERT(spi); + spi->func = (struct _spi_m_sync_hpl_interface *)func; +} + +int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw) +{ + int32_t rc = 0; + ASSERT(spi && hw); + spi->dev.prvt = (void *)hw; + rc = _spi_m_sync_init(&spi->dev, hw); + + if (rc < 0) { + return rc; + } + + spi->flags = SPI_DEACTIVATE_NEXT; + spi->io.read = _spi_m_sync_io_read; + spi->io.write = _spi_m_sync_io_write; + + return ERR_NONE; +} + +void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + _spi_m_sync_deinit(&spi->dev); +} + +void spi_m_sync_enable(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + _spi_m_sync_enable(&spi->dev); +} + +void spi_m_sync_disable(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + _spi_m_sync_disable(&spi->dev); +} + +int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val) +{ + ASSERT(spi); + return _spi_m_sync_set_baudrate(&spi->dev, baud_val); +} + +int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode) +{ + ASSERT(spi); + return _spi_m_sync_set_mode(&spi->dev, mode); +} + +int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size) +{ + ASSERT(spi); + return _spi_m_sync_set_char_size(&spi->dev, char_size); +} + +int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord) +{ + ASSERT(spi); + return _spi_m_sync_set_data_order(&spi->dev, dord); +} + +/** \brief Do SPI read in polling way + * For SPI master, activate CS, do send 0xFFs and read data, deactivate CS. + * + * It blocks until all data read or error. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[out] buf Pointer to the buffer to store read data. + * \param[in] size Size of the data in number of characters. + * \return Operation status. + * \retval size Success. + * \retval >=0 Time out, with number of characters read. + */ +static int32_t _spi_m_sync_io_read(struct io_descriptor *io, uint8_t *buf, const uint16_t length) +{ + ASSERT(io); + + struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); + struct spi_xfer xfer; + + xfer.rxbuf = buf; + xfer.txbuf = 0; + xfer.size = length; + + return spi_m_sync_transfer(spi, &xfer); +} + +/** \brief Do SPI data write in polling way + * For SPI master, activate CS, do buffer send and deactivate CS. The data back + * is discarded. + * + * The data read back is discarded. + * + * It blocks until all data sent or error. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[in] p_xfer Pointer to the transfer information (\ref spi_transfer). + * \return Operation status. + * \retval size Success. + * \retval >=0 Timeout, with number of characters transferred. + */ +static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io); + + struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); + struct spi_xfer xfer; + + xfer.rxbuf = 0; + xfer.txbuf = (uint8_t *)buf; + xfer.size = length; + + return spi_m_sync_transfer(spi, &xfer); +} + +int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *p_xfer) +{ + struct spi_msg msg; + + ASSERT(spi && p_xfer); + + msg.txbuf = p_xfer->txbuf; + msg.rxbuf = p_xfer->rxbuf; + msg.size = p_xfer->size; + return _spi_m_sync_trans(&spi->dev, &msg); +} + +int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io) +{ + ASSERT(spi && io); + *io = &spi->io; + return 0; +} + +uint32_t spi_m_sync_get_version(void) +{ + return SPI_M_SYNC_DRIVER_VERSION; +} + +#ifdef __cplusplus +} +#endif diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_timer.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_timer.c new file mode 100644 index 0000000..565c6db --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_timer.c @@ -0,0 +1,250 @@ +/** + * \file + * + * \brief Timer functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_timer.h" +#include +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Timer flags + */ +#define TIMER_FLAG_QUEUE_IS_TAKEN 1 +#define TIMER_FLAG_INTERRUPT_TRIGERRED 2 + +static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time); +static void timer_process_counted(struct _timer_device *device); + +/** + * \brief Initialize timer + */ +int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func) +{ + ASSERT(descr && hw); + _timer_init(&descr->device, hw); + descr->time = 0; + descr->device.timer_cb.period_expired = timer_process_counted; + + return ERR_NONE; +} + +/** + * \brief Deinitialize timer + */ +int32_t timer_deinit(struct timer_descriptor *const descr) +{ + ASSERT(descr); + _timer_deinit(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Start timer + */ +int32_t timer_start(struct timer_descriptor *const descr) +{ + ASSERT(descr); + if (_timer_is_started(&descr->device)) { + return ERR_DENIED; + } + _timer_start(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Stop timer + */ +int32_t timer_stop(struct timer_descriptor *const descr) +{ + ASSERT(descr); + if (!_timer_is_started(&descr->device)) { + return ERR_DENIED; + } + _timer_stop(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Set amount of clock cycler per timer tick + */ +int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles) +{ + ASSERT(descr); + _timer_set_period(&descr->device, clock_cycles); + + return ERR_NONE; +} + +/** + * \brief Add timer task + */ +int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task) +{ + ASSERT(descr && task); + + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + if (is_list_element(&descr->tasks, task)) { + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + ASSERT(false); + return ERR_ALREADY_INITIALIZED; + } + task->time_label = descr->time; + timer_add_timer_task(&descr->tasks, task, descr->time); + + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { + CRITICAL_SECTION_ENTER() + descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; + _timer_set_irq(&descr->device); + CRITICAL_SECTION_LEAVE() + } + + return ERR_NONE; +} + +/** + * \brief Remove timer task + */ +int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task) +{ + ASSERT(descr && task); + + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + if (!is_list_element(&descr->tasks, task)) { + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + ASSERT(false); + return ERR_NOT_FOUND; + } + list_delete_element(&descr->tasks, task); + + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { + CRITICAL_SECTION_ENTER() + descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; + _timer_set_irq(&descr->device); + CRITICAL_SECTION_LEAVE() + } + + return ERR_NONE; +} + +/** + * \brief Retrieve the amount of clock cycles in a tick + */ +int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles) +{ + ASSERT(descr && cycles); + *cycles = _timer_get_period(&descr->device); + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t timer_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal Insert a timer task into sorted timer's list + * + * \param[in] head The pointer to the head of timer task list + * \param[in] task The pointer to task to add + * \param[in] time Current timer time + */ +static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time) +{ + struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); + + if (!head) { + list_insert_as_head(list, new_task); + return; + } + + for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { + uint32_t time_left; + + if (it->time_label <= time) { + time_left = it->interval - (time - it->time_label); + } else { + time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; + } + if (time_left >= new_task->interval) + break; + prev = it; + } + + if (it == head) { + list_insert_as_head(list, new_task); + } else { + list_insert_after(prev, new_task); + } +} + +/** + * \internal Process interrupts + */ +static void timer_process_counted(struct _timer_device *device) +{ + struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); + struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); + uint32_t time = ++timer->time; + + if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { + timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED; + return; + } + + while (it && ((time - it->time_label) >= it->interval)) { + struct timer_task *tmp = it; + + list_remove_head(&timer->tasks); + if (TIMER_TASK_REPEAT == tmp->mode) { + tmp->time_label = time; + timer_add_timer_task(&timer->tasks, tmp, time); + } + it = (struct timer_task *)list_get_head(&timer->tasks); + + tmp->cb(tmp); + } +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_usart_sync.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_usart_sync.c new file mode 100644 index 0000000..ab99c1d --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_usart_sync.c @@ -0,0 +1,276 @@ +/** + * \file + * + * \brief I/O USART related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_usart_sync.h" +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief Initialize usart interface + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) +{ + int32_t init_status; + ASSERT(descr && hw); + init_status = _usart_sync_init(&descr->device, hw); + if (init_status) { + return init_status; + } + + descr->io.read = usart_sync_read; + descr->io.write = usart_sync_write; + + return ERR_NONE; +} + +/** + * \brief Uninitialize usart interface + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_deinit(&descr->device); + + descr->io.read = NULL; + descr->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable usart interface + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Disable usart interface + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) +{ + ASSERT(descr && io); + + *io = &descr->io; + return ERR_NONE; +} + +/** + * \brief Specify action for flow control pins + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state) +{ + ASSERT(descr); + _usart_sync_set_flow_control_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Set usart baud rate + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) +{ + ASSERT(descr); + _usart_sync_set_baud_rate(&descr->device, baud_rate); + + return ERR_NONE; +} + +/** + * \brief Set usart data order + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) +{ + ASSERT(descr); + _usart_sync_set_data_order(&descr->device, data_order); + + return ERR_NONE; +} + +/** + * \brief Set usart mode + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) +{ + ASSERT(descr); + _usart_sync_set_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set usart parity + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) +{ + ASSERT(descr); + _usart_sync_set_parity(&descr->device, parity); + + return ERR_NONE; +} + +/** + * \brief Set usart stop bits + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) +{ + ASSERT(descr); + _usart_sync_set_stop_bits(&descr->device, stop_bits); + + return ERR_NONE; +} + +/** + * \brief Set usart character size + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) +{ + ASSERT(descr); + _usart_sync_set_character_size(&descr->device, size); + + return ERR_NONE; +} + +/** + * \brief Retrieve the state of flow control pins + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state) +{ + ASSERT(descr && state); + *state = _usart_sync_get_flow_control_state(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Check if the usart transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_ready_to_send(&descr->device); +} + +/** + * \brief Check if the usart receiver is not empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_byte_received(&descr->device); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t usart_sync_get_version(void) +{ + return DRIVER_VERSION; +} + +/* + * \internal Write the given data to usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf Data to write to usart + * \param[in] length The number of bytes to write + * + * \return The number of bytes written. + */ +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + do { + _usart_sync_write_byte(&descr->device, buf[offset]); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + } while (++offset < length); + while (!_usart_sync_is_transmit_done(&descr->device)) + ; + return (int32_t)offset; +} + +/* + * \internal Read data from usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + do { + while (!_usart_sync_is_byte_received(&descr->device)) + ; + buf[offset] = _usart_sync_read_byte(&descr->device); + } while (++offset < length); + + return (int32_t)offset; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/compiler.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/compiler.h new file mode 100644 index 0000000..f35db3d --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/compiler.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Header + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +/****************************************************************************** + * compiler.h + * + * Created: 05.05.2014 + * Author: N. Fomin + ******************************************************************************/ + +#ifndef _COMPILER_H +#define _COMPILER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef _UNIT_TEST_ +#include "parts.h" +#endif +#include "err_codes.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _COMPILER_H */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/err_codes.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/err_codes.h new file mode 100644 index 0000000..a7aff01 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/err_codes.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Error code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ERROR_CODES_H_INCLUDED +#define ERROR_CODES_H_INCLUDED + +#define ERR_NONE 0 +#define ERR_INVALID_DATA -1 +#define ERR_NO_CHANGE -2 +#define ERR_ABORTED -3 +#define ERR_BUSY -4 +#define ERR_SUSPEND -5 +#define ERR_IO -6 +#define ERR_REQ_FLUSHED -7 +#define ERR_TIMEOUT -8 +#define ERR_BAD_DATA -9 +#define ERR_NOT_FOUND -10 +#define ERR_UNSUPPORTED_DEV -11 +#define ERR_NO_MEMORY -12 +#define ERR_INVALID_ARG -13 +#define ERR_BAD_ADDRESS -14 +#define ERR_BAD_FORMAT -15 +#define ERR_BAD_FRQ -16 +#define ERR_DENIED -17 +#define ERR_ALREADY_INITIALIZED -18 +#define ERR_OVERFLOW -19 +#define ERR_NOT_INITIALIZED -20 +#define ERR_SAMPLERATE_UNAVAILABLE -21 +#define ERR_RESOLUTION_UNAVAILABLE -22 +#define ERR_BAUDRATE_UNAVAILABLE -23 +#define ERR_PACKET_COLLISION -24 +#define ERR_PROTOCOL -25 +#define ERR_PIN_MUX_INVALID -26 +#define ERR_UNSUPPORTED_OP -27 +#define ERR_NO_RESOURCE -28 +#define ERR_NOT_READY -29 +#define ERR_FAILURE -30 +#define ERR_WRONG_LENGTH -31 + +#endif diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/events.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/events.h new file mode 100644 index 0000000..3ee891a --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/events.h @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _EVENTS_H_INCLUDED +#define _EVENTS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \brief List of events. Must start with 0, be unique and follow numerical order. + */ +#define EVENT_IS_READY_TO_SLEEP_ID 0 +#define EVENT_PREPARE_TO_SLEEP_ID 1 +#define EVENT_WOKEN_UP_ID 2 + +#ifdef __cplusplus +} +#endif + +#endif /* _EVENTS_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/parts.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/parts.h new file mode 100644 index 0000000..98bb969 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/parts.h @@ -0,0 +1,41 @@ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +#include "same54.h" + +#include "hri_e54.h" + +#endif /* ATMEL_PARTS_H */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils.h new file mode 100644 index 0000000..1cf2699 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils.h @@ -0,0 +1,368 @@ +/** + * \file + * + * \brief Different macros. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef UTILS_H_INCLUDED +#define UTILS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_macro + * + * @{ + */ + +/** + * \brief Retrieve pointer to parent structure + */ +#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) + +/** + * \brief Retrieve array size + */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param[in] arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set aligned boundary. + */ +#if defined __GNUC__ +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined __ICCARM__ +#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined __CC_ARM +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Flash located data macros + */ +#if defined __GNUC__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __ICCARM__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __CC_ARM +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#endif + +/** + * \brief Optimization + */ +#if defined __GNUC__ +#define OPTIMIZE_HIGH __attribute__((optimize(s))) +#elif defined __CC_ARM +#define OPTIMIZE_HIGH _Pragma("O3") +#elif defined __ICCARM__ +#define OPTIMIZE_HIGH _Pragma("optimize=high") +#endif + +/** + * \brief RAM located function attribute + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define RAMFUNC __ramfunc +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#endif + +/** + * \brief No-init section. + * Place a data object or a function in a no-init section. + */ +#if defined(__CC_ARM) +#define NO_INIT(a) __attribute__((zero_init)) +#elif defined(__ICCARM__) +#define NO_INIT(a) __no_init +#elif defined(__GNUC__) +#define NO_INIT(a) __attribute__((section(".no_init"))) +#endif + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined(__CC_ARM) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined(__ICCARM__) +#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined(__GNUC__) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Define WEAK attribute. + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define WEAK __attribute__((weak)) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define WEAK __weak +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define WEAK __attribute__((weak)) +#endif + +/** + * \brief Pointer to function + */ +typedef void (*FUNC_PTR)(void); + +#define LE_BYTE0(a) ((uint8_t)(a)) +#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) +#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) +#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) + +#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) +#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) + +/** \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + * + * @{ */ + +/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define clz(u) __builtin_clz(u) +#else +#define clz(u) \ + ( \ + ((u) == 0) \ + ? 32 \ + : ((u) & (1ul << 31)) \ + ? 0 \ + : ((u) & (1ul << 30)) \ + ? 1 \ + : ((u) & (1ul << 29)) \ + ? 2 \ + : ((u) & (1ul << 28)) \ + ? 3 \ + : ((u) & (1ul << 27)) \ + ? 4 \ + : ((u) & (1ul << 26)) \ + ? 5 \ + : ((u) & (1ul << 25)) \ + ? 6 \ + : ((u) & (1ul << 24)) \ + ? 7 \ + : ((u) & (1ul << 23)) \ + ? 8 \ + : ((u) & (1ul << 22)) \ + ? 9 \ + : ((u) & (1ul << 21)) \ + ? 10 \ + : ((u) & (1ul << 20)) \ + ? 11 \ + : ((u) & (1ul << 19)) \ + ? 12 \ + : ((u) & (1ul << 18)) \ + ? 13 \ + : ((u) & (1ul << 17)) ? 14 \ + : ((u) & (1ul << 16)) ? 15 \ + : ((u) & (1ul << 15)) ? 16 \ + : ((u) & (1ul << 14)) ? 17 \ + : ((u) & (1ul << 13)) ? 18 \ + : ((u) & (1ul << 12)) ? 19 \ + : ((u) \ + & (1ul \ + << 11)) \ + ? 20 \ + : ((u) \ + & (1ul \ + << 10)) \ + ? 21 \ + : ((u) \ + & (1ul \ + << 9)) \ + ? 22 \ + : ((u) \ + & (1ul \ + << 8)) \ + ? 23 \ + : ((u) & (1ul << 7)) ? 24 \ + : ((u) & (1ul << 6)) ? 25 \ + : ((u) \ + & (1ul \ + << 5)) \ + ? 26 \ + : ((u) & (1ul << 4)) ? 27 \ + : ((u) & (1ul << 3)) ? 28 \ + : ((u) & (1ul << 2)) ? 29 \ + : ( \ + (u) & (1ul << 1)) \ + ? 30 \ + : 31) +#endif + +/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define ctz(u) __builtin_ctz(u) +#else +#define ctz(u) \ + ( \ + (u) & (1ul << 0) \ + ? 0 \ + : (u) & (1ul << 1) \ + ? 1 \ + : (u) & (1ul << 2) \ + ? 2 \ + : (u) & (1ul << 3) \ + ? 3 \ + : (u) & (1ul << 4) \ + ? 4 \ + : (u) & (1ul << 5) \ + ? 5 \ + : (u) & (1ul << 6) \ + ? 6 \ + : (u) & (1ul << 7) \ + ? 7 \ + : (u) & (1ul << 8) \ + ? 8 \ + : (u) & (1ul << 9) \ + ? 9 \ + : (u) & (1ul << 10) \ + ? 10 \ + : (u) & (1ul << 11) \ + ? 11 \ + : (u) & (1ul << 12) \ + ? 12 \ + : (u) & (1ul << 13) \ + ? 13 \ + : (u) & (1ul << 14) \ + ? 14 \ + : (u) & (1ul << 15) \ + ? 15 \ + : (u) & (1ul << 16) \ + ? 16 \ + : (u) & (1ul << 17) \ + ? 17 \ + : (u) & (1ul << 18) \ + ? 18 \ + : (u) & (1ul << 19) ? 19 \ + : (u) & (1ul << 20) ? 20 \ + : (u) & (1ul << 21) ? 21 \ + : (u) & (1ul << 22) ? 22 \ + : (u) & (1ul << 23) ? 23 \ + : (u) & (1ul << 24) ? 24 \ + : (u) & (1ul << 25) ? 25 \ + : (u) & (1ul << 26) ? 26 \ + : (u) & (1ul << 27) ? 27 \ + : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32) +#endif +/** @} */ + +/** + * \brief Counts the number of bits in a mask (no more than 32 bits) + * \param[in] mask Mask of which to count the bits. + */ +#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) + +/** + * \brief Retrieve the start position of bits mask (no more than 32 bits) + * \param[in] mask Mask of which to retrieve the start position. + */ +#define pos_of_mask(mask) ctz(mask) + +/** + * \brief Return division result of a/b and round up the result to the closest + * number divisible by "b" + */ +#define round_up(a, b) (((a)-1) / (b) + 1) + +/** + * \brief Get the minimum of x and y + */ +#define min(x, y) ((x) > (y) ? (y) : (x)) + +/** + * \brief Get the maximum of x and y + */ +#define max(x, y) ((x) > (y) ? (x) : (y)) + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* UTILS_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_assert.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_assert.h new file mode 100644 index 0000000..c2328d6 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_assert.h @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _ASSERT_H_INCLUDED +#define _ASSERT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifndef USE_SIMPLE_ASSERT +//# define USE_SIMPLE_ASSERT +#endif + +/** + * \brief Assert macro + * + * This macro is used to throw asserts. It can be mapped to different function + * based on debug level. + * + * \param[in] condition A condition to be checked; + * assert is thrown if the given condition is false + */ +#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) + +#ifdef DEBUG + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) \ + if (!(condition)) \ + __asm("BKPT #0"); +#else +#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) +#endif + +#else /* DEBUG */ + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) ((void)0) +#else +#define ASSERT_IMPL(condition, file, line) ((void)0) +#endif + +#endif /* DEBUG */ + +/** + * \brief Assert function + * + * This function is used to throw asserts. + * + * \param[in] condition A condition to be checked; assert is thrown if the given + * condition is false + * \param[in] file File name + * \param[in] line Line number + */ +void assert(const bool condition, const char *const file, const int line); + +#ifdef __cplusplus +} +#endif +#endif /* _ASSERT_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_event.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_event.h new file mode 100644 index 0000000..13067c4 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_event.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_EVENT_H_INCLUDED +#define _UTILS_EVENT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * \brief The maximum amount of events + */ +#define EVENT_MAX_AMOUNT 8 + +/** + * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the + * closest number divisible by 8. + */ +#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) + +/** + * \brief The type of event ID. IDs should start with 0 and be in numerical order. + */ +typedef uint8_t event_id_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef uintptr_t event_data_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef void (*event_cb_t)(event_id_t id, event_data_t data); + +/** + * \brief Event structure + */ +struct event { + struct list_element elem; /*! The pointer to next event */ + uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ + event_cb_t cb; /*! Callback to be called when an event occurs */ +}; + +/** + * \brief Subscribe to event + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to subscribe to + * \param[in] cb The callback function to call when the given event occurs + * + * \return The status of subscription + */ +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); + +/** + * \brief Remove event from subscription + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to remove subscription from + * + * \return The status of subscription removing + */ +int32_t event_unsubscribe(struct event *const event, const event_id_t id); + +/** + * \brief Post event + * + * \param[in] id The event ID to post + * \param[in] data The event data to be passed to event subscribers + */ +void event_post(const event_id_t id, const event_data_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_increment_macro.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_increment_macro.h new file mode 100644 index 0000000..464c6cb --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_increment_macro.h @@ -0,0 +1,308 @@ +/** + * \file + * + * \brief Increment macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_INCREMENT_MACRO_H +#define _UTILS_INCREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time increment, result value is entire integer literal + * + * \param[in] val - value to be incremented (254 max) + */ +#define INC_VALUE(val) SP_INC_##val + +// Preprocessor increment implementation +#define SP_INC_0 1 +#define SP_INC_1 2 +#define SP_INC_2 3 +#define SP_INC_3 4 +#define SP_INC_4 5 +#define SP_INC_5 6 +#define SP_INC_6 7 +#define SP_INC_7 8 +#define SP_INC_8 9 +#define SP_INC_9 10 +#define SP_INC_10 11 +#define SP_INC_11 12 +#define SP_INC_12 13 +#define SP_INC_13 14 +#define SP_INC_14 15 +#define SP_INC_15 16 +#define SP_INC_16 17 +#define SP_INC_17 18 +#define SP_INC_18 19 +#define SP_INC_19 20 +#define SP_INC_20 21 +#define SP_INC_21 22 +#define SP_INC_22 23 +#define SP_INC_23 24 +#define SP_INC_24 25 +#define SP_INC_25 26 +#define SP_INC_26 27 +#define SP_INC_27 28 +#define SP_INC_28 29 +#define SP_INC_29 30 +#define SP_INC_30 31 +#define SP_INC_31 32 +#define SP_INC_32 33 +#define SP_INC_33 34 +#define SP_INC_34 35 +#define SP_INC_35 36 +#define SP_INC_36 37 +#define SP_INC_37 38 +#define SP_INC_38 39 +#define SP_INC_39 40 +#define SP_INC_40 41 +#define SP_INC_41 42 +#define SP_INC_42 43 +#define SP_INC_43 44 +#define SP_INC_44 45 +#define SP_INC_45 46 +#define SP_INC_46 47 +#define SP_INC_47 48 +#define SP_INC_48 49 +#define SP_INC_49 50 +#define SP_INC_50 51 +#define SP_INC_51 52 +#define SP_INC_52 53 +#define SP_INC_53 54 +#define SP_INC_54 55 +#define SP_INC_55 56 +#define SP_INC_56 57 +#define SP_INC_57 58 +#define SP_INC_58 59 +#define SP_INC_59 60 +#define SP_INC_60 61 +#define SP_INC_61 62 +#define SP_INC_62 63 +#define SP_INC_63 64 +#define SP_INC_64 65 +#define SP_INC_65 66 +#define SP_INC_66 67 +#define SP_INC_67 68 +#define SP_INC_68 69 +#define SP_INC_69 70 +#define SP_INC_70 71 +#define SP_INC_71 72 +#define SP_INC_72 73 +#define SP_INC_73 74 +#define SP_INC_74 75 +#define SP_INC_75 76 +#define SP_INC_76 77 +#define SP_INC_77 78 +#define SP_INC_78 79 +#define SP_INC_79 80 +#define SP_INC_80 81 +#define SP_INC_81 82 +#define SP_INC_82 83 +#define SP_INC_83 84 +#define SP_INC_84 85 +#define SP_INC_85 86 +#define SP_INC_86 87 +#define SP_INC_87 88 +#define SP_INC_88 89 +#define SP_INC_89 90 +#define SP_INC_90 91 +#define SP_INC_91 92 +#define SP_INC_92 93 +#define SP_INC_93 94 +#define SP_INC_94 95 +#define SP_INC_95 96 +#define SP_INC_96 97 +#define SP_INC_97 98 +#define SP_INC_98 99 +#define SP_INC_99 100 +#define SP_INC_100 101 +#define SP_INC_101 102 +#define SP_INC_102 103 +#define SP_INC_103 104 +#define SP_INC_104 105 +#define SP_INC_105 106 +#define SP_INC_106 107 +#define SP_INC_107 108 +#define SP_INC_108 109 +#define SP_INC_109 110 +#define SP_INC_110 111 +#define SP_INC_111 112 +#define SP_INC_112 113 +#define SP_INC_113 114 +#define SP_INC_114 115 +#define SP_INC_115 116 +#define SP_INC_116 117 +#define SP_INC_117 118 +#define SP_INC_118 119 +#define SP_INC_119 120 +#define SP_INC_120 121 +#define SP_INC_121 122 +#define SP_INC_122 123 +#define SP_INC_123 124 +#define SP_INC_124 125 +#define SP_INC_125 126 +#define SP_INC_126 127 +#define SP_INC_127 128 +#define SP_INC_128 129 +#define SP_INC_129 130 +#define SP_INC_130 131 +#define SP_INC_131 132 +#define SP_INC_132 133 +#define SP_INC_133 134 +#define SP_INC_134 135 +#define SP_INC_135 136 +#define SP_INC_136 137 +#define SP_INC_137 138 +#define SP_INC_138 139 +#define SP_INC_139 140 +#define SP_INC_140 141 +#define SP_INC_141 142 +#define SP_INC_142 143 +#define SP_INC_143 144 +#define SP_INC_144 145 +#define SP_INC_145 146 +#define SP_INC_146 147 +#define SP_INC_147 148 +#define SP_INC_148 149 +#define SP_INC_149 150 +#define SP_INC_150 151 +#define SP_INC_151 152 +#define SP_INC_152 153 +#define SP_INC_153 154 +#define SP_INC_154 155 +#define SP_INC_155 156 +#define SP_INC_156 157 +#define SP_INC_157 158 +#define SP_INC_158 159 +#define SP_INC_159 160 +#define SP_INC_160 161 +#define SP_INC_161 162 +#define SP_INC_162 163 +#define SP_INC_163 164 +#define SP_INC_164 165 +#define SP_INC_165 166 +#define SP_INC_166 167 +#define SP_INC_167 168 +#define SP_INC_168 169 +#define SP_INC_169 170 +#define SP_INC_170 171 +#define SP_INC_171 172 +#define SP_INC_172 173 +#define SP_INC_173 174 +#define SP_INC_174 175 +#define SP_INC_175 176 +#define SP_INC_176 177 +#define SP_INC_177 178 +#define SP_INC_178 179 +#define SP_INC_179 180 +#define SP_INC_180 181 +#define SP_INC_181 182 +#define SP_INC_182 183 +#define SP_INC_183 184 +#define SP_INC_184 185 +#define SP_INC_185 186 +#define SP_INC_186 187 +#define SP_INC_187 188 +#define SP_INC_188 189 +#define SP_INC_189 190 +#define SP_INC_190 191 +#define SP_INC_191 192 +#define SP_INC_192 193 +#define SP_INC_193 194 +#define SP_INC_194 195 +#define SP_INC_195 196 +#define SP_INC_196 197 +#define SP_INC_197 198 +#define SP_INC_198 199 +#define SP_INC_199 200 +#define SP_INC_200 201 +#define SP_INC_201 202 +#define SP_INC_202 203 +#define SP_INC_203 204 +#define SP_INC_204 205 +#define SP_INC_205 206 +#define SP_INC_206 207 +#define SP_INC_207 208 +#define SP_INC_208 209 +#define SP_INC_209 210 +#define SP_INC_210 211 +#define SP_INC_211 212 +#define SP_INC_212 213 +#define SP_INC_213 214 +#define SP_INC_214 215 +#define SP_INC_215 216 +#define SP_INC_216 217 +#define SP_INC_217 218 +#define SP_INC_218 219 +#define SP_INC_219 220 +#define SP_INC_220 221 +#define SP_INC_221 222 +#define SP_INC_222 223 +#define SP_INC_223 224 +#define SP_INC_224 225 +#define SP_INC_225 226 +#define SP_INC_226 227 +#define SP_INC_227 228 +#define SP_INC_228 229 +#define SP_INC_229 230 +#define SP_INC_230 231 +#define SP_INC_231 232 +#define SP_INC_232 233 +#define SP_INC_233 234 +#define SP_INC_234 235 +#define SP_INC_235 236 +#define SP_INC_236 237 +#define SP_INC_237 238 +#define SP_INC_238 239 +#define SP_INC_239 240 +#define SP_INC_240 241 +#define SP_INC_241 242 +#define SP_INC_242 243 +#define SP_INC_243 244 +#define SP_INC_244 245 +#define SP_INC_245 246 +#define SP_INC_246 247 +#define SP_INC_247 248 +#define SP_INC_248 249 +#define SP_INC_249 250 +#define SP_INC_250 251 +#define SP_INC_251 252 +#define SP_INC_252 253 +#define SP_INC_253 254 +#define SP_INC_254 255 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_list.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_list.h new file mode 100644 index 0000000..977e8cc --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_list.h @@ -0,0 +1,164 @@ +/** + * \file + * + * \brief List declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_LIST_H_INCLUDED +#define _UTILS_LIST_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_list + * + * @{ + */ + +#include + +/** + * \brief List element type + */ +struct list_element { + struct list_element *next; +}; + +/** + * \brief List head type + */ +struct list_descriptor { + struct list_element *head; +}; + +/** + * \brief Reset list + * + * \param[in] list The pointer to a list descriptor + */ +static inline void list_reset(struct list_descriptor *const list) +{ + list->head = NULL; +} + +/** + * \brief Retrieve list head + * + * \param[in] list The pointer to a list descriptor + * + * \return A pointer to the head of the given list or NULL if the list is + * empty + */ +static inline void *list_get_head(const struct list_descriptor *const list) +{ + return (void *)list->head; +} + +/** + * \brief Retrieve next list head + * + * \param[in] list The pointer to a list element + * + * \return A pointer to the next list element or NULL if there is not next + * element + */ +static inline void *list_get_next_element(const void *const element) +{ + return element ? ((struct list_element *)element)->next : NULL; +} + +/** + * \brief Insert an element as list head + * + * \param[in] list The pointer to a list element + * \param[in] element An element to insert to the given list + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element); + +/** + * \brief Insert an element after the given list element + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_after(void *const after, void *const element); + +/** + * \brief Insert an element at list end + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element); + +/** + * \brief Check whether an element belongs to a list + * + * \param[in] list The pointer to a list + * \param[in] element An element to check + * + * \return The result of checking + * \retval true If the given element is an element of the given list + * \retval false Otherwise + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element); + +/** + * \brief Removes list head + * + * This function removes the list head and sets the next element after the list + * head as a new list head. + * + * \param[in] list The pointer to a list + * + * \return The pointer to the new list head of NULL if the list head is NULL + */ +void *list_remove_head(struct list_descriptor *const list); + +/** + * \brief Removes the list element + * + * \param[in] list The pointer to a list + * \param[in] element An element to remove + * + * \return The result of element removing + * \retval true The given element is removed from the given list + * \retval false The given element is not an element of the given list + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_repeat_macro.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_repeat_macro.h new file mode 100644 index 0000000..89e6f52 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_repeat_macro.h @@ -0,0 +1,322 @@ +/** + * \file + * + * \brief Repeat macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_REPEAT_MACRO_H +#define _UTILS_REPEAT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Sequently repeates specified macro for n times (255 max). + * + * Specified macro shall have two arguments: macro(arg, i) + * arg - user defined argument, which have the same value for all iterations. + * i - iteration number; numbering begins from zero and increments on each + * iteration. + * + * \param[in] macro - macro to be repeated + * \param[in] arg - user defined argument for repeated macro + * \param[in] n - total number of iterations (255 max) + */ +#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) + +#define REPEAT1(macro, arg, n) macro(arg, n) +#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) +#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) +#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) +#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) +#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) +#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) +#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) +#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) +#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) +#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) +#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) +#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) +#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) +#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) +#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) +#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) +#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) +#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) +#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) +#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) +#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) +#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) +#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) +#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) +#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) +#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) +#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) +#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) +#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) +#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) +#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) +#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) +#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) +#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) +#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) +#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) +#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) +#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) +#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) +#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) +#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) +#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) +#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) +#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) +#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) +#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) +#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) +#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) +#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) +#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) +#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) +#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) +#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) +#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) +#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) +#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) +#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) +#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) +#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) +#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) +#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) +#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) +#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) +#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) +#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) +#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) +#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) +#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) +#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) +#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) +#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) +#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) +#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) +#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) +#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) +#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) +#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) +#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) +#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) +#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) +#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) +#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) +#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) +#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) +#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) +#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) +#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) +#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) +#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) +#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) +#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) +#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) +#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) +#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) +#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) +#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) +#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) +#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) +#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) +#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) +#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) +#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) +#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) +#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) +#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) +#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) +#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) +#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) +#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) +#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) +#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) +#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) +#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) +#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) +#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) +#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) +#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) +#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) +#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) +#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) +#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) +#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) +#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) +#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) +#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) +#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) +#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) +#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) +#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) +#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) +#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) +#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) +#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) +#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) +#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) +#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) +#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) +#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) +#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) +#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) +#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) +#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) +#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) +#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) +#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) +#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) +#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) +#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) +#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) +#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) +#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) +#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) +#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) +#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) +#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) +#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) +#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) +#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) +#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) +#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) +#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) +#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) +#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) +#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) +#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) +#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) +#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) +#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) +#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) +#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) +#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) +#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) +#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) +#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) +#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) +#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) +#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) +#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) +#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) +#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) +#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) +#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) +#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) +#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) +#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) +#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) +#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) +#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) +#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) +#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) +#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) +#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) +#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) +#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) +#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) +#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) +#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) +#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) +#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) +#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) +#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) +#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) +#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) +#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) +#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) +#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) +#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) +#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) +#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) +#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) +#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) +#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) +#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) +#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) +#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) +#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) +#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) +#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) +#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) +#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) +#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) +#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) +#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) +#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) +#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) +#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) +#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) +#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) +#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) +#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) +#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) +#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) +#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) +#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) +#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) +#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) +#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) +#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) +#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) +#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) +#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) +#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) +#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) +#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) +#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) +#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) +#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) +#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) +#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) +#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) +#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) +#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) +#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) +#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_assert.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_assert.c new file mode 100644 index 0000000..b376c97 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_assert.c @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include + +/** + * \brief Assert function + */ +void assert(const bool condition, const char *const file, const int line) +{ + if (!(condition)) { + __asm("BKPT #0"); + } + (void)file; + (void)line; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_event.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_event.c new file mode 100644 index 0000000..d1af9d0 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_event.c @@ -0,0 +1,125 @@ +/** + * \file + * + * \brief Events implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) + +static struct list_descriptor events; +static uint8_t subscribed[EVENT_MASK_SIZE]; + +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + + ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); + + if (event->mask[position] & mask) { + return ERR_NO_CHANGE; /* Already subscribed */ + } + + if (!is_list_element(&events, event)) { + memset(event->mask, 0, EVENT_MASK_SIZE); + list_insert_as_head(&events, event); + } + event->cb = cb; + event->mask[position] |= mask; + + subscribed[position] |= mask; + + return ERR_NONE; +} + +int32_t event_unsubscribe(struct event *const event, const event_id_t id) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + uint8_t i; + + ASSERT(event && (id < EVENT_MAX_AMOUNT)); + + if (!(event->mask[position] & mask)) { + return ERR_NO_CHANGE; /* Already unsubscribed */ + } + + event->mask[position] &= ~mask; + + /* Check if there are more subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + break; + } + } + if (!current) { + subscribed[position] &= ~mask; + } + + /* Remove event from the list. Can be unsave, document it! */ + for (i = 0; i < ARRAY_SIZE(event->mask); i++) { + if (event->mask[i]) { + return ERR_NONE; + } + } + list_delete_element(&events, event); + + return ERR_NONE; +} + +void event_post(const event_id_t id, const event_data_t data) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + + ASSERT((id < EVENT_MAX_AMOUNT)); + + if (!(subscribed[position] & mask)) { + return; /* No subscribers */ + } + + /* Find all subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + current->cb(id, data); + } + } +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_list.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_list.c new file mode 100644 index 0000000..4006a01 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_list.c @@ -0,0 +1,136 @@ +/** + * \file + * + * \brief List functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Check whether element belongs to list + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element) +{ + struct list_element *it; + for (it = list->head; it; it = it->next) { + if (it == element) { + return true; + } + } + + return false; +} + +/** + * \brief Insert an element as list head + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element) +{ + ASSERT(!is_list_element(list, element)); + + ((struct list_element *)element)->next = list->head; + list->head = (struct list_element *)element; +} + +/** + * \brief Insert an element after the given list element + */ +void list_insert_after(void *const after, void *const element) +{ + ((struct list_element *)element)->next = ((struct list_element *)after)->next; + ((struct list_element *)after)->next = (struct list_element *)element; +} + +/** + * \brief Insert an element at list end + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element) +{ + struct list_element *it = list->head; + + ASSERT(!is_list_element(list, element)); + + if (!list->head) { + list->head = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; + return; + } + + while (it->next) { + it = it->next; + } + it->next = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; +} + +/** + * \brief Removes list head + */ +void *list_remove_head(struct list_descriptor *const list) +{ + if (list->head) { + struct list_element *tmp = list->head; + + list->head = list->head->next; + return (void *)tmp; + } + + return NULL; +} + +/** + * \brief Removes list element + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element) +{ + if (!element) { + return false; + } + + if (list->head == element) { + list->head = list->head->next; + return true; + } else { + struct list_element *it = list->head; + + while (it && it->next != element) { + it = it->next; + } + if (it) { + it->next = ((struct list_element *)element)->next; + return true; + } + } + + return false; +} + +//@} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_syscalls.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_syscalls.c new file mode 100644 index 0000000..79e2f1f --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_syscalls.c @@ -0,0 +1,152 @@ +/** + * \file + * + * \brief Syscalls for SAM0 (GCC). + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#undef errno +extern int errno; +extern int _end; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *_new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +/** + * \brief Replacement of C library of _sbrk + */ +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char * prev_heap; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t)prev_heap; +} + +/** + * \brief Replacement of C library of link + */ +extern int link(char *old, char *_new) +{ + (void)old, (void)_new; + return -1; +} + +/** + * \brief Replacement of C library of _close + */ +extern int _close(int file) +{ + (void)file; + return -1; +} + +/** + * \brief Replacement of C library of _fstat + */ +extern int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + + return 0; +} + +/** + * \brief Replacement of C library of _isatty + */ +extern int _isatty(int file) +{ + (void)file; + return 1; +} + +/** + * \brief Replacement of C library of _lseek + */ +extern int _lseek(int file, int ptr, int dir) +{ + (void)file, (void)ptr, (void)dir; + return 0; +} + +/** + * \brief Replacement of C library of _exit + */ +extern void _exit(int status) +{ + printf("Exiting with status %d.\n", status); + + for (;;) + ; +} + +/** + * \brief Replacement of C library of _kill + */ +extern void _kill(int pid, int sig) +{ + (void)pid, (void)sig; + return; +} + +/** + * \brief Replacement of C library of _getpid + */ +extern int _getpid(void) +{ + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/cmcc/hpl_cmcc.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/cmcc/hpl_cmcc.c new file mode 100644 index 0000000..bddf0e1 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/cmcc/hpl_cmcc.c @@ -0,0 +1,354 @@ +/** + * \file + * + * \brief Generic CMCC(Cortex M Cache Controller) related functionality. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include +#include + +/** + * \brief Initialize Cache Module + * + * This function does low level cache configuration. + * + * \return initialize status + */ +int32_t _cmcc_init(void) +{ + int32_t return_value; + + _cmcc_disable(CMCC); + + if (_is_cache_disabled(CMCC)) { + hri_cmcc_write_CFG_reg( + CMCC, + (CMCC_CFG_CSIZESW(CONF_CMCC_CACHE_SIZE) | (CONF_CMCC_DATA_CACHE_DISABLE << CMCC_CFG_DCDIS_Pos) + | (CONF_CMCC_INST_CACHE_DISABLE << CMCC_CFG_ICDIS_Pos) | (CONF_CMCC_CLK_GATING_DISABLE))); + + _cmcc_enable(CMCC); + return_value = _is_cache_enabled(CMCC) == true ? ERR_NONE : ERR_FAILURE; + } else { + return_value = ERR_NOT_INITIALIZED; + } + + return return_value; +} + +/** + * \brief Configure CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] cache configuration structure pointer + * + * \return status of operation + */ +int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl) +{ + int32_t return_value; + + _cmcc_disable(hw); + + if (_is_cache_disabled(hw)) { + hri_cmcc_write_CFG_reg( + hw, + (CMCC_CFG_CSIZESW(cache_ctrl->cache_size) | (cache_ctrl->data_cache_disable << CMCC_CFG_DCDIS_Pos) + | (cache_ctrl->inst_cache_disable << CMCC_CFG_ICDIS_Pos) | (cache_ctrl->gclk_gate_disable))); + + return_value = ERR_NONE; + } else { + return_value = ERR_NOT_INITIALIZED; + } + + return return_value; +} + +/** + * \brief Enable data cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache + * + * \return status of operation + */ +int32_t _cmcc_enable_data_cache(const void *hw, bool value) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp &= ~CMCC_CFG_DCDIS; + tmp |= ((!value) << CMCC_CFG_DCDIS_Pos); + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Enable instruction cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache + * + * \return status of operation + */ +int32_t _cmcc_enable_inst_cache(const void *hw, bool value) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp &= ~CMCC_CFG_ICDIS; + tmp |= ((!value) << CMCC_CFG_ICDIS_Pos); + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Enable clock gating in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate + * + * \return status of operation + */ +int32_t _cmcc_enable_clock_gating(const void *hw, bool value) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp |= value; + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Configure the cache size in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache size configuration enumerator + * 0->1K, 1->2K, 2->4K(default) + * + * \return status of operation + */ +int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp &= (~CMCC_CFG_CSIZESW_Msk); + tmp |= (size << CMCC_CFG_CSIZESW_Pos); + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Lock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_lock_way(const void *hw, enum way_num_index num) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_LCKWAY_reg(hw); + tmp |= CMCC_LCKWAY_LCKWAY(num); + + ret = _cmcc_disable(hw); + hri_cmcc_write_LCKWAY_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Unlock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_unlock_way(const void *hw, enum way_num_index num) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_LCKWAY_reg(hw); + tmp &= (~CMCC_LCKWAY_LCKWAY(num)); + + ret = _cmcc_disable(hw); + hri_cmcc_write_LCKWAY_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Invalidate the mentioned cache line in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num" enumerator (valid arg is 0-3) + * \param[in] line number (valid arg is 0-63 as each way will have 64 lines) + * + * \return status of operation + */ +int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num) +{ + int32_t return_value; + + if ((way_num < CMCC_WAY_NOS) && (line_num < CMCC_LINE_NOS)) { + _cmcc_disable(hw); + while (!(_is_cache_disabled(hw))) + ; + hri_cmcc_write_MAINT1_reg(hw, (CMCC_MAINT1_INDEX(line_num) | CMCC_MAINT1_WAY(way_num))); + return_value = ERR_NONE; + } else { + return_value = ERR_INVALID_ARG; + } + + return return_value; +} + +/** + * \brief Invalidate entire cache entries in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_invalidate_all(const void *hw) +{ + int32_t return_value; + + _cmcc_disable(hw); + if (_is_cache_disabled(hw)) { + hri_cmcc_write_MAINT0_reg(hw, CMCC_MAINT0_INVALL); + return_value = ERR_NONE; + } else { + return_value = ERR_FAILURE; + } + + return return_value; +} + +/** + * \brief Configure cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache monitor configurations enumerator + * + * \return status of operation + */ +int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg) +{ + hri_cmcc_write_MCFG_reg(hw, CMCC_MCFG_MODE(monitor_cfg)); + + return ERR_NONE; +} + +/** + * \brief Enable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_enable_monitor(const void *hw) +{ + hri_cmcc_write_MEN_reg(hw, CMCC_MEN_MENABLE); + + return ERR_NONE; +} + +/** + * \brief Disable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_disable_monitor(const void *hw) +{ + hri_cmcc_write_MEN_reg(hw, (CMCC_MONITOR_DISABLE << CMCC_MEN_MENABLE_Pos)); + + return ERR_NONE; +} + +/** + * \brief Reset cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_reset_monitor(const void *hw) +{ + hri_cmcc_write_MCTRL_reg(hw, CMCC_MCTRL_SWRST); + + return ERR_NONE; +} + +/** + * \brief Get cache monitor event counter value from CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return event counter value + */ +uint32_t _cmcc_get_monitor_event_count(const void *hw) +{ + return hri_cmcc_read_MSR_reg(hw); +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_core_m4.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_core_m4.c new file mode 100644 index 0000000..4680ec3 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_core_m4.c @@ -0,0 +1,241 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#ifndef _UNIT_TEST_ +#include +#endif +#include +#include + +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 1000000 +#endif + +#if CONF_CPU_FREQUENCY < 1000 +#define CPU_FREQ_POWER 3 +#elif CONF_CPU_FREQUENCY < 10000 +#define CPU_FREQ_POWER 4 +#elif CONF_CPU_FREQUENCY < 100000 +#define CPU_FREQ_POWER 5 +#elif CONF_CPU_FREQUENCY < 1000000 +#define CPU_FREQ_POWER 6 +#elif CONF_CPU_FREQUENCY < 10000000 +#define CPU_FREQ_POWER 7 +#elif CONF_CPU_FREQUENCY < 100000000 +#define CPU_FREQ_POWER 8 +#elif CONF_CPU_FREQUENCY < 1000000000 +#define CPU_FREQ_POWER 9 +#endif + +/** + * \brief The array of interrupt handlers + */ +struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; + +/** + * \brief Reset MCU + */ +void _reset_mcu(void) +{ + NVIC_SystemReset(); +} + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void) +{ + __DSB(); + __WFI(); +} + +/** + * \brief Retrieve current IRQ number + */ +uint8_t _irq_get_current(void) +{ + return (uint8_t)__get_IPSR() - 16; +} + +/** + * \brief Disable the given IRQ + */ +void _irq_disable(uint8_t n) +{ + NVIC_DisableIRQ((IRQn_Type)n); +} + +/** + * \brief Set the given IRQ + */ +void _irq_set(uint8_t n) +{ + NVIC_SetPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Clear the given IRQ + */ +void _irq_clear(uint8_t n) +{ + NVIC_ClearPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Enable the given IRQ + */ +void _irq_enable(uint8_t n) +{ + NVIC_EnableIRQ((IRQn_Type)n); +} + +/** + * \brief Register IRQ handler + */ +void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) +{ + ASSERT(n < PERIPH_COUNT_IRQn); + + _irq_table[n] = irq; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Default_Handler(void) +{ + while (1) { + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 9: + return (us * (freq / 1000000) + 2) / 3; + case 8: + return (us * (freq / 100000) + 29) / 30; + case 7: + return (us * (freq / 10000) + 299) / 300; + case 6: + return (us * (freq / 1000) + 2999) / 3000; + case 5: + return (us * (freq / 100) + 29999) / 30000; + case 4: + return (us * (freq / 10) + 299999) / 300000; + default: + return (us * freq + 2999999) / 3000000; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +uint32_t _get_cycles_for_us(const uint16_t us) +{ + return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 9: + return (ms * (freq / 1000000) + 2) / 3 * 1000; + case 8: + return (ms * (freq / 100000) + 2) / 3 * 100; + case 7: + return (ms * (freq / 10000) + 2) / 3 * 10; + case 6: + return (ms * (freq / 1000) + 2) / 3; + case 5: + return (ms * (freq / 100) + 29) / 30; + case 4: + return (ms * (freq / 10) + 299) / 300; + default: + return (ms * (freq / 1) + 2999) / 3000; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +uint32_t _get_cycles_for_ms(const uint16_t ms) +{ + return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} +/** + * \brief Initialize delay functionality + */ +void _delay_init(void *const hw) +{ + (void)hw; +} +/** + * \brief Delay loop to delay n number of cycles + */ +void _delay_cycles(void *const hw, uint32_t cycles) +{ +#ifndef _UNIT_TEST_ + (void)hw; + (void)cycles; +#if defined(__GNUC__) && (__ARMCOMPILER_VERSION > 6000000) /* Keil MDK with ARM Compiler 6 */ + __asm(".align 3 \n" + "__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n"); +#elif defined __GNUC__ + __asm(".syntax unified\n" + ".align 3 \n" + "__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n" + ".syntax divided"); +#elif defined __CC_ARM + __asm("__delay:\n" + "subs cycles, cycles, #1\n" + "bhi __delay\n"); +#elif defined __ICCARM__ + __asm("__delay:\n" + "subs r1, r1, #1\n" + "bhi.n __delay\n"); +#endif +#endif +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_core_port.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_core_port.h new file mode 100644 index 0000000..3f3e8f2 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_core_port.h @@ -0,0 +1,61 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_PORT_H_INCLUDED +#define _HPL_CORE_PORT_H_INCLUDED + +#include + +/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR + * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), + * there will be assembling errors. + * So the following things are not included for assembling. + */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + +#ifndef _UNIT_TEST_ +#include +#endif + +/** + * \brief Check if it's in ISR handling + * \return \c true if it's in ISR + */ +static inline bool _is_in_isr(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); +} + +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_init.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_init.c new file mode 100644 index 0000000..be0db93 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_init.c @@ -0,0 +1,78 @@ +/** + * \file + * + * \brief HPL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +/* Referenced GCLKs (out of 0~11), should be initialized firstly + */ +#define _GCLK_INIT_1ST 0x00000000 +/* Not referenced GCLKs, initialized last */ +#define _GCLK_INIT_LAST 0x00000FFF + +/** + * \brief Initialize the hardware abstraction layer + */ +void _init_chip(void) +{ + hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); + + _osc32kctrl_init_sources(); + _oscctrl_init_sources(); + _mclk_init(); +#if _GCLK_INIT_1ST + _gclk_init_generators_by_fref(_GCLK_INIT_1ST); +#endif + _oscctrl_init_referenced_generators(); + _gclk_init_generators_by_fref(_GCLK_INIT_LAST); + +#if CONF_DMAC_ENABLE + hri_mclk_set_AHBMASK_DMAC_bit(MCLK); + _dma_init(); +#endif + +#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) + _port_event_init(); +#endif + +#if CONF_CMCC_ENABLE + cache_init(); +#endif +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/dmac/hpl_dmac.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/dmac/hpl_dmac.c new file mode 100644 index 0000000..7dddc9d --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/dmac/hpl_dmac.c @@ -0,0 +1,260 @@ + +/** + * \file + * + * \brief Generic DMAC related functionality. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include + +/* Section containing first descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _descriptor_section[DMAC_CH_NUM]; + +/* Section containing current descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _write_back_section[DMAC_CH_NUM]; + +/* Array containing callbacks for DMAC channels */ +static struct _dma_resource _resources[DMAC_CH_NUM]; + +/* DMAC interrupt handler */ +static void _dmac_handler(void); + +/* This macro DMAC configuration */ +#define DMAC_CHANNEL_CFG(i, n) \ + {(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | DMAC_CHCTRLA_TRIGACT(CONF_DMAC_TRIGACT_##n) \ + | DMAC_CHCTRLA_TRIGSRC(CONF_DMAC_TRIGSRC_##n), \ + DMAC_CHPRILVL_PRILVL(CONF_DMAC_LVL_##n), \ + (CONF_DMAC_EVIE_##n << DMAC_CHEVCTRL_EVIE_Pos) | (CONF_DMAC_EVOE_##n << DMAC_CHEVCTRL_EVOE_Pos) \ + | (CONF_DMAC_EVACT_##n << DMAC_CHEVCTRL_EVACT_Pos), \ + DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ + | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ + | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ + | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, + +/* DMAC channel configuration */ +struct dmac_channel_cfg { + uint32_t ctrla; + uint8_t prilvl; + uint8_t evctrl; + uint16_t btctrl; +}; + +/* DMAC channel configurations */ +const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; + +/** + * \brief Initialize DMAC + */ +int32_t _dma_init(void) +{ + uint8_t i; + + hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); + hri_dmac_clear_CRCCTRL_reg(DMAC, DMAC_CRCCTRL_CRCSRC_Msk); + hri_dmac_set_CTRL_SWRST_bit(DMAC); + while (hri_dmac_get_CTRL_SWRST_bit(DMAC)) + ; + + hri_dmac_write_CTRL_reg(DMAC, + (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) + | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) + | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); + hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); + + hri_dmac_write_PRICTRL0_reg( + DMAC, + DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) + | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) + | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) + | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); + hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); + hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); + + for (i = 0; i < DMAC_CH_NUM; i++) { + hri_dmac_write_CHCTRLA_reg(DMAC, i, _cfgs[i].ctrla); + hri_dmac_write_CHPRILVL_reg(DMAC, i, _cfgs[i].prilvl); + hri_dmac_write_CHEVCTRL_reg(DMAC, i, _cfgs[i].evctrl); + hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0); + } + + for (i = 0; i < 5; i++) { + NVIC_DisableIRQ(DMAC_0_IRQn + i); + NVIC_ClearPendingIRQ(DMAC_0_IRQn + i); + NVIC_EnableIRQ(DMAC_0_IRQn + i); + } + + hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); + + return ERR_NONE; +} + +/** + * \brief Enable/disable DMA interrupt + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) +{ + if (DMA_TRANSFER_COMPLETE_CB == type) { + hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, channel, state); + } else if (DMA_TRANSFER_ERROR_CB == type) { + hri_dmac_write_CHINTEN_TERR_bit(DMAC, channel, state); + } +} + +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) +{ + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); + + return ERR_NONE; +} + +int32_t _dma_set_source_address(const uint8_t channel, const void *const src) +{ + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); + + return ERR_NONE; +} + +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel) +{ + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel], + (uint32_t)&_descriptor_section[next_channel]); + + return ERR_NONE; +} + +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) +{ + uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); + uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); + + return ERR_NONE; +} + +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) +{ + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); + hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC, channel); + + if (software_trigger) { + hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); + } + + return ERR_NONE; +} + +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) +{ + *resource = &_resources[channel]; + + return ERR_NONE; +} + +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} +/** + * \internal DMAC interrupt handler + */ +static void _dmac_handler(void) +{ + uint8_t channel = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk); + struct _dma_resource *tmp_resource = &_resources[channel]; + + if (hri_dmac_get_INTPEND_TERR_bit(DMAC)) { + hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel); + tmp_resource->dma_cb.error(tmp_resource); + } else if (hri_dmac_get_INTPEND_TCMPL_bit(DMAC)) { + hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC, channel); + tmp_resource->dma_cb.transfer_done(tmp_resource); + } +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_0_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_1_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_2_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_3_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_4_Handler(void) +{ + _dmac_handler(); +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/evsys/hpl_evsys.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/evsys/hpl_evsys.c new file mode 100644 index 0000000..da0847a --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/evsys/hpl_evsys.c @@ -0,0 +1,140 @@ + +/** + * \file + * + * \brief EVSYS related functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +/* Stub macros for reserved channel */ +#define CONF_CHANNEL_38 0 +#define CONF_ONDEMAND_38 0 +#define CONF_RUNSTDBY_38 0 +#define CONF_EDGSEL_38 0 +#define CONF_PATH_38 0 +#define CONF_EVGEN_38 0 + +#define CONF_CHANNEL_39 0 +#define CONF_ONDEMAND_39 0 +#define CONF_RUNSTDBY_39 0 +#define CONF_EDGSEL_39 0 +#define CONF_PATH_39 0 +#define CONF_EVGEN_39 0 + +#define CONF_CHANNEL_113 0 +#define CONF_ONDEMAND_113 0 +#define CONF_RUNSTDBY_113 0 +#define CONF_EDGSEL_113 0 +#define CONF_PATH_113 0 +#define CONF_EVGEN_113 0 + +/* Event user configuration */ +#define USER_MUX_CONF(i, n) EVSYS_USER_CHANNEL(CONF_CHANNEL_##n), + +/* This macro is used for repeat macro: i - unused, n - amount of channels. + * It contains channel configuration. */ +#define CHANNEL_CONF(i, n) \ + (CONF_ONDEMAND_##n << EVSYS_CHANNEL_ONDEMAND_Pos) | (CONF_RUNSTDBY_##n << EVSYS_CHANNEL_RUNSTDBY_Pos) \ + | EVSYS_CHANNEL_EDGSEL(CONF_EDGSEL_##n) | EVSYS_CHANNEL_PATH(CONF_PATH_##n) \ + | EVSYS_CHANNEL_EVGEN(CONF_EVGEN_##n), + +/* This macro is used for repeat macro: i - unused, n - amount of channels + * It contains interrupts configuration. */ +#define INT_CFG(i, n) (CONF_OVR_##n << EVSYS_CHINTFLAG_OVR_Pos) | (CONF_EVD_##n << EVSYS_CHINTFLAG_EVD_Pos), + +static const uint8_t user_mux_confs[] = {REPEAT_MACRO(USER_MUX_CONF, i, EVSYS_USERS)}; + +static const uint16_t channel_confs[] = {REPEAT_MACRO(CHANNEL_CONF, i, EVSYS_CHANNELS)}; + +static const uint32_t interrupt_cfg[] = {REPEAT_MACRO(INT_CFG, i, EVSYS_CHANNELS)}; + +/** + * \brief Initialize event system + */ +int32_t _event_system_init(void) +{ + uint8_t i; + /* configure user multiplexers */ + for (i = 0; i < EVSYS_USERS; i++) { + hri_evsys_write_USER_reg(EVSYS, i, user_mux_confs[i]); + } + + /* configure channels */ + for (i = 0; i < EVSYS_CHANNELS; i++) { + hri_evsys_write_CHANNEL_reg(EVSYS, i, channel_confs[i]); + hri_evsys_write_CHINTEN_reg(EVSYS, i, interrupt_cfg[i]); + } + + return ERR_NONE; +} + +/** + * \brief De-initialize event system. + */ +int32_t _event_system_deinit() +{ + hri_evsys_write_CTRLA_reg(EVSYS, EVSYS_CTRLA_SWRST); + + return ERR_NONE; +} + +/** + * \brief Enable/disable event reception by the given user from the given + * channel + */ +int32_t _event_system_enable_user(const uint16_t user, const uint16_t channel, const bool on) +{ + if (on) { + hri_evsys_write_USER_reg(EVSYS, user, channel); + } else { + hri_evsys_write_USER_reg(EVSYS, user, 0); + } + + return ERR_NONE; +} + +/** + * \brief Enable/disable event generation by the given generator for the given + * channel + */ +int32_t _event_system_enable_generator(const uint16_t generator, const uint16_t channel, const bool on) +{ + if (on) { + hri_evsys_write_CHANNEL_EVGEN_bf(EVSYS, channel, generator); + } else { + hri_evsys_write_CHANNEL_EVGEN_bf(EVSYS, channel, 0); + } + + return ERR_NONE; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/gclk/hpl_gclk.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/gclk/hpl_gclk.c new file mode 100644 index 0000000..211ccc3 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/gclk/hpl_gclk.c @@ -0,0 +1,312 @@ + +/** + * \file + * + * \brief Generic Clock Controller related functionality. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initializes generators + */ +void _gclk_init_generators(void) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_9_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 9, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_10_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 10, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_11_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 11, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); +#endif +} + +void _gclk_init_generators_by_fref(uint32_t bm) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + if (bm & (1ul << 0)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + if (bm & (1ul << 1)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + if (bm & (1ul << 2)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + if (bm & (1ul << 3)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + if (bm & (1ul << 4)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + if (bm & (1ul << 5)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + if (bm & (1ul << 6)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + if (bm & (1ul << 7)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + if (bm & (1ul << 8)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_9_CONFIG == 1 + if (bm & (1ul << 9)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 9, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_10_CONFIG == 1 + if (bm & (1ul << 10)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 10, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_11_CONFIG == 1 + if (bm & (1ul << 11)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 11, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); + } +#endif +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/gclk/hpl_gclk_base.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/gclk/hpl_gclk_base.h new file mode 100644 index 0000000..3e7d282 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/gclk/hpl_gclk_base.h @@ -0,0 +1,87 @@ +/** + * \file + * + * \brief Generic Clock Controller. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GCLK_H_INCLUDED +#define _HPL_GCLK_H_INCLUDED + +#include +#ifdef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup gclk_group GCLK Hardware Proxy Layer + * + * \section gclk_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Enable clock on the given channel with the given clock source + * + * This function maps the given clock source to the given clock channel + * and enables channel. + * + * \param[in] channel The channel to enable clock for + * \param[in] source The clock source for the given channel + */ +static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) +{ + + hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); +} + +/** + * \brief Initialize GCLK generators by function references + * \param[in] bm Bit mapping for referenced generators, + * a bit 1 in position triggers generator initialization. + */ +void _gclk_init_generators_by_fref(uint32_t bm); + +//@} +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/mclk/hpl_mclk.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/mclk/hpl_mclk.c new file mode 100644 index 0000000..6684320 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/mclk/hpl_mclk.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief SAM Main Clock. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void) +{ + void *hw = (void *)MCLK; + hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV)); +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/osc32kctrl/hpl_osc32kctrl.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/osc32kctrl/hpl_osc32kctrl.c new file mode 100644 index 0000000..8859b42 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/osc32kctrl/hpl_osc32kctrl.c @@ -0,0 +1,82 @@ + +/** + * \file + * + * \brief SAM 32k Oscillators Controller. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void) +{ + void * hw = (void *)OSC32KCTRL; + uint16_t calib = 0; + +#if CONF_XOSC32K_CONFIG == 1 + hri_osc32kctrl_write_XOSC32K_reg( + hw, + OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) + | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) + | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos) + | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) | +#ifdef CONF_XOSC32K_CGM + OSC32KCTRL_XOSC32K_CGM(CONF_XOSC32K_CGM) | +#endif + (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos)); + + hri_osc32kctrl_write_CFDCTRL_reg(hw, (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos)); + + hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos)); +#endif + +#if CONF_OSCULP32K_CONFIG == 1 + calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); + hri_osc32kctrl_write_OSCULP32K_reg(hw, +#if CONF_OSCULP32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) +#else + OSC32KCTRL_OSCULP32K_CALIB(calib) +#endif + ); +#endif + +#if CONF_XOSC32K_CONFIG +#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0 + while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw)) + ; +#endif +#endif + + hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); + (void)calib; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/oscctrl/hpl_oscctrl.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/oscctrl/hpl_oscctrl.c new file mode 100644 index 0000000..9f55076 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/oscctrl/hpl_oscctrl.c @@ -0,0 +1,230 @@ + +/** + * \file + * + * \brief SAM Oscillators Controller. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_XOSC0_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg( + hw, + 0, + OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC0_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC0_STARTUP) + | (CONF_XOSC0_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC0_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC0_IMULT) + | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC0_IPTAT) | (CONF_XOSC0_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC0_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) + | (CONF_XOSC0_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC0_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); +#endif + +#if CONF_XOSC0_CONFIG == 1 +#if CONF_XOSC0_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY0_bit(hw)) + ; +#endif +#if CONF_XOSC0_ENALC == 1 + hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 0); +#endif +#if CONF_XOSC0_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 0); +#endif +#endif + +#if CONF_XOSC1_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg( + hw, + 1, + OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC1_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC1_STARTUP) + | (CONF_XOSC1_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC1_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC1_IMULT) + | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC1_IPTAT) | (CONF_XOSC1_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC1_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) + | (CONF_XOSC1_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC1_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); +#endif + +#if CONF_XOSC1_CONFIG == 1 +#if CONF_XOSC1_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY1_bit(hw)) + ; +#endif +#if CONF_XOSC1_ENALC == 1 + hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 1); +#endif +#if CONF_XOSC1_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1); +#endif +#endif + + (void)hw; +} + +void _oscctrl_init_referenced_generators(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_DFLL_CONFIG == 1 + hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, GCLK_GENCTRL_SRC_OSCULP32K); + while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) + ; + uint8_t tmp; + hri_oscctrl_write_DFLLCTRLA_reg(hw, 0); +#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_DFLL48, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK)); +#endif + + hri_oscctrl_write_DFLLMUL_reg(hw, + OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) + | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); + while (hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(hw)) + ; + + hri_oscctrl_write_DFLLCTRLB_reg(hw, 0); + while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) + ; + + tmp = (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) | OSCCTRL_DFLLCTRLA_ENABLE; + hri_oscctrl_write_DFLLCTRLA_reg(hw, tmp); + while (hri_oscctrl_get_DFLLSYNC_ENABLE_bit(hw)) + ; + +#if CONF_DFLL_OVERWRITE_CALIBRATION == 1 + hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)); +#endif + hri_oscctrl_write_DFLLVAL_reg(hw, hri_oscctrl_read_DFLLVAL_reg(hw)); + while (hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(hw)) + ; + + tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRLB_BPLCKC_Pos) + | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRLB_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRLB_CCDIS_Pos) + | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRLB_USBCRM_Pos) | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRLB_LLAW_Pos) + | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRLB_STABLE_Pos) | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRLB_MODE_Pos) | 0; + hri_oscctrl_write_DFLLCTRLB_reg(hw, tmp); + while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) + ; +#endif + +#if CONF_FDPLL0_CONFIG == 1 +#if CONF_FDPLL0_REFCLK == 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_FDPLL0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL0_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, 0, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL0_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL0_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg( + hw, + 0, + OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL0_DIV) | (CONF_FDPLL0_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) + | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL0_DCOFILTER) + | (CONF_FDPLL0_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL0_LTIME) + | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL0_REFCLK) | (CONF_FDPLL0_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL0_FILTER)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + 0, + (CONF_FDPLL0_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_FDPLL0_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_FDPLL1_CONFIG == 1 +#if CONF_FDPLL1_REFCLK == 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_FDPLL1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL1_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, 1, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL1_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL1_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg( + hw, + 1, + OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL1_DIV) | (CONF_FDPLL1_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) + | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL1_DCOFILTER) + | (CONF_FDPLL1_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL1_LTIME) + | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL1_REFCLK) | (CONF_FDPLL1_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL1_FILTER)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + 1, + (CONF_FDPLL1_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_FDPLL1_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_DFLL_CONFIG == 1 + if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(hw)) { + hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC; + + while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask) + ; + } else { + while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) + ; + } +#if CONF_DFLL_ONDEMAND == 1 + hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_FDPLL0_CONFIG == 1 +#if CONF_FDPLL0_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0))) + ; +#endif +#if CONF_FDPLL0_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 0); +#endif +#endif + +#if CONF_FDPLL1_CONFIG == 1 +#if CONF_FDPLL1_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 1) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 1))) + ; +#endif +#if CONF_FDPLL1_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 1); +#endif +#endif + +#if CONF_DFLL_CONFIG == 1 + while (hri_gclk_read_SYNCBUSY_reg(GCLK)) + ; + hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE); + while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) + ; +#endif + (void)hw; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/pm/hpl_pm.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/pm/hpl_pm.c new file mode 100644 index 0000000..55dc4db --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/pm/hpl_pm.c @@ -0,0 +1,68 @@ + +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Set the sleep mode for the device + */ +int32_t _set_sleep_mode(const uint8_t mode) +{ + uint8_t delay = 10; + + switch (mode) { + case 2: + case 4: + case 5: + case 6: + case 7: + hri_pm_write_SLEEPCFG_reg(PM, mode); + /* A small latency happens between the store instruction and actual + * writing of the SLEEPCFG register due to bridges. Software has to make + * sure the SLEEPCFG register reads the wanted value before issuing WFI + * instruction. + */ + do { + if (hri_pm_read_SLEEPCFG_reg(PM) == mode) { + break; + } + } while (--delay); + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/pm/hpl_pm_base.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/pm/hpl_pm_base.h new file mode 100644 index 0000000..5a50a91 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/pm/hpl_pm_base.h @@ -0,0 +1,45 @@ +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HPL_PM_BASE_H_INCLUDED +#define _HPL_PM_BASE_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/port/hpl_gpio_base.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/port/hpl_gpio_base.h new file mode 100644 index 0000000..f32c40f --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/port/hpl_gpio_base.h @@ -0,0 +1,172 @@ + +/** + * \file + * + * \brief SAM PORT. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include + +/** + * \brief Set direction on port with mask + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + switch (direction) { + case GPIO_DIRECTION_OFF: + hri_port_clear_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_IN: + hri_port_clear_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg(PORT, + port, + PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN + | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_OUT: + hri_port_set_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + default: + ASSERT(false); + } +} + +/** + * \brief Set output level on port with mask + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + if (level) { + hri_port_set_OUT_reg(PORT, port, mask); + } else { + hri_port_clear_OUT_reg(PORT, port, mask); + } +} + +/** + * \brief Change output level to the opposite with mask + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) +{ + hri_port_toggle_OUT_reg(PORT, port, mask); +} + +/** + * \brief Get input levels on all port pins + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port) +{ + uint32_t tmp; + + CRITICAL_SECTION_ENTER(); + + uint32_t dir_tmp = hri_port_read_DIR_reg(PORT, port); + + tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; + tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp; + + CRITICAL_SECTION_LEAVE(); + + return tmp; +} + +/** + * \brief Set pin pull mode + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode) +{ + switch (pull_mode) { + case GPIO_PULL_OFF: + hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); + break; + + case GPIO_PULL_UP: + hri_port_clear_DIR_reg(PORT, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_set_OUT_reg(PORT, port, 1U << pin); + break; + + case GPIO_PULL_DOWN: + hri_port_clear_DIR_reg(PORT, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_clear_OUT_reg(PORT, port, 1U << pin); + break; + + default: + ASSERT(false); + break; + } +} + +/** + * \brief Set gpio pin function + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) +{ + uint8_t port = GPIO_PORT(gpio); + uint8_t pin = GPIO_PIN(gpio); + + if (function == GPIO_PIN_FUNCTION_OFF) { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); + + } else { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); + + if (pin & 1) { + // Odd numbered pin + hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); + } else { + // Even numbered pin + hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); + } + } +} + +static inline void _port_event_init() +{ + hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 2, CONF_PORTC_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 3, CONF_PORTD_EVCTRL); +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/ramecc/hpl_ramecc.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/ramecc/hpl_ramecc.c new file mode 100644 index 0000000..4c158b2 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/ramecc/hpl_ramecc.c @@ -0,0 +1,83 @@ +/** + * \file + * + * \brief Generic RAMECC related functionality. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/* RAMECC device descriptor */ +struct _ramecc_device device; + +/** + * \brief Initialize RAMECC + */ +int32_t _ramecc_init(void) +{ + if (hri_ramecc_get_STATUS_ECCDIS_bit(RAMECC)) { + return ERR_ABORTED; + } + + NVIC_DisableIRQ(RAMECC_IRQn); + NVIC_ClearPendingIRQ(RAMECC_IRQn); + NVIC_EnableIRQ(RAMECC_IRQn); + + return ERR_NONE; +} + +void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb) +{ + if (RAMECC_DUAL_ERROR_CB == type) { + device.ramecc_cb.dual_bit_err = cb; + hri_ramecc_write_INTEN_DUALE_bit(RAMECC, NULL != cb); + } else if (RAMECC_SINGLE_ERROR_CB == type) { + device.ramecc_cb.single_bit_err = cb; + hri_ramecc_write_INTEN_SINGLEE_bit(RAMECC, NULL != cb); + } +} + +/** + * \internal RAMECC interrupt handler + */ +void RAMECC_Handler(void) +{ + struct _ramecc_device *dev = (struct _ramecc_device *)&device; + volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC); + + if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) { + dev->ramecc_cb.dual_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); + } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { + dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); + } else { + return; + } +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/sercom/hpl_sercom.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/sercom/hpl_sercom.c new file mode 100644 index 0000000..0c0d1ed --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/sercom/hpl_sercom.c @@ -0,0 +1,3385 @@ + +/** + * \file + * + * \brief SAM Serial Communication Interface + * + * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONF_SERCOM_0_USART_ENABLE +#define CONF_SERCOM_0_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_USART_ENABLE +#define CONF_SERCOM_1_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_USART_ENABLE +#define CONF_SERCOM_3_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_USART_ENABLE +#define CONF_SERCOM_4_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_USART_ENABLE +#define CONF_SERCOM_5_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_USART_ENABLE +#define CONF_SERCOM_6_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_USART_ENABLE +#define CONF_SERCOM_7_USART_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as USART. */ +#define SERCOM_USART_AMOUNT \ + (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ + + CONF_SERCOM_4_USART_ENABLE + CONF_SERCOM_5_USART_ENABLE + CONF_SERCOM_6_USART_ENABLE \ + + CONF_SERCOM_7_USART_ENABLE) + +/** + * \brief Macro is used to fill usart configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define SERCOM_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ + | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_USART_TXINV << SERCOM_USART_CTRLA_TXINV_Pos) \ + | (CONF_SERCOM_##n##_USART_RXINV << SERCOM_USART_CTRLA_RXINV_Pos) \ + | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ + | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ + | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ + | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ + | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ + | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ + SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ + | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ + | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ + | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ + | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ + | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ + SERCOM_USART_CTRLC_GTIME(CONF_SERCOM_##n##_USART_GTIME) \ + | (CONF_SERCOM_##n##_USART_DSNACK << SERCOM_USART_CTRLC_DSNACK_Pos) \ + | (CONF_SERCOM_##n##_USART_INACK << SERCOM_USART_CTRLC_INACK_Pos) \ + | SERCOM_USART_CTRLC_MAXITER(CONF_SERCOM_##n##_USART_MAXITER), \ + (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ + CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ + } + +/** + * \brief SERCOM USART configuration type + */ +struct usart_configuration { + uint8_t number; + hri_sercomusart_ctrla_reg_t ctrl_a; + hri_sercomusart_ctrlb_reg_t ctrl_b; + hri_sercomusart_ctrlc_reg_t ctrl_c; + hri_sercomusart_baud_reg_t baud; + uint8_t fractional; + hri_sercomusart_rxpl_reg_t rxpl; + hri_sercomusart_dbgctrl_reg_t debug_ctrl; +}; + +#if SERCOM_USART_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct usart_configuration _usarts[1] = {{0}}; +#else +/** + * \brief Array of SERCOM USART configurations + */ +static struct usart_configuration _usarts[] = { +#if CONF_SERCOM_0_USART_ENABLE == 1 + SERCOM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_USART_ENABLE == 1 + SERCOM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_USART_ENABLE == 1 + SERCOM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_USART_ENABLE == 1 + SERCOM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_USART_ENABLE == 1 + SERCOM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_USART_ENABLE == 1 + SERCOM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_USART_ENABLE == 1 + SERCOM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_USART_ENABLE == 1 + SERCOM_CONFIGURATION(7), +#endif +}; +#endif + +static uint8_t _get_sercom_index(const void *const hw); +static uint8_t _sercom_get_irq_num(const void *const hw); +static void _sercom_init_irq_param(const void *const hw, void *dev); +static uint8_t _sercom_get_hardware_index(const void *const hw); + +static int32_t _usart_init(void *const hw); +static inline void _usart_deinit(void *const hw); +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); +static void _usart_set_data_order(void *const hw, const enum usart_data_order order); +static void _usart_set_mode(void *const hw, const enum usart_mode mode); +static void _usart_set_parity(void *const hw, const enum usart_parity parity); +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); +static void _usart_set_character_size(void *const hw, const enum usart_character_size size); + +/** + * \brief Initialize synchronous SERCOM USART + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _usart_init(hw); +} + +/** + * \brief Initialize asynchronous SERCOM USART + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _usart_init(hw); + if (init_status) { + return init_status; + } + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + return ERR_NONE; +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_sync_deinit(struct _usart_sync_device *const device) +{ + _usart_deinit(device->hw); +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_async_deinit(struct _usart_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _usart_deinit(device->hw); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_sync_enable(struct _usart_sync_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_async_enable(struct _usart_async_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_sync_disable(struct _usart_sync_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_async_disable(struct _usart_async_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Set baud rate + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set baud rate + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set data order + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set data order + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set mode + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set mode + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set parity + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set parity + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set stop bits mode + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set stop bits mode + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set character size + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Set character size + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given SERCOM USART instance + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_DATA_reg(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if USART transmission complete + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_TXC_bit(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if there is data received by USART + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_RXC_bit(device->hw); +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Enable data register empty interrupt + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_DRE_bit(device->hw); +} + +/** + * \brief Enable transmission complete interrupt + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_TXC_bit(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given sercom hardware instance + */ +static uint8_t _sercom_get_hardware_index(const void *const hw) +{ + Sercom *const sercom_modules[] = SERCOM_INSTS; + /* Find index for SERCOM instance. */ + for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { + if ((uint32_t)hw == (uint32_t)sercom_modules[i]) { + return i; + } + } + return 0; +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Enable/disable USART interrupt + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { + hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); + hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); + } else if (USART_ASYNC_RX_DONE == type) { + hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); + } else if (USART_ASYNC_ERROR == type) { + hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static uint8_t _get_sercom_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_usarts); i++) { + if (_usarts[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return 0; +} + +/** + * \brief Init irq param with the given sercom hardware instance + */ +static void _sercom_init_irq_param(const void *const hw, void *dev) +{ +} + +/** + * \internal Initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + * + * \return The status of initialization + */ +static int32_t _usart_init(void *const hw) +{ + uint8_t i = _get_sercom_index(hw); + + if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { + uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk; + if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + } + hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); + } + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + + hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); + hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); + hri_sercomusart_write_CTRLC_reg(hw, _usarts[i].ctrl_c); + if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { + ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; + ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; + } else { + hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); + } + + hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); + hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); + + return ERR_NONE; +} + +/** + * \internal De-initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _usart_deinit(void *const hw) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate SERCOM clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { + return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; + } + + if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { + return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); + } + + if (USART_BAUDRATE_SYNCH == mode) { + return clock_rate / baud / 2 - 1; + } + + return 0; +} + +/** + * \internal Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_BAUD_reg(hw, baud_rate); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +static void _usart_set_data_order(void *const hw, const enum usart_data_order order) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_DORD_bit(hw, order); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +static void _usart_set_mode(void *const hw, const enum usart_mode mode) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +static void _usart_set_parity(void *const hw, const enum usart_parity parity) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + + if (USART_PARITY_NONE != parity) { + hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); + } else { + hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); + } + + hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +static void _usart_set_character_size(void *const hw, const enum usart_character_size size) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomusart_set_CTRLA_ENABLE_bit(hw); + } +} + + /* Sercom I2C implementation */ + +#ifndef CONF_SERCOM_0_I2CM_ENABLE +#define CONF_SERCOM_0_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CM_ENABLE +#define CONF_SERCOM_2_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CM_ENABLE +#define CONF_SERCOM_3_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CM_ENABLE +#define CONF_SERCOM_4_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CM_ENABLE +#define CONF_SERCOM_5_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CM_ENABLE +#define CONF_SERCOM_6_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CM_ENABLE +#define CONF_SERCOM_7_I2CM_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Master. */ +#define SERCOM_I2CM_AMOUNT \ + (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ + + CONF_SERCOM_4_I2CM_ENABLE + CONF_SERCOM_5_I2CM_ENABLE + CONF_SERCOM_6_I2CM_ENABLE + CONF_SERCOM_7_I2CM_ENABLE) + +/** + * \brief Macro is used to fill i2cm configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CM_CONFIGURATION(n) \ + { \ + (n), \ + (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ + | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ + SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ + CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ + } + +#define ERROR_FLAG (1 << 7) +#define SB_FLAG (1 << 1) +#define MB_FLAG (1 << 0) + +#define CMD_STOP 0x3 +#define I2C_IDLE 0x1 +#define I2C_SM 0x0 +#define I2C_FM 0x1 +#define I2C_HS 0x2 +#define TEN_ADDR_FRAME 0x78 +#define TEN_ADDR_MASK 0x3ff +#define SEVEN_ADDR_MASK 0x7f + +/** + * \brief SERCOM I2CM configuration type + */ +struct i2cm_configuration { + uint8_t number; + hri_sercomi2cm_ctrla_reg_t ctrl_a; + hri_sercomi2cm_ctrlb_reg_t ctrl_b; + hri_sercomi2cm_baud_reg_t baud; + hri_sercomi2cm_dbgctrl_reg_t dbgctrl; + uint16_t trise; + uint32_t clk; /* SERCOM peripheral clock frequency */ +}; + +static inline int32_t _i2c_m_enable_implementation(void *hw); +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); + +#if SERCOM_I2CM_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct i2cm_configuration _i2cms[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2CM configurations + */ +static struct i2cm_configuration _i2cms[] = { +#if CONF_SERCOM_0_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2cm_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { + if (_i2cms[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +static inline void _sercom_i2c_send_stop(void *const hw) +{ + hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); +} + +/** + * \brief SERCOM I2CM analyze hardware status and transfer next byte + */ +static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) +{ + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); + + if (flags & MB_FLAG) { + /* tx error */ + if (status & SERCOM_I2CM_STATUS_ARBLOST) { + hri_sercomi2cm_clear_interrupt_MB_bit(hw); + msg->flags |= I2C_M_FAIL; + msg->flags &= ~I2C_M_BUSY; + + if (status & SERCOM_I2CM_STATUS_BUSERR) { + return I2C_ERR_BUS; + } + + return I2C_ERR_BAD_ADDRESS; + } else { + if (status & SERCOM_I2CM_STATUS_RXNACK) { + + /* Slave rejects to receive more data */ + if (msg->len > 0) { + msg->flags |= I2C_M_FAIL; + } + + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + + return I2C_NACK; + } + + if (msg->flags & I2C_M_TEN) { + hri_sercomi2cm_write_ADDR_reg(hw, + ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + msg->flags &= ~I2C_M_TEN; + + return I2C_OK; + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } else { + hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); + msg->buffer++; + msg->len--; + } + + return I2C_OK; + } + } else if (flags & SB_FLAG) { + if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { + msg->len--; + + /* last byte, send nack */ + if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + hri_sercomi2cm_clear_CTRLB_SMEN_bit(hw); + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } + + /* Accessing DATA.DATA auto-triggers I2C bus operations. + * The operation performed depends on the state of + * CTRLB.ACKACT, CTRLB.SMEN + **/ + *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); + } else { + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + return I2C_NACK; + } + + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + } + + return I2C_OK; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + return _i2c_m_enable_implementation(i2c_dev->hw); +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Retrieve IRQ number for the given hardware instance + */ +static uint8_t _sercom_get_irq_num(const void *const hw) +{ + return SERCOM0_0_IRQn + (_sercom_get_hardware_index(hw) << 2); +} + +/** + * \brief Initialize sercom i2c module to use in async mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) +{ + int32_t init_status; + + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); + if (init_status) { + return init_status; + } + + _sercom_init_irq_param(hw, (void *)i2c_dev); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + return ERR_NONE; +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Transfer the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + return ERR_NONE; +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail, return the error code + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) +{ + int ret; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (msg->len == 0) { + return ERR_NONE; + } + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(i2c_dev->hw); + + ret = _sercom_i2c_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Set callback to be called in interrupt handler + * + * \param[in] i2c_dev The pointer to master i2c device + * \param[in] type The callback type + * \param[in] func The callback function pointer + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, + FUNC_PTR func) +{ + switch (type) { + case I2C_M_ASYNC_DEVICE_ERROR: + i2c_dev->cb.error = (_i2c_error_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_TX_COMPLETE: + i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_RX_COMPLETE: + i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; + break; + default: + /* error */ + break; + } + + return ERR_NONE; +} + +/** + * \brief Set stop condition on I2C + * + * \param i2c_dev Pointer to master i2c device + * + * \return Operation status + * \retval I2C_OK Operation was successfull + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +/** + * \brief Get number of bytes left in transfer buffer + * + * \param i2c_dev Pointer to i2c master device + * + * \return Bytes left in buffer + * \retval =>0 Bytes left in buffer + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) +{ + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return i2c_dev->service.msg.len; + } + + return 0; +} + +/** + * \brief Initialize sercom i2c module to use in sync mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) +{ + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + return _i2c_m_sync_init_impl(&i2c_dev->service, hw); +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + return _i2c_m_enable_implementation(i2c_dev->hw); +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C master interrupt + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state) +{ + if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); + hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); + } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { + hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \brief Wait for bus response + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] flags Store the hardware response + * + * \return Bus response status. + * \retval 0 Bus response status OK + * \retval <0 Bus response fail + */ +inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) +{ + uint32_t timeout = 65535; + void * hw = i2c_dev->hw; + + do { + *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); + + if (timeout-- == 0) { + return I2C_ERR_BUS; + } + } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); + + return I2C_OK; +} + +/** + * \brief Send the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint32_t flags; + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + return _sercom_i2c_sync_analyse_flags(hw, flags, msg); +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail or partial fail, return the error code + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) +{ + uint32_t flags; + int ret; + void * hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return I2C_ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(hw); + + ret = _sercom_i2c_sync_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + while (i2c_dev->service.msg.flags & I2C_M_BUSY) { + ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + + if (ret) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); + } + + return ret; +} + +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +static inline int32_t _i2c_m_enable_implementation(void *const hw) +{ + int timeout = 65535; + int timeout_attempt = 4; + + ASSERT(hw); + + /* Enable interrupts */ + hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); + + while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { + timeout--; + + if (timeout <= 0) { + if (--timeout_attempt) + timeout = 65535; + else + return I2C_ERR_BUSY; + hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); + } + } + return ERR_NONE; +} + +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) +{ + uint8_t i = _get_i2cm_index(hw); + + if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { + uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; + if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE); + } + hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode); + } + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + + hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); + hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); + hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); + + service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); + + service->trise = _i2cms[i].trise; + + return ERR_NONE; +} + + /* SERCOM I2C slave */ + +#ifndef CONF_SERCOM_0_I2CS_ENABLE +#define CONF_SERCOM_0_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CS_ENABLE +#define CONF_SERCOM_1_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CS_ENABLE +#define CONF_SERCOM_2_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CS_ENABLE +#define CONF_SERCOM_3_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CS_ENABLE +#define CONF_SERCOM_4_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CS_ENABLE +#define CONF_SERCOM_5_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CS_ENABLE +#define CONF_SERCOM_6_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CS_ENABLE +#define CONF_SERCOM_7_I2CS_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Slave. */ +#define SERCOM_I2CS_AMOUNT \ + (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ + + CONF_SERCOM_4_I2CS_ENABLE + CONF_SERCOM_5_I2CS_ENABLE + CONF_SERCOM_6_I2CS_ENABLE + CONF_SERCOM_7_I2CS_ENABLE) + +/** + * \brief Macro is used to fill I2C slave configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CS_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ + | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ + | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ + SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ + (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ + | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ + } + +/** + * \brief Macro to check 10-bit addressing + */ +#define I2CS_7BIT_ADDRESSING_MASK 0x7F + +static int32_t _i2c_s_init(void *const hw); +static int8_t _get_i2c_s_index(const void *const hw); +static inline void _i2c_s_deinit(void *const hw); +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); + +/** + * \brief SERCOM I2C slave configuration type + */ +struct i2cs_configuration { + uint8_t number; + hri_sercomi2cs_ctrla_reg_t ctrl_a; + hri_sercomi2cs_ctrlb_reg_t ctrl_b; + hri_sercomi2cs_addr_reg_t address; +}; + +#if SERCOM_I2CS_AMOUNT < 1 +/** Dummy array for compiling. */ +static struct i2cs_configuration _i2css[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2C slave configurations + */ +static struct i2cs_configuration _i2css[] = { +#if CONF_SERCOM_0_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \brief Initialize synchronous I2C slave + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) +{ + int32_t status; + + ASSERT(device); + + status = _i2c_s_init(hw); + if (status) { + return status; + } + device->hw = hw; + + return ERR_NONE; +} + +/** + * \brief Initialize asynchronous I2C slave + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _i2c_s_init(hw); + if (init_status) { + return init_status; + } + + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + // Enable Address Match and PREC interrupt by default. + hri_sercomi2cs_set_INTEN_AMATCH_bit(hw); + hri_sercomi2cs_set_INTEN_PREC_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize synchronous I2C + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) +{ + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize asynchronous I2C + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given I2C instance + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_DATA_reg(device->hw); +} + +/** + * \brief Check if I2C is ready to send next byt + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Check if there is data received by I2C + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Clear the Data Ready interrupt flag + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_INTFLAG_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Abort data transmission + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C slave interrupt + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); + } else if (I2C_S_DEVICE_ERROR == type) { + hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); + } + + return ERR_NONE; +} + +/** + * \internal Initalize i2c slave hardware + * + * \param[in] p The pointer to hardware instance + * + *\ return status of initialization + */ +static int32_t _i2c_s_init(void *const hw) +{ + int8_t i = _get_i2c_s_index(hw); + if (i == -1) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomi2cs_is_syncing(hw, SERCOM_I2CS_CTRLA_SWRST)) { + uint32_t mode = _i2css[i].ctrl_a & SERCOM_I2CS_CTRLA_MODE_Msk; + if (hri_sercomi2cs_get_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_ENABLE)) { + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_ENABLE); + } + hri_sercomi2cs_write_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_SWRST | mode); + } + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + + hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); + hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); + hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); + + return ERR_NONE; +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + * + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2c_s_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2css); i++) { + if (_i2css[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _i2c_s_deinit(void *const hw) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + * \param[in] address Address to set + */ +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) +{ + bool enabled; + + enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); + } + + return ERR_NONE; +} + + /* Sercom SPI implementation */ + +#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE +#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) +#endif + +#define SPI_DEV_IRQ_MODE 0x8000 + +#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) +#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) + +COMPILER_PACK_SET(1) +/** Initialization configuration of registers. */ +struct sercomspi_regs_cfg { + uint32_t ctrla; + uint32_t ctrlb; + uint32_t addr; + uint8_t baud; + uint8_t dbgctrl; + uint16_t dummy_byte; + uint8_t n; +}; +COMPILER_PACK_RESET() + +/** Build configuration from header macros. */ +#define SERCOMSPI_REGS(n) \ + { \ + (((CONF_SERCOM_##n##_SPI_DORD) << SERCOM_SPI_CTRLA_DORD_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ + | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ + | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ + | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ + ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ + | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ + | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ + | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ + (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ + | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ + ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ + (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ + CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ + n /* sercom number */ \ + } + +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_SPI_ENABLE +#define CONF_SERCOM_1_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_SPI_ENABLE +#define CONF_SERCOM_2_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_SPI_ENABLE +#define CONF_SERCOM_4_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_SPI_ENABLE +#define CONF_SERCOM_5_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_SPI_ENABLE +#define CONF_SERCOM_6_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_SPI_ENABLE +#define CONF_SERCOM_7_SPI_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as SPI */ +#define SERCOM_SPI_AMOUNT \ + (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ + + CONF_SERCOM_4_SPI_ENABLE + CONF_SERCOM_5_SPI_ENABLE + CONF_SERCOM_6_SPI_ENABLE + CONF_SERCOM_7_SPI_ENABLE) + +#if SERCOM_SPI_AMOUNT < 1 +/** Dummy array for compiling. */ +static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; +#else +/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ +static const struct sercomspi_regs_cfg sercomspi_regs[] = { +#if CONF_SERCOM_0_SPI_ENABLE + SERCOMSPI_REGS(0), +#endif +#if CONF_SERCOM_1_SPI_ENABLE + SERCOMSPI_REGS(1), +#endif +#if CONF_SERCOM_2_SPI_ENABLE + SERCOMSPI_REGS(2), +#endif +#if CONF_SERCOM_3_SPI_ENABLE + SERCOMSPI_REGS(3), +#endif +#if CONF_SERCOM_4_SPI_ENABLE + SERCOMSPI_REGS(4), +#endif +#if CONF_SERCOM_5_SPI_ENABLE + SERCOMSPI_REGS(5), +#endif +#if CONF_SERCOM_6_SPI_ENABLE + SERCOMSPI_REGS(6), +#endif +#if CONF_SERCOM_7_SPI_ENABLE + SERCOMSPI_REGS(7), +#endif +}; +#endif + +/** \internal De-initialize SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return De-initialization status + */ +static int32_t _spi_deinit(void *const hw) +{ + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_set_CTRLA_SWRST_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_sync_enable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_set_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_async_enable(void *const hw) +{ + _spi_sync_enable(hw); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_EnableIRQ((IRQn_Type)irq++); + } + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_sync_disable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_async_disable(void *const hw) +{ + _spi_sync_disable(hw); + hri_sercomspi_clear_INTEN_reg( + hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq++); + } + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI mode + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] mode The mode to set + * + * \return Setting mode status + */ +static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); + ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI baudrate + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting baudrate status + */ +static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_write_BAUD_reg(hw, baud_val); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI char size + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * \param[out] size Stored char size + * + * \return Setting char size status + */ +static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) +{ + /* Only 8-bit or 9-bit accepted */ + if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { + return ERR_INVALID_ARG; + } + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { + return ERR_BUSY; + } + + hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); + *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI data order + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting data order status + */ +static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + + if (dord == SPI_DATA_ORDER_LSB_1ST) { + ctrla |= SERCOM_SPI_CTRLA_DORD; + } else { + ctrla &= ~SERCOM_SPI_CTRLA_DORD; + } + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \brief Load SERCOM registers to init for SPI master mode + * The settings will be applied with default master mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg( + hw, + (regs->ctrlb + & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) + | (SERCOM_SPI_CTRLB_RXEN)); + hri_sercomspi_write_BAUD_reg(hw, regs->baud); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); +} + +/** \brief Load SERCOM registers to init for SPI slave mode + * The settings will be applied with default slave mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg(hw, + (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) + | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); + hri_sercomspi_write_ADDR_reg(hw, regs->addr); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); + while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) + ; +} + +/** \brief Return the pointer to register settings of specific SERCOM + * \param[in] hw_addr The hardware register base address. + * \return Pointer to register settings of specific SERCOM. + */ +static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) +{ + uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); + uint8_t i; + + for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { + if (sercomspi_regs[i].n == n) { + return &sercomspi_regs[i]; + } + } + + return NULL; +} + +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) +{ + const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); + + ASSERT(dev && hw); + + if (regs == NULL) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; + if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE); + } + hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode); + } + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + + dev->prvt = hw; + + if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { + _spi_load_regs_slave(hw, regs); + } else { + _spi_load_regs_master(hw, regs); + } + + /* Load character size from default hardware configuration */ + dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; + + dev->dummy_byte = regs->dummy_byte; + + return ERR_NONE; +} + +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) +{ + return _spi_m_sync_init(dev, hw); +} + +int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) +{ + struct _spi_async_dev *spid = dev; + /* Do hardware initialize. */ + int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); + + if (rc < 0) { + return rc; + } + + _sercom_init_irq_param(hw, (void *)dev); + /* Initialize callbacks: must use them */ + spid->callbacks.complete = NULL; + spid->callbacks.rx = NULL; + spid->callbacks.tx = NULL; + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + irq++; + } + + return ERR_NONE; +} + +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) +{ + return _spi_m_async_init(dev, hw); +} + +int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_m_async_enable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_m_async_disable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) +{ + int32_t rc; + ASSERT(dev); + + /* Not accept 0es */ + if (clk == 0 || baud == 0) { + return ERR_INVALID_ARG; + } + + /* Check baudrate range of current assigned clock */ + if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { + return ERR_INVALID_ARG; + } + + rc = ((clk >> 1) / baud) - 1; + return rc; +} + +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +/** Wait until SPI bus idle. */ +static inline void _spi_wait_bus_idle(void *const hw) +{ + while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { + ; + } + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); +} + +/** Holds run time information for message sync transaction. */ +struct _spi_trans_ctrl { + /** Pointer to transmitting data buffer. */ + uint8_t *txbuf; + /** Pointer to receiving data buffer. */ + uint8_t *rxbuf; + /** Count number of data transmitted. */ + uint32_t txcnt; + /** Count number of data received. */ + uint32_t rxcnt; + /** Data character size. */ + uint8_t char_size; +}; + +/** Check interrupt flag of RXC and update transaction runtime information. */ +static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) +{ + uint32_t data; + + if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { + return false; + } + + data = hri_sercomspi_read_DATA_reg(hw); + + if (ctrl->rxbuf) { + *ctrl->rxbuf++ = (uint8_t)data; + + if (ctrl->char_size > 1) { + *ctrl->rxbuf++ = (uint8_t)(data >> 8); + } + } + + ctrl->rxcnt++; + + return true; +} + +/** Check interrupt flag of DRE and update transaction runtime information. */ +static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, + uint16_t dummy) +{ + uint32_t data; + + if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { + return; + } + + if (ctrl->txbuf) { + data = *ctrl->txbuf++; + + if (ctrl->char_size > 1) { + data |= (*ctrl->txbuf) << 8; + ctrl->txbuf++; + } + } else { + data = dummy; + } + + ctrl->txcnt++; + hri_sercomspi_write_DATA_reg(hw, data); +} + +/** Check interrupt flag of ERROR and update transaction runtime information. */ +static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) +{ + if (SERCOM_SPI_INTFLAG_ERROR & iflag) { + hri_sercomspi_clear_STATUS_reg(hw, ~0); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return ERR_OVERFLOW; + } + + return ERR_NONE; +} + +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) +{ + void * hw = dev->prvt; + int32_t rc = 0; + struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; + + ASSERT(dev && hw); + + /* If settings are not applied (pending), we can not go on */ + if (hri_sercomspi_is_syncing( + hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { + return ERR_BUSY; + } + + /* SPI must be enabled to start synchronous transfer */ + if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { + return ERR_NOT_INITIALIZED; + } + + for (;;) { + uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); + + if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { + /* In master mode, do not start next byte before previous byte received + * to make better output waveform */ + if (ctrl.rxcnt >= ctrl.txcnt) { + _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); + } + } + + rc = _spi_err_check(iflag, hw); + + if (rc < 0) { + break; + } + if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { + rc = ctrl.txcnt; + break; + } + } + /* Wait until SPI bus idle */ + _spi_wait_bus_idle(hw); + + return rc; +} + +int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (state) { + hri_sercomspi_set_INTEN_DRE_bit(hw); + } else { + hri_sercomspi_clear_INTEN_DRE_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx(dev, state); +} + +int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev); + ASSERT(hw); + + if (state) { + hri_sercomspi_set_INTEN_RXC_bit(hw); + } else { + hri_sercomspi_clear_INTEN_RXC_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_rx(dev, state); +} + +int32_t _spi_m_async_enable_tx_complete(struct _spi_async_dev *dev, bool state) +{ + ASSERT(dev && dev->prvt); + + if (state) { + hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); + } else { + hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx_complete(dev, state); +} + +int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + typedef void (*func_t)(void); + struct _spi_async_dev *spid = dev; + + ASSERT(dev && (cb_type < SPI_DEV_CB_N)); + + func_t *p_ls = (func_t *)&spid->callbacks; + p_ls[cb_type] = (func_t)func; + + return ERR_NONE; +} + +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + return _spi_m_async_register_callback(dev, cb_type, func); +} + +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); +} + +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); +} + +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); + return true; + } + return false; +} + +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { + hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return true; + } + return false; +} + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + ASSERT(device); + + if (SPI_DEV_CB_ERROR == type) { + hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); + } +} + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + _spi_m_async_set_irq_state(device, type, state); +} +#ifndef CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL +#define CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_0_SPI_M_DMA_RX_CHANNEL +#define CONF_SERCOM_0_SPI_M_DMA_RX_CHANNEL 1 +#endif +#ifndef CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL +#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL +#define CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL 1 +#endif +#ifndef CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL +#define CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL +#define CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL 1 +#endif +#ifndef CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL +#define CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL +#define CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL 1 +#endif +#ifndef CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL +#define CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL +#define CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL 1 +#endif +#ifndef CONF_SERCOM_5_SPI_M_DMA_TX_CHANNEL +#define CONF_SERCOM_5_SPI_M_DMA_TX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_5_SPI_M_DMA_RX_CHANNEL +#define CONF_SERCOM_5_SPI_M_DMA_RX_CHANNEL 1 +#endif +#ifndef CONF_SERCOM_6_SPI_M_DMA_TX_CHANNEL +#define CONF_SERCOM_6_SPI_M_DMA_TX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_6_SPI_M_DMA_RX_CHANNEL +#define CONF_SERCOM_6_SPI_M_DMA_RX_CHANNEL 1 +#endif +#ifndef CONF_SERCOM_7_SPI_M_DMA_TX_CHANNEL +#define CONF_SERCOM_7_SPI_M_DMA_TX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_7_SPI_M_DMA_RX_CHANNEL +#define CONF_SERCOM_7_SPI_M_DMA_RX_CHANNEL 1 +#endif + +#ifndef CONF_SERCOM_0_SPI_RX_CHANNEL +#define CONF_SERCOM_0_SPI_RX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_1_SPI_RX_CHANNEL +#define CONF_SERCOM_1_SPI_RX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_2_SPI_RX_CHANNEL +#define CONF_SERCOM_2_SPI_RX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_3_SPI_RX_CHANNEL +#define CONF_SERCOM_3_SPI_RX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_4_SPI_RX_CHANNEL +#define CONF_SERCOM_4_SPI_RX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_5_SPI_RX_CHANNEL +#define CONF_SERCOM_5_SPI_RX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_6_SPI_RX_CHANNEL +#define CONF_SERCOM_6_SPI_RX_CHANNEL 0 +#endif +#ifndef CONF_SERCOM_7_SPI_RX_CHANNEL +#define CONF_SERCOM_7_SPI_RX_CHANNEL 0 +#endif + +/** \internal Enable SERCOM SPI RX + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_sync_rx_enable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_CTRLB)) { + return ERR_BUSY; + } + + hri_sercomspi_set_CTRLB_RXEN_bit(hw); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI RX + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_sync_rx_disable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_CTRLB)) { + return ERR_BUSY; + } + hri_sercomspi_clear_CTRLB_RXEN_bit(hw); + + return ERR_NONE; +} + +static int32_t _spi_m_dma_rx_enable(struct _spi_m_dma_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_rx_enable(dev->prvt); +} + +static int32_t _spi_m_dma_rx_disable(struct _spi_m_dma_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_rx_disable(dev->prvt); +} + +/** + * \brief Get the spi source address for DMA + * \param[in] dev Pointer to the SPI device instance + * + * \return The spi source address + */ +static uint32_t _spi_m_get_source_for_dma(void *const hw) +{ + return (uint32_t) & (((Sercom *)hw)->SPI.DATA); +} + +/** + * \brief Get the spi destination address for DMA + * \param[in] dev Pointer to the SPI device instance + * + * \return The spi destination address + */ +static uint32_t _spi_m_get_destination_for_dma(void *const hw) +{ + return (uint32_t) & (((Sercom *)hw)->SPI.DATA); +} + +/** + * \brief Return the SPI TX DMA channel index + * \param[in] hw_addr The hardware register base address + * + * \return SPI TX DMA channel index. + */ +static uint8_t _spi_get_tx_dma_channel(const void *const hw) +{ + uint8_t index = _sercom_get_hardware_index(hw); + + switch (index) { + case 0: + return CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL; + case 1: + return CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL; + case 2: + return CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL; + case 3: + return CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL; + case 4: + return CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL; + case 5: + return CONF_SERCOM_5_SPI_M_DMA_TX_CHANNEL; + case 6: + return CONF_SERCOM_6_SPI_M_DMA_TX_CHANNEL; + case 7: + return CONF_SERCOM_7_SPI_M_DMA_TX_CHANNEL; + default: + return CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL; + } +} + +/** + * \brief Return whether SPI RX DMA channel is enabled or not + * \param[in] hw_addr The hardware register base address + * + * \return one if enabled. + */ +static uint8_t _spi_is_rx_dma_channel_enabled(const void *const hw) +{ + uint8_t index = _sercom_get_hardware_index(hw); + + switch (index) { + case 0: + return CONF_SERCOM_0_SPI_RX_CHANNEL; + case 1: + return CONF_SERCOM_1_SPI_RX_CHANNEL; + case 2: + return CONF_SERCOM_2_SPI_RX_CHANNEL; + case 3: + return CONF_SERCOM_3_SPI_RX_CHANNEL; + case 4: + return CONF_SERCOM_4_SPI_RX_CHANNEL; + case 5: + return CONF_SERCOM_5_SPI_RX_CHANNEL; + case 6: + return CONF_SERCOM_6_SPI_RX_CHANNEL; + case 7: + return CONF_SERCOM_7_SPI_RX_CHANNEL; + default: + return false; + } +} + +/** + * \brief Return the SPI RX DMA channel index + * \param[in] hw_addr The hardware register base address + * + * \return SPI RX DMA channel index. + */ +static uint8_t _spi_get_rx_dma_channel(const void *const hw) +{ + uint8_t index = _sercom_get_hardware_index(hw); + + switch (index) { + case 0: + return CONF_SERCOM_0_SPI_M_DMA_RX_CHANNEL; + case 1: + return CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL; + case 2: + return CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL; + case 3: + return CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL; + case 4: + return CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL; + case 5: + return CONF_SERCOM_5_SPI_M_DMA_RX_CHANNEL; + case 6: + return CONF_SERCOM_6_SPI_M_DMA_RX_CHANNEL; + case 7: + return CONF_SERCOM_7_SPI_M_DMA_RX_CHANNEL; + default: + return CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL; + } +} + +/** + * \brief Callback for RX + * \param[in, out] dev Pointer to the DMA resource. + */ +static void _spi_dma_rx_complete(struct _dma_resource *resource) +{ + struct _spi_m_dma_dev *dev = (struct _spi_m_dma_dev *)resource->back; + + if (dev->callbacks.rx) { + dev->callbacks.rx(resource); + } +} + +/** + * \brief Callback for TX + * \param[in, out] dev Pointer to the DMA resource. + */ +static void _spi_dma_tx_complete(struct _dma_resource *resource) +{ + struct _spi_m_dma_dev *dev = (struct _spi_m_dma_dev *)resource->back; + + if (dev->callbacks.tx) { + dev->callbacks.tx(resource); + } +} + +/** + * \brief Callback for ERROR + * \param[in, out] dev Pointer to the DMA resource. + */ +static void _spi_dma_error_occured(struct _dma_resource *resource) +{ + struct _spi_m_dma_dev *dev = (struct _spi_m_dma_dev *)resource->back; + + if (dev->callbacks.error) { + dev->callbacks.error(resource); + } +} + +int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw) +{ + const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); + + ASSERT(dev && hw); + + if (regs == NULL) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; + if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE); + } + hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode); + } + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + + dev->prvt = hw; + + _spi_load_regs_master(hw, regs); + + /* If enabled, initialize DMA rx channel */ + if (_spi_is_rx_dma_channel_enabled(hw)) { + _dma_get_channel_resource(&dev->resource, _spi_get_rx_dma_channel(hw)); + dev->resource->back = dev; + dev->resource->dma_cb.transfer_done = _spi_dma_rx_complete; + dev->resource->dma_cb.error = _spi_dma_error_occured; + } + /* Initialize DMA tx channel */ + _dma_get_channel_resource(&dev->resource, _spi_get_tx_dma_channel(hw)); + dev->resource->back = dev; + dev->resource->dma_cb.transfer_done = _spi_dma_tx_complete; + dev->resource->dma_cb.error = _spi_dma_error_occured; + + return ERR_NONE; +} + +int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size) +{ + uint8_t size; + + ASSERT(dev && dev->prvt); + + _spi_set_char_size(dev->prvt, char_size, &size); + + return size; +} + +void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type type, _spi_dma_cb_t func) +{ + switch (type) { + case SPI_DEV_CB_DMA_TX: + dev->callbacks.tx = func; + _dma_set_irq_state(_spi_get_tx_dma_channel(dev->prvt), DMA_TRANSFER_COMPLETE_CB, func != NULL); + break; + case SPI_DEV_CB_DMA_RX: + dev->callbacks.rx = func; + _dma_set_irq_state(_spi_get_rx_dma_channel(dev->prvt), DMA_TRANSFER_COMPLETE_CB, func != NULL); + break; + case SPI_DEV_CB_DMA_ERROR: + dev->callbacks.error = func; + _dma_set_irq_state(_spi_get_rx_dma_channel(dev->prvt), DMA_TRANSFER_ERROR_CB, func != NULL); + _dma_set_irq_state(_spi_get_tx_dma_channel(dev->prvt), DMA_TRANSFER_ERROR_CB, func != NULL); + break; + case SPI_DEV_CB_DMA_N: + break; + } +} + +int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, + const uint16_t length) +{ + const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)dev->prvt); + uint8_t rx_ch = _spi_get_rx_dma_channel(dev->prvt); + uint8_t tx_ch = _spi_get_tx_dma_channel(dev->prvt); + + if (rxbuf) { + /* Enable spi rx */ + _spi_m_dma_rx_enable(dev); + _dma_set_source_address(rx_ch, (void *)_spi_m_get_source_for_dma(dev->prvt)); + _dma_set_destination_address(rx_ch, rxbuf); + _dma_set_data_amount(rx_ch, length); + _dma_enable_transaction(rx_ch, false); + } else { + /* Disable spi rx */ + _spi_m_dma_rx_disable(dev); + } + + if (txbuf) { + /* Enable spi tx */ + _dma_set_source_address(tx_ch, txbuf); + _dma_set_destination_address(tx_ch, (void *)_spi_m_get_destination_for_dma(dev->prvt)); + _dma_srcinc_enable(tx_ch, true); + _dma_set_data_amount(tx_ch, length); + } else { + _dma_set_source_address(tx_ch, ®s->dummy_byte); + _dma_set_destination_address(tx_ch, (void *)_spi_m_get_destination_for_dma(dev->prvt)); + _dma_srcinc_enable(tx_ch, false); + _dma_set_data_amount(tx_ch, length); + } + _dma_enable_transaction(tx_ch, false); + + return ERR_NONE; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/hpl_tc.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/hpl_tc.c new file mode 100644 index 0000000..c50f65d --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/hpl_tc.c @@ -0,0 +1,347 @@ + +/** + * \file + * + * \brief SAM TC + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#include + +#ifndef CONF_TC0_ENABLE +#define CONF_TC0_ENABLE 0 +#endif +#ifndef CONF_TC1_ENABLE +#define CONF_TC1_ENABLE 0 +#endif +#ifndef CONF_TC2_ENABLE +#define CONF_TC2_ENABLE 0 +#endif +#ifndef CONF_TC3_ENABLE +#define CONF_TC3_ENABLE 0 +#endif +#ifndef CONF_TC4_ENABLE +#define CONF_TC4_ENABLE 0 +#endif +#ifndef CONF_TC5_ENABLE +#define CONF_TC5_ENABLE 0 +#endif +#ifndef CONF_TC6_ENABLE +#define CONF_TC6_ENABLE 0 +#endif +#ifndef CONF_TC7_ENABLE +#define CONF_TC7_ENABLE 0 +#endif + +/** + * \brief Macro is used to fill usart configuration structure based on its + * number + * + * \param[in] n The number of structures + */ +#define TC_CONFIGURATION(n) \ + { \ + n, TC##n##_IRQn, \ + TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC) \ + | (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) | (CONF_TC##n##_ONDEMAND << TC_CTRLA_ONDEMAND_Pos) \ + | TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_ALOCK << TC_CTRLA_ALOCK_Pos), \ + (CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos) \ + | (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos) \ + | (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos), \ + (CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1, \ + } +/** + * \brief TC configuration type + */ +struct tc_configuration { + uint8_t number; + IRQn_Type irq; + hri_tc_ctrla_reg_t ctrl_a; + hri_tc_evctrl_reg_t event_ctrl; + hri_tc_dbgctrl_reg_t dbg_ctrl; + hri_tccount8_per_reg_t per; + hri_tccount32_cc_reg_t cc0; + hri_tccount32_cc_reg_t cc1; +}; + +/** + * \brief Array of TC configurations + */ +static struct tc_configuration _tcs[] = { +#if CONF_TC0_ENABLE == 1 + TC_CONFIGURATION(0), +#endif +#if CONF_TC1_ENABLE == 1 + TC_CONFIGURATION(1), +#endif +#if CONF_TC2_ENABLE == 1 + TC_CONFIGURATION(2), +#endif +#if CONF_TC3_ENABLE == 1 + TC_CONFIGURATION(3), +#endif +#if CONF_TC4_ENABLE == 1 + TC_CONFIGURATION(4), +#endif +#if CONF_TC5_ENABLE == 1 + TC_CONFIGURATION(5), +#endif +#if CONF_TC6_ENABLE == 1 + TC_CONFIGURATION(6), +#endif +#if CONF_TC7_ENABLE == 1 + TC_CONFIGURATION(7), +#endif +}; + +static struct _timer_device *_tc0_dev = NULL; + +static int8_t get_tc_index(const void *const hw); +static void _tc_init_irq_param(const void *const hw, void *dev); +static inline uint8_t _get_hardware_offset(const void *const hw); +/** + * \brief Initialize TC + */ +int32_t _timer_init(struct _timer_device *const device, void *const hw) +{ + int8_t i = get_tc_index(hw); + + device->hw = hw; + ASSERT(ARRAY_SIZE(_tcs)); + + if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) { + if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) { + hri_tc_clear_CTRLA_ENABLE_bit(hw); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE); + } + hri_tc_write_CTRLA_reg(hw, TC_CTRLA_SWRST); + } + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + + hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); + hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl); + hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl); + hri_tc_write_WAVE_reg(hw, TC_WAVE_WAVEGEN_MFRQ); + + if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { + hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); + hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1); + + } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) { + hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0); + hri_tccount16_write_CC_reg(hw, 1, (uint16_t)_tcs[i].cc1); + + } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT8) { + hri_tccount8_write_CC_reg(hw, 0, (uint8_t)_tcs[i].cc0); + hri_tccount8_write_CC_reg(hw, 1, (uint8_t)_tcs[i].cc1); + hri_tccount8_write_PER_reg(hw, _tcs[i].per); + } + hri_tc_set_INTEN_OVF_bit(hw); + + _tc_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ(_tcs[i].irq); + NVIC_ClearPendingIRQ(_tcs[i].irq); + NVIC_EnableIRQ(_tcs[i].irq); + + return ERR_NONE; +} +/** + * \brief De-initialize TC + */ +void _timer_deinit(struct _timer_device *const device) +{ + void *const hw = device->hw; + int8_t i = get_tc_index(hw); + ASSERT(ARRAY_SIZE(_tcs)); + + NVIC_DisableIRQ(_tcs[i].irq); + + hri_tc_clear_CTRLA_ENABLE_bit(hw); + hri_tc_set_CTRLA_SWRST_bit(hw); +} +/** + * \brief Start hardware timer + */ +void _timer_start(struct _timer_device *const device) +{ + hri_tc_set_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Stop hardware timer + */ +void _timer_stop(struct _timer_device *const device) +{ + hri_tc_clear_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Set timer period + */ +void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles) +{ + void *const hw = device->hw; + + if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + hri_tccount32_write_CC_reg(hw, 0, clock_cycles); + } else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + hri_tccount16_write_CC_reg(hw, 0, (uint16_t)clock_cycles); + } else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + hri_tccount8_write_PER_reg(hw, clock_cycles); + } +} +/** + * \brief Retrieve timer period + */ +uint32_t _timer_get_period(const struct _timer_device *const device) +{ + void *const hw = device->hw; + + if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + return hri_tccount32_read_CC_reg(hw, 0); + } else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + return hri_tccount16_read_CC_reg(hw, 0); + } else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + return hri_tccount8_read_PER_reg(hw); + } + + return 0; +} +/** + * \brief Check if timer is running + */ +bool _timer_is_started(const struct _timer_device *const device) +{ + return hri_tc_get_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Retrieve timer helper functions + */ +struct _timer_hpl_interface *_tc_get_timer(void) +{ + return NULL; +} + +/** + * \brief Retrieve pwm helper functions + */ +struct _pwm_hpl_interface *_tc_get_pwm(void) +{ + return NULL; +} +/** + * \brief Set timer IRQ + * + * \param[in] hw The pointer to hardware instance + */ +void _timer_set_irq(struct _timer_device *const device) +{ + void *const hw = device->hw; + int8_t i = get_tc_index(hw); + ASSERT(ARRAY_SIZE(_tcs)); + + _irq_set(_tcs[i].irq); +} +/** + * \internal TC interrupt handler for Timer + * + * \param[in] instance TC instance number + */ +static void tc_interrupt_handler(struct _timer_device *device) +{ + void *const hw = device->hw; + + if (hri_tc_get_interrupt_OVF_bit(hw)) { + hri_tc_clear_interrupt_OVF_bit(hw); + device->timer_cb.period_expired(device); + } +} + +/** + * \brief TC interrupt handler + */ +void TC0_Handler(void) +{ + tc_interrupt_handler(_tc0_dev); +} + +/** + * \internal Retrieve TC index + * + * \param[in] hw The pointer to hardware instance + * + * \return The index of TC configuration + */ +static int8_t get_tc_index(const void *const hw) +{ + uint8_t index = _get_hardware_offset(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_tcs); i++) { + if (_tcs[i].number == index) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \brief Init irq param with the given tc hardware instance + */ +static void _tc_init_irq_param(const void *const hw, void *dev) +{ + if (hw == TC0) { + _tc0_dev = (struct _timer_device *)dev; + } +} + +/** + * \internal Retrieve TC hardware index + * + * \param[in] hw The pointer to hardware instance + */ +static inline uint8_t _get_hardware_offset(const void *const hw) +{ + /* List of available TC modules. */ + Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; + + /* Find index for TC instance. */ + for (uint32_t i = 0; i < TC_INST_NUM; i++) { + if ((uint32_t)hw == (uint32_t)tc_modules[i]) { + return i; + } + } + return 0; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/hpl_tc_base.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/hpl_tc_base.h new file mode 100644 index 0000000..ae77c90 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/hpl_tc_base.h @@ -0,0 +1,77 @@ +/** + * \file + * + * \brief SAM Timer/Counter + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HPL_TC_BASE_H_INCLUDED +#define _HPL_TC_BASE_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup tc_group TC Hardware Proxy Layer + * + * \section tc_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Retrieve timer helper functions + * + * \return A pointer to set of timer helper functions + */ +struct _timer_hpl_interface *_tc_get_timer(void); + +/** + * \brief Retrieve pwm helper functions + * + * \return A pointer to set of pwm helper functions + */ +struct _pwm_hpl_interface *_tc_get_pwm(void); + +//@} +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_TC_BASE_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ac_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ac_e54.h new file mode 100644 index 0000000..588499e --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ac_e54.h @@ -0,0 +1,1836 @@ +/** + * \file + * + * \brief SAM AC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_AC_COMPONENT_ +#ifndef _HRI_AC_E54_H_INCLUDED_ +#define _HRI_AC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AC_CRITICAL_SECTIONS) +#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AC_CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_ac_calib_reg_t; +typedef uint16_t hri_ac_evctrl_reg_t; +typedef uint32_t hri_ac_compctrl_reg_t; +typedef uint32_t hri_ac_syncbusy_reg_t; +typedef uint8_t hri_ac_ctrla_reg_t; +typedef uint8_t hri_ac_ctrlb_reg_t; +typedef uint8_t hri_ac_dbgctrl_reg_t; +typedef uint8_t hri_ac_intenset_reg_t; +typedef uint8_t hri_ac_intflag_reg_t; +typedef uint8_t hri_ac_scaler_reg_t; +typedef uint8_t hri_ac_statusa_reg_t; +typedef uint8_t hri_ac_statusb_reg_t; +typedef uint8_t hri_ac_winctrl_reg_t; + +static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + while (((Ac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + return ((Ac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) +{ + return ((Ac *)hw)->INTFLAG.reg; +} + +static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + ((Ac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; +} + +static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; +} + +static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; + } +} + +static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; +} + +static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; +} + +static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; +} + +static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; + } +} + +static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; +} + +static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; +} + +static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; +} + +static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; + } +} + +static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; +} + +static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENSET.reg = mask; +} + +static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) +{ + return ((Ac *)hw)->INTENSET.reg; +} + +static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) +{ + ((Ac *)hw)->INTENSET.reg = data; + ((Ac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSA.reg; +} + +static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; +} + +static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSB.reg; +} + +static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Ac *)hw)->SYNCBUSY.reg; +} + +static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= ~AC_CTRLA_ENABLE; + tmp |= value << AC_CTRLA_ENABLE_Pos; + ((Ac *)hw)->CTRLA.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->CTRLA.reg; +} + +static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO0; + tmp |= value << AC_EVCTRL_COMPEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO1; + tmp |= value << AC_EVCTRL_COMPEO1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_WINEO0; + tmp |= value << AC_EVCTRL_WINEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI0; + tmp |= value << AC_EVCTRL_COMPEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI1; + tmp |= value << AC_EVCTRL_COMPEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI0; + tmp |= value << AC_EVCTRL_INVEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI1; + tmp |= value << AC_EVCTRL_INVEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->EVCTRL.reg; +} + +static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= ~AC_DBGCTRL_DBGRUN; + tmp |= value << AC_DBGCTRL_DBGRUN_Pos; + ((Ac *)hw)->DBGCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->DBGCTRL.reg; +} + +static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WEN0; + tmp |= value << AC_WINCTRL_WEN0_Pos; + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WINTSEL0_Msk; + tmp |= AC_WINCTRL_WINTSEL0(data); + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + return ((Ac *)hw)->WINCTRL.reg; +} + +static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, + hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= ~AC_SCALER_VALUE_Msk; + tmp |= AC_SCALER_VALUE(data); + ((Ac *)hw)->SCALER[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) +{ + return ((Ac *)hw)->SCALER[index].reg; +} + +static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_ENABLE; + tmp |= value << AC_COMPCTRL_ENABLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SINGLE; + tmp |= value << AC_COMPCTRL_SINGLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_RUNSTDBY; + tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SWAP; + tmp |= value << AC_COMPCTRL_SWAP_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYSTEN; + tmp |= value << AC_COMPCTRL_HYSTEN_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_INTSEL_Msk; + tmp |= AC_COMPCTRL_INTSEL(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXNEG_Msk; + tmp |= AC_COMPCTRL_MUXNEG(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXPOS_Msk; + tmp |= AC_COMPCTRL_MUXPOS(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SPEED_Msk; + tmp |= AC_COMPCTRL_SPEED(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYST_Msk; + tmp |= AC_COMPCTRL_HYST(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_FLEN_Msk; + tmp |= AC_COMPCTRL_FLEN(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_OUT_Msk; + tmp |= AC_COMPCTRL_OUT(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->COMPCTRL[index].reg; +} + +static inline void hri_ac_set_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg |= AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_get_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp = (tmp & AC_CALIB_BIAS0(mask)) >> AC_CALIB_BIAS0_Pos; + return tmp; +} + +static inline void hri_ac_write_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t data) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->CALIB.reg; + tmp &= ~AC_CALIB_BIAS0_Msk; + tmp |= AC_CALIB_BIAS0(data); + ((Ac *)hw)->CALIB.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg &= ~AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg ^= AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_read_CALIB_BIAS0_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp = (tmp & AC_CALIB_BIAS0_Msk) >> AC_CALIB_BIAS0_Pos; + return tmp; +} + +static inline void hri_ac_set_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_get_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CALIB_reg(const void *const hw, hri_ac_calib_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_read_CALIB_reg(const void *const hw) +{ + return ((Ac *)hw)->CALIB.reg; +} + +static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AC_E54_H_INCLUDED */ +#endif /* _SAME54_AC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_adc_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_adc_e54.h new file mode 100644 index 0000000..7bb7e6f --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_adc_e54.h @@ -0,0 +1,3663 @@ +/** + * \file + * + * \brief SAM ADC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_ADC_COMPONENT_ +#ifndef _HRI_ADC_E54_H_INCLUDED_ +#define _HRI_ADC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ADC_CRITICAL_SECTIONS) +#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ADC_CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_adc_calib_reg_t; +typedef uint16_t hri_adc_ctrla_reg_t; +typedef uint16_t hri_adc_ctrlb_reg_t; +typedef uint16_t hri_adc_gaincorr_reg_t; +typedef uint16_t hri_adc_inputctrl_reg_t; +typedef uint16_t hri_adc_offsetcorr_reg_t; +typedef uint16_t hri_adc_ress_reg_t; +typedef uint16_t hri_adc_result_reg_t; +typedef uint16_t hri_adc_winlt_reg_t; +typedef uint16_t hri_adc_winut_reg_t; +typedef uint32_t hri_adc_dseqctrl_reg_t; +typedef uint32_t hri_adc_dseqdata_reg_t; +typedef uint32_t hri_adc_dseqstat_reg_t; +typedef uint32_t hri_adc_syncbusy_reg_t; +typedef uint8_t hri_adc_avgctrl_reg_t; +typedef uint8_t hri_adc_dbgctrl_reg_t; +typedef uint8_t hri_adc_evctrl_reg_t; +typedef uint8_t hri_adc_intenset_reg_t; +typedef uint8_t hri_adc_intflag_reg_t; +typedef uint8_t hri_adc_refctrl_reg_t; +typedef uint8_t hri_adc_sampctrl_reg_t; +typedef uint8_t hri_adc_status_reg_t; +typedef uint8_t hri_adc_swtrig_reg_t; + +static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + while (((Adc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + return ((Adc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) +{ + return ((Adc *)hw)->INTFLAG.reg; +} + +static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + ((Adc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; +} + +static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; +} + +static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; + } +} + +static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; +} + +static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; +} + +static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; +} + +static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; + } +} + +static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; +} + +static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; +} + +static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; +} + +static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; + } +} + +static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; +} + +static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENSET.reg = mask; +} + +static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) +{ + return ((Adc *)hw)->INTENSET.reg; +} + +static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) +{ + ((Adc *)hw)->INTENSET.reg = data; + ((Adc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_adc_get_STATUS_ADCBUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_ADCBUSY) >> ADC_STATUS_ADCBUSY_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_get_STATUS_WCC_bf(const void *const hw, hri_adc_status_reg_t mask) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC(mask)) >> ADC_STATUS_WCC_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_read_STATUS_WCC_bf(const void *const hw) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC_Msk) >> ADC_STATUS_WCC_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw) +{ + return ((Adc *)hw)->STATUS.reg; +} + +static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLB) >> ADC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_REFCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL) >> ADC_SYNCBUSY_REFCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Adc *)hw)->SYNCBUSY.reg; +} + +static inline bool hri_adc_get_DSEQSTAT_INPUTCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_INPUTCTRL) >> ADC_DSEQSTAT_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_CTRLB_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_CTRLB) >> ADC_DSEQSTAT_CTRLB_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_REFCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_REFCTRL) >> ADC_DSEQSTAT_REFCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_AVGCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_AVGCTRL) >> ADC_DSEQSTAT_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_SAMPCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_SAMPCTRL) >> ADC_DSEQSTAT_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_WINLT_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINLT) >> ADC_DSEQSTAT_WINLT_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_WINUT_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINUT) >> ADC_DSEQSTAT_WINUT_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_GAINCORR_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_GAINCORR) >> ADC_DSEQSTAT_GAINCORR_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_OFFSETCORR_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_OFFSETCORR) >> ADC_DSEQSTAT_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_BUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_BUSY) >> ADC_DSEQSTAT_BUSY_Pos; +} + +static inline hri_adc_dseqstat_reg_t hri_adc_get_DSEQSTAT_reg(const void *const hw, hri_adc_dseqstat_reg_t mask) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQSTAT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_dseqstat_reg_t hri_adc_read_DSEQSTAT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->DSEQSTAT.reg; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) +{ + return ((Adc *)hw)->RESULT.reg; +} + +static inline hri_adc_ress_reg_t hri_adc_get_RESS_RESS_bf(const void *const hw, hri_adc_ress_reg_t mask) +{ + return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS(mask)) >> ADC_RESS_RESS_Pos; +} + +static inline hri_adc_ress_reg_t hri_adc_read_RESS_RESS_bf(const void *const hw) +{ + return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS_Msk) >> ADC_RESS_RESS_Pos; +} + +static inline hri_adc_ress_reg_t hri_adc_get_RESS_reg(const void *const hw, hri_adc_ress_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_ress_reg_t hri_adc_read_RESS_reg(const void *const hw) +{ + return ((Adc *)hw)->RESS.reg; +} + +static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ENABLE; + tmp |= value << ADC_CTRLA_ENABLE_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SLAVEEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SLAVEEN) >> ADC_CTRLA_SLAVEEN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_SLAVEEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_SLAVEEN; + tmp |= value << ADC_CTRLA_SLAVEEN_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_RUNSTDBY; + tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ONDEMAND; + tmp |= value << ADC_CTRLA_ONDEMAND_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_R2R_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_R2R) >> ADC_CTRLA_R2R_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_R2R_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_R2R; + tmp |= value << ADC_CTRLA_R2R_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_DUALSEL(mask)) >> ADC_CTRLA_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_DUALSEL_Msk; + tmp |= ADC_CTRLA_DUALSEL(data); + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_DUALSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_DUALSEL_Msk) >> ADC_CTRLA_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_PRESCALER(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_PRESCALER(mask)) >> ADC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_PRESCALER_Msk; + tmp |= ADC_CTRLA_PRESCALER(data); + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_PRESCALER(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_PRESCALER(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_PRESCALER_Msk) >> ADC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + return ((Adc *)hw)->CTRLA.reg; +} + +static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHEI; + tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTEI; + tmp |= value << ADC_EVCTRL_STARTEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHINV; + tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTINV; + tmp |= value << ADC_EVCTRL_STARTINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_RESRDYEO; + tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_WINMONEO; + tmp |= value << ADC_EVCTRL_WINMONEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->EVCTRL.reg; +} + +static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= ~ADC_DBGCTRL_DBGRUN; + tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; + ((Adc *)hw)->DBGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->DBGCTRL.reg; +} + +static inline void hri_adc_set_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_DIFFMODE) >> ADC_INPUTCTRL_DIFFMODE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_INPUTCTRL_DIFFMODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_DIFFMODE; + tmp |= value << ADC_INPUTCTRL_DIFFMODE_Pos; + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DSEQSTOP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_DSEQSTOP) >> ADC_INPUTCTRL_DSEQSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_INPUTCTRL_DSEQSTOP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_DSEQSTOP; + tmp |= value << ADC_INPUTCTRL_DSEQSTOP_Pos; + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DSEQSTOP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DSEQSTOP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; + tmp |= ADC_INPUTCTRL_MUXPOS(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; + tmp |= ADC_INPUTCTRL_MUXNEG(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->INPUTCTRL.reg; +} + +static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_LEFTADJ; + tmp |= value << ADC_CTRLB_LEFTADJ_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_FREERUN; + tmp |= value << ADC_CTRLB_FREERUN_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_CORREN; + tmp |= value << ADC_CTRLB_CORREN_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINSS; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_WINSS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINSS) >> ADC_CTRLB_WINSS_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_WINSS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_WINSS; + tmp |= value << ADC_CTRLB_WINSS_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINSS; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINSS; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_RESSEL_Msk; + tmp |= ADC_CTRLB_RESSEL(data); + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINMODE(mask)) >> ADC_CTRLB_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_WINMODE_Msk; + tmp |= ADC_CTRLB_WINMODE(data); + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_WINMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINMODE_Msk) >> ADC_CTRLB_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->CTRLB.reg; +} + +static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFCOMP; + tmp |= value << ADC_REFCTRL_REFCOMP_Pos; + ((Adc *)hw)->REFCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFSEL_Msk; + tmp |= ADC_REFCTRL_REFSEL(data); + ((Adc *)hw)->REFCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->REFCTRL.reg; +} + +static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; + tmp |= ADC_AVGCTRL_SAMPLENUM(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_ADJRES_Msk; + tmp |= ADC_AVGCTRL_ADJRES(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->AVGCTRL.reg; +} + +static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_OFFCOMP; + tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; + tmp |= ADC_SAMPCTRL_SAMPLEN(data); + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SAMPCTRL.reg; +} + +static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= ~ADC_WINLT_WINLT_Msk; + tmp |= ADC_WINLT_WINLT(data); + ((Adc *)hw)->WINLT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + return ((Adc *)hw)->WINLT.reg; +} + +static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= ~ADC_WINUT_WINUT_Msk; + tmp |= ADC_WINUT_WINUT(data); + ((Adc *)hw)->WINUT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + return ((Adc *)hw)->WINUT.reg; +} + +static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= ~ADC_GAINCORR_GAINCORR_Msk; + tmp |= ADC_GAINCORR_GAINCORR(data); + ((Adc *)hw)->GAINCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + return ((Adc *)hw)->GAINCORR.reg; +} + +static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, + hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; + tmp |= ADC_OFFSETCORR_OFFSETCORR(data); + ((Adc *)hw)->OFFSETCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->OFFSETCORR.reg; +} + +static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_FLUSH; + tmp |= value << ADC_SWTRIG_FLUSH_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_START; + tmp |= value << ADC_SWTRIG_START_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SWTRIG.reg; +} + +static inline void hri_adc_set_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_INPUTCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_INPUTCTRL) >> ADC_DSEQCTRL_INPUTCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_INPUTCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_INPUTCTRL; + tmp |= value << ADC_DSEQCTRL_INPUTCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_INPUTCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_INPUTCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_CTRLB; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_CTRLB) >> ADC_DSEQCTRL_CTRLB_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_CTRLB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_CTRLB; + tmp |= value << ADC_DSEQCTRL_CTRLB_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_CTRLB; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_CTRLB; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_REFCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_REFCTRL) >> ADC_DSEQCTRL_REFCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_REFCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_REFCTRL; + tmp |= value << ADC_DSEQCTRL_REFCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_REFCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_REFCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AVGCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_AVGCTRL) >> ADC_DSEQCTRL_AVGCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_AVGCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_AVGCTRL; + tmp |= value << ADC_DSEQCTRL_AVGCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AVGCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AVGCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_SAMPCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_SAMPCTRL) >> ADC_DSEQCTRL_SAMPCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_SAMPCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_SAMPCTRL; + tmp |= value << ADC_DSEQCTRL_SAMPCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_SAMPCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_SAMPCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINLT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_WINLT_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_WINLT) >> ADC_DSEQCTRL_WINLT_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_WINLT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_WINLT; + tmp |= value << ADC_DSEQCTRL_WINLT_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINLT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINLT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINUT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_WINUT_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_WINUT) >> ADC_DSEQCTRL_WINUT_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_WINUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_WINUT; + tmp |= value << ADC_DSEQCTRL_WINUT_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINUT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINUT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_GAINCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_GAINCORR) >> ADC_DSEQCTRL_GAINCORR_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_GAINCORR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_GAINCORR; + tmp |= value << ADC_DSEQCTRL_GAINCORR_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_GAINCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_GAINCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_OFFSETCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_OFFSETCORR) >> ADC_DSEQCTRL_OFFSETCORR_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_OFFSETCORR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_OFFSETCORR; + tmp |= value << ADC_DSEQCTRL_OFFSETCORR_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_OFFSETCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_OFFSETCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AUTOSTART; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_AUTOSTART) >> ADC_DSEQCTRL_AUTOSTART_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_AUTOSTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_AUTOSTART; + tmp |= value << ADC_DSEQCTRL_AUTOSTART_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AUTOSTART; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AUTOSTART; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dseqctrl_reg_t hri_adc_get_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg = data; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dseqctrl_reg_t hri_adc_read_DSEQCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->DSEQCTRL.reg; +} + +static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASCOMP_Msk; + tmp |= ADC_CALIB_BIASCOMP(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASR2R(mask)) >> ADC_CALIB_BIASR2R_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASR2R_Msk; + tmp |= ADC_CALIB_BIASR2R(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASR2R_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASR2R_Msk) >> ADC_CALIB_BIASR2R_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASREFBUF_Msk; + tmp |= ADC_CALIB_BIASREFBUF(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) +{ + return ((Adc *)hw)->CALIB.reg; +} + +static inline void hri_adc_write_DSEQDATA_reg(const void *const hw, hri_adc_dseqdata_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQDATA.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ADC_E54_H_INCLUDED */ +#endif /* _SAME54_ADC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_aes_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_aes_e54.h new file mode 100644 index 0000000..c1070e2 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_aes_e54.h @@ -0,0 +1,1287 @@ +/** + * \file + * + * \brief SAM AES + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_AES_COMPONENT_ +#ifndef _HRI_AES_E54_H_INCLUDED_ +#define _HRI_AES_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AES_CRITICAL_SECTIONS) +#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AES_CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_aes_ciplen_reg_t; +typedef uint32_t hri_aes_ctrla_reg_t; +typedef uint32_t hri_aes_ghash_reg_t; +typedef uint32_t hri_aes_hashkey_reg_t; +typedef uint32_t hri_aes_indata_reg_t; +typedef uint32_t hri_aes_intvectv_reg_t; +typedef uint32_t hri_aes_keyword_reg_t; +typedef uint32_t hri_aes_randseed_reg_t; +typedef uint8_t hri_aes_ctrlb_reg_t; +typedef uint8_t hri_aes_databufptr_reg_t; +typedef uint8_t hri_aes_dbgctrl_reg_t; +typedef uint8_t hri_aes_intenset_reg_t; +typedef uint8_t hri_aes_intflag_reg_t; + +static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw) +{ + return ((Aes *)hw)->INTFLAG.reg; +} + +static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + ((Aes *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; +} + +static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; +} + +static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; + } +} + +static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; +} + +static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; +} + +static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; +} + +static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; + } +} + +static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; +} + +static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENSET.reg = mask; +} + +static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw) +{ + return ((Aes *)hw)->INTENSET.reg; +} + +static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data) +{ + ((Aes *)hw)->INTENSET.reg = data; + ((Aes *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_ENABLE; + tmp |= value << AES_CTRLA_ENABLE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CIPHER; + tmp |= value << AES_CTRLA_CIPHER_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_STARTMODE; + tmp |= value << AES_CTRLA_STARTMODE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_LOD; + tmp |= value << AES_CTRLA_LOD_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYGEN; + tmp |= value << AES_CTRLA_KEYGEN_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_XORKEY; + tmp |= value << AES_CTRLA_XORKEY_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_AESMODE_Msk; + tmp |= AES_CTRLA_AESMODE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CFBS_Msk; + tmp |= AES_CTRLA_CFBS(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYSIZE_Msk; + tmp |= AES_CTRLA_KEYSIZE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CTYPE_Msk; + tmp |= AES_CTRLA_CTYPE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLA.reg; +} + +static inline void hri_aes_set_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_START; + tmp |= value << AES_CTRLB_START_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_NEWMSG; + tmp |= value << AES_CTRLB_NEWMSG_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_EOM; + tmp |= value << AES_CTRLB_EOM_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_GFMUL; + tmp |= value << AES_CTRLB_GFMUL_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLB.reg; +} + +static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const hw, + hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk; + tmp |= AES_DATABUFPTR_INDATAPTR(data); + ((Aes *)hw)->DATABUFPTR.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw) +{ + return ((Aes *)hw)->DATABUFPTR.reg; +} + +static inline void hri_aes_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg |= AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp = (tmp & AES_DBGCTRL_DBGRUN) >> AES_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp &= ~AES_DBGCTRL_DBGRUN; + tmp |= value << AES_DBGCTRL_DBGRUN_Pos; + ((Aes *)hw)->DBGCTRL.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg &= ~AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg ^= AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_dbgctrl_reg_t hri_aes_get_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_dbgctrl_reg_t hri_aes_read_DBGCTRL_reg(const void *const hw) +{ + return ((Aes *)hw)->DBGCTRL.reg; +} + +static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->INDATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw) +{ + return ((Aes *)hw)->INDATA.reg; +} + +static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index, + hri_aes_hashkey_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->HASHKEY[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->HASHKEY[index].reg; +} + +static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->GHASH[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->GHASH[index].reg; +} + +static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CIPLEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw) +{ + return ((Aes *)hw)->CIPLEN.reg; +} + +static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->RANDSEED.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw) +{ + return ((Aes *)hw)->RANDSEED.reg; +} + +static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->KEYWORD[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INTVECTV[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AES_E54_H_INCLUDED */ +#endif /* _SAME54_AES_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_can_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_can_e54.h new file mode 100644 index 0000000..2c02884 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_can_e54.h @@ -0,0 +1,16997 @@ +/** + * \file + * + * \brief SAM CAN + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_CAN_COMPONENT_ +#ifndef _HRI_CAN_E54_H_INCLUDED_ +#define _HRI_CAN_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CAN_CRITICAL_SECTIONS) +#define CAN_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CAN_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CAN_CRITICAL_SECTION_ENTER() +#define CAN_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_can_cccr_reg_t; +typedef uint32_t hri_can_crel_reg_t; +typedef uint32_t hri_can_dbtp_reg_t; +typedef uint32_t hri_can_ecr_reg_t; +typedef uint32_t hri_can_endn_reg_t; +typedef uint32_t hri_can_gfc_reg_t; +typedef uint32_t hri_can_hpms_reg_t; +typedef uint32_t hri_can_ie_reg_t; +typedef uint32_t hri_can_ile_reg_t; +typedef uint32_t hri_can_ils_reg_t; +typedef uint32_t hri_can_ir_reg_t; +typedef uint32_t hri_can_mrcfg_reg_t; +typedef uint32_t hri_can_nbtp_reg_t; +typedef uint32_t hri_can_ndat1_reg_t; +typedef uint32_t hri_can_ndat2_reg_t; +typedef uint32_t hri_can_psr_reg_t; +typedef uint32_t hri_can_rwd_reg_t; +typedef uint32_t hri_can_rxbc_reg_t; +typedef uint32_t hri_can_rxesc_reg_t; +typedef uint32_t hri_can_rxf0a_reg_t; +typedef uint32_t hri_can_rxf0c_reg_t; +typedef uint32_t hri_can_rxf0s_reg_t; +typedef uint32_t hri_can_rxf1a_reg_t; +typedef uint32_t hri_can_rxf1c_reg_t; +typedef uint32_t hri_can_rxf1s_reg_t; +typedef uint32_t hri_can_sidfc_reg_t; +typedef uint32_t hri_can_tdcr_reg_t; +typedef uint32_t hri_can_test_reg_t; +typedef uint32_t hri_can_tocc_reg_t; +typedef uint32_t hri_can_tocv_reg_t; +typedef uint32_t hri_can_tscc_reg_t; +typedef uint32_t hri_can_tscv_reg_t; +typedef uint32_t hri_can_txbar_reg_t; +typedef uint32_t hri_can_txbc_reg_t; +typedef uint32_t hri_can_txbcf_reg_t; +typedef uint32_t hri_can_txbcie_reg_t; +typedef uint32_t hri_can_txbcr_reg_t; +typedef uint32_t hri_can_txbrp_reg_t; +typedef uint32_t hri_can_txbtie_reg_t; +typedef uint32_t hri_can_txbto_reg_t; +typedef uint32_t hri_can_txefa_reg_t; +typedef uint32_t hri_can_txefc_reg_t; +typedef uint32_t hri_can_txefs_reg_t; +typedef uint32_t hri_can_txesc_reg_t; +typedef uint32_t hri_can_txfqs_reg_t; +typedef uint32_t hri_can_xidam_reg_t; +typedef uint32_t hri_can_xidfc_reg_t; + +static inline hri_can_crel_reg_t hri_can_get_CREL_SUBSTEP_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP(mask)) >> CAN_CREL_SUBSTEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_SUBSTEP_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP_Msk) >> CAN_CREL_SUBSTEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_STEP_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_STEP(mask)) >> CAN_CREL_STEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_STEP_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_STEP_Msk) >> CAN_CREL_STEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_REL_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_REL(mask)) >> CAN_CREL_REL_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_REL_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_REL_Msk) >> CAN_CREL_REL_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_reg(const void *const hw, hri_can_crel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CREL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_reg(const void *const hw) +{ + return ((Can *)hw)->CREL.reg; +} + +static inline hri_can_endn_reg_t hri_can_get_ENDN_ETV_bf(const void *const hw, hri_can_endn_reg_t mask) +{ + return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV(mask)) >> CAN_ENDN_ETV_Pos; +} + +static inline hri_can_endn_reg_t hri_can_read_ENDN_ETV_bf(const void *const hw) +{ + return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV_Msk) >> CAN_ENDN_ETV_Pos; +} + +static inline hri_can_endn_reg_t hri_can_get_ENDN_reg(const void *const hw, hri_can_endn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ENDN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_endn_reg_t hri_can_read_ENDN_reg(const void *const hw) +{ + return ((Can *)hw)->ENDN.reg; +} + +static inline hri_can_tscv_reg_t hri_can_get_TSCV_TSC_bf(const void *const hw, hri_can_tscv_reg_t mask) +{ + return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC(mask)) >> CAN_TSCV_TSC_Pos; +} + +static inline hri_can_tscv_reg_t hri_can_read_TSCV_TSC_bf(const void *const hw) +{ + return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC_Msk) >> CAN_TSCV_TSC_Pos; +} + +static inline hri_can_tscv_reg_t hri_can_get_TSCV_reg(const void *const hw, hri_can_tscv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCV.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_tscv_reg_t hri_can_read_TSCV_reg(const void *const hw) +{ + return ((Can *)hw)->TSCV.reg; +} + +static inline bool hri_can_get_ECR_RP_bit(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_RP) >> CAN_ECR_RP_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_TEC_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_TEC(mask)) >> CAN_ECR_TEC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_TEC_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_REC_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_REC(mask)) >> CAN_ECR_REC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_REC_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_CEL_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_CEL(mask)) >> CAN_ECR_CEL_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_CEL_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_CEL_Msk) >> CAN_ECR_CEL_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_reg(const void *const hw, hri_can_ecr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ECR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_reg(const void *const hw) +{ + return ((Can *)hw)->ECR.reg; +} + +static inline bool hri_can_get_PSR_EP_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_EP) >> CAN_PSR_EP_Pos; +} + +static inline bool hri_can_get_PSR_EW_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_EW) >> CAN_PSR_EW_Pos; +} + +static inline bool hri_can_get_PSR_BO_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_BO) >> CAN_PSR_BO_Pos; +} + +static inline bool hri_can_get_PSR_RESI_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RESI) >> CAN_PSR_RESI_Pos; +} + +static inline bool hri_can_get_PSR_RBRS_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RBRS) >> CAN_PSR_RBRS_Pos; +} + +static inline bool hri_can_get_PSR_RFDF_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RFDF) >> CAN_PSR_RFDF_Pos; +} + +static inline bool hri_can_get_PSR_PXE_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_PXE) >> CAN_PSR_PXE_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_LEC_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_LEC(mask)) >> CAN_PSR_LEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_LEC_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_LEC_Msk) >> CAN_PSR_LEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_ACT_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_ACT(mask)) >> CAN_PSR_ACT_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_ACT_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_ACT_Msk) >> CAN_PSR_ACT_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_DLEC_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC(mask)) >> CAN_PSR_DLEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_DLEC_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC_Msk) >> CAN_PSR_DLEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_TDCV_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV(mask)) >> CAN_PSR_TDCV_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_TDCV_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV_Msk) >> CAN_PSR_TDCV_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_reg(const void *const hw, hri_can_psr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->PSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_reg(const void *const hw) +{ + return ((Can *)hw)->PSR.reg; +} + +static inline bool hri_can_get_HPMS_FLST_bit(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FLST) >> CAN_HPMS_FLST_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_BIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX(mask)) >> CAN_HPMS_BIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_BIDX_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX_Msk) >> CAN_HPMS_BIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_MSI_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI(mask)) >> CAN_HPMS_MSI_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_MSI_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI_Msk) >> CAN_HPMS_MSI_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_FIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX(mask)) >> CAN_HPMS_FIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_FIDX_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX_Msk) >> CAN_HPMS_FIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_reg(const void *const hw, hri_can_hpms_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->HPMS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_reg(const void *const hw) +{ + return ((Can *)hw)->HPMS.reg; +} + +static inline bool hri_can_get_RXF0S_F0F_bit(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0F) >> CAN_RXF0S_F0F_Pos; +} + +static inline bool hri_can_get_RXF0S_RF0L_bit(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_RF0L) >> CAN_RXF0S_RF0L_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0FL_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL(mask)) >> CAN_RXF0S_F0FL_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0FL_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL_Msk) >> CAN_RXF0S_F0FL_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0GI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI(mask)) >> CAN_RXF0S_F0GI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0GI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0PI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI(mask)) >> CAN_RXF0S_F0PI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0PI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI_Msk) >> CAN_RXF0S_F0PI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_reg(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0S.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0S.reg; +} + +static inline bool hri_can_get_RXF1S_F1F_bit(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1F) >> CAN_RXF1S_F1F_Pos; +} + +static inline bool hri_can_get_RXF1S_RF1L_bit(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_RF1L) >> CAN_RXF1S_RF1L_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1FL_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL(mask)) >> CAN_RXF1S_F1FL_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1FL_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL_Msk) >> CAN_RXF1S_F1FL_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1GI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI(mask)) >> CAN_RXF1S_F1GI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1GI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1PI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI(mask)) >> CAN_RXF1S_F1PI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1PI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI_Msk) >> CAN_RXF1S_F1PI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_DMS_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS(mask)) >> CAN_RXF1S_DMS_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_DMS_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS_Msk) >> CAN_RXF1S_DMS_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_reg(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1S.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1S.reg; +} + +static inline bool hri_can_get_TXFQS_TFQF_bit(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQF) >> CAN_TXFQS_TFQF_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFFL_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL(mask)) >> CAN_TXFQS_TFFL_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFFL_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL_Msk) >> CAN_TXFQS_TFFL_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFGI_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI(mask)) >> CAN_TXFQS_TFGI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFGI_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI_Msk) >> CAN_TXFQS_TFGI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFQPI_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI(mask)) >> CAN_TXFQS_TFQPI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFQPI_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_reg(const void *const hw, hri_can_txfqs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXFQS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_reg(const void *const hw) +{ + return ((Can *)hw)->TXFQS.reg; +} + +static inline bool hri_can_get_TXBRP_TRP0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP0) >> CAN_TXBRP_TRP0_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP1) >> CAN_TXBRP_TRP1_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP2) >> CAN_TXBRP_TRP2_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP3) >> CAN_TXBRP_TRP3_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP4) >> CAN_TXBRP_TRP4_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP5) >> CAN_TXBRP_TRP5_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP6) >> CAN_TXBRP_TRP6_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP7) >> CAN_TXBRP_TRP7_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP8) >> CAN_TXBRP_TRP8_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP9) >> CAN_TXBRP_TRP9_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP10) >> CAN_TXBRP_TRP10_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP11) >> CAN_TXBRP_TRP11_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP12) >> CAN_TXBRP_TRP12_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP13) >> CAN_TXBRP_TRP13_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP14) >> CAN_TXBRP_TRP14_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP15) >> CAN_TXBRP_TRP15_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP16) >> CAN_TXBRP_TRP16_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP17) >> CAN_TXBRP_TRP17_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP18) >> CAN_TXBRP_TRP18_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP19) >> CAN_TXBRP_TRP19_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP20) >> CAN_TXBRP_TRP20_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP21) >> CAN_TXBRP_TRP21_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP22) >> CAN_TXBRP_TRP22_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP23) >> CAN_TXBRP_TRP23_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP24) >> CAN_TXBRP_TRP24_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP25) >> CAN_TXBRP_TRP25_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP26) >> CAN_TXBRP_TRP26_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP27) >> CAN_TXBRP_TRP27_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP28) >> CAN_TXBRP_TRP28_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP29) >> CAN_TXBRP_TRP29_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP30) >> CAN_TXBRP_TRP30_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP31) >> CAN_TXBRP_TRP31_Pos; +} + +static inline hri_can_txbrp_reg_t hri_can_get_TXBRP_reg(const void *const hw, hri_can_txbrp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBRP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbrp_reg_t hri_can_read_TXBRP_reg(const void *const hw) +{ + return ((Can *)hw)->TXBRP.reg; +} + +static inline bool hri_can_get_TXBTO_TO0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO0) >> CAN_TXBTO_TO0_Pos; +} + +static inline bool hri_can_get_TXBTO_TO1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO1) >> CAN_TXBTO_TO1_Pos; +} + +static inline bool hri_can_get_TXBTO_TO2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO2) >> CAN_TXBTO_TO2_Pos; +} + +static inline bool hri_can_get_TXBTO_TO3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO3) >> CAN_TXBTO_TO3_Pos; +} + +static inline bool hri_can_get_TXBTO_TO4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO4) >> CAN_TXBTO_TO4_Pos; +} + +static inline bool hri_can_get_TXBTO_TO5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO5) >> CAN_TXBTO_TO5_Pos; +} + +static inline bool hri_can_get_TXBTO_TO6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO6) >> CAN_TXBTO_TO6_Pos; +} + +static inline bool hri_can_get_TXBTO_TO7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO7) >> CAN_TXBTO_TO7_Pos; +} + +static inline bool hri_can_get_TXBTO_TO8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO8) >> CAN_TXBTO_TO8_Pos; +} + +static inline bool hri_can_get_TXBTO_TO9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO9) >> CAN_TXBTO_TO9_Pos; +} + +static inline bool hri_can_get_TXBTO_TO10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO10) >> CAN_TXBTO_TO10_Pos; +} + +static inline bool hri_can_get_TXBTO_TO11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO11) >> CAN_TXBTO_TO11_Pos; +} + +static inline bool hri_can_get_TXBTO_TO12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO12) >> CAN_TXBTO_TO12_Pos; +} + +static inline bool hri_can_get_TXBTO_TO13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO13) >> CAN_TXBTO_TO13_Pos; +} + +static inline bool hri_can_get_TXBTO_TO14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO14) >> CAN_TXBTO_TO14_Pos; +} + +static inline bool hri_can_get_TXBTO_TO15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO15) >> CAN_TXBTO_TO15_Pos; +} + +static inline bool hri_can_get_TXBTO_TO16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO16) >> CAN_TXBTO_TO16_Pos; +} + +static inline bool hri_can_get_TXBTO_TO17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO17) >> CAN_TXBTO_TO17_Pos; +} + +static inline bool hri_can_get_TXBTO_TO18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO18) >> CAN_TXBTO_TO18_Pos; +} + +static inline bool hri_can_get_TXBTO_TO19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO19) >> CAN_TXBTO_TO19_Pos; +} + +static inline bool hri_can_get_TXBTO_TO20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO20) >> CAN_TXBTO_TO20_Pos; +} + +static inline bool hri_can_get_TXBTO_TO21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO21) >> CAN_TXBTO_TO21_Pos; +} + +static inline bool hri_can_get_TXBTO_TO22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO22) >> CAN_TXBTO_TO22_Pos; +} + +static inline bool hri_can_get_TXBTO_TO23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO23) >> CAN_TXBTO_TO23_Pos; +} + +static inline bool hri_can_get_TXBTO_TO24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO24) >> CAN_TXBTO_TO24_Pos; +} + +static inline bool hri_can_get_TXBTO_TO25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO25) >> CAN_TXBTO_TO25_Pos; +} + +static inline bool hri_can_get_TXBTO_TO26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO26) >> CAN_TXBTO_TO26_Pos; +} + +static inline bool hri_can_get_TXBTO_TO27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO27) >> CAN_TXBTO_TO27_Pos; +} + +static inline bool hri_can_get_TXBTO_TO28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO28) >> CAN_TXBTO_TO28_Pos; +} + +static inline bool hri_can_get_TXBTO_TO29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO29) >> CAN_TXBTO_TO29_Pos; +} + +static inline bool hri_can_get_TXBTO_TO30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO30) >> CAN_TXBTO_TO30_Pos; +} + +static inline bool hri_can_get_TXBTO_TO31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO31) >> CAN_TXBTO_TO31_Pos; +} + +static inline hri_can_txbto_reg_t hri_can_get_TXBTO_reg(const void *const hw, hri_can_txbto_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTO.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbto_reg_t hri_can_read_TXBTO_reg(const void *const hw) +{ + return ((Can *)hw)->TXBTO.reg; +} + +static inline bool hri_can_get_TXBCF_CF0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF0) >> CAN_TXBCF_CF0_Pos; +} + +static inline bool hri_can_get_TXBCF_CF1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF1) >> CAN_TXBCF_CF1_Pos; +} + +static inline bool hri_can_get_TXBCF_CF2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF2) >> CAN_TXBCF_CF2_Pos; +} + +static inline bool hri_can_get_TXBCF_CF3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF3) >> CAN_TXBCF_CF3_Pos; +} + +static inline bool hri_can_get_TXBCF_CF4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF4) >> CAN_TXBCF_CF4_Pos; +} + +static inline bool hri_can_get_TXBCF_CF5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF5) >> CAN_TXBCF_CF5_Pos; +} + +static inline bool hri_can_get_TXBCF_CF6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF6) >> CAN_TXBCF_CF6_Pos; +} + +static inline bool hri_can_get_TXBCF_CF7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF7) >> CAN_TXBCF_CF7_Pos; +} + +static inline bool hri_can_get_TXBCF_CF8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF8) >> CAN_TXBCF_CF8_Pos; +} + +static inline bool hri_can_get_TXBCF_CF9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF9) >> CAN_TXBCF_CF9_Pos; +} + +static inline bool hri_can_get_TXBCF_CF10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF10) >> CAN_TXBCF_CF10_Pos; +} + +static inline bool hri_can_get_TXBCF_CF11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF11) >> CAN_TXBCF_CF11_Pos; +} + +static inline bool hri_can_get_TXBCF_CF12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF12) >> CAN_TXBCF_CF12_Pos; +} + +static inline bool hri_can_get_TXBCF_CF13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF13) >> CAN_TXBCF_CF13_Pos; +} + +static inline bool hri_can_get_TXBCF_CF14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF14) >> CAN_TXBCF_CF14_Pos; +} + +static inline bool hri_can_get_TXBCF_CF15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF15) >> CAN_TXBCF_CF15_Pos; +} + +static inline bool hri_can_get_TXBCF_CF16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF16) >> CAN_TXBCF_CF16_Pos; +} + +static inline bool hri_can_get_TXBCF_CF17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF17) >> CAN_TXBCF_CF17_Pos; +} + +static inline bool hri_can_get_TXBCF_CF18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF18) >> CAN_TXBCF_CF18_Pos; +} + +static inline bool hri_can_get_TXBCF_CF19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF19) >> CAN_TXBCF_CF19_Pos; +} + +static inline bool hri_can_get_TXBCF_CF20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF20) >> CAN_TXBCF_CF20_Pos; +} + +static inline bool hri_can_get_TXBCF_CF21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF21) >> CAN_TXBCF_CF21_Pos; +} + +static inline bool hri_can_get_TXBCF_CF22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF22) >> CAN_TXBCF_CF22_Pos; +} + +static inline bool hri_can_get_TXBCF_CF23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF23) >> CAN_TXBCF_CF23_Pos; +} + +static inline bool hri_can_get_TXBCF_CF24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF24) >> CAN_TXBCF_CF24_Pos; +} + +static inline bool hri_can_get_TXBCF_CF25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF25) >> CAN_TXBCF_CF25_Pos; +} + +static inline bool hri_can_get_TXBCF_CF26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF26) >> CAN_TXBCF_CF26_Pos; +} + +static inline bool hri_can_get_TXBCF_CF27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF27) >> CAN_TXBCF_CF27_Pos; +} + +static inline bool hri_can_get_TXBCF_CF28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF28) >> CAN_TXBCF_CF28_Pos; +} + +static inline bool hri_can_get_TXBCF_CF29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF29) >> CAN_TXBCF_CF29_Pos; +} + +static inline bool hri_can_get_TXBCF_CF30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF30) >> CAN_TXBCF_CF30_Pos; +} + +static inline bool hri_can_get_TXBCF_CF31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF31) >> CAN_TXBCF_CF31_Pos; +} + +static inline hri_can_txbcf_reg_t hri_can_get_TXBCF_reg(const void *const hw, hri_can_txbcf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbcf_reg_t hri_can_read_TXBCF_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCF.reg; +} + +static inline bool hri_can_get_TXEFS_EFF_bit(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFF) >> CAN_TXEFS_EFF_Pos; +} + +static inline bool hri_can_get_TXEFS_TEFL_bit(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_TEFL) >> CAN_TXEFS_TEFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFFL_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL(mask)) >> CAN_TXEFS_EFFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFFL_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL_Msk) >> CAN_TXEFS_EFFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFGI_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI(mask)) >> CAN_TXEFS_EFGI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFGI_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFPI_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI(mask)) >> CAN_TXEFS_EFPI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFPI_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI_Msk) >> CAN_TXEFS_EFPI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_reg(const void *const hw, hri_can_txefs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFS.reg; +} + +static inline void hri_can_set_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg |= CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp = (tmp & CAN_MRCFG_QOS(mask)) >> CAN_MRCFG_QOS_Pos; + return tmp; +} + +static inline void hri_can_write_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->MRCFG.reg; + tmp &= ~CAN_MRCFG_QOS_Msk; + tmp |= CAN_MRCFG_QOS(data); + ((Can *)hw)->MRCFG.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg &= ~CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg ^= CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_QOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp = (tmp & CAN_MRCFG_QOS_Msk) >> CAN_MRCFG_QOS_Pos; + return tmp; +} + +static inline void hri_can_set_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_reg(const void *const hw) +{ + return ((Can *)hw)->MRCFG.reg; +} + +static inline void hri_can_set_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_DBTP_TDC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_TDC) >> CAN_DBTP_TDC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_DBTP_TDC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_TDC; + tmp |= value << CAN_DBTP_TDC_Pos; + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DSJW(mask)) >> CAN_DBTP_DSJW_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DSJW_Msk; + tmp |= CAN_DBTP_DSJW(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DSJW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DSJW_Msk) >> CAN_DBTP_DSJW_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG2(mask)) >> CAN_DBTP_DTSEG2_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DTSEG2_Msk; + tmp |= CAN_DBTP_DTSEG2(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG2_Msk) >> CAN_DBTP_DTSEG2_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG1(mask)) >> CAN_DBTP_DTSEG1_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DTSEG1_Msk; + tmp |= CAN_DBTP_DTSEG1(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG1_Msk) >> CAN_DBTP_DTSEG1_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DBRP(mask)) >> CAN_DBTP_DBRP_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DBRP_Msk; + tmp |= CAN_DBTP_DBRP(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DBRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DBRP_Msk) >> CAN_DBTP_DBRP_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_reg(const void *const hw) +{ + return ((Can *)hw)->DBTP.reg; +} + +static inline void hri_can_set_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TEST_LBCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_LBCK) >> CAN_TEST_LBCK_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TEST_LBCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_LBCK; + tmp |= value << CAN_TEST_LBCK_Pos; + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TEST_RX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_RX) >> CAN_TEST_RX_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TEST_RX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_RX; + tmp |= value << CAN_TEST_RX_Pos; + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_get_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_TX(mask)) >> CAN_TEST_TX_Pos; + return tmp; +} + +static inline void hri_can_write_TEST_TX_bf(const void *const hw, hri_can_test_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_TX_Msk; + tmp |= CAN_TEST_TX(data); + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_read_TEST_TX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_TX_Msk) >> CAN_TEST_TX_Pos; + return tmp; +} + +static inline void hri_can_set_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_get_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TEST_reg(const void *const hw, hri_can_test_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_read_TEST_reg(const void *const hw) +{ + return ((Can *)hw)->TEST.reg; +} + +static inline void hri_can_set_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDC(mask)) >> CAN_RWD_WDC_Pos; + return tmp; +} + +static inline void hri_can_write_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RWD.reg; + tmp &= ~CAN_RWD_WDC_Msk; + tmp |= CAN_RWD_WDC(data); + ((Can *)hw)->RWD.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_WDC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDC_Msk) >> CAN_RWD_WDC_Pos; + return tmp; +} + +static inline void hri_can_set_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDV(mask)) >> CAN_RWD_WDV_Pos; + return tmp; +} + +static inline void hri_can_write_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RWD.reg; + tmp &= ~CAN_RWD_WDV_Msk; + tmp |= CAN_RWD_WDV(data); + ((Can *)hw)->RWD.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_WDV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDV_Msk) >> CAN_RWD_WDV_Pos; + return tmp; +} + +static inline void hri_can_set_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RWD_reg(const void *const hw, hri_can_rwd_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_reg(const void *const hw) +{ + return ((Can *)hw)->RWD.reg; +} + +static inline void hri_can_set_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_INIT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_INIT) >> CAN_CCCR_INIT_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_INIT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_INIT; + tmp |= value << CAN_CCCR_INIT_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CCE) >> CAN_CCCR_CCE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CCE; + tmp |= value << CAN_CCCR_CCE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_ASM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_ASM) >> CAN_CCCR_ASM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_ASM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_ASM; + tmp |= value << CAN_CCCR_ASM_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CSA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CSA) >> CAN_CCCR_CSA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CSA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CSA; + tmp |= value << CAN_CCCR_CSA_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CSR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CSR) >> CAN_CCCR_CSR_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CSR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CSR; + tmp |= value << CAN_CCCR_CSR_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_MON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_MON) >> CAN_CCCR_MON_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_MON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_MON; + tmp |= value << CAN_CCCR_MON_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_DAR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_DAR) >> CAN_CCCR_DAR_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_DAR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_DAR; + tmp |= value << CAN_CCCR_DAR_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_TEST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_TEST) >> CAN_CCCR_TEST_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_TEST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_TEST; + tmp |= value << CAN_CCCR_TEST_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_FDOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_FDOE) >> CAN_CCCR_FDOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_FDOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_FDOE; + tmp |= value << CAN_CCCR_FDOE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_BRSE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_BRSE) >> CAN_CCCR_BRSE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_BRSE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_BRSE; + tmp |= value << CAN_CCCR_BRSE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_PXHD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_PXHD) >> CAN_CCCR_PXHD_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_PXHD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_PXHD; + tmp |= value << CAN_CCCR_PXHD_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_EFBI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_EFBI) >> CAN_CCCR_EFBI_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_EFBI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_EFBI; + tmp |= value << CAN_CCCR_EFBI_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_TXP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_TXP) >> CAN_CCCR_TXP_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_TXP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_TXP; + tmp |= value << CAN_CCCR_TXP_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_NISO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_NISO) >> CAN_CCCR_NISO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_NISO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_NISO; + tmp |= value << CAN_CCCR_NISO_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_cccr_reg_t hri_can_get_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_CCCR_reg(const void *const hw, hri_can_cccr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_cccr_reg_t hri_can_read_CCCR_reg(const void *const hw) +{ + return ((Can *)hw)->CCCR.reg; +} + +static inline void hri_can_set_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG2(mask)) >> CAN_NBTP_NTSEG2_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NTSEG2_Msk; + tmp |= CAN_NBTP_NTSEG2(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG2_Msk) >> CAN_NBTP_NTSEG2_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG1(mask)) >> CAN_NBTP_NTSEG1_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NTSEG1_Msk; + tmp |= CAN_NBTP_NTSEG1(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG1_Msk) >> CAN_NBTP_NTSEG1_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NBRP(mask)) >> CAN_NBTP_NBRP_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NBRP_Msk; + tmp |= CAN_NBTP_NBRP(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NBRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NBRP_Msk) >> CAN_NBTP_NBRP_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NSJW(mask)) >> CAN_NBTP_NSJW_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NSJW_Msk; + tmp |= CAN_NBTP_NSJW(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NSJW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NSJW_Msk) >> CAN_NBTP_NSJW_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_reg(const void *const hw) +{ + return ((Can *)hw)->NBTP.reg; +} + +static inline void hri_can_set_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TSS(mask)) >> CAN_TSCC_TSS_Pos; + return tmp; +} + +static inline void hri_can_write_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TSCC.reg; + tmp &= ~CAN_TSCC_TSS_Msk; + tmp |= CAN_TSCC_TSS(data); + ((Can *)hw)->TSCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_TSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TSS_Msk) >> CAN_TSCC_TSS_Pos; + return tmp; +} + +static inline void hri_can_set_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TCP(mask)) >> CAN_TSCC_TCP_Pos; + return tmp; +} + +static inline void hri_can_write_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TSCC.reg; + tmp &= ~CAN_TSCC_TCP_Msk; + tmp |= CAN_TSCC_TCP(data); + ((Can *)hw)->TSCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_TCP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TCP_Msk) >> CAN_TSCC_TCP_Pos; + return tmp; +} + +static inline void hri_can_set_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TSCC_reg(const void *const hw, hri_can_tscc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_reg(const void *const hw) +{ + return ((Can *)hw)->TSCC.reg; +} + +static inline void hri_can_set_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TOCC_ETOC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_ETOC) >> CAN_TOCC_ETOC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TOCC_ETOC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_ETOC; + tmp |= value << CAN_TOCC_ETOC_Pos; + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOS(mask)) >> CAN_TOCC_TOS_Pos; + return tmp; +} + +static inline void hri_can_write_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_TOS_Msk; + tmp |= CAN_TOCC_TOS(data); + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOS_Msk) >> CAN_TOCC_TOS_Pos; + return tmp; +} + +static inline void hri_can_set_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOP(mask)) >> CAN_TOCC_TOP_Pos; + return tmp; +} + +static inline void hri_can_write_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_TOP_Msk; + tmp |= CAN_TOCC_TOP(data); + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOP_Msk) >> CAN_TOCC_TOP_Pos; + return tmp; +} + +static inline void hri_can_set_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TOCC_reg(const void *const hw, hri_can_tocc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_reg(const void *const hw) +{ + return ((Can *)hw)->TOCC.reg; +} + +static inline void hri_can_set_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg |= CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_get_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp = (tmp & CAN_TOCV_TOC(mask)) >> CAN_TOCV_TOC_Pos; + return tmp; +} + +static inline void hri_can_write_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCV.reg; + tmp &= ~CAN_TOCV_TOC_Msk; + tmp |= CAN_TOCV_TOC(data); + ((Can *)hw)->TOCV.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg &= ~CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg ^= CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_read_TOCV_TOC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp = (tmp & CAN_TOCV_TOC_Msk) >> CAN_TOCV_TOC_Pos; + return tmp; +} + +static inline void hri_can_set_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_get_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TOCV_reg(const void *const hw, hri_can_tocv_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_read_TOCV_reg(const void *const hw) +{ + return ((Can *)hw)->TOCV.reg; +} + +static inline void hri_can_set_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCF(mask)) >> CAN_TDCR_TDCF_Pos; + return tmp; +} + +static inline void hri_can_write_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TDCR.reg; + tmp &= ~CAN_TDCR_TDCF_Msk; + tmp |= CAN_TDCR_TDCF(data); + ((Can *)hw)->TDCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCF_Msk) >> CAN_TDCR_TDCF_Pos; + return tmp; +} + +static inline void hri_can_set_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCO(mask)) >> CAN_TDCR_TDCO_Pos; + return tmp; +} + +static inline void hri_can_write_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TDCR.reg; + tmp &= ~CAN_TDCR_TDCO_Msk; + tmp |= CAN_TDCR_TDCO(data); + ((Can *)hw)->TDCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCO_Msk) >> CAN_TDCR_TDCO_Pos; + return tmp; +} + +static inline void hri_can_set_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_reg(const void *const hw) +{ + return ((Can *)hw)->TDCR.reg; +} + +static inline void hri_can_set_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0N_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0N) >> CAN_IR_RF0N_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0N_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0N; + tmp |= value << CAN_IR_RF0N_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0W_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0W) >> CAN_IR_RF0W_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0W_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0W; + tmp |= value << CAN_IR_RF0W_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0F_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0F) >> CAN_IR_RF0F_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0F_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0F; + tmp |= value << CAN_IR_RF0F_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0L_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0L) >> CAN_IR_RF0L_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0L_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0L; + tmp |= value << CAN_IR_RF0L_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1N_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1N) >> CAN_IR_RF1N_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1N_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1N; + tmp |= value << CAN_IR_RF1N_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1W_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1W) >> CAN_IR_RF1W_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1W_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1W; + tmp |= value << CAN_IR_RF1W_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1F_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1F) >> CAN_IR_RF1F_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1F_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1F; + tmp |= value << CAN_IR_RF1F_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1L_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1L) >> CAN_IR_RF1L_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1L_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1L; + tmp |= value << CAN_IR_RF1L_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_HPM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_HPM) >> CAN_IR_HPM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_HPM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_HPM; + tmp |= value << CAN_IR_HPM_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TC) >> CAN_IR_TC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TC; + tmp |= value << CAN_IR_TC_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TCF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TCF) >> CAN_IR_TCF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TCF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TCF; + tmp |= value << CAN_IR_TCF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TFE) >> CAN_IR_TFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TFE; + tmp |= value << CAN_IR_TFE_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFN) >> CAN_IR_TEFN_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFN; + tmp |= value << CAN_IR_TEFN_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFW) >> CAN_IR_TEFW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFW; + tmp |= value << CAN_IR_TEFW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFF) >> CAN_IR_TEFF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFF; + tmp |= value << CAN_IR_TEFF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFL) >> CAN_IR_TEFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFL; + tmp |= value << CAN_IR_TEFL_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TSW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TSW) >> CAN_IR_TSW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TSW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TSW; + tmp |= value << CAN_IR_TSW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_MRAF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_MRAF) >> CAN_IR_MRAF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_MRAF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_MRAF; + tmp |= value << CAN_IR_MRAF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TOO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TOO) >> CAN_IR_TOO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TOO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TOO; + tmp |= value << CAN_IR_TOO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_DRX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_DRX) >> CAN_IR_DRX_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_DRX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_DRX; + tmp |= value << CAN_IR_DRX_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BEC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BEC) >> CAN_IR_BEC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BEC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BEC; + tmp |= value << CAN_IR_BEC_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BEU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BEU) >> CAN_IR_BEU_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BEU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BEU; + tmp |= value << CAN_IR_BEU_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_ELO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_ELO) >> CAN_IR_ELO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_ELO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_ELO; + tmp |= value << CAN_IR_ELO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_EP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_EP) >> CAN_IR_EP_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_EP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_EP; + tmp |= value << CAN_IR_EP_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_EW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_EW) >> CAN_IR_EW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_EW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_EW; + tmp |= value << CAN_IR_EW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BO) >> CAN_IR_BO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BO; + tmp |= value << CAN_IR_BO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_WDI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_WDI) >> CAN_IR_WDI_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_WDI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_WDI; + tmp |= value << CAN_IR_WDI_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_PEA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_PEA) >> CAN_IR_PEA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_PEA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_PEA; + tmp |= value << CAN_IR_PEA_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_PED_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_PED) >> CAN_IR_PED_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_PED_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_PED; + tmp |= value << CAN_IR_PED_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_ARA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_ARA) >> CAN_IR_ARA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_ARA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_ARA; + tmp |= value << CAN_IR_ARA_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ir_reg_t hri_can_get_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_IR_reg(const void *const hw, hri_can_ir_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ir_reg_t hri_can_read_IR_reg(const void *const hw) +{ + return ((Can *)hw)->IR.reg; +} + +static inline void hri_can_set_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0NE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0NE) >> CAN_IE_RF0NE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0NE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0NE; + tmp |= value << CAN_IE_RF0NE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0WE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0WE) >> CAN_IE_RF0WE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0WE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0WE; + tmp |= value << CAN_IE_RF0WE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0FE) >> CAN_IE_RF0FE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0FE; + tmp |= value << CAN_IE_RF0FE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0LE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0LE) >> CAN_IE_RF0LE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0LE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0LE; + tmp |= value << CAN_IE_RF0LE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1NE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1NE) >> CAN_IE_RF1NE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1NE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1NE; + tmp |= value << CAN_IE_RF1NE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1WE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1WE) >> CAN_IE_RF1WE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1WE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1WE; + tmp |= value << CAN_IE_RF1WE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1FE) >> CAN_IE_RF1FE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1FE; + tmp |= value << CAN_IE_RF1FE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1LE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1LE) >> CAN_IE_RF1LE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1LE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1LE; + tmp |= value << CAN_IE_RF1LE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_HPME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_HPME) >> CAN_IE_HPME_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_HPME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_HPME; + tmp |= value << CAN_IE_HPME_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TCE) >> CAN_IE_TCE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TCE; + tmp |= value << CAN_IE_TCE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TCFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TCFE) >> CAN_IE_TCFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TCFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TCFE; + tmp |= value << CAN_IE_TCFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TFEE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TFEE) >> CAN_IE_TFEE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TFEE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TFEE; + tmp |= value << CAN_IE_TFEE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFNE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFNE) >> CAN_IE_TEFNE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFNE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFNE; + tmp |= value << CAN_IE_TEFNE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFWE) >> CAN_IE_TEFWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFWE; + tmp |= value << CAN_IE_TEFWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFFE) >> CAN_IE_TEFFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFFE; + tmp |= value << CAN_IE_TEFFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFLE) >> CAN_IE_TEFLE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFLE; + tmp |= value << CAN_IE_TEFLE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TSWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TSWE) >> CAN_IE_TSWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TSWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TSWE; + tmp |= value << CAN_IE_TSWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_MRAFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_MRAFE) >> CAN_IE_MRAFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_MRAFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_MRAFE; + tmp |= value << CAN_IE_MRAFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TOOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TOOE) >> CAN_IE_TOOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TOOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TOOE; + tmp |= value << CAN_IE_TOOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_DRXE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_DRXE) >> CAN_IE_DRXE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_DRXE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_DRXE; + tmp |= value << CAN_IE_DRXE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BECE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BECE) >> CAN_IE_BECE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BECE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BECE; + tmp |= value << CAN_IE_BECE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BEUE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BEUE) >> CAN_IE_BEUE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BEUE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BEUE; + tmp |= value << CAN_IE_BEUE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_ELOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_ELOE) >> CAN_IE_ELOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_ELOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_ELOE; + tmp |= value << CAN_IE_ELOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_EPE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_EPE) >> CAN_IE_EPE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_EPE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_EPE; + tmp |= value << CAN_IE_EPE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_EWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_EWE) >> CAN_IE_EWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_EWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_EWE; + tmp |= value << CAN_IE_EWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BOE) >> CAN_IE_BOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BOE; + tmp |= value << CAN_IE_BOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_WDIE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_WDIE) >> CAN_IE_WDIE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_WDIE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_WDIE; + tmp |= value << CAN_IE_WDIE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_PEAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_PEAE) >> CAN_IE_PEAE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_PEAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_PEAE; + tmp |= value << CAN_IE_PEAE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_PEDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_PEDE) >> CAN_IE_PEDE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_PEDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_PEDE; + tmp |= value << CAN_IE_PEDE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_ARAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_ARAE) >> CAN_IE_ARAE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_ARAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_ARAE; + tmp |= value << CAN_IE_ARAE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ie_reg_t hri_can_get_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_IE_reg(const void *const hw, hri_can_ie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ie_reg_t hri_can_read_IE_reg(const void *const hw) +{ + return ((Can *)hw)->IE.reg; +} + +static inline void hri_can_set_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0NL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0NL) >> CAN_ILS_RF0NL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0NL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0NL; + tmp |= value << CAN_ILS_RF0NL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0WL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0WL) >> CAN_ILS_RF0WL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0WL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0WL; + tmp |= value << CAN_ILS_RF0WL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0FL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0FL) >> CAN_ILS_RF0FL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0FL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0FL; + tmp |= value << CAN_ILS_RF0FL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0LL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0LL) >> CAN_ILS_RF0LL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0LL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0LL; + tmp |= value << CAN_ILS_RF0LL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1NL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1NL) >> CAN_ILS_RF1NL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1NL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1NL; + tmp |= value << CAN_ILS_RF1NL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1WL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1WL) >> CAN_ILS_RF1WL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1WL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1WL; + tmp |= value << CAN_ILS_RF1WL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1FL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1FL) >> CAN_ILS_RF1FL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1FL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1FL; + tmp |= value << CAN_ILS_RF1FL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1LL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1LL) >> CAN_ILS_RF1LL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1LL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1LL; + tmp |= value << CAN_ILS_RF1LL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_HPML_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_HPML) >> CAN_ILS_HPML_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_HPML_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_HPML; + tmp |= value << CAN_ILS_HPML_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TCL) >> CAN_ILS_TCL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TCL; + tmp |= value << CAN_ILS_TCL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TCFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TCFL) >> CAN_ILS_TCFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TCFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TCFL; + tmp |= value << CAN_ILS_TCFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TFEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TFEL) >> CAN_ILS_TFEL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TFEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TFEL; + tmp |= value << CAN_ILS_TFEL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFNL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFNL) >> CAN_ILS_TEFNL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFNL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFNL; + tmp |= value << CAN_ILS_TEFNL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFWL) >> CAN_ILS_TEFWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFWL; + tmp |= value << CAN_ILS_TEFWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFFL) >> CAN_ILS_TEFFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFFL; + tmp |= value << CAN_ILS_TEFFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFLL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFLL) >> CAN_ILS_TEFLL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFLL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFLL; + tmp |= value << CAN_ILS_TEFLL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TSWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TSWL) >> CAN_ILS_TSWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TSWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TSWL; + tmp |= value << CAN_ILS_TSWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_MRAFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_MRAFL) >> CAN_ILS_MRAFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_MRAFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_MRAFL; + tmp |= value << CAN_ILS_MRAFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TOOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TOOL) >> CAN_ILS_TOOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TOOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TOOL; + tmp |= value << CAN_ILS_TOOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_DRXL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_DRXL) >> CAN_ILS_DRXL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_DRXL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_DRXL; + tmp |= value << CAN_ILS_DRXL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BECL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BECL) >> CAN_ILS_BECL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BECL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BECL; + tmp |= value << CAN_ILS_BECL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BEUL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BEUL) >> CAN_ILS_BEUL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BEUL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BEUL; + tmp |= value << CAN_ILS_BEUL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_ELOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_ELOL) >> CAN_ILS_ELOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_ELOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_ELOL; + tmp |= value << CAN_ILS_ELOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_EPL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_EPL) >> CAN_ILS_EPL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_EPL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_EPL; + tmp |= value << CAN_ILS_EPL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_EWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_EWL) >> CAN_ILS_EWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_EWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_EWL; + tmp |= value << CAN_ILS_EWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BOL) >> CAN_ILS_BOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BOL; + tmp |= value << CAN_ILS_BOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_WDIL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_WDIL) >> CAN_ILS_WDIL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_WDIL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_WDIL; + tmp |= value << CAN_ILS_WDIL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_PEAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_PEAL) >> CAN_ILS_PEAL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_PEAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_PEAL; + tmp |= value << CAN_ILS_PEAL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_PEDL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_PEDL) >> CAN_ILS_PEDL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_PEDL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_PEDL; + tmp |= value << CAN_ILS_PEDL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_ARAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_ARAL) >> CAN_ILS_ARAL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_ARAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_ARAL; + tmp |= value << CAN_ILS_ARAL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ils_reg_t hri_can_get_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_ILS_reg(const void *const hw, hri_can_ils_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ils_reg_t hri_can_read_ILS_reg(const void *const hw) +{ + return ((Can *)hw)->ILS.reg; +} + +static inline void hri_can_set_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILE_EINT0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp = (tmp & CAN_ILE_EINT0) >> CAN_ILE_EINT0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILE_EINT0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILE.reg; + tmp &= ~CAN_ILE_EINT0; + tmp |= value << CAN_ILE_EINT0_Pos; + ((Can *)hw)->ILE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILE_EINT1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp = (tmp & CAN_ILE_EINT1) >> CAN_ILE_EINT1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILE_EINT1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILE.reg; + tmp &= ~CAN_ILE_EINT1; + tmp |= value << CAN_ILE_EINT1_Pos; + ((Can *)hw)->ILE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ile_reg_t hri_can_get_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_ILE_reg(const void *const hw, hri_can_ile_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ile_reg_t hri_can_read_ILE_reg(const void *const hw) +{ + return ((Can *)hw)->ILE.reg; +} + +static inline void hri_can_set_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_GFC_RRFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_RRFE) >> CAN_GFC_RRFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_GFC_RRFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_RRFE; + tmp |= value << CAN_GFC_RRFE_Pos; + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_GFC_RRFS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_RRFS) >> CAN_GFC_RRFS_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_GFC_RRFS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_RRFS; + tmp |= value << CAN_GFC_RRFS_Pos; + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFE(mask)) >> CAN_GFC_ANFE_Pos; + return tmp; +} + +static inline void hri_can_write_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_ANFE_Msk; + tmp |= CAN_GFC_ANFE(data); + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFE_Msk) >> CAN_GFC_ANFE_Pos; + return tmp; +} + +static inline void hri_can_set_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFS(mask)) >> CAN_GFC_ANFS_Pos; + return tmp; +} + +static inline void hri_can_write_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_ANFS_Msk; + tmp |= CAN_GFC_ANFS(data); + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFS_Msk) >> CAN_GFC_ANFS_Pos; + return tmp; +} + +static inline void hri_can_set_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_GFC_reg(const void *const hw, hri_can_gfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_reg(const void *const hw) +{ + return ((Can *)hw)->GFC.reg; +} + +static inline void hri_can_set_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_FLSSA(mask)) >> CAN_SIDFC_FLSSA_Pos; + return tmp; +} + +static inline void hri_can_write_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= ~CAN_SIDFC_FLSSA_Msk; + tmp |= CAN_SIDFC_FLSSA(data); + ((Can *)hw)->SIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_FLSSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_FLSSA_Msk) >> CAN_SIDFC_FLSSA_Pos; + return tmp; +} + +static inline void hri_can_set_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_LSS(mask)) >> CAN_SIDFC_LSS_Pos; + return tmp; +} + +static inline void hri_can_write_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= ~CAN_SIDFC_LSS_Msk; + tmp |= CAN_SIDFC_LSS(data); + ((Can *)hw)->SIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_LSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_LSS_Msk) >> CAN_SIDFC_LSS_Pos; + return tmp; +} + +static inline void hri_can_set_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_reg(const void *const hw) +{ + return ((Can *)hw)->SIDFC.reg; +} + +static inline void hri_can_set_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_FLESA(mask)) >> CAN_XIDFC_FLESA_Pos; + return tmp; +} + +static inline void hri_can_write_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= ~CAN_XIDFC_FLESA_Msk; + tmp |= CAN_XIDFC_FLESA(data); + ((Can *)hw)->XIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_FLESA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_FLESA_Msk) >> CAN_XIDFC_FLESA_Pos; + return tmp; +} + +static inline void hri_can_set_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_LSE(mask)) >> CAN_XIDFC_LSE_Pos; + return tmp; +} + +static inline void hri_can_write_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= ~CAN_XIDFC_LSE_Msk; + tmp |= CAN_XIDFC_LSE(data); + ((Can *)hw)->XIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_LSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_LSE_Msk) >> CAN_XIDFC_LSE_Pos; + return tmp; +} + +static inline void hri_can_set_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_reg(const void *const hw) +{ + return ((Can *)hw)->XIDFC.reg; +} + +static inline void hri_can_set_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg |= CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_get_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp = (tmp & CAN_XIDAM_EIDM(mask)) >> CAN_XIDAM_EIDM_Pos; + return tmp; +} + +static inline void hri_can_write_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDAM.reg; + tmp &= ~CAN_XIDAM_EIDM_Msk; + tmp |= CAN_XIDAM_EIDM(data); + ((Can *)hw)->XIDAM.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg &= ~CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg ^= CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_read_XIDAM_EIDM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp = (tmp & CAN_XIDAM_EIDM_Msk) >> CAN_XIDAM_EIDM_Pos; + return tmp; +} + +static inline void hri_can_set_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_get_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_read_XIDAM_reg(const void *const hw) +{ + return ((Can *)hw)->XIDAM.reg; +} + +static inline void hri_can_set_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND0) >> CAN_NDAT1_ND0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND0; + tmp |= value << CAN_NDAT1_ND0_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND1) >> CAN_NDAT1_ND1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND1; + tmp |= value << CAN_NDAT1_ND1_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND2) >> CAN_NDAT1_ND2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND2; + tmp |= value << CAN_NDAT1_ND2_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND3) >> CAN_NDAT1_ND3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND3; + tmp |= value << CAN_NDAT1_ND3_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND4) >> CAN_NDAT1_ND4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND4; + tmp |= value << CAN_NDAT1_ND4_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND5) >> CAN_NDAT1_ND5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND5; + tmp |= value << CAN_NDAT1_ND5_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND6) >> CAN_NDAT1_ND6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND6; + tmp |= value << CAN_NDAT1_ND6_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND7) >> CAN_NDAT1_ND7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND7; + tmp |= value << CAN_NDAT1_ND7_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND8) >> CAN_NDAT1_ND8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND8; + tmp |= value << CAN_NDAT1_ND8_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND9) >> CAN_NDAT1_ND9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND9; + tmp |= value << CAN_NDAT1_ND9_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND10) >> CAN_NDAT1_ND10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND10; + tmp |= value << CAN_NDAT1_ND10_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND11) >> CAN_NDAT1_ND11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND11; + tmp |= value << CAN_NDAT1_ND11_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND12) >> CAN_NDAT1_ND12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND12; + tmp |= value << CAN_NDAT1_ND12_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND13) >> CAN_NDAT1_ND13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND13; + tmp |= value << CAN_NDAT1_ND13_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND14) >> CAN_NDAT1_ND14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND14; + tmp |= value << CAN_NDAT1_ND14_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND15) >> CAN_NDAT1_ND15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND15; + tmp |= value << CAN_NDAT1_ND15_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND16) >> CAN_NDAT1_ND16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND16; + tmp |= value << CAN_NDAT1_ND16_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND17) >> CAN_NDAT1_ND17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND17; + tmp |= value << CAN_NDAT1_ND17_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND18) >> CAN_NDAT1_ND18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND18; + tmp |= value << CAN_NDAT1_ND18_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND19) >> CAN_NDAT1_ND19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND19; + tmp |= value << CAN_NDAT1_ND19_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND20) >> CAN_NDAT1_ND20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND20; + tmp |= value << CAN_NDAT1_ND20_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND21) >> CAN_NDAT1_ND21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND21; + tmp |= value << CAN_NDAT1_ND21_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND22) >> CAN_NDAT1_ND22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND22; + tmp |= value << CAN_NDAT1_ND22_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND23) >> CAN_NDAT1_ND23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND23; + tmp |= value << CAN_NDAT1_ND23_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND24) >> CAN_NDAT1_ND24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND24; + tmp |= value << CAN_NDAT1_ND24_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND25) >> CAN_NDAT1_ND25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND25; + tmp |= value << CAN_NDAT1_ND25_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND26) >> CAN_NDAT1_ND26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND26; + tmp |= value << CAN_NDAT1_ND26_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND27) >> CAN_NDAT1_ND27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND27; + tmp |= value << CAN_NDAT1_ND27_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND28) >> CAN_NDAT1_ND28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND28; + tmp |= value << CAN_NDAT1_ND28_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND29) >> CAN_NDAT1_ND29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND29; + tmp |= value << CAN_NDAT1_ND29_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND30) >> CAN_NDAT1_ND30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND30; + tmp |= value << CAN_NDAT1_ND30_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND31) >> CAN_NDAT1_ND31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND31; + tmp |= value << CAN_NDAT1_ND31_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat1_reg_t hri_can_get_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat1_reg_t hri_can_read_NDAT1_reg(const void *const hw) +{ + return ((Can *)hw)->NDAT1.reg; +} + +static inline void hri_can_set_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND32_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND32) >> CAN_NDAT2_ND32_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND32_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND32; + tmp |= value << CAN_NDAT2_ND32_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND33_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND33) >> CAN_NDAT2_ND33_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND33_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND33; + tmp |= value << CAN_NDAT2_ND33_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND34_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND34) >> CAN_NDAT2_ND34_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND34_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND34; + tmp |= value << CAN_NDAT2_ND34_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND35_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND35) >> CAN_NDAT2_ND35_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND35_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND35; + tmp |= value << CAN_NDAT2_ND35_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND36_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND36) >> CAN_NDAT2_ND36_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND36_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND36; + tmp |= value << CAN_NDAT2_ND36_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND37_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND37) >> CAN_NDAT2_ND37_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND37_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND37; + tmp |= value << CAN_NDAT2_ND37_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND38_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND38) >> CAN_NDAT2_ND38_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND38_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND38; + tmp |= value << CAN_NDAT2_ND38_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND39_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND39) >> CAN_NDAT2_ND39_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND39_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND39; + tmp |= value << CAN_NDAT2_ND39_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND40_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND40) >> CAN_NDAT2_ND40_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND40_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND40; + tmp |= value << CAN_NDAT2_ND40_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND41_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND41) >> CAN_NDAT2_ND41_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND41_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND41; + tmp |= value << CAN_NDAT2_ND41_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND42_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND42) >> CAN_NDAT2_ND42_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND42_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND42; + tmp |= value << CAN_NDAT2_ND42_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND43_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND43) >> CAN_NDAT2_ND43_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND43_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND43; + tmp |= value << CAN_NDAT2_ND43_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND44_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND44) >> CAN_NDAT2_ND44_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND44_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND44; + tmp |= value << CAN_NDAT2_ND44_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND45_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND45) >> CAN_NDAT2_ND45_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND45_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND45; + tmp |= value << CAN_NDAT2_ND45_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND46_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND46) >> CAN_NDAT2_ND46_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND46_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND46; + tmp |= value << CAN_NDAT2_ND46_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND47_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND47) >> CAN_NDAT2_ND47_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND47_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND47; + tmp |= value << CAN_NDAT2_ND47_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND48_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND48) >> CAN_NDAT2_ND48_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND48_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND48; + tmp |= value << CAN_NDAT2_ND48_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND49_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND49) >> CAN_NDAT2_ND49_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND49_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND49; + tmp |= value << CAN_NDAT2_ND49_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND50_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND50) >> CAN_NDAT2_ND50_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND50_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND50; + tmp |= value << CAN_NDAT2_ND50_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND51_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND51) >> CAN_NDAT2_ND51_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND51_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND51; + tmp |= value << CAN_NDAT2_ND51_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND52_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND52) >> CAN_NDAT2_ND52_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND52_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND52; + tmp |= value << CAN_NDAT2_ND52_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND53_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND53) >> CAN_NDAT2_ND53_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND53_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND53; + tmp |= value << CAN_NDAT2_ND53_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND54_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND54) >> CAN_NDAT2_ND54_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND54_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND54; + tmp |= value << CAN_NDAT2_ND54_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND55_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND55) >> CAN_NDAT2_ND55_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND55_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND55; + tmp |= value << CAN_NDAT2_ND55_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND56_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND56) >> CAN_NDAT2_ND56_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND56_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND56; + tmp |= value << CAN_NDAT2_ND56_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND57_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND57) >> CAN_NDAT2_ND57_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND57_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND57; + tmp |= value << CAN_NDAT2_ND57_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND58_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND58) >> CAN_NDAT2_ND58_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND58_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND58; + tmp |= value << CAN_NDAT2_ND58_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND59_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND59) >> CAN_NDAT2_ND59_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND59_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND59; + tmp |= value << CAN_NDAT2_ND59_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND60_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND60) >> CAN_NDAT2_ND60_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND60_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND60; + tmp |= value << CAN_NDAT2_ND60_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND61_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND61) >> CAN_NDAT2_ND61_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND61_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND61; + tmp |= value << CAN_NDAT2_ND61_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND62_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND62) >> CAN_NDAT2_ND62_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND62_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND62; + tmp |= value << CAN_NDAT2_ND62_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND63_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND63) >> CAN_NDAT2_ND63_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND63_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND63; + tmp |= value << CAN_NDAT2_ND63_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat2_reg_t hri_can_get_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat2_reg_t hri_can_read_NDAT2_reg(const void *const hw) +{ + return ((Can *)hw)->NDAT2.reg; +} + +static inline void hri_can_set_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_RXF0C_F0OM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0OM) >> CAN_RXF0C_F0OM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_RXF0C_F0OM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0OM; + tmp |= value << CAN_RXF0C_F0OM_Pos; + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0SA(mask)) >> CAN_RXF0C_F0SA_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0SA_Msk; + tmp |= CAN_RXF0C_F0SA(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0SA_Msk) >> CAN_RXF0C_F0SA_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0S(mask)) >> CAN_RXF0C_F0S_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0S_Msk; + tmp |= CAN_RXF0C_F0S(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0S_Msk) >> CAN_RXF0C_F0S_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0WM(mask)) >> CAN_RXF0C_F0WM_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0WM_Msk; + tmp |= CAN_RXF0C_F0WM(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0WM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0WM_Msk) >> CAN_RXF0C_F0WM_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0C.reg; +} + +static inline void hri_can_set_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg |= CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp = (tmp & CAN_RXF0A_F0AI(mask)) >> CAN_RXF0A_F0AI_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0A.reg; + tmp &= ~CAN_RXF0A_F0AI_Msk; + tmp |= CAN_RXF0A_F0AI(data); + ((Can *)hw)->RXF0A.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg &= ~CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg ^= CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_F0AI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp = (tmp & CAN_RXF0A_F0AI_Msk) >> CAN_RXF0A_F0AI_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0A.reg; +} + +static inline void hri_can_set_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg |= CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_get_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp = (tmp & CAN_RXBC_RBSA(mask)) >> CAN_RXBC_RBSA_Pos; + return tmp; +} + +static inline void hri_can_write_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXBC.reg; + tmp &= ~CAN_RXBC_RBSA_Msk; + tmp |= CAN_RXBC_RBSA(data); + ((Can *)hw)->RXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg &= ~CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg ^= CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_read_RXBC_RBSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp = (tmp & CAN_RXBC_RBSA_Msk) >> CAN_RXBC_RBSA_Pos; + return tmp; +} + +static inline void hri_can_set_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_get_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_read_RXBC_reg(const void *const hw) +{ + return ((Can *)hw)->RXBC.reg; +} + +static inline void hri_can_set_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_RXF1C_F1OM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1OM) >> CAN_RXF1C_F1OM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_RXF1C_F1OM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1OM; + tmp |= value << CAN_RXF1C_F1OM_Pos; + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1SA(mask)) >> CAN_RXF1C_F1SA_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1SA_Msk; + tmp |= CAN_RXF1C_F1SA(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1SA_Msk) >> CAN_RXF1C_F1SA_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1S(mask)) >> CAN_RXF1C_F1S_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1S_Msk; + tmp |= CAN_RXF1C_F1S(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1S_Msk) >> CAN_RXF1C_F1S_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1WM(mask)) >> CAN_RXF1C_F1WM_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1WM_Msk; + tmp |= CAN_RXF1C_F1WM(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1WM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1WM_Msk) >> CAN_RXF1C_F1WM_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1C.reg; +} + +static inline void hri_can_set_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg |= CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp = (tmp & CAN_RXF1A_F1AI(mask)) >> CAN_RXF1A_F1AI_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1A.reg; + tmp &= ~CAN_RXF1A_F1AI_Msk; + tmp |= CAN_RXF1A_F1AI(data); + ((Can *)hw)->RXF1A.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg &= ~CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg ^= CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_F1AI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp = (tmp & CAN_RXF1A_F1AI_Msk) >> CAN_RXF1A_F1AI_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1A.reg; +} + +static inline void hri_can_set_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F0DS(mask)) >> CAN_RXESC_F0DS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_F0DS_Msk; + tmp |= CAN_RXESC_F0DS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F0DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F0DS_Msk) >> CAN_RXESC_F0DS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F1DS(mask)) >> CAN_RXESC_F1DS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_F1DS_Msk; + tmp |= CAN_RXESC_F1DS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F1DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F1DS_Msk) >> CAN_RXESC_F1DS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_RBDS(mask)) >> CAN_RXESC_RBDS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_RBDS_Msk; + tmp |= CAN_RXESC_RBDS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_RBDS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_RBDS_Msk) >> CAN_RXESC_RBDS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_reg(const void *const hw) +{ + return ((Can *)hw)->RXESC.reg; +} + +static inline void hri_can_set_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBC_TFQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQM) >> CAN_TXBC_TFQM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBC_TFQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TFQM; + tmp |= value << CAN_TXBC_TFQM_Pos; + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TBSA(mask)) >> CAN_TXBC_TBSA_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TBSA_Msk; + tmp |= CAN_TXBC_TBSA(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_TBSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TBSA_Msk) >> CAN_TXBC_TBSA_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_NDTB(mask)) >> CAN_TXBC_NDTB_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_NDTB_Msk; + tmp |= CAN_TXBC_NDTB(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_NDTB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_NDTB_Msk) >> CAN_TXBC_NDTB_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQS(mask)) >> CAN_TXBC_TFQS_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TFQS_Msk; + tmp |= CAN_TXBC_TFQS(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_TFQS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQS_Msk) >> CAN_TXBC_TFQS_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBC_reg(const void *const hw, hri_can_txbc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_reg(const void *const hw) +{ + return ((Can *)hw)->TXBC.reg; +} + +static inline void hri_can_set_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg |= CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_get_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp = (tmp & CAN_TXESC_TBDS(mask)) >> CAN_TXESC_TBDS_Pos; + return tmp; +} + +static inline void hri_can_write_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXESC.reg; + tmp &= ~CAN_TXESC_TBDS_Msk; + tmp |= CAN_TXESC_TBDS(data); + ((Can *)hw)->TXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg &= ~CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg ^= CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_read_TXESC_TBDS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp = (tmp & CAN_TXESC_TBDS_Msk) >> CAN_TXESC_TBDS_Pos; + return tmp; +} + +static inline void hri_can_set_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_get_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXESC_reg(const void *const hw, hri_can_txesc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_read_TXESC_reg(const void *const hw) +{ + return ((Can *)hw)->TXESC.reg; +} + +static inline void hri_can_set_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR0) >> CAN_TXBAR_AR0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR0; + tmp |= value << CAN_TXBAR_AR0_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR1) >> CAN_TXBAR_AR1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR1; + tmp |= value << CAN_TXBAR_AR1_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR2) >> CAN_TXBAR_AR2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR2; + tmp |= value << CAN_TXBAR_AR2_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR3) >> CAN_TXBAR_AR3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR3; + tmp |= value << CAN_TXBAR_AR3_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR4) >> CAN_TXBAR_AR4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR4; + tmp |= value << CAN_TXBAR_AR4_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR5) >> CAN_TXBAR_AR5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR5; + tmp |= value << CAN_TXBAR_AR5_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR6) >> CAN_TXBAR_AR6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR6; + tmp |= value << CAN_TXBAR_AR6_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR7) >> CAN_TXBAR_AR7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR7; + tmp |= value << CAN_TXBAR_AR7_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR8) >> CAN_TXBAR_AR8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR8; + tmp |= value << CAN_TXBAR_AR8_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR9) >> CAN_TXBAR_AR9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR9; + tmp |= value << CAN_TXBAR_AR9_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR10) >> CAN_TXBAR_AR10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR10; + tmp |= value << CAN_TXBAR_AR10_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR11) >> CAN_TXBAR_AR11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR11; + tmp |= value << CAN_TXBAR_AR11_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR12) >> CAN_TXBAR_AR12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR12; + tmp |= value << CAN_TXBAR_AR12_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR13) >> CAN_TXBAR_AR13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR13; + tmp |= value << CAN_TXBAR_AR13_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR14) >> CAN_TXBAR_AR14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR14; + tmp |= value << CAN_TXBAR_AR14_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR15) >> CAN_TXBAR_AR15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR15; + tmp |= value << CAN_TXBAR_AR15_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR16) >> CAN_TXBAR_AR16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR16; + tmp |= value << CAN_TXBAR_AR16_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR17) >> CAN_TXBAR_AR17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR17; + tmp |= value << CAN_TXBAR_AR17_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR18) >> CAN_TXBAR_AR18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR18; + tmp |= value << CAN_TXBAR_AR18_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR19) >> CAN_TXBAR_AR19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR19; + tmp |= value << CAN_TXBAR_AR19_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR20) >> CAN_TXBAR_AR20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR20; + tmp |= value << CAN_TXBAR_AR20_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR21) >> CAN_TXBAR_AR21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR21; + tmp |= value << CAN_TXBAR_AR21_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR22) >> CAN_TXBAR_AR22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR22; + tmp |= value << CAN_TXBAR_AR22_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR23) >> CAN_TXBAR_AR23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR23; + tmp |= value << CAN_TXBAR_AR23_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR24) >> CAN_TXBAR_AR24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR24; + tmp |= value << CAN_TXBAR_AR24_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR25) >> CAN_TXBAR_AR25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR25; + tmp |= value << CAN_TXBAR_AR25_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR26) >> CAN_TXBAR_AR26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR26; + tmp |= value << CAN_TXBAR_AR26_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR27) >> CAN_TXBAR_AR27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR27; + tmp |= value << CAN_TXBAR_AR27_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR28) >> CAN_TXBAR_AR28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR28; + tmp |= value << CAN_TXBAR_AR28_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR29) >> CAN_TXBAR_AR29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR29; + tmp |= value << CAN_TXBAR_AR29_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR30) >> CAN_TXBAR_AR30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR30; + tmp |= value << CAN_TXBAR_AR30_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR31) >> CAN_TXBAR_AR31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR31; + tmp |= value << CAN_TXBAR_AR31_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbar_reg_t hri_can_get_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbar_reg_t hri_can_read_TXBAR_reg(const void *const hw) +{ + return ((Can *)hw)->TXBAR.reg; +} + +static inline void hri_can_set_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR0) >> CAN_TXBCR_CR0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR0; + tmp |= value << CAN_TXBCR_CR0_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR1) >> CAN_TXBCR_CR1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR1; + tmp |= value << CAN_TXBCR_CR1_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR2) >> CAN_TXBCR_CR2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR2; + tmp |= value << CAN_TXBCR_CR2_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR3) >> CAN_TXBCR_CR3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR3; + tmp |= value << CAN_TXBCR_CR3_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR4) >> CAN_TXBCR_CR4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR4; + tmp |= value << CAN_TXBCR_CR4_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR5) >> CAN_TXBCR_CR5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR5; + tmp |= value << CAN_TXBCR_CR5_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR6) >> CAN_TXBCR_CR6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR6; + tmp |= value << CAN_TXBCR_CR6_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR7) >> CAN_TXBCR_CR7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR7; + tmp |= value << CAN_TXBCR_CR7_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR8) >> CAN_TXBCR_CR8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR8; + tmp |= value << CAN_TXBCR_CR8_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR9) >> CAN_TXBCR_CR9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR9; + tmp |= value << CAN_TXBCR_CR9_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR10) >> CAN_TXBCR_CR10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR10; + tmp |= value << CAN_TXBCR_CR10_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR11) >> CAN_TXBCR_CR11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR11; + tmp |= value << CAN_TXBCR_CR11_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR12) >> CAN_TXBCR_CR12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR12; + tmp |= value << CAN_TXBCR_CR12_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR13) >> CAN_TXBCR_CR13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR13; + tmp |= value << CAN_TXBCR_CR13_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR14) >> CAN_TXBCR_CR14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR14; + tmp |= value << CAN_TXBCR_CR14_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR15) >> CAN_TXBCR_CR15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR15; + tmp |= value << CAN_TXBCR_CR15_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR16) >> CAN_TXBCR_CR16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR16; + tmp |= value << CAN_TXBCR_CR16_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR17) >> CAN_TXBCR_CR17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR17; + tmp |= value << CAN_TXBCR_CR17_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR18) >> CAN_TXBCR_CR18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR18; + tmp |= value << CAN_TXBCR_CR18_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR19) >> CAN_TXBCR_CR19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR19; + tmp |= value << CAN_TXBCR_CR19_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR20) >> CAN_TXBCR_CR20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR20; + tmp |= value << CAN_TXBCR_CR20_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR21) >> CAN_TXBCR_CR21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR21; + tmp |= value << CAN_TXBCR_CR21_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR22) >> CAN_TXBCR_CR22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR22; + tmp |= value << CAN_TXBCR_CR22_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR23) >> CAN_TXBCR_CR23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR23; + tmp |= value << CAN_TXBCR_CR23_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR24) >> CAN_TXBCR_CR24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR24; + tmp |= value << CAN_TXBCR_CR24_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR25) >> CAN_TXBCR_CR25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR25; + tmp |= value << CAN_TXBCR_CR25_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR26) >> CAN_TXBCR_CR26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR26; + tmp |= value << CAN_TXBCR_CR26_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR27) >> CAN_TXBCR_CR27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR27; + tmp |= value << CAN_TXBCR_CR27_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR28) >> CAN_TXBCR_CR28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR28; + tmp |= value << CAN_TXBCR_CR28_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR29) >> CAN_TXBCR_CR29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR29; + tmp |= value << CAN_TXBCR_CR29_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR30) >> CAN_TXBCR_CR30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR30; + tmp |= value << CAN_TXBCR_CR30_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR31) >> CAN_TXBCR_CR31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR31; + tmp |= value << CAN_TXBCR_CR31_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcr_reg_t hri_can_get_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcr_reg_t hri_can_read_TXBCR_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCR.reg; +} + +static inline void hri_can_set_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE0) >> CAN_TXBTIE_TIE0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE0; + tmp |= value << CAN_TXBTIE_TIE0_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE1) >> CAN_TXBTIE_TIE1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE1; + tmp |= value << CAN_TXBTIE_TIE1_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE2) >> CAN_TXBTIE_TIE2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE2; + tmp |= value << CAN_TXBTIE_TIE2_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE3) >> CAN_TXBTIE_TIE3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE3; + tmp |= value << CAN_TXBTIE_TIE3_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE4) >> CAN_TXBTIE_TIE4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE4; + tmp |= value << CAN_TXBTIE_TIE4_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE5) >> CAN_TXBTIE_TIE5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE5; + tmp |= value << CAN_TXBTIE_TIE5_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE6) >> CAN_TXBTIE_TIE6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE6; + tmp |= value << CAN_TXBTIE_TIE6_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE7) >> CAN_TXBTIE_TIE7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE7; + tmp |= value << CAN_TXBTIE_TIE7_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE8) >> CAN_TXBTIE_TIE8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE8; + tmp |= value << CAN_TXBTIE_TIE8_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE9) >> CAN_TXBTIE_TIE9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE9; + tmp |= value << CAN_TXBTIE_TIE9_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE10) >> CAN_TXBTIE_TIE10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE10; + tmp |= value << CAN_TXBTIE_TIE10_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE11) >> CAN_TXBTIE_TIE11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE11; + tmp |= value << CAN_TXBTIE_TIE11_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE12) >> CAN_TXBTIE_TIE12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE12; + tmp |= value << CAN_TXBTIE_TIE12_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE13) >> CAN_TXBTIE_TIE13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE13; + tmp |= value << CAN_TXBTIE_TIE13_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE14) >> CAN_TXBTIE_TIE14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE14; + tmp |= value << CAN_TXBTIE_TIE14_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE15) >> CAN_TXBTIE_TIE15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE15; + tmp |= value << CAN_TXBTIE_TIE15_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE16) >> CAN_TXBTIE_TIE16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE16; + tmp |= value << CAN_TXBTIE_TIE16_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE17) >> CAN_TXBTIE_TIE17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE17; + tmp |= value << CAN_TXBTIE_TIE17_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE18) >> CAN_TXBTIE_TIE18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE18; + tmp |= value << CAN_TXBTIE_TIE18_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE19) >> CAN_TXBTIE_TIE19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE19; + tmp |= value << CAN_TXBTIE_TIE19_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE20) >> CAN_TXBTIE_TIE20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE20; + tmp |= value << CAN_TXBTIE_TIE20_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE21) >> CAN_TXBTIE_TIE21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE21; + tmp |= value << CAN_TXBTIE_TIE21_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE22) >> CAN_TXBTIE_TIE22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE22; + tmp |= value << CAN_TXBTIE_TIE22_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE23) >> CAN_TXBTIE_TIE23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE23; + tmp |= value << CAN_TXBTIE_TIE23_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE24) >> CAN_TXBTIE_TIE24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE24; + tmp |= value << CAN_TXBTIE_TIE24_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE25) >> CAN_TXBTIE_TIE25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE25; + tmp |= value << CAN_TXBTIE_TIE25_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE26) >> CAN_TXBTIE_TIE26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE26; + tmp |= value << CAN_TXBTIE_TIE26_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE27) >> CAN_TXBTIE_TIE27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE27; + tmp |= value << CAN_TXBTIE_TIE27_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE28) >> CAN_TXBTIE_TIE28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE28; + tmp |= value << CAN_TXBTIE_TIE28_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE29) >> CAN_TXBTIE_TIE29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE29; + tmp |= value << CAN_TXBTIE_TIE29_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE30) >> CAN_TXBTIE_TIE30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE30; + tmp |= value << CAN_TXBTIE_TIE30_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE31) >> CAN_TXBTIE_TIE31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE31; + tmp |= value << CAN_TXBTIE_TIE31_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbtie_reg_t hri_can_get_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbtie_reg_t hri_can_read_TXBTIE_reg(const void *const hw) +{ + return ((Can *)hw)->TXBTIE.reg; +} + +static inline void hri_can_set_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE0) >> CAN_TXBCIE_CFIE0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE0; + tmp |= value << CAN_TXBCIE_CFIE0_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE1) >> CAN_TXBCIE_CFIE1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE1; + tmp |= value << CAN_TXBCIE_CFIE1_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE2) >> CAN_TXBCIE_CFIE2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE2; + tmp |= value << CAN_TXBCIE_CFIE2_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE3) >> CAN_TXBCIE_CFIE3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE3; + tmp |= value << CAN_TXBCIE_CFIE3_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE4) >> CAN_TXBCIE_CFIE4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE4; + tmp |= value << CAN_TXBCIE_CFIE4_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE5) >> CAN_TXBCIE_CFIE5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE5; + tmp |= value << CAN_TXBCIE_CFIE5_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE6) >> CAN_TXBCIE_CFIE6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE6; + tmp |= value << CAN_TXBCIE_CFIE6_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE7) >> CAN_TXBCIE_CFIE7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE7; + tmp |= value << CAN_TXBCIE_CFIE7_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE8) >> CAN_TXBCIE_CFIE8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE8; + tmp |= value << CAN_TXBCIE_CFIE8_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE9) >> CAN_TXBCIE_CFIE9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE9; + tmp |= value << CAN_TXBCIE_CFIE9_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE10) >> CAN_TXBCIE_CFIE10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE10; + tmp |= value << CAN_TXBCIE_CFIE10_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE11) >> CAN_TXBCIE_CFIE11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE11; + tmp |= value << CAN_TXBCIE_CFIE11_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE12) >> CAN_TXBCIE_CFIE12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE12; + tmp |= value << CAN_TXBCIE_CFIE12_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE13) >> CAN_TXBCIE_CFIE13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE13; + tmp |= value << CAN_TXBCIE_CFIE13_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE14) >> CAN_TXBCIE_CFIE14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE14; + tmp |= value << CAN_TXBCIE_CFIE14_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE15) >> CAN_TXBCIE_CFIE15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE15; + tmp |= value << CAN_TXBCIE_CFIE15_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE16) >> CAN_TXBCIE_CFIE16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE16; + tmp |= value << CAN_TXBCIE_CFIE16_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE17) >> CAN_TXBCIE_CFIE17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE17; + tmp |= value << CAN_TXBCIE_CFIE17_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE18) >> CAN_TXBCIE_CFIE18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE18; + tmp |= value << CAN_TXBCIE_CFIE18_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE19) >> CAN_TXBCIE_CFIE19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE19; + tmp |= value << CAN_TXBCIE_CFIE19_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE20) >> CAN_TXBCIE_CFIE20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE20; + tmp |= value << CAN_TXBCIE_CFIE20_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE21) >> CAN_TXBCIE_CFIE21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE21; + tmp |= value << CAN_TXBCIE_CFIE21_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE22) >> CAN_TXBCIE_CFIE22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE22; + tmp |= value << CAN_TXBCIE_CFIE22_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE23) >> CAN_TXBCIE_CFIE23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE23; + tmp |= value << CAN_TXBCIE_CFIE23_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE24) >> CAN_TXBCIE_CFIE24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE24; + tmp |= value << CAN_TXBCIE_CFIE24_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE25) >> CAN_TXBCIE_CFIE25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE25; + tmp |= value << CAN_TXBCIE_CFIE25_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE26) >> CAN_TXBCIE_CFIE26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE26; + tmp |= value << CAN_TXBCIE_CFIE26_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE27) >> CAN_TXBCIE_CFIE27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE27; + tmp |= value << CAN_TXBCIE_CFIE27_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE28) >> CAN_TXBCIE_CFIE28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE28; + tmp |= value << CAN_TXBCIE_CFIE28_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE29) >> CAN_TXBCIE_CFIE29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE29; + tmp |= value << CAN_TXBCIE_CFIE29_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE30) >> CAN_TXBCIE_CFIE30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE30; + tmp |= value << CAN_TXBCIE_CFIE30_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE31) >> CAN_TXBCIE_CFIE31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE31; + tmp |= value << CAN_TXBCIE_CFIE31_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcie_reg_t hri_can_get_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcie_reg_t hri_can_read_TXBCIE_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCIE.reg; +} + +static inline void hri_can_set_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFSA(mask)) >> CAN_TXEFC_EFSA_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFSA_Msk; + tmp |= CAN_TXEFC_EFSA(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFSA_Msk) >> CAN_TXEFC_EFSA_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFS(mask)) >> CAN_TXEFC_EFS_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFS_Msk; + tmp |= CAN_TXEFC_EFS(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFS_Msk) >> CAN_TXEFC_EFS_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFWM(mask)) >> CAN_TXEFC_EFWM_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFWM_Msk; + tmp |= CAN_TXEFC_EFWM(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFWM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFWM_Msk) >> CAN_TXEFC_EFWM_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFC.reg; +} + +static inline void hri_can_set_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg |= CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_get_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp = (tmp & CAN_TXEFA_EFAI(mask)) >> CAN_TXEFA_EFAI_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFA.reg; + tmp &= ~CAN_TXEFA_EFAI_Msk; + tmp |= CAN_TXEFA_EFAI(data); + ((Can *)hw)->TXEFA.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg &= ~CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg ^= CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_read_TXEFA_EFAI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp = (tmp & CAN_TXEFA_EFAI_Msk) >> CAN_TXEFA_EFAI_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_get_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_read_TXEFA_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFA.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CAN_E54_H_INCLUDED */ +#endif /* _SAME54_CAN_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ccl_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ccl_e54.h new file mode 100644 index 0000000..c5c4867 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ccl_e54.h @@ -0,0 +1,776 @@ +/** + * \file + * + * \brief SAM CCL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_CCL_COMPONENT_ +#ifndef _HRI_CCL_E54_H_INCLUDED_ +#define _HRI_CCL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CCL_CRITICAL_SECTIONS) +#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CCL_CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ccl_lutctrl_reg_t; +typedef uint8_t hri_ccl_ctrl_reg_t; +typedef uint8_t hri_ccl_seqctrl_reg_t; + +static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_ENABLE; + tmp |= value << CCL_CTRL_ENABLE_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_RUNSTDBY; + tmp |= value << CCL_CTRL_RUNSTDBY_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw) +{ + return ((Ccl *)hw)->CTRL.reg; +} + +static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= ~CCL_SEQCTRL_SEQSEL_Msk; + tmp |= CCL_SEQCTRL_SEQSEL(data); + ((Ccl *)hw)->SEQCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->SEQCTRL[index].reg; +} + +static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_ENABLE; + tmp |= value << CCL_LUTCTRL_ENABLE_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_EDGESEL; + tmp |= value << CCL_LUTCTRL_EDGESEL_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INVEI; + tmp |= value << CCL_LUTCTRL_INVEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEI; + tmp |= value << CCL_LUTCTRL_LUTEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEO; + tmp |= value << CCL_LUTCTRL_LUTEO_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_FILTSEL_Msk; + tmp |= CCL_LUTCTRL_FILTSEL(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL0_Msk; + tmp |= CCL_LUTCTRL_INSEL0(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL1_Msk; + tmp |= CCL_LUTCTRL_INSEL1(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL2_Msk; + tmp |= CCL_LUTCTRL_INSEL2(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_TRUTH_Msk; + tmp |= CCL_LUTCTRL_TRUTH(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->LUTCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CCL_E54_H_INCLUDED */ +#endif /* _SAME54_CCL_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_cmcc_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_cmcc_e54.h new file mode 100644 index 0000000..c973d35 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_cmcc_e54.h @@ -0,0 +1,361 @@ +/** + * \file + * + * \brief SAM CMCC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_CMCC_COMPONENT_ +#ifndef _HRI_CMCC_E54_H_INCLUDED_ +#define _HRI_CMCC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CMCC_CRITICAL_SECTIONS) +#define CMCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CMCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CMCC_CRITICAL_SECTION_ENTER() +#define CMCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_cmcc_cfg_reg_t; +typedef uint32_t hri_cmcc_ctrl_reg_t; +typedef uint32_t hri_cmcc_lckway_reg_t; +typedef uint32_t hri_cmcc_maint0_reg_t; +typedef uint32_t hri_cmcc_maint1_reg_t; +typedef uint32_t hri_cmcc_mcfg_reg_t; +typedef uint32_t hri_cmcc_mctrl_reg_t; +typedef uint32_t hri_cmcc_men_reg_t; +typedef uint32_t hri_cmcc_msr_reg_t; +typedef uint32_t hri_cmcc_sr_reg_t; +typedef uint32_t hri_cmcc_type_reg_t; + +static inline bool hri_cmcc_get_TYPE_GCLK_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos; +} + +static inline bool hri_cmcc_get_TYPE_RRP_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos; +} + +static inline bool hri_cmcc_get_TYPE_LCKDOWN_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_WAYNUM_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_WAYNUM_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CSIZE_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CLSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CLSIZE_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_reg(const void *const hw, hri_cmcc_type_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->TYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_reg(const void *const hw) +{ + return ((Cmcc *)hw)->TYPE.reg; +} + +static inline bool hri_cmcc_get_SR_CSTS_bit(const void *const hw) +{ + return (((Cmcc *)hw)->SR.reg & CMCC_SR_CSTS) >> CMCC_SR_CSTS_Pos; +} + +static inline hri_cmcc_sr_reg_t hri_cmcc_get_SR_reg(const void *const hw, hri_cmcc_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->SR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_sr_reg_t hri_cmcc_read_SR_reg(const void *const hw) +{ + return ((Cmcc *)hw)->SR.reg; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_EVENT_CNT_bf(const void *const hw, hri_cmcc_msr_reg_t mask) +{ + return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT(mask)) >> CMCC_MSR_EVENT_CNT_Pos; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_EVENT_CNT_bf(const void *const hw) +{ + return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT_Msk) >> CMCC_MSR_EVENT_CNT_Pos; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_reg(const void *const hw, hri_cmcc_msr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MSR.reg; +} + +static inline void hri_cmcc_set_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_cfg_reg_t hri_cmcc_get_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_cfg_reg_t hri_cmcc_read_CFG_reg(const void *const hw) +{ + return ((Cmcc *)hw)->CFG.reg; +} + +static inline void hri_cmcc_set_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_lckway_reg_t hri_cmcc_get_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->LCKWAY.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_lckway_reg_t hri_cmcc_read_LCKWAY_reg(const void *const hw) +{ + return ((Cmcc *)hw)->LCKWAY.reg; +} + +static inline void hri_cmcc_set_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_mcfg_reg_t hri_cmcc_get_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_mcfg_reg_t hri_cmcc_read_MCFG_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MCFG.reg; +} + +static inline void hri_cmcc_set_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_men_reg_t hri_cmcc_get_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_MEN_reg(const void *const hw, hri_cmcc_men_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_men_reg_t hri_cmcc_read_MEN_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MEN.reg; +} + +static inline void hri_cmcc_write_CTRL_reg(const void *const hw, hri_cmcc_ctrl_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CTRL.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MAINT0_reg(const void *const hw, hri_cmcc_maint0_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MAINT0.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MAINT1_reg(const void *const hw, hri_cmcc_maint1_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MAINT1.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MCTRL_reg(const void *const hw, hri_cmcc_mctrl_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCTRL.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CMCC_E54_H_INCLUDED */ +#endif /* _SAME54_CMCC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dac_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dac_e54.h new file mode 100644 index 0000000..911dd52 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dac_e54.h @@ -0,0 +1,1706 @@ +/** + * \file + * + * \brief SAM DAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_DAC_COMPONENT_ +#ifndef _HRI_DAC_E54_H_INCLUDED_ +#define _HRI_DAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DAC_CRITICAL_SECTIONS) +#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DAC_CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dac_dacctrl_reg_t; +typedef uint16_t hri_dac_data_reg_t; +typedef uint16_t hri_dac_databuf_reg_t; +typedef uint16_t hri_dac_result_reg_t; +typedef uint32_t hri_dac_syncbusy_reg_t; +typedef uint8_t hri_dac_ctrla_reg_t; +typedef uint8_t hri_dac_ctrlb_reg_t; +typedef uint8_t hri_dac_dbgctrl_reg_t; +typedef uint8_t hri_dac_evctrl_reg_t; +typedef uint8_t hri_dac_intenset_reg_t; +typedef uint8_t hri_dac_intflag_reg_t; +typedef uint8_t hri_dac_status_reg_t; + +static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + while (((Dac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + return ((Dac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; +} + +static inline bool hri_dac_get_INTFLAG_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; +} + +static inline bool hri_dac_get_INTFLAG_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; +} + +static inline bool hri_dac_get_INTFLAG_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; +} + +static inline bool hri_dac_get_INTFLAG_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; +} + +static inline bool hri_dac_get_interrupt_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; +} + +static inline bool hri_dac_get_interrupt_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; +} + +static inline bool hri_dac_get_interrupt_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; +} + +static inline void hri_dac_clear_interrupt_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; +} + +static inline bool hri_dac_get_interrupt_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; +} + +static inline void hri_dac_clear_interrupt_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; +} + +static inline bool hri_dac_get_interrupt_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; +} + +static inline void hri_dac_clear_interrupt_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; +} + +static inline bool hri_dac_get_interrupt_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; +} + +static inline void hri_dac_clear_interrupt_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; +} + +static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) +{ + return ((Dac *)hw)->INTFLAG.reg; +} + +static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + ((Dac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; +} + +static inline void hri_dac_set_INTEN_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; +} + +static inline void hri_dac_set_INTEN_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; +} + +static inline bool hri_dac_get_INTEN_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; +} + +static inline void hri_dac_set_INTEN_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; +} + +static inline bool hri_dac_get_INTEN_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY1) >> DAC_INTENSET_EMPTY1_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; +} + +static inline void hri_dac_set_INTEN_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; +} + +static inline bool hri_dac_get_INTEN_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY0) >> DAC_INTENSET_RESRDY0_Pos; +} + +static inline void hri_dac_write_INTEN_RESRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; + } +} + +static inline void hri_dac_clear_INTEN_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; +} + +static inline void hri_dac_set_INTEN_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; +} + +static inline bool hri_dac_get_INTEN_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY1) >> DAC_INTENSET_RESRDY1_Pos; +} + +static inline void hri_dac_write_INTEN_RESRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; + } +} + +static inline void hri_dac_clear_INTEN_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; +} + +static inline void hri_dac_set_INTEN_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; +} + +static inline bool hri_dac_get_INTEN_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN0) >> DAC_INTENSET_OVERRUN0_Pos; +} + +static inline void hri_dac_write_INTEN_OVERRUN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; + } +} + +static inline void hri_dac_clear_INTEN_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; +} + +static inline void hri_dac_set_INTEN_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; +} + +static inline bool hri_dac_get_INTEN_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN1) >> DAC_INTENSET_OVERRUN1_Pos; +} + +static inline void hri_dac_write_INTEN_OVERRUN1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; + } +} + +static inline void hri_dac_clear_INTEN_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; +} + +static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENSET.reg = mask; +} + +static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) +{ + return ((Dac *)hw)->INTENSET.reg; +} + +static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) +{ + ((Dac *)hw)->INTENSET.reg = data; + ((Dac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_dac_get_STATUS_READY0_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY0) >> DAC_STATUS_READY0_Pos; +} + +static inline bool hri_dac_get_STATUS_READY1_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY1) >> DAC_STATUS_READY1_Pos; +} + +static inline bool hri_dac_get_STATUS_EOC0_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC0) >> DAC_STATUS_EOC0_Pos; +} + +static inline bool hri_dac_get_STATUS_EOC1_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC1) >> DAC_STATUS_EOC1_Pos; +} + +static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) +{ + return ((Dac *)hw)->STATUS.reg; +} + +static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA0_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA0) >> DAC_SYNCBUSY_DATA0_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA1_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA1) >> DAC_SYNCBUSY_DATA1_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF0_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF0) >> DAC_SYNCBUSY_DATABUF0_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF1_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF1) >> DAC_SYNCBUSY_DATABUF1_Pos; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Dac *)hw)->SYNCBUSY.reg; +} + +static inline hri_dac_result_reg_t hri_dac_get_RESULT_RESULT_bf(const void *const hw, uint8_t index, + hri_dac_result_reg_t mask) +{ + return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT(mask)) >> DAC_RESULT_RESULT_Pos; +} + +static inline hri_dac_result_reg_t hri_dac_read_RESULT_RESULT_bf(const void *const hw, uint8_t index) +{ + return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT_Msk) >> DAC_RESULT_RESULT_Pos; +} + +static inline hri_dac_result_reg_t hri_dac_get_RESULT_reg(const void *const hw, uint8_t index, + hri_dac_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->RESULT[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_result_reg_t hri_dac_read_RESULT_reg(const void *const hw, uint8_t index) +{ + return ((Dac *)hw)->RESULT[index].reg; +} + +static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= ~DAC_CTRLA_ENABLE; + tmp |= value << DAC_CTRLA_ENABLE_Pos; + ((Dac *)hw)->CTRLA.reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) +{ + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + return ((Dac *)hw)->CTRLA.reg; +} + +static inline void hri_dac_set_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_DIFF_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_DIFF) >> DAC_CTRLB_DIFF_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_DIFF_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_DIFF; + tmp |= value << DAC_CTRLB_DIFF_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_REFSEL_Msk; + tmp |= DAC_CTRLB_REFSEL(data); + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) +{ + return ((Dac *)hw)->CTRLB.reg; +} + +static inline void hri_dac_set_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI0) >> DAC_EVCTRL_STARTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI0; + tmp |= value << DAC_EVCTRL_STARTEI0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI1) >> DAC_EVCTRL_STARTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI1; + tmp |= value << DAC_EVCTRL_STARTEI1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO0) >> DAC_EVCTRL_EMPTYEO0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO0; + tmp |= value << DAC_EVCTRL_EMPTYEO0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO1) >> DAC_EVCTRL_EMPTYEO1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO1; + tmp |= value << DAC_EVCTRL_EMPTYEO1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI0) >> DAC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI0; + tmp |= value << DAC_EVCTRL_INVEI0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI1) >> DAC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI1; + tmp |= value << DAC_EVCTRL_INVEI1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_RESRDYEO0) >> DAC_EVCTRL_RESRDYEO0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_RESRDYEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_RESRDYEO0; + tmp |= value << DAC_EVCTRL_RESRDYEO0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_RESRDYEO1) >> DAC_EVCTRL_RESRDYEO1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_RESRDYEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_RESRDYEO1; + tmp |= value << DAC_EVCTRL_RESRDYEO1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->EVCTRL.reg; +} + +static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_LEFTADJ) >> DAC_DACCTRL_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_LEFTADJ; + tmp |= value << DAC_DACCTRL_LEFTADJ_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_ENABLE) >> DAC_DACCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_ENABLE; + tmp |= value << DAC_DACCTRL_ENABLE_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_FEXT; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_FEXT) >> DAC_DACCTRL_FEXT_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_FEXT_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_FEXT; + tmp |= value << DAC_DACCTRL_FEXT_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_FEXT; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_FEXT; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_RUNSTDBY) >> DAC_DACCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_RUNSTDBY; + tmp |= value << DAC_DACCTRL_RUNSTDBY_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_DITHER) >> DAC_DACCTRL_DITHER_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_DITHER_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_DITHER; + tmp |= value << DAC_DACCTRL_DITHER_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_CCTRL(mask)) >> DAC_DACCTRL_CCTRL_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_CCTRL_Msk; + tmp |= DAC_DACCTRL_CCTRL(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_CCTRL_Msk) >> DAC_DACCTRL_CCTRL_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_REFRESH(mask)) >> DAC_DACCTRL_REFRESH_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_REFRESH_Msk; + tmp |= DAC_DACCTRL_REFRESH(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_REFRESH_Msk) >> DAC_DACCTRL_REFRESH_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_OSR(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_OSR_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_OSR(mask)) >> DAC_DACCTRL_OSR_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_OSR_Msk; + tmp |= DAC_DACCTRL_OSR(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_OSR(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_OSR(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_OSR_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_OSR_Msk) >> DAC_DACCTRL_OSR_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_reg(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_reg(const void *const hw, uint8_t index) +{ + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + return ((Dac *)hw)->DACCTRL[index].reg; +} + +static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= ~DAC_DBGCTRL_DBGRUN; + tmp |= value << DAC_DBGCTRL_DBGRUN_Pos; + ((Dac *)hw)->DBGCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATA[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATA0 | DAC_SYNCBUSY_DATA1); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATABUF[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATABUF0 | DAC_SYNCBUSY_DATABUF1); + DAC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DAC_E54_H_INCLUDED */ +#endif /* _SAME54_DAC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dmac_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dmac_e54.h new file mode 100644 index 0000000..b4a6ba1 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dmac_e54.h @@ -0,0 +1,6800 @@ +/** + * \file + * + * \brief SAM DMAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_DMAC_COMPONENT_ +#ifndef _HRI_DMAC_E54_H_INCLUDED_ +#define _HRI_DMAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) +#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DMAC_CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dmac_crcctrl_reg_t; +typedef uint16_t hri_dmac_ctrl_reg_t; +typedef uint16_t hri_dmac_intpend_reg_t; +typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; +typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; +typedef uint32_t hri_dmac_active_reg_t; +typedef uint32_t hri_dmac_baseaddr_reg_t; +typedef uint32_t hri_dmac_busych_reg_t; +typedef uint32_t hri_dmac_chctrla_reg_t; +typedef uint32_t hri_dmac_crcchksum_reg_t; +typedef uint32_t hri_dmac_crcdatain_reg_t; +typedef uint32_t hri_dmac_intstatus_reg_t; +typedef uint32_t hri_dmac_pendch_reg_t; +typedef uint32_t hri_dmac_prictrl0_reg_t; +typedef uint32_t hri_dmac_swtrigctrl_reg_t; +typedef uint32_t hri_dmac_wrbaddr_reg_t; +typedef uint32_t hri_dmacchannel_chctrla_reg_t; +typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; +typedef uint8_t hri_dmac_chctrlb_reg_t; +typedef uint8_t hri_dmac_chevctrl_reg_t; +typedef uint8_t hri_dmac_chintenset_reg_t; +typedef uint8_t hri_dmac_chintflag_reg_t; +typedef uint8_t hri_dmac_chprilvl_reg_t; +typedef uint8_t hri_dmac_chstatus_reg_t; +typedef uint8_t hri_dmac_crcstatus_reg_t; +typedef uint8_t hri_dmac_dbgctrl_reg_t; +typedef uint8_t hri_dmacchannel_chctrlb_reg_t; +typedef uint8_t hri_dmacchannel_chevctrl_reg_t; +typedef uint8_t hri_dmacchannel_chintenset_reg_t; +typedef uint8_t hri_dmacchannel_chintflag_reg_t; +typedef uint8_t hri_dmacchannel_chprilvl_reg_t; +typedef uint8_t hri_dmacchannel_chstatus_reg_t; + +static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT16_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT16) >> DMAC_INTSTATUS_CHINT16_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT17_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT17) >> DMAC_INTSTATUS_CHINT17_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT18_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT18) >> DMAC_INTSTATUS_CHINT18_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT19_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT19) >> DMAC_INTSTATUS_CHINT19_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT20_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT20) >> DMAC_INTSTATUS_CHINT20_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT21_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT21) >> DMAC_INTSTATUS_CHINT21_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT22_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT22) >> DMAC_INTSTATUS_CHINT22_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT23_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT23) >> DMAC_INTSTATUS_CHINT23_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT24_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT24) >> DMAC_INTSTATUS_CHINT24_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT25_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT25) >> DMAC_INTSTATUS_CHINT25_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT26_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT26) >> DMAC_INTSTATUS_CHINT26_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT27_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT27) >> DMAC_INTSTATUS_CHINT27_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT28_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT28) >> DMAC_INTSTATUS_CHINT28_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT29_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT29) >> DMAC_INTSTATUS_CHINT29_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT30_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT30) >> DMAC_INTSTATUS_CHINT30_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT31_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT31) >> DMAC_INTSTATUS_CHINT31_Pos; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTSTATUS.reg; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH16_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH16) >> DMAC_BUSYCH_BUSYCH16_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH17_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH17) >> DMAC_BUSYCH_BUSYCH17_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH18_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH18) >> DMAC_BUSYCH_BUSYCH18_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH19_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH19) >> DMAC_BUSYCH_BUSYCH19_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH20_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH20) >> DMAC_BUSYCH_BUSYCH20_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH21_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH21) >> DMAC_BUSYCH_BUSYCH21_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH22_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH22) >> DMAC_BUSYCH_BUSYCH22_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH23_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH23) >> DMAC_BUSYCH_BUSYCH23_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH24_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH24) >> DMAC_BUSYCH_BUSYCH24_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH25_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH25) >> DMAC_BUSYCH_BUSYCH25_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH26_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH26) >> DMAC_BUSYCH_BUSYCH26_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH27_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH27) >> DMAC_BUSYCH_BUSYCH27_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH28_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH28) >> DMAC_BUSYCH_BUSYCH28_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH29_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH29) >> DMAC_BUSYCH_BUSYCH29_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH30_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH30) >> DMAC_BUSYCH_BUSYCH30_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH31_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH31) >> DMAC_BUSYCH_BUSYCH31_Pos; +} + +static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->BUSYCH.reg; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH16_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH16) >> DMAC_PENDCH_PENDCH16_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH17_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH17) >> DMAC_PENDCH_PENDCH17_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH18_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH18) >> DMAC_PENDCH_PENDCH18_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH19_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH19) >> DMAC_PENDCH_PENDCH19_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH20_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH20) >> DMAC_PENDCH_PENDCH20_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH21_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH21) >> DMAC_PENDCH_PENDCH21_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH22_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH22) >> DMAC_PENDCH_PENDCH22_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH23_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH23) >> DMAC_PENDCH_PENDCH23_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH24_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH24) >> DMAC_PENDCH_PENDCH24_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH25_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH25) >> DMAC_PENDCH_PENDCH25_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH26_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH26) >> DMAC_PENDCH_PENDCH26_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH27_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH27) >> DMAC_PENDCH_PENDCH27_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH28_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH28) >> DMAC_PENDCH_PENDCH28_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH29_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH29) >> DMAC_PENDCH_PENDCH29_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH30_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH30) >> DMAC_PENDCH_PENDCH30_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH31_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH31) >> DMAC_PENDCH_PENDCH31_Pos; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PENDCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->PENDCH.reg; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->ACTIVE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) +{ + return ((Dmac *)hw)->ACTIVE.reg; +} + +static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_DMAENABLE; + tmp |= value << DMAC_CTRL_DMAENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN0; + tmp |= value << DMAC_CTRL_LVLEN0_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN1; + tmp |= value << DMAC_CTRL_LVLEN1_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN2; + tmp |= value << DMAC_CTRL_LVLEN2_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN3; + tmp |= value << DMAC_CTRL_LVLEN3_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CTRL.reg; +} + +static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, + hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; + tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; + tmp |= DMAC_CRCCTRL_CRCPOLY(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; + tmp |= DMAC_CRCCTRL_CRCSRC(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCMODE(mask)) >> DMAC_CRCCTRL_CRCMODE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCMODE_Msk; + tmp |= DMAC_CRCCTRL_CRCMODE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCMODE_Msk) >> DMAC_CRCCTRL_CRCMODE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCTRL.reg; +} + +static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, + hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; + tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); + ((Dmac *)hw)->CRCDATAIN.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCDATAIN.reg; +} + +static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, + hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; + tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); + ((Dmac *)hw)->CRCCHKSUM.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCHKSUM.reg; +} + +static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= ~DMAC_DBGCTRL_DBGRUN; + tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; + ((Dmac *)hw)->DBGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG16) >> DMAC_SWTRIGCTRL_SWTRIG16_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG16; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG16_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG17) >> DMAC_SWTRIGCTRL_SWTRIG17_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG17; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG17_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG18) >> DMAC_SWTRIGCTRL_SWTRIG18_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG18; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG18_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG19) >> DMAC_SWTRIGCTRL_SWTRIG19_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG19; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG19_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG20) >> DMAC_SWTRIGCTRL_SWTRIG20_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG20; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG20_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG21) >> DMAC_SWTRIGCTRL_SWTRIG21_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG21; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG21_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG22) >> DMAC_SWTRIGCTRL_SWTRIG22_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG22; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG22_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG23) >> DMAC_SWTRIGCTRL_SWTRIG23_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG23; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG23_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG24) >> DMAC_SWTRIGCTRL_SWTRIG24_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG24; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG24_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG25) >> DMAC_SWTRIGCTRL_SWTRIG25_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG25; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG25_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG26) >> DMAC_SWTRIGCTRL_SWTRIG26_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG26; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG26_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG27) >> DMAC_SWTRIGCTRL_SWTRIG27_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG27; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG27_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG28) >> DMAC_SWTRIGCTRL_SWTRIG28_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG28; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG28_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG29) >> DMAC_SWTRIGCTRL_SWTRIG29_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG29; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG29_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG30) >> DMAC_SWTRIGCTRL_SWTRIG30_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG30; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG30_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG31) >> DMAC_SWTRIGCTRL_SWTRIG31_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG31; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG31_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, + hri_dmac_swtrigctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->SWTRIGCTRL.reg; +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN0; + tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN1; + tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN2; + tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN3; + tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS0(mask)) >> DMAC_PRICTRL0_QOS0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS0_Msk; + tmp |= DMAC_PRICTRL0_QOS0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS0_Msk) >> DMAC_PRICTRL0_QOS0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS1(mask)) >> DMAC_PRICTRL0_QOS1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS1_Msk; + tmp |= DMAC_PRICTRL0_QOS1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS1_Msk) >> DMAC_PRICTRL0_QOS1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS2(mask)) >> DMAC_PRICTRL0_QOS2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS2_Msk; + tmp |= DMAC_PRICTRL0_QOS2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS2_Msk) >> DMAC_PRICTRL0_QOS2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS3(mask)) >> DMAC_PRICTRL0_QOS3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS3_Msk; + tmp |= DMAC_PRICTRL0_QOS3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS3_Msk) >> DMAC_PRICTRL0_QOS3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) +{ + return ((Dmac *)hw)->PRICTRL0.reg; +} + +static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TERR; + tmp |= value << DMAC_INTPEND_TERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TCMPL; + tmp |= value << DMAC_INTPEND_TCMPL_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_SUSP; + tmp |= value << DMAC_INTPEND_SUSP_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_CRCERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_CRCERR) >> DMAC_INTPEND_CRCERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_CRCERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_CRCERR; + tmp |= value << DMAC_INTPEND_CRCERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_FERR; + tmp |= value << DMAC_INTPEND_FERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_BUSY; + tmp |= value << DMAC_INTPEND_BUSY_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_PEND; + tmp |= value << DMAC_INTPEND_PEND_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_ID_Msk; + tmp |= DMAC_INTPEND_ID(data); + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTPEND.reg; +} + +static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, + hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; + tmp |= DMAC_BASEADDR_BASEADDR(data); + ((Dmac *)hw)->BASEADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->BASEADDR.reg; +} + +static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; + tmp |= DMAC_WRBADDR_WRBADDR(data); + ((Dmac *)hw)->WRBADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->WRBADDR.reg; +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCERR) >> DMAC_CRCSTATUS_CRCERR_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CRCSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCSTATUS.reg; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_VALID; + tmp |= value << DMAC_BTCTRL_VALID_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_SRCINC; + tmp |= value << DMAC_BTCTRL_SRCINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_DSTINC; + tmp |= value << DMAC_BTCTRL_DSTINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSEL; + tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; + tmp |= DMAC_BTCTRL_EVOSEL(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; + tmp |= DMAC_BTCTRL_BLOCKACT(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; + tmp |= DMAC_BTCTRL_BEATSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; + tmp |= DMAC_BTCTRL_STEPSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCTRL.reg; +} + +static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= ~DMAC_BTCNT_BTCNT_Msk; + tmp |= DMAC_BTCNT_BTCNT(data); + ((DmacDescriptor *)hw)->BTCNT.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCNT.reg; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t +hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; + tmp |= DMAC_SRCADDR_SRCADDR(data); + ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->SRCADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_CRC_CHKINIT_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT(mask)) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_CRC_CHKINIT_Msk; + tmp |= DMAC_DSTADDR_CRC_CHKINIT(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_CRC_CHKINIT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT_Msk) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; + tmp |= DMAC_DSTADDR_DSTADDR(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DSTADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; + tmp |= DMAC_DESCADDR_DESCADDR(data); + ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DESCADDR.reg; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmacchannel_get_interrupt_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmacchannel_get_interrupt_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmacchannel_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmacchannel_get_CHINTFLAG_reg(const void *const hw, + hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmacchannel_read_CHINTFLAG_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHINTFLAG.reg; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_dmacchannel_set_CHINTEN_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmacchannel_get_CHINTEN_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_TERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmacchannel_set_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmacchannel_get_CHINTEN_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmacchannel_set_CHINTEN_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmacchannel_get_CHINTEN_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmacchannel_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmacchannel_get_CHINTEN_reg(const void *const hw, + hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmacchannel_read_CHINTEN_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHINTENSET.reg; +} + +static inline void hri_dmacchannel_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = data; + ((DmacChannel *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_dmacchannel_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = mask; +} + +static inline void hri_dmacchannel_set_CHCTRLA_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGSRC_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLA_TRIGSRC(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGSRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGACT_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; + tmp |= DMAC_CHCTRLA_TRIGACT(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_BURSTLEN_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; + tmp |= DMAC_CHCTRLA_BURSTLEN(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_BURSTLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_THRESHOLD_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; + tmp |= DMAC_CHCTRLA_THRESHOLD(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_THRESHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHCTRLA.reg; +} + +static inline void hri_dmacchannel_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_CMD_bf(const void *const hw, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((DmacChannel *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHCTRLB.reg; +} + +static inline void hri_dmacchannel_set_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_PRILVL_bf(const void *const hw, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; + tmp |= DMAC_CHPRILVL_PRILVL(data); + ((DmacChannel *)hw)->CHPRILVL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_PRILVL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_reg(const void *const hw, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHPRILVL.reg; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHEVCTRL_EVIE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVIE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVIE; + tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHEVCTRL_EVOE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVOE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOE; + tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVACT_bf(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; + tmp |= DMAC_CHEVCTRL_EVACT(data); + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVACT_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVOMODE_bf(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; + tmp |= DMAC_CHEVCTRL_EVOMODE(data); + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVOMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_reg(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHEVCTRL.reg; +} + +static inline bool hri_dmacchannel_get_CHSTATUS_PEND_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_BUSY_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_FERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_CRCERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmacchannel_get_CHSTATUS_reg(const void *const hw, + hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmacchannel_read_CHSTATUS_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHSTATUS.reg; +} + +static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; +} + +static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintflag_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; +} + +static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; +} + +static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t data) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = data; + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; +} + +static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; +} + +static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLA_TRIGSRC(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; + tmp |= DMAC_CHCTRLA_TRIGACT(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; + tmp |= DMAC_CHCTRLA_BURSTLEN(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; + tmp |= DMAC_CHCTRLA_THRESHOLD(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; +} + +static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; +} + +static inline void hri_dmac_set_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; + tmp |= DMAC_CHPRILVL_PRILVL(data); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; +} + +static inline void hri_dmac_set_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVIE; + tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOE; + tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; + tmp |= DMAC_CHEVCTRL_EVACT(data); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; + tmp |= DMAC_CHEVCTRL_EVOMODE(data); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; +} + +static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_dmacdescriptor_set_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_set_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_get_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_get_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_write_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_write_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_clear_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_clear_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_toggle_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_toggle_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_read_DSTADDR_CRC_reg(a) hri_dmacdescriptor_read_DSTADDR_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DMAC_E54_H_INCLUDED */ +#endif /* _SAME54_DMAC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dsu_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dsu_e54.h new file mode 100644 index 0000000..b192276 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dsu_e54.h @@ -0,0 +1,1256 @@ +/** + * \file + * + * \brief SAM DSU + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_DSU_COMPONENT_ +#ifndef _HRI_DSU_E54_H_INCLUDED_ +#define _HRI_DSU_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DSU_CRITICAL_SECTIONS) +#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DSU_CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_dsu_addr_reg_t; +typedef uint32_t hri_dsu_cfg_reg_t; +typedef uint32_t hri_dsu_cid0_reg_t; +typedef uint32_t hri_dsu_cid1_reg_t; +typedef uint32_t hri_dsu_cid2_reg_t; +typedef uint32_t hri_dsu_cid3_reg_t; +typedef uint32_t hri_dsu_data_reg_t; +typedef uint32_t hri_dsu_dcc_reg_t; +typedef uint32_t hri_dsu_did_reg_t; +typedef uint32_t hri_dsu_end_reg_t; +typedef uint32_t hri_dsu_entry0_reg_t; +typedef uint32_t hri_dsu_entry1_reg_t; +typedef uint32_t hri_dsu_length_reg_t; +typedef uint32_t hri_dsu_memtype_reg_t; +typedef uint32_t hri_dsu_pid0_reg_t; +typedef uint32_t hri_dsu_pid1_reg_t; +typedef uint32_t hri_dsu_pid2_reg_t; +typedef uint32_t hri_dsu_pid3_reg_t; +typedef uint32_t hri_dsu_pid4_reg_t; +typedef uint32_t hri_dsu_pid5_reg_t; +typedef uint32_t hri_dsu_pid6_reg_t; +typedef uint32_t hri_dsu_pid7_reg_t; +typedef uint8_t hri_dsu_ctrl_reg_t; +typedef uint8_t hri_dsu_statusa_reg_t; +typedef uint8_t hri_dsu_statusb_reg_t; + +static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; +} + +static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; +} + +static inline bool hri_dsu_get_STATUSB_CELCK_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_CELCK) >> DSU_STATUSB_CELCK_Pos; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSB.reg; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) +{ + return ((Dsu *)hw)->DID.reg; +} + +static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; +} + +static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY0.reg; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY1.reg; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->END.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) +{ + return ((Dsu *)hw)->END.reg; +} + +static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) +{ + return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MEMTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) +{ + return ((Dsu *)hw)->MEMTYPE.reg; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID4.reg; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID5.reg; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID6.reg; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID7.reg; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID0.reg; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID1.reg; +} + +static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID2.reg; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID3.reg; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID0.reg; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID1.reg; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID2.reg; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID3.reg; +} + +static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_AMOD_Msk; + tmp |= DSU_ADDR_AMOD(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_ADDR_Msk; + tmp |= DSU_ADDR_ADDR(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) +{ + return ((Dsu *)hw)->ADDR.reg; +} + +static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= ~DSU_LENGTH_LENGTH_Msk; + tmp |= DSU_LENGTH_LENGTH(data); + ((Dsu *)hw)->LENGTH.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) +{ + return ((Dsu *)hw)->LENGTH.reg; +} + +static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= ~DSU_DATA_DATA_Msk; + tmp |= DSU_DATA_DATA(data); + ((Dsu *)hw)->DATA.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) +{ + return ((Dsu *)hw)->DATA.reg; +} + +static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= ~DSU_DCC_DATA_Msk; + tmp |= DSU_DCC_DATA(data); + ((Dsu *)hw)->DCC[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCC[index].reg; +} + +static inline void hri_dsu_set_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_CFG_ETBRAMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_ETBRAMEN) >> DSU_CFG_ETBRAMEN_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_CFG_ETBRAMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_ETBRAMEN; + tmp |= value << DSU_CFG_ETBRAMEN_Pos; + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_LQOS(mask)) >> DSU_CFG_LQOS_Pos; + return tmp; +} + +static inline void hri_dsu_write_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_LQOS_Msk; + tmp |= DSU_CFG_LQOS(data); + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_LQOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_LQOS_Msk) >> DSU_CFG_LQOS_Pos; + return tmp; +} + +static inline void hri_dsu_set_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_DCCDMALEVEL(mask)) >> DSU_CFG_DCCDMALEVEL_Pos; + return tmp; +} + +static inline void hri_dsu_write_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_DCCDMALEVEL_Msk; + tmp |= DSU_CFG_DCCDMALEVEL(data); + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_DCCDMALEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_DCCDMALEVEL_Msk) >> DSU_CFG_DCCDMALEVEL_Pos; + return tmp; +} + +static inline void hri_dsu_set_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_reg(const void *const hw) +{ + return ((Dsu *)hw)->CFG.reg; +} + +static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; +} + +static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; +} + +static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; +} + +static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSA.reg; +} + +static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CTRL.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DSU_E54_H_INCLUDED */ +#endif /* _SAME54_DSU_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_e54.h new file mode 100644 index 0000000..46e77ca --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_e54.h @@ -0,0 +1,76 @@ +/** + * \file + * + * \brief SAM E54 HRI top-level header file + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HRI_E54_H_INCLUDED_ +#define _HRI_E54_H_INCLUDED_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* _HRI_E54_H_INCLUDED_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_eic_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_eic_e54.h new file mode 100644 index 0000000..f86e452 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_eic_e54.h @@ -0,0 +1,1838 @@ +/** + * \file + * + * \brief SAM EIC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_EIC_COMPONENT_ +#ifndef _HRI_EIC_E54_H_INCLUDED_ +#define _HRI_EIC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EIC_CRITICAL_SECTIONS) +#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EIC_CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_eic_nmiflag_reg_t; +typedef uint32_t hri_eic_asynch_reg_t; +typedef uint32_t hri_eic_config_reg_t; +typedef uint32_t hri_eic_debouncen_reg_t; +typedef uint32_t hri_eic_dprescaler_reg_t; +typedef uint32_t hri_eic_evctrl_reg_t; +typedef uint32_t hri_eic_intenset_reg_t; +typedef uint32_t hri_eic_intflag_reg_t; +typedef uint32_t hri_eic_pinstate_reg_t; +typedef uint32_t hri_eic_syncbusy_reg_t; +typedef uint8_t hri_eic_ctrla_reg_t; +typedef uint8_t hri_eic_nmictrl_reg_t; + +static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + while (((Eic *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + return ((Eic *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) +{ + return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; +} + +static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) +{ + ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Eic *)hw)->NMIFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->NMIFLAG.reg; +} + +static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + ((Eic *)hw)->NMIFLAG.reg = mask; +} + +static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->INTFLAG.reg; +} + +static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + ((Eic *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); + ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); +} + +static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = mask; +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) +{ + return ((Eic *)hw)->INTENSET.reg; +} + +static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = data; + ((Eic *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Eic *)hw)->SYNCBUSY.reg; +} + +static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_PINSTATE_bf(const void *const hw, hri_eic_pinstate_reg_t mask) +{ + return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE(mask)) >> EIC_PINSTATE_PINSTATE_Pos; +} + +static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_PINSTATE_bf(const void *const hw) +{ + return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE_Msk) >> EIC_PINSTATE_PINSTATE_Pos; +} + +static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_reg(const void *const hw, hri_eic_pinstate_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->PINSTATE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_reg(const void *const hw) +{ + return ((Eic *)hw)->PINSTATE.reg; +} + +static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_ENABLE; + tmp |= value << EIC_CTRLA_ENABLE_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_CKSEL; + tmp |= value << EIC_CTRLA_CKSEL_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg = data; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) +{ + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + return ((Eic *)hw)->CTRLA.reg; +} + +static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIFILTEN; + tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIASYNCH; + tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMISENSE_Msk; + tmp |= EIC_NMICTRL_NMISENSE(data); + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->NMICTRL.reg; +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; + tmp |= EIC_EVCTRL_EXTINTEO(data); + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->EVCTRL.reg; +} + +static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= ~EIC_ASYNCH_ASYNCH_Msk; + tmp |= EIC_ASYNCH_ASYNCH(data); + ((Eic *)hw)->ASYNCH.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) +{ + return ((Eic *)hw)->ASYNCH.reg; +} + +static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN0; + tmp |= value << EIC_CONFIG_FILTEN0_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN1; + tmp |= value << EIC_CONFIG_FILTEN1_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN2; + tmp |= value << EIC_CONFIG_FILTEN2_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN3; + tmp |= value << EIC_CONFIG_FILTEN3_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN4; + tmp |= value << EIC_CONFIG_FILTEN4_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN5; + tmp |= value << EIC_CONFIG_FILTEN5_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN6; + tmp |= value << EIC_CONFIG_FILTEN6_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN7; + tmp |= value << EIC_CONFIG_FILTEN7_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE0_Msk; + tmp |= EIC_CONFIG_SENSE0(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE1_Msk; + tmp |= EIC_CONFIG_SENSE1(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE2_Msk; + tmp |= EIC_CONFIG_SENSE2(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE3_Msk; + tmp |= EIC_CONFIG_SENSE3(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE4_Msk; + tmp |= EIC_CONFIG_SENSE4(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE5_Msk; + tmp |= EIC_CONFIG_SENSE5(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE6_Msk; + tmp |= EIC_CONFIG_SENSE6(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE7_Msk; + tmp |= EIC_CONFIG_SENSE7(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) +{ + return ((Eic *)hw)->CONFIG[index].reg; +} + +static inline void hri_eic_set_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg |= EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, + hri_eic_debouncen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN(mask)) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; + return tmp; +} + +static inline void hri_eic_write_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp &= ~EIC_DEBOUNCEN_DEBOUNCEN_Msk; + tmp |= EIC_DEBOUNCEN_DEBOUNCEN(data); + ((Eic *)hw)->DEBOUNCEN.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg &= ~EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg ^= EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN_Msk) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; + return tmp; +} + +static inline void hri_eic_set_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_reg(const void *const hw) +{ + return ((Eic *)hw)->DEBOUNCEN.reg; +} + +static inline void hri_eic_set_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_STATES0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_STATES0) >> EIC_DPRESCALER_STATES0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_STATES0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_STATES0; + tmp |= value << EIC_DPRESCALER_STATES0_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_STATES1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_STATES1) >> EIC_DPRESCALER_STATES1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_STATES1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_STATES1; + tmp |= value << EIC_DPRESCALER_STATES1_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_TICKON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_TICKON) >> EIC_DPRESCALER_TICKON_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_TICKON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_TICKON; + tmp |= value << EIC_DPRESCALER_TICKON_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER0_bf(const void *const hw, + hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER0(mask)) >> EIC_DPRESCALER_PRESCALER0_Pos; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_PRESCALER0_Msk; + tmp |= EIC_DPRESCALER_PRESCALER0(data); + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER0_Msk) >> EIC_DPRESCALER_PRESCALER0_Pos; + return tmp; +} + +static inline void hri_eic_set_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER1_bf(const void *const hw, + hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER1(mask)) >> EIC_DPRESCALER_PRESCALER1_Pos; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_PRESCALER1_Msk; + tmp |= EIC_DPRESCALER_PRESCALER1(data); + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER1_Msk) >> EIC_DPRESCALER_PRESCALER1_Pos; + return tmp; +} + +static inline void hri_eic_set_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_reg(const void *const hw) +{ + return ((Eic *)hw)->DPRESCALER.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EIC_E54_H_INCLUDED */ +#endif /* _SAME54_EIC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_evsys_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_evsys_e54.h new file mode 100644 index 0000000..cd4a98a --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_evsys_e54.h @@ -0,0 +1,1707 @@ +/** + * \file + * + * \brief SAM EVSYS + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_EVSYS_COMPONENT_ +#ifndef _HRI_EVSYS_E54_H_INCLUDED_ +#define _HRI_EVSYS_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) +#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EVSYS_CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_evsys_intpend_reg_t; +typedef uint32_t hri_evsys_busych_reg_t; +typedef uint32_t hri_evsys_channel_reg_t; +typedef uint32_t hri_evsys_intstatus_reg_t; +typedef uint32_t hri_evsys_readyusr_reg_t; +typedef uint32_t hri_evsys_swevt_reg_t; +typedef uint32_t hri_evsys_user_reg_t; +typedef uint32_t hri_evsyschannel_channel_reg_t; +typedef uint8_t hri_evsys_chintenset_reg_t; +typedef uint8_t hri_evsys_chintflag_reg_t; +typedef uint8_t hri_evsys_chstatus_reg_t; +typedef uint8_t hri_evsys_ctrla_reg_t; +typedef uint8_t hri_evsys_prictrl_reg_t; +typedef uint8_t hri_evsyschannel_chintenset_reg_t; +typedef uint8_t hri_evsyschannel_chintflag_reg_t; +typedef uint8_t hri_evsyschannel_chstatus_reg_t; + +static inline bool hri_evsys_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT9) >> EVSYS_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT10) >> EVSYS_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT11) >> EVSYS_INTSTATUS_CHINT11_Pos; +} + +static inline hri_evsys_intstatus_reg_t hri_evsys_get_INTSTATUS_reg(const void *const hw, + hri_evsys_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intstatus_reg_t hri_evsys_read_INTSTATUS_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTSTATUS.reg; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH0) >> EVSYS_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH1) >> EVSYS_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH2) >> EVSYS_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH3) >> EVSYS_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH4) >> EVSYS_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH5) >> EVSYS_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH6) >> EVSYS_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH7) >> EVSYS_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH8) >> EVSYS_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH9) >> EVSYS_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH10) >> EVSYS_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH11) >> EVSYS_BUSYCH_BUSYCH11_Pos; +} + +static inline hri_evsys_busych_reg_t hri_evsys_get_BUSYCH_reg(const void *const hw, hri_evsys_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_busych_reg_t hri_evsys_read_BUSYCH_reg(const void *const hw) +{ + return ((Evsys *)hw)->BUSYCH.reg; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR0) >> EVSYS_READYUSR_READYUSR0_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR1) >> EVSYS_READYUSR_READYUSR1_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR2) >> EVSYS_READYUSR_READYUSR2_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR3) >> EVSYS_READYUSR_READYUSR3_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR4) >> EVSYS_READYUSR_READYUSR4_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR5) >> EVSYS_READYUSR_READYUSR5_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR6) >> EVSYS_READYUSR_READYUSR6_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR7) >> EVSYS_READYUSR_READYUSR7_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR8) >> EVSYS_READYUSR_READYUSR8_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR9) >> EVSYS_READYUSR_READYUSR9_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR10) >> EVSYS_READYUSR_READYUSR10_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR11) >> EVSYS_READYUSR_READYUSR11_Pos; +} + +static inline hri_evsys_readyusr_reg_t hri_evsys_get_READYUSR_reg(const void *const hw, hri_evsys_readyusr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->READYUSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_readyusr_reg_t hri_evsys_read_READYUSR_reg(const void *const hw) +{ + return ((Evsys *)hw)->READYUSR.reg; +} + +static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) +{ + return ((Evsys *)hw)->CTRLA.reg; +} + +static inline void hri_evsys_set_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_PRICTRL_RREN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_RREN) >> EVSYS_PRICTRL_RREN_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_PRICTRL_RREN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= ~EVSYS_PRICTRL_RREN; + tmp |= value << EVSYS_PRICTRL_RREN_Pos; + ((Evsys *)hw)->PRICTRL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_PRI(mask)) >> EVSYS_PRICTRL_PRI_Pos; + return tmp; +} + +static inline void hri_evsys_write_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t data) +{ + uint8_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= ~EVSYS_PRICTRL_PRI_Msk; + tmp |= EVSYS_PRICTRL_PRI(data); + ((Evsys *)hw)->PRICTRL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_PRI_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_PRI_Msk) >> EVSYS_PRICTRL_PRI_Pos; + return tmp; +} + +static inline void hri_evsys_set_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_reg(const void *const hw) +{ + return ((Evsys *)hw)->PRICTRL.reg; +} + +static inline void hri_evsys_set_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_OVR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_OVR) >> EVSYS_INTPEND_OVR_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_OVR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_OVR; + tmp |= value << EVSYS_INTPEND_OVR_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_EVD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_EVD) >> EVSYS_INTPEND_EVD_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_EVD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_EVD; + tmp |= value << EVSYS_INTPEND_EVD_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_READY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_READY) >> EVSYS_INTPEND_READY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_READY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_READY; + tmp |= value << EVSYS_INTPEND_READY_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_BUSY) >> EVSYS_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_BUSY; + tmp |= value << EVSYS_INTPEND_BUSY_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_ID(mask)) >> EVSYS_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_evsys_write_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t data) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_ID_Msk; + tmp |= EVSYS_INTPEND_ID(data); + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_ID_Msk) >> EVSYS_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_evsys_set_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTPEND.reg; +} + +static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= ~EVSYS_USER_CHANNEL_Msk; + tmp |= EVSYS_USER_CHANNEL(data); + ((Evsys *)hw)->USER[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->USER[index].reg; +} + +static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->SWEVT.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsyschannel_get_CHINTFLAG_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsyschannel_get_CHINTFLAG_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline bool hri_evsyschannel_get_interrupt_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsyschannel_clear_interrupt_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsyschannel_get_interrupt_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsyschannel_clear_interrupt_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline hri_evsys_chintflag_reg_t hri_evsyschannel_get_CHINTFLAG_reg(const void *const hw, + hri_evsys_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintflag_reg_t hri_evsyschannel_read_CHINTFLAG_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHINTFLAG.reg; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_reg(const void *const hw, hri_evsys_chintflag_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_evsyschannel_set_CHINTEN_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; +} + +static inline bool hri_evsyschannel_get_CHINTEN_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; +} + +static inline void hri_evsyschannel_write_CHINTEN_OVR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; + } else { + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; + } +} + +static inline void hri_evsyschannel_clear_CHINTEN_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; +} + +static inline void hri_evsyschannel_set_CHINTEN_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; +} + +static inline bool hri_evsyschannel_get_CHINTEN_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; +} + +static inline void hri_evsyschannel_write_CHINTEN_EVD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; + } else { + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; + } +} + +static inline void hri_evsyschannel_clear_CHINTEN_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; +} + +static inline void hri_evsyschannel_set_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_evsys_chintenset_reg_t hri_evsyschannel_get_CHINTEN_reg(const void *const hw, + hri_evsys_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintenset_reg_t hri_evsyschannel_read_CHINTEN_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHINTENSET.reg; +} + +static inline void hri_evsyschannel_write_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t data) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = data; + ((EvsysChannel *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_evsyschannel_clear_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = mask; +} + +static inline bool hri_evsyschannel_get_CHSTATUS_RDYUSR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; +} + +static inline bool hri_evsyschannel_get_CHSTATUS_BUSYCH_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsyschannel_get_CHSTATUS_reg(const void *const hw, + hri_evsys_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsyschannel_read_CHSTATUS_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHSTATUS.reg; +} + +static inline void hri_evsyschannel_set_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_set_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsyschannel_get_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EVGEN_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EVGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_PATH_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_PATH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EDGSEL_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EDGSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_reg(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHANNEL.reg; +} + +static inline bool hri_evsys_get_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsys_clear_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsys_get_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsys_clear_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline bool hri_evsys_get_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsys_get_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline hri_evsys_chintflag_reg_t hri_evsys_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintflag_reg_t hri_evsys_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; +} + +static inline void hri_evsys_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintflag_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; +} + +static inline void hri_evsys_set_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; +} + +static inline bool hri_evsys_get_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; +} + +static inline void hri_evsys_write_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; + } else { + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; + } +} + +static inline void hri_evsys_clear_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; +} + +static inline void hri_evsys_set_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; +} + +static inline bool hri_evsys_get_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; +} + +static inline void hri_evsys_write_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; + } else { + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; + } +} + +static inline void hri_evsys_clear_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; +} + +static inline void hri_evsys_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; +} + +static inline hri_evsys_chintenset_reg_t hri_evsys_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintenset_reg_t hri_evsys_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; +} + +static inline void hri_evsys_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t data) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = data; + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; +} + +static inline void hri_evsys_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; +} + +static inline bool hri_evsys_get_CHSTATUS_RDYUSR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_BUSYCH_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; +} + +static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EVSYS_E54_H_INCLUDED */ +#endif /* _SAME54_EVSYS_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_freqm_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_freqm_e54.h new file mode 100644 index 0000000..8cbc484 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_freqm_e54.h @@ -0,0 +1,464 @@ +/** + * \file + * + * \brief SAM FREQM + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_FREQM_COMPONENT_ +#ifndef _HRI_FREQM_E54_H_INCLUDED_ +#define _HRI_FREQM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_FREQM_CRITICAL_SECTIONS) +#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define FREQM_CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_freqm_cfga_reg_t; +typedef uint32_t hri_freqm_syncbusy_reg_t; +typedef uint32_t hri_freqm_value_reg_t; +typedef uint8_t hri_freqm_ctrla_reg_t; +typedef uint8_t hri_freqm_ctrlb_reg_t; +typedef uint8_t hri_freqm_intenset_reg_t; +typedef uint8_t hri_freqm_intflag_reg_t; +typedef uint8_t hri_freqm_status_reg_t; + +static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + while (((Freqm *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + return ((Freqm *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTFLAG.reg; +} + +static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + ((Freqm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; +} + +static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos; +} + +static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; + } else { + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; + } +} + +static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; +} + +static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENSET.reg = mask; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTENSET.reg; +} + +static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data) +{ + ((Freqm *)hw)->INTENSET.reg = data; + ((Freqm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Freqm *)hw)->SYNCBUSY.reg; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->VALUE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw) +{ + return ((Freqm *)hw)->VALUE.reg; +} + +static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= ~FREQM_CTRLA_ENABLE; + tmp |= value << FREQM_CTRLA_ENABLE_Pos; + ((Freqm *)hw)->CTRLA.reg = tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg = data; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw) +{ + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + return ((Freqm *)hw)->CTRLA.reg; +} + +static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data) +{ + uint16_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= ~FREQM_CFGA_REFNUM_Msk; + tmp |= FREQM_CFGA_REFNUM(data); + ((Freqm *)hw)->CFGA.reg = tmp; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw) +{ + return ((Freqm *)hw)->CFGA.reg; +} + +static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos; +} + +static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos; +} + +static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw) +{ + return ((Freqm *)hw)->STATUS.reg; +} + +static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLB.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_FREQM_E54_H_INCLUDED */ +#endif /* _SAME54_FREQM_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_gclk_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_gclk_e54.h new file mode 100644 index 0000000..f83af2a --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_gclk_e54.h @@ -0,0 +1,805 @@ +/** + * \file + * + * \brief SAM GCLK + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_GCLK_COMPONENT_ +#ifndef _HRI_GCLK_E54_H_INCLUDED_ +#define _HRI_GCLK_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) +#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GCLK_CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gclk_genctrl_reg_t; +typedef uint32_t hri_gclk_pchctrl_reg_t; +typedef uint32_t hri_gclk_syncbusy_reg_t; +typedef uint8_t hri_gclk_ctrla_reg_t; + +static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + while (((Gclk *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + return ((Gclk *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL9_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL9) >> GCLK_SYNCBUSY_GENCTRL9_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL10_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL10) >> GCLK_SYNCBUSY_GENCTRL10_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL11_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL11) >> GCLK_SYNCBUSY_GENCTRL11_Pos; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Gclk *)hw)->SYNCBUSY.reg; +} + +static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + return ((Gclk *)hw)->CTRLA.reg; +} + +static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_GENEN; + tmp |= value << GCLK_GENCTRL_GENEN_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_IDC; + tmp |= value << GCLK_GENCTRL_IDC_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OOV; + tmp |= value << GCLK_GENCTRL_OOV_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OE; + tmp |= value << GCLK_GENCTRL_OE_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIVSEL; + tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_RUNSTDBY; + tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_SRC_Msk; + tmp |= GCLK_GENCTRL_SRC(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIV_Msk; + tmp |= GCLK_GENCTRL_DIV(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + return ((Gclk *)hw)->GENCTRL[index].reg; +} + +static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_CHEN; + tmp |= value << GCLK_PCHCTRL_CHEN_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_WRTLOCK; + tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_GEN_Msk; + tmp |= GCLK_PCHCTRL_GEN(data); + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Gclk *)hw)->PCHCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GCLK_E54_H_INCLUDED */ +#endif /* _SAME54_GCLK_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_gmac_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_gmac_e54.h new file mode 100644 index 0000000..2875061 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_gmac_e54.h @@ -0,0 +1,3766 @@ +/** + * \file + * + * \brief SAM GMAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_GMAC_COMPONENT_ +#ifndef _HRI_GMAC_E54_H_INCLUDED_ +#define _HRI_GMAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GMAC_CRITICAL_SECTIONS) +#define GMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GMAC_CRITICAL_SECTION_ENTER() +#define GMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gmac_ae_reg_t; +typedef uint32_t hri_gmac_bcfr_reg_t; +typedef uint32_t hri_gmac_bcft_reg_t; +typedef uint32_t hri_gmac_bfr64_reg_t; +typedef uint32_t hri_gmac_bft64_reg_t; +typedef uint32_t hri_gmac_cse_reg_t; +typedef uint32_t hri_gmac_dcfgr_reg_t; +typedef uint32_t hri_gmac_dtf_reg_t; +typedef uint32_t hri_gmac_ec_reg_t; +typedef uint32_t hri_gmac_efrn_reg_t; +typedef uint32_t hri_gmac_efrsh_reg_t; +typedef uint32_t hri_gmac_efrsl_reg_t; +typedef uint32_t hri_gmac_eftn_reg_t; +typedef uint32_t hri_gmac_eftsh_reg_t; +typedef uint32_t hri_gmac_eftsl_reg_t; +typedef uint32_t hri_gmac_fcse_reg_t; +typedef uint32_t hri_gmac_fr_reg_t; +typedef uint32_t hri_gmac_ft_reg_t; +typedef uint32_t hri_gmac_gtbft1518_reg_t; +typedef uint32_t hri_gmac_hrb_reg_t; +typedef uint32_t hri_gmac_hrt_reg_t; +typedef uint32_t hri_gmac_ihce_reg_t; +typedef uint32_t hri_gmac_imr_reg_t; +typedef uint32_t hri_gmac_ipgs_reg_t; +typedef uint32_t hri_gmac_isr_reg_t; +typedef uint32_t hri_gmac_jr_reg_t; +typedef uint32_t hri_gmac_lc_reg_t; +typedef uint32_t hri_gmac_lffe_reg_t; +typedef uint32_t hri_gmac_man_reg_t; +typedef uint32_t hri_gmac_mcf_reg_t; +typedef uint32_t hri_gmac_mfr_reg_t; +typedef uint32_t hri_gmac_mft_reg_t; +typedef uint32_t hri_gmac_ncfgr_reg_t; +typedef uint32_t hri_gmac_ncr_reg_t; +typedef uint32_t hri_gmac_nsc_reg_t; +typedef uint32_t hri_gmac_nsr_reg_t; +typedef uint32_t hri_gmac_ofr_reg_t; +typedef uint32_t hri_gmac_orhi_reg_t; +typedef uint32_t hri_gmac_orlo_reg_t; +typedef uint32_t hri_gmac_othi_reg_t; +typedef uint32_t hri_gmac_otlo_reg_t; +typedef uint32_t hri_gmac_pefrn_reg_t; +typedef uint32_t hri_gmac_pefrsh_reg_t; +typedef uint32_t hri_gmac_pefrsl_reg_t; +typedef uint32_t hri_gmac_peftn_reg_t; +typedef uint32_t hri_gmac_peftsh_reg_t; +typedef uint32_t hri_gmac_peftsl_reg_t; +typedef uint32_t hri_gmac_pfr_reg_t; +typedef uint32_t hri_gmac_pft_reg_t; +typedef uint32_t hri_gmac_rbqb_reg_t; +typedef uint32_t hri_gmac_rjfml_reg_t; +typedef uint32_t hri_gmac_rlpiti_reg_t; +typedef uint32_t hri_gmac_rlpitr_reg_t; +typedef uint32_t hri_gmac_roe_reg_t; +typedef uint32_t hri_gmac_rpq_reg_t; +typedef uint32_t hri_gmac_rpsf_reg_t; +typedef uint32_t hri_gmac_rre_reg_t; +typedef uint32_t hri_gmac_rse_reg_t; +typedef uint32_t hri_gmac_rsr_reg_t; +typedef uint32_t hri_gmac_sab_reg_t; +typedef uint32_t hri_gmac_samb1_reg_t; +typedef uint32_t hri_gmac_samt1_reg_t; +typedef uint32_t hri_gmac_sat_reg_t; +typedef uint32_t hri_gmac_scf_reg_t; +typedef uint32_t hri_gmac_sch_reg_t; +typedef uint32_t hri_gmac_scl_reg_t; +typedef uint32_t hri_gmac_svlan_reg_t; +typedef uint32_t hri_gmac_ta_reg_t; +typedef uint32_t hri_gmac_tbfr1023_reg_t; +typedef uint32_t hri_gmac_tbfr127_reg_t; +typedef uint32_t hri_gmac_tbfr1518_reg_t; +typedef uint32_t hri_gmac_tbfr255_reg_t; +typedef uint32_t hri_gmac_tbfr511_reg_t; +typedef uint32_t hri_gmac_tbft1023_reg_t; +typedef uint32_t hri_gmac_tbft127_reg_t; +typedef uint32_t hri_gmac_tbft1518_reg_t; +typedef uint32_t hri_gmac_tbft255_reg_t; +typedef uint32_t hri_gmac_tbft511_reg_t; +typedef uint32_t hri_gmac_tbqb_reg_t; +typedef uint32_t hri_gmac_tce_reg_t; +typedef uint32_t hri_gmac_ti_reg_t; +typedef uint32_t hri_gmac_tidm_reg_t; +typedef uint32_t hri_gmac_tisubn_reg_t; +typedef uint32_t hri_gmac_tlpiti_reg_t; +typedef uint32_t hri_gmac_tlpitr_reg_t; +typedef uint32_t hri_gmac_tmxbfr_reg_t; +typedef uint32_t hri_gmac_tn_reg_t; +typedef uint32_t hri_gmac_tpfcp_reg_t; +typedef uint32_t hri_gmac_tpq_reg_t; +typedef uint32_t hri_gmac_tpsf_reg_t; +typedef uint32_t hri_gmac_tsh_reg_t; +typedef uint32_t hri_gmac_tsl_reg_t; +typedef uint32_t hri_gmac_tsr_reg_t; +typedef uint32_t hri_gmac_tssn_reg_t; +typedef uint32_t hri_gmac_tsssl_reg_t; +typedef uint32_t hri_gmac_tur_reg_t; +typedef uint32_t hri_gmac_uce_reg_t; +typedef uint32_t hri_gmac_ufr_reg_t; +typedef uint32_t hri_gmac_ur_reg_t; +typedef uint32_t hri_gmac_wol_reg_t; +typedef uint32_t hri_gmacsa_sab_reg_t; +typedef uint32_t hri_gmacsa_sat_reg_t; + +static inline void hri_gmacsa_set_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmacsa_get_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSa *)hw)->SAB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmacsa_write_SAB_reg(const void *const hw, hri_gmac_sab_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_clear_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_toggle_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmacsa_read_SAB_reg(const void *const hw) +{ + return ((GmacSa *)hw)->SAB.reg; +} + +static inline void hri_gmacsa_set_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmacsa_get_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSa *)hw)->SAT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmacsa_write_SAT_reg(const void *const hw, hri_gmac_sat_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_clear_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_toggle_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmacsa_read_SAT_reg(const void *const hw) +{ + return ((GmacSa *)hw)->SAT.reg; +} + +static inline void hri_gmac_set_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmac_get_SAB_reg(const void *const hw, uint8_t submodule_index, + hri_gmac_sab_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->Sa[submodule_index].SAB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmac_read_SAB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Gmac *)hw)->Sa[submodule_index].SAB.reg; +} + +static inline void hri_gmac_set_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmac_get_SAT_reg(const void *const hw, uint8_t submodule_index, + hri_gmac_sat_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->Sa[submodule_index].SAT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmac_read_SAT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Gmac *)hw)->Sa[submodule_index].SAT.reg; +} + +static inline void hri_gmac_set_IMR_MFS_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_MFS; +} + +static inline bool hri_gmac_get_IMR_MFS_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_MFS) >> GMAC_IMR_MFS_Pos; +} + +static inline void hri_gmac_write_IMR_MFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_MFS; + } +} + +static inline void hri_gmac_clear_IMR_MFS_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS; +} + +static inline void hri_gmac_set_IMR_RCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP; +} + +static inline bool hri_gmac_get_IMR_RCOMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RCOMP) >> GMAC_IMR_RCOMP_Pos; +} + +static inline void hri_gmac_write_IMR_RCOMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP; + } +} + +static inline void hri_gmac_clear_IMR_RCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP; +} + +static inline void hri_gmac_set_IMR_RXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR; +} + +static inline bool hri_gmac_get_IMR_RXUBR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RXUBR) >> GMAC_IMR_RXUBR_Pos; +} + +static inline void hri_gmac_write_IMR_RXUBR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR; + } +} + +static inline void hri_gmac_clear_IMR_RXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR; +} + +static inline void hri_gmac_set_IMR_TXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR; +} + +static inline bool hri_gmac_get_IMR_TXUBR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TXUBR) >> GMAC_IMR_TXUBR_Pos; +} + +static inline void hri_gmac_write_IMR_TXUBR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR; + } +} + +static inline void hri_gmac_clear_IMR_TXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR; +} + +static inline void hri_gmac_set_IMR_TUR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TUR; +} + +static inline bool hri_gmac_get_IMR_TUR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TUR) >> GMAC_IMR_TUR_Pos; +} + +static inline void hri_gmac_write_IMR_TUR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TUR; + } +} + +static inline void hri_gmac_clear_IMR_TUR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR; +} + +static inline void hri_gmac_set_IMR_RLEX_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX; +} + +static inline bool hri_gmac_get_IMR_RLEX_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RLEX) >> GMAC_IMR_RLEX_Pos; +} + +static inline void hri_gmac_write_IMR_RLEX_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX; + } +} + +static inline void hri_gmac_clear_IMR_RLEX_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX; +} + +static inline void hri_gmac_set_IMR_TFC_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TFC; +} + +static inline bool hri_gmac_get_IMR_TFC_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TFC) >> GMAC_IMR_TFC_Pos; +} + +static inline void hri_gmac_write_IMR_TFC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TFC; + } +} + +static inline void hri_gmac_clear_IMR_TFC_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC; +} + +static inline void hri_gmac_set_IMR_TCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP; +} + +static inline bool hri_gmac_get_IMR_TCOMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TCOMP) >> GMAC_IMR_TCOMP_Pos; +} + +static inline void hri_gmac_write_IMR_TCOMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP; + } +} + +static inline void hri_gmac_clear_IMR_TCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP; +} + +static inline void hri_gmac_set_IMR_ROVR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR; +} + +static inline bool hri_gmac_get_IMR_ROVR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_ROVR) >> GMAC_IMR_ROVR_Pos; +} + +static inline void hri_gmac_write_IMR_ROVR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR; + } +} + +static inline void hri_gmac_clear_IMR_ROVR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR; +} + +static inline void hri_gmac_set_IMR_HRESP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP; +} + +static inline bool hri_gmac_get_IMR_HRESP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_HRESP) >> GMAC_IMR_HRESP_Pos; +} + +static inline void hri_gmac_write_IMR_HRESP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP; + } +} + +static inline void hri_gmac_clear_IMR_HRESP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP; +} + +static inline void hri_gmac_set_IMR_PFNZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ; +} + +static inline bool hri_gmac_get_IMR_PFNZ_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFNZ) >> GMAC_IMR_PFNZ_Pos; +} + +static inline void hri_gmac_write_IMR_PFNZ_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ; + } +} + +static inline void hri_gmac_clear_IMR_PFNZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ; +} + +static inline void hri_gmac_set_IMR_PTZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ; +} + +static inline bool hri_gmac_get_IMR_PTZ_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PTZ) >> GMAC_IMR_PTZ_Pos; +} + +static inline void hri_gmac_write_IMR_PTZ_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ; + } +} + +static inline void hri_gmac_clear_IMR_PTZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ; +} + +static inline void hri_gmac_set_IMR_PFTR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR; +} + +static inline bool hri_gmac_get_IMR_PFTR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFTR) >> GMAC_IMR_PFTR_Pos; +} + +static inline void hri_gmac_write_IMR_PFTR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR; + } +} + +static inline void hri_gmac_clear_IMR_PFTR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR; +} + +static inline void hri_gmac_set_IMR_EXINT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT; +} + +static inline bool hri_gmac_get_IMR_EXINT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_EXINT) >> GMAC_IMR_EXINT_Pos; +} + +static inline void hri_gmac_write_IMR_EXINT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT; + } +} + +static inline void hri_gmac_clear_IMR_EXINT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT; +} + +static inline void hri_gmac_set_IMR_DRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR; +} + +static inline bool hri_gmac_get_IMR_DRQFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFR) >> GMAC_IMR_DRQFR_Pos; +} + +static inline void hri_gmac_write_IMR_DRQFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR; + } +} + +static inline void hri_gmac_clear_IMR_DRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR; +} + +static inline void hri_gmac_set_IMR_SFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFR; +} + +static inline bool hri_gmac_get_IMR_SFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFR) >> GMAC_IMR_SFR_Pos; +} + +static inline void hri_gmac_write_IMR_SFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFR; + } +} + +static inline void hri_gmac_clear_IMR_SFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR; +} + +static inline void hri_gmac_set_IMR_DRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT; +} + +static inline bool hri_gmac_get_IMR_DRQFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFT) >> GMAC_IMR_DRQFT_Pos; +} + +static inline void hri_gmac_write_IMR_DRQFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT; + } +} + +static inline void hri_gmac_clear_IMR_DRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT; +} + +static inline void hri_gmac_set_IMR_SFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFT; +} + +static inline bool hri_gmac_get_IMR_SFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFT) >> GMAC_IMR_SFT_Pos; +} + +static inline void hri_gmac_write_IMR_SFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFT; + } +} + +static inline void hri_gmac_clear_IMR_SFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT; +} + +static inline void hri_gmac_set_IMR_PDRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR; +} + +static inline bool hri_gmac_get_IMR_PDRQFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFR) >> GMAC_IMR_PDRQFR_Pos; +} + +static inline void hri_gmac_write_IMR_PDRQFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR; + } +} + +static inline void hri_gmac_clear_IMR_PDRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR; +} + +static inline void hri_gmac_set_IMR_PDRSFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR; +} + +static inline bool hri_gmac_get_IMR_PDRSFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFR) >> GMAC_IMR_PDRSFR_Pos; +} + +static inline void hri_gmac_write_IMR_PDRSFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR; + } +} + +static inline void hri_gmac_clear_IMR_PDRSFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR; +} + +static inline void hri_gmac_set_IMR_PDRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT; +} + +static inline bool hri_gmac_get_IMR_PDRQFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFT) >> GMAC_IMR_PDRQFT_Pos; +} + +static inline void hri_gmac_write_IMR_PDRQFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT; + } +} + +static inline void hri_gmac_clear_IMR_PDRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT; +} + +static inline void hri_gmac_set_IMR_PDRSFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT; +} + +static inline bool hri_gmac_get_IMR_PDRSFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFT) >> GMAC_IMR_PDRSFT_Pos; +} + +static inline void hri_gmac_write_IMR_PDRSFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT; + } +} + +static inline void hri_gmac_clear_IMR_PDRSFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT; +} + +static inline void hri_gmac_set_IMR_SRI_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_SRI; +} + +static inline bool hri_gmac_get_IMR_SRI_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SRI) >> GMAC_IMR_SRI_Pos; +} + +static inline void hri_gmac_write_IMR_SRI_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_SRI; + } +} + +static inline void hri_gmac_clear_IMR_SRI_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI; +} + +static inline void hri_gmac_set_IMR_WOL_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_WOL; +} + +static inline bool hri_gmac_get_IMR_WOL_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_WOL) >> GMAC_IMR_WOL_Pos; +} + +static inline void hri_gmac_write_IMR_WOL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_WOL; + } +} + +static inline void hri_gmac_clear_IMR_WOL_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL; +} + +static inline void hri_gmac_set_IMR_TSUCMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP; +} + +static inline bool hri_gmac_get_IMR_TSUCMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TSUCMP) >> GMAC_IMR_TSUCMP_Pos; +} + +static inline void hri_gmac_write_IMR_TSUCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP; + } +} + +static inline void hri_gmac_clear_IMR_TSUCMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP; +} + +static inline void hri_gmac_set_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + ((Gmac *)hw)->IER.reg = mask; +} + +static inline hri_gmac_imr_reg_t hri_gmac_get_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->IMR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_imr_reg_t hri_gmac_read_IMR_reg(const void *const hw) +{ + return ((Gmac *)hw)->IMR.reg; +} + +static inline void hri_gmac_write_IMR_reg(const void *const hw, hri_gmac_imr_reg_t data) +{ + ((Gmac *)hw)->IER.reg = data; + ((Gmac *)hw)->IDR.reg = ~data; +} + +static inline void hri_gmac_clear_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + ((Gmac *)hw)->IDR.reg = mask; +} + +static inline bool hri_gmac_get_NSR_MDIO_bit(const void *const hw) +{ + return (((Gmac *)hw)->NSR.reg & GMAC_NSR_MDIO) >> GMAC_NSR_MDIO_Pos; +} + +static inline bool hri_gmac_get_NSR_IDLE_bit(const void *const hw) +{ + return (((Gmac *)hw)->NSR.reg & GMAC_NSR_IDLE) >> GMAC_NSR_IDLE_Pos; +} + +static inline hri_gmac_nsr_reg_t hri_gmac_get_NSR_reg(const void *const hw, hri_gmac_nsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_nsr_reg_t hri_gmac_read_NSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->NSR.reg; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_RPQ_bf(const void *const hw, hri_gmac_rpq_reg_t mask) +{ + return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ(mask)) >> GMAC_RPQ_RPQ_Pos; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_RPQ_bf(const void *const hw) +{ + return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ_Msk) >> GMAC_RPQ_RPQ_Pos; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_reg(const void *const hw, hri_gmac_rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RPQ.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_reg(const void *const hw) +{ + return ((Gmac *)hw)->RPQ.reg; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_RUD_bf(const void *const hw, hri_gmac_eftsh_reg_t mask) +{ + return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD(mask)) >> GMAC_EFTSH_RUD_Pos; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD_Msk) >> GMAC_EFTSH_RUD_Pos; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_reg(const void *const hw, hri_gmac_eftsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFTSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFTSH.reg; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_RUD_bf(const void *const hw, hri_gmac_efrsh_reg_t mask) +{ + return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD(mask)) >> GMAC_EFRSH_RUD_Pos; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD_Msk) >> GMAC_EFRSH_RUD_Pos; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_reg(const void *const hw, hri_gmac_efrsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFRSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFRSH.reg; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_RUD_bf(const void *const hw, hri_gmac_peftsh_reg_t mask) +{ + return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD(mask)) >> GMAC_PEFTSH_RUD_Pos; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD_Msk) >> GMAC_PEFTSH_RUD_Pos; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_reg(const void *const hw, hri_gmac_peftsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFTSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFTSH.reg; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_RUD_bf(const void *const hw, hri_gmac_pefrsh_reg_t mask) +{ + return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD(mask)) >> GMAC_PEFRSH_RUD_Pos; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD_Msk) >> GMAC_PEFRSH_RUD_Pos; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_reg(const void *const hw, hri_gmac_pefrsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFRSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFRSH.reg; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_TXO_bf(const void *const hw, hri_gmac_otlo_reg_t mask) +{ + return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO(mask)) >> GMAC_OTLO_TXO_Pos; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_TXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO_Msk) >> GMAC_OTLO_TXO_Pos; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_reg(const void *const hw, hri_gmac_otlo_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->OTLO.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_reg(const void *const hw) +{ + return ((Gmac *)hw)->OTLO.reg; +} + +static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_TXO_bf(const void *const hw, hri_gmac_othi_reg_t mask) +{ + return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO(mask)) >> GMAC_OTHI_TXO_Pos; +} + +static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_TXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO_Msk) >> GMAC_OTHI_TXO_Pos; +} + +static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_reg(const void *const hw, hri_gmac_othi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->OTHI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_reg(const void *const hw) +{ + return ((Gmac *)hw)->OTHI.reg; +} + +static inline hri_gmac_ft_reg_t hri_gmac_get_FT_FTX_bf(const void *const hw, hri_gmac_ft_reg_t mask) +{ + return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX(mask)) >> GMAC_FT_FTX_Pos; +} + +static inline hri_gmac_ft_reg_t hri_gmac_read_FT_FTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX_Msk) >> GMAC_FT_FTX_Pos; +} + +static inline hri_gmac_ft_reg_t hri_gmac_get_FT_reg(const void *const hw, hri_gmac_ft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->FT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ft_reg_t hri_gmac_read_FT_reg(const void *const hw) +{ + return ((Gmac *)hw)->FT.reg; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_BFTX_bf(const void *const hw, hri_gmac_bcft_reg_t mask) +{ + return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX(mask)) >> GMAC_BCFT_BFTX_Pos; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_BFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX_Msk) >> GMAC_BCFT_BFTX_Pos; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_reg(const void *const hw, hri_gmac_bcft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BCFT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->BCFT.reg; +} + +static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_MFTX_bf(const void *const hw, hri_gmac_mft_reg_t mask) +{ + return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX(mask)) >> GMAC_MFT_MFTX_Pos; +} + +static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_MFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX_Msk) >> GMAC_MFT_MFTX_Pos; +} + +static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_reg(const void *const hw, hri_gmac_mft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MFT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->MFT.reg; +} + +static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_PFTX_bf(const void *const hw, hri_gmac_pft_reg_t mask) +{ + return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX(mask)) >> GMAC_PFT_PFTX_Pos; +} + +static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_PFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX_Msk) >> GMAC_PFT_PFTX_Pos; +} + +static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_reg(const void *const hw, hri_gmac_pft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PFT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->PFT.reg; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_NFTX_bf(const void *const hw, hri_gmac_bft64_reg_t mask) +{ + return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX(mask)) >> GMAC_BFT64_NFTX_Pos; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX_Msk) >> GMAC_BFT64_NFTX_Pos; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_reg(const void *const hw, hri_gmac_bft64_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BFT64.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_reg(const void *const hw) +{ + return ((Gmac *)hw)->BFT64.reg; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_NFTX_bf(const void *const hw, hri_gmac_tbft127_reg_t mask) +{ + return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX(mask)) >> GMAC_TBFT127_NFTX_Pos; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX_Msk) >> GMAC_TBFT127_NFTX_Pos; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_reg(const void *const hw, hri_gmac_tbft127_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT127.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT127.reg; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_NFTX_bf(const void *const hw, hri_gmac_tbft255_reg_t mask) +{ + return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX(mask)) >> GMAC_TBFT255_NFTX_Pos; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX_Msk) >> GMAC_TBFT255_NFTX_Pos; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_reg(const void *const hw, hri_gmac_tbft255_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT255.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT255.reg; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_NFTX_bf(const void *const hw, hri_gmac_tbft511_reg_t mask) +{ + return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX(mask)) >> GMAC_TBFT511_NFTX_Pos; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX_Msk) >> GMAC_TBFT511_NFTX_Pos; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_reg(const void *const hw, hri_gmac_tbft511_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT511.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT511.reg; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_NFTX_bf(const void *const hw, hri_gmac_tbft1023_reg_t mask) +{ + return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX(mask)) >> GMAC_TBFT1023_NFTX_Pos; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX_Msk) >> GMAC_TBFT1023_NFTX_Pos; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_reg(const void *const hw, hri_gmac_tbft1023_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT1023.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT1023.reg; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_NFTX_bf(const void *const hw, hri_gmac_tbft1518_reg_t mask) +{ + return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX(mask)) >> GMAC_TBFT1518_NFTX_Pos; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX_Msk) >> GMAC_TBFT1518_NFTX_Pos; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_reg(const void *const hw, hri_gmac_tbft1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT1518.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT1518.reg; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_NFTX_bf(const void *const hw, + hri_gmac_gtbft1518_reg_t mask) +{ + return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX(mask)) >> GMAC_GTBFT1518_NFTX_Pos; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX_Msk) >> GMAC_GTBFT1518_NFTX_Pos; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_reg(const void *const hw, hri_gmac_gtbft1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GTBFT1518.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->GTBFT1518.reg; +} + +static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_TXUNR_bf(const void *const hw, hri_gmac_tur_reg_t mask) +{ + return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR(mask)) >> GMAC_TUR_TXUNR_Pos; +} + +static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_TXUNR_bf(const void *const hw) +{ + return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR_Msk) >> GMAC_TUR_TXUNR_Pos; +} + +static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_reg(const void *const hw, hri_gmac_tur_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TUR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TUR.reg; +} + +static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_SCOL_bf(const void *const hw, hri_gmac_scf_reg_t mask) +{ + return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL(mask)) >> GMAC_SCF_SCOL_Pos; +} + +static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_SCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL_Msk) >> GMAC_SCF_SCOL_Pos; +} + +static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_reg(const void *const hw, hri_gmac_scf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SCF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_reg(const void *const hw) +{ + return ((Gmac *)hw)->SCF.reg; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_MCOL_bf(const void *const hw, hri_gmac_mcf_reg_t mask) +{ + return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL(mask)) >> GMAC_MCF_MCOL_Pos; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_MCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL_Msk) >> GMAC_MCF_MCOL_Pos; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_reg(const void *const hw, hri_gmac_mcf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MCF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_reg(const void *const hw) +{ + return ((Gmac *)hw)->MCF.reg; +} + +static inline hri_gmac_ec_reg_t hri_gmac_get_EC_XCOL_bf(const void *const hw, hri_gmac_ec_reg_t mask) +{ + return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL(mask)) >> GMAC_EC_XCOL_Pos; +} + +static inline hri_gmac_ec_reg_t hri_gmac_read_EC_XCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL_Msk) >> GMAC_EC_XCOL_Pos; +} + +static inline hri_gmac_ec_reg_t hri_gmac_get_EC_reg(const void *const hw, hri_gmac_ec_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ec_reg_t hri_gmac_read_EC_reg(const void *const hw) +{ + return ((Gmac *)hw)->EC.reg; +} + +static inline hri_gmac_lc_reg_t hri_gmac_get_LC_LCOL_bf(const void *const hw, hri_gmac_lc_reg_t mask) +{ + return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL(mask)) >> GMAC_LC_LCOL_Pos; +} + +static inline hri_gmac_lc_reg_t hri_gmac_read_LC_LCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL_Msk) >> GMAC_LC_LCOL_Pos; +} + +static inline hri_gmac_lc_reg_t hri_gmac_get_LC_reg(const void *const hw, hri_gmac_lc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->LC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_lc_reg_t hri_gmac_read_LC_reg(const void *const hw) +{ + return ((Gmac *)hw)->LC.reg; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_DEFT_bf(const void *const hw, hri_gmac_dtf_reg_t mask) +{ + return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT(mask)) >> GMAC_DTF_DEFT_Pos; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_DEFT_bf(const void *const hw) +{ + return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT_Msk) >> GMAC_DTF_DEFT_Pos; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_reg(const void *const hw, hri_gmac_dtf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->DTF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_reg(const void *const hw) +{ + return ((Gmac *)hw)->DTF.reg; +} + +static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_CSR_bf(const void *const hw, hri_gmac_cse_reg_t mask) +{ + return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR(mask)) >> GMAC_CSE_CSR_Pos; +} + +static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_CSR_bf(const void *const hw) +{ + return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR_Msk) >> GMAC_CSE_CSR_Pos; +} + +static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_reg(const void *const hw, hri_gmac_cse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->CSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->CSE.reg; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_RXO_bf(const void *const hw, hri_gmac_orlo_reg_t mask) +{ + return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO(mask)) >> GMAC_ORLO_RXO_Pos; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_RXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO_Msk) >> GMAC_ORLO_RXO_Pos; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_reg(const void *const hw, hri_gmac_orlo_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ORLO.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_reg(const void *const hw) +{ + return ((Gmac *)hw)->ORLO.reg; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_RXO_bf(const void *const hw, hri_gmac_orhi_reg_t mask) +{ + return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO(mask)) >> GMAC_ORHI_RXO_Pos; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_RXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO_Msk) >> GMAC_ORHI_RXO_Pos; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_reg(const void *const hw, hri_gmac_orhi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ORHI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_reg(const void *const hw) +{ + return ((Gmac *)hw)->ORHI.reg; +} + +static inline hri_gmac_fr_reg_t hri_gmac_get_FR_FRX_bf(const void *const hw, hri_gmac_fr_reg_t mask) +{ + return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX(mask)) >> GMAC_FR_FRX_Pos; +} + +static inline hri_gmac_fr_reg_t hri_gmac_read_FR_FRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX_Msk) >> GMAC_FR_FRX_Pos; +} + +static inline hri_gmac_fr_reg_t hri_gmac_get_FR_reg(const void *const hw, hri_gmac_fr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->FR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_fr_reg_t hri_gmac_read_FR_reg(const void *const hw) +{ + return ((Gmac *)hw)->FR.reg; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_BFRX_bf(const void *const hw, hri_gmac_bcfr_reg_t mask) +{ + return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX(mask)) >> GMAC_BCFR_BFRX_Pos; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_BFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX_Msk) >> GMAC_BCFR_BFRX_Pos; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_reg(const void *const hw, hri_gmac_bcfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BCFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->BCFR.reg; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_MFRX_bf(const void *const hw, hri_gmac_mfr_reg_t mask) +{ + return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX(mask)) >> GMAC_MFR_MFRX_Pos; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_MFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX_Msk) >> GMAC_MFR_MFRX_Pos; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_reg(const void *const hw, hri_gmac_mfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->MFR.reg; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_PFRX_bf(const void *const hw, hri_gmac_pfr_reg_t mask) +{ + return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX(mask)) >> GMAC_PFR_PFRX_Pos; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_PFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX_Msk) >> GMAC_PFR_PFRX_Pos; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_reg(const void *const hw, hri_gmac_pfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->PFR.reg; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_NFRX_bf(const void *const hw, hri_gmac_bfr64_reg_t mask) +{ + return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX(mask)) >> GMAC_BFR64_NFRX_Pos; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX_Msk) >> GMAC_BFR64_NFRX_Pos; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_reg(const void *const hw, hri_gmac_bfr64_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BFR64.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_reg(const void *const hw) +{ + return ((Gmac *)hw)->BFR64.reg; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_NFRX_bf(const void *const hw, hri_gmac_tbfr127_reg_t mask) +{ + return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX(mask)) >> GMAC_TBFR127_NFRX_Pos; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX_Msk) >> GMAC_TBFR127_NFRX_Pos; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_reg(const void *const hw, hri_gmac_tbfr127_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR127.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR127.reg; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_NFRX_bf(const void *const hw, hri_gmac_tbfr255_reg_t mask) +{ + return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX(mask)) >> GMAC_TBFR255_NFRX_Pos; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX_Msk) >> GMAC_TBFR255_NFRX_Pos; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_reg(const void *const hw, hri_gmac_tbfr255_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR255.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR255.reg; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_NFRX_bf(const void *const hw, hri_gmac_tbfr511_reg_t mask) +{ + return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX(mask)) >> GMAC_TBFR511_NFRX_Pos; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX_Msk) >> GMAC_TBFR511_NFRX_Pos; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_reg(const void *const hw, hri_gmac_tbfr511_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR511.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR511.reg; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_NFRX_bf(const void *const hw, hri_gmac_tbfr1023_reg_t mask) +{ + return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX(mask)) >> GMAC_TBFR1023_NFRX_Pos; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX_Msk) >> GMAC_TBFR1023_NFRX_Pos; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_reg(const void *const hw, hri_gmac_tbfr1023_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR1023.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR1023.reg; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_NFRX_bf(const void *const hw, hri_gmac_tbfr1518_reg_t mask) +{ + return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX(mask)) >> GMAC_TBFR1518_NFRX_Pos; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX_Msk) >> GMAC_TBFR1518_NFRX_Pos; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_reg(const void *const hw, hri_gmac_tbfr1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR1518.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR1518.reg; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_NFRX_bf(const void *const hw, hri_gmac_tmxbfr_reg_t mask) +{ + return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX(mask)) >> GMAC_TMXBFR_NFRX_Pos; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX_Msk) >> GMAC_TMXBFR_NFRX_Pos; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_reg(const void *const hw, hri_gmac_tmxbfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TMXBFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TMXBFR.reg; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_UFRX_bf(const void *const hw, hri_gmac_ufr_reg_t mask) +{ + return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX(mask)) >> GMAC_UFR_UFRX_Pos; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_UFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX_Msk) >> GMAC_UFR_UFRX_Pos; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_reg(const void *const hw, hri_gmac_ufr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->UFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->UFR.reg; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_OFRX_bf(const void *const hw, hri_gmac_ofr_reg_t mask) +{ + return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX(mask)) >> GMAC_OFR_OFRX_Pos; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_OFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX_Msk) >> GMAC_OFR_OFRX_Pos; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_reg(const void *const hw, hri_gmac_ofr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->OFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->OFR.reg; +} + +static inline hri_gmac_jr_reg_t hri_gmac_get_JR_JRX_bf(const void *const hw, hri_gmac_jr_reg_t mask) +{ + return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX(mask)) >> GMAC_JR_JRX_Pos; +} + +static inline hri_gmac_jr_reg_t hri_gmac_read_JR_JRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX_Msk) >> GMAC_JR_JRX_Pos; +} + +static inline hri_gmac_jr_reg_t hri_gmac_get_JR_reg(const void *const hw, hri_gmac_jr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->JR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_jr_reg_t hri_gmac_read_JR_reg(const void *const hw) +{ + return ((Gmac *)hw)->JR.reg; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_FCKR_bf(const void *const hw, hri_gmac_fcse_reg_t mask) +{ + return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR(mask)) >> GMAC_FCSE_FCKR_Pos; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_FCKR_bf(const void *const hw) +{ + return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR_Msk) >> GMAC_FCSE_FCKR_Pos; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_reg(const void *const hw, hri_gmac_fcse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->FCSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->FCSE.reg; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_LFER_bf(const void *const hw, hri_gmac_lffe_reg_t mask) +{ + return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER(mask)) >> GMAC_LFFE_LFER_Pos; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_LFER_bf(const void *const hw) +{ + return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER_Msk) >> GMAC_LFFE_LFER_Pos; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_reg(const void *const hw, hri_gmac_lffe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->LFFE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_reg(const void *const hw) +{ + return ((Gmac *)hw)->LFFE.reg; +} + +static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_RXSE_bf(const void *const hw, hri_gmac_rse_reg_t mask) +{ + return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE(mask)) >> GMAC_RSE_RXSE_Pos; +} + +static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_RXSE_bf(const void *const hw) +{ + return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE_Msk) >> GMAC_RSE_RXSE_Pos; +} + +static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_reg(const void *const hw, hri_gmac_rse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->RSE.reg; +} + +static inline hri_gmac_ae_reg_t hri_gmac_get_AE_AER_bf(const void *const hw, hri_gmac_ae_reg_t mask) +{ + return (((Gmac *)hw)->AE.reg & GMAC_AE_AER(mask)) >> GMAC_AE_AER_Pos; +} + +static inline hri_gmac_ae_reg_t hri_gmac_read_AE_AER_bf(const void *const hw) +{ + return (((Gmac *)hw)->AE.reg & GMAC_AE_AER_Msk) >> GMAC_AE_AER_Pos; +} + +static inline hri_gmac_ae_reg_t hri_gmac_get_AE_reg(const void *const hw, hri_gmac_ae_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->AE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ae_reg_t hri_gmac_read_AE_reg(const void *const hw) +{ + return ((Gmac *)hw)->AE.reg; +} + +static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_RXRER_bf(const void *const hw, hri_gmac_rre_reg_t mask) +{ + return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER(mask)) >> GMAC_RRE_RXRER_Pos; +} + +static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_RXRER_bf(const void *const hw) +{ + return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER_Msk) >> GMAC_RRE_RXRER_Pos; +} + +static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_reg(const void *const hw, hri_gmac_rre_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RRE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_reg(const void *const hw) +{ + return ((Gmac *)hw)->RRE.reg; +} + +static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_RXOVR_bf(const void *const hw, hri_gmac_roe_reg_t mask) +{ + return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR(mask)) >> GMAC_ROE_RXOVR_Pos; +} + +static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_RXOVR_bf(const void *const hw) +{ + return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR_Msk) >> GMAC_ROE_RXOVR_Pos; +} + +static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_reg(const void *const hw, hri_gmac_roe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ROE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_reg(const void *const hw) +{ + return ((Gmac *)hw)->ROE.reg; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_HCKER_bf(const void *const hw, hri_gmac_ihce_reg_t mask) +{ + return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER(mask)) >> GMAC_IHCE_HCKER_Pos; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_HCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER_Msk) >> GMAC_IHCE_HCKER_Pos; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_reg(const void *const hw, hri_gmac_ihce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->IHCE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->IHCE.reg; +} + +static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_TCKER_bf(const void *const hw, hri_gmac_tce_reg_t mask) +{ + return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER(mask)) >> GMAC_TCE_TCKER_Pos; +} + +static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_TCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER_Msk) >> GMAC_TCE_TCKER_Pos; +} + +static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_reg(const void *const hw, hri_gmac_tce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TCE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->TCE.reg; +} + +static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_UCKER_bf(const void *const hw, hri_gmac_uce_reg_t mask) +{ + return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER(mask)) >> GMAC_UCE_UCKER_Pos; +} + +static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_UCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER_Msk) >> GMAC_UCE_UCKER_Pos; +} + +static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_reg(const void *const hw, hri_gmac_uce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->UCE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->UCE.reg; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_RUD_bf(const void *const hw, hri_gmac_eftsl_reg_t mask) +{ + return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD(mask)) >> GMAC_EFTSL_RUD_Pos; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD_Msk) >> GMAC_EFTSL_RUD_Pos; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_reg(const void *const hw, hri_gmac_eftsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFTSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFTSL.reg; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_RUD_bf(const void *const hw, hri_gmac_eftn_reg_t mask) +{ + return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD(mask)) >> GMAC_EFTN_RUD_Pos; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD_Msk) >> GMAC_EFTN_RUD_Pos; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_reg(const void *const hw, hri_gmac_eftn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFTN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFTN.reg; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_RUD_bf(const void *const hw, hri_gmac_efrsl_reg_t mask) +{ + return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD(mask)) >> GMAC_EFRSL_RUD_Pos; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD_Msk) >> GMAC_EFRSL_RUD_Pos; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_reg(const void *const hw, hri_gmac_efrsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFRSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFRSL.reg; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_RUD_bf(const void *const hw, hri_gmac_efrn_reg_t mask) +{ + return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD(mask)) >> GMAC_EFRN_RUD_Pos; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD_Msk) >> GMAC_EFRN_RUD_Pos; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_reg(const void *const hw, hri_gmac_efrn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFRN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFRN.reg; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_RUD_bf(const void *const hw, hri_gmac_peftsl_reg_t mask) +{ + return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD(mask)) >> GMAC_PEFTSL_RUD_Pos; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD_Msk) >> GMAC_PEFTSL_RUD_Pos; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_reg(const void *const hw, hri_gmac_peftsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFTSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFTSL.reg; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_RUD_bf(const void *const hw, hri_gmac_peftn_reg_t mask) +{ + return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD(mask)) >> GMAC_PEFTN_RUD_Pos; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD_Msk) >> GMAC_PEFTN_RUD_Pos; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_reg(const void *const hw, hri_gmac_peftn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFTN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFTN.reg; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_RUD_bf(const void *const hw, hri_gmac_pefrsl_reg_t mask) +{ + return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD(mask)) >> GMAC_PEFRSL_RUD_Pos; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD_Msk) >> GMAC_PEFRSL_RUD_Pos; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_reg(const void *const hw, hri_gmac_pefrsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFRSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFRSL.reg; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_RUD_bf(const void *const hw, hri_gmac_pefrn_reg_t mask) +{ + return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD(mask)) >> GMAC_PEFRN_RUD_Pos; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD_Msk) >> GMAC_PEFRN_RUD_Pos; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_reg(const void *const hw, hri_gmac_pefrn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFRN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFRN.reg; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_RLPITR_bf(const void *const hw, hri_gmac_rlpitr_reg_t mask) +{ + return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR(mask)) >> GMAC_RLPITR_RLPITR_Pos; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_RLPITR_bf(const void *const hw) +{ + return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR_Msk) >> GMAC_RLPITR_RLPITR_Pos; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_reg(const void *const hw, hri_gmac_rlpitr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RLPITR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_reg(const void *const hw) +{ + return ((Gmac *)hw)->RLPITR.reg; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_RLPITI_bf(const void *const hw, hri_gmac_rlpiti_reg_t mask) +{ + return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI(mask)) >> GMAC_RLPITI_RLPITI_Pos; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_RLPITI_bf(const void *const hw) +{ + return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI_Msk) >> GMAC_RLPITI_RLPITI_Pos; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_reg(const void *const hw, hri_gmac_rlpiti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RLPITI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_reg(const void *const hw) +{ + return ((Gmac *)hw)->RLPITI.reg; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_TLPITR_bf(const void *const hw, hri_gmac_tlpitr_reg_t mask) +{ + return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR(mask)) >> GMAC_TLPITR_TLPITR_Pos; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_TLPITR_bf(const void *const hw) +{ + return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR_Msk) >> GMAC_TLPITR_TLPITR_Pos; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_reg(const void *const hw, hri_gmac_tlpitr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TLPITR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TLPITR.reg; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_TLPITI_bf(const void *const hw, hri_gmac_tlpiti_reg_t mask) +{ + return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI(mask)) >> GMAC_TLPITI_TLPITI_Pos; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_TLPITI_bf(const void *const hw) +{ + return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI_Msk) >> GMAC_TLPITI_TLPITI_Pos; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_reg(const void *const hw, hri_gmac_tlpiti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TLPITI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_reg(const void *const hw) +{ + return ((Gmac *)hw)->TLPITI.reg; +} + +static inline void hri_gmac_set_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncr_reg_t hri_gmac_get_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncr_reg_t hri_gmac_read_NCR_reg(const void *const hw) +{ + return ((Gmac *)hw)->NCR.reg; +} + +static inline void hri_gmac_set_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_get_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NCFGR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_read_NCFGR_reg(const void *const hw) +{ + return ((Gmac *)hw)->NCFGR.reg; +} + +static inline void hri_gmac_set_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ur_reg_t hri_gmac_get_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->UR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_UR_reg(const void *const hw, hri_gmac_ur_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ur_reg_t hri_gmac_read_UR_reg(const void *const hw) +{ + return ((Gmac *)hw)->UR.reg; +} + +static inline void hri_gmac_set_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_get_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->DCFGR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_read_DCFGR_reg(const void *const hw) +{ + return ((Gmac *)hw)->DCFGR.reg; +} + +static inline void hri_gmac_set_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsr_reg_t hri_gmac_get_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsr_reg_t hri_gmac_read_TSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSR.reg; +} + +static inline void hri_gmac_set_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqb_reg_t hri_gmac_get_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RBQB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqb_reg_t hri_gmac_read_RBQB_reg(const void *const hw) +{ + return ((Gmac *)hw)->RBQB.reg; +} + +static inline void hri_gmac_set_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqb_reg_t hri_gmac_get_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBQB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqb_reg_t hri_gmac_read_TBQB_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBQB.reg; +} + +static inline void hri_gmac_set_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rsr_reg_t hri_gmac_get_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rsr_reg_t hri_gmac_read_RSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->RSR.reg; +} + +static inline void hri_gmac_set_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_isr_reg_t hri_gmac_get_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ISR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_ISR_reg(const void *const hw, hri_gmac_isr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_isr_reg_t hri_gmac_read_ISR_reg(const void *const hw) +{ + return ((Gmac *)hw)->ISR.reg; +} + +static inline void hri_gmac_set_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_get_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MAN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_MAN_reg(const void *const hw, hri_gmac_man_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_read_MAN_reg(const void *const hw) +{ + return ((Gmac *)hw)->MAN.reg; +} + +static inline void hri_gmac_set_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpq_reg_t hri_gmac_get_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TPQ.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpq_reg_t hri_gmac_read_TPQ_reg(const void *const hw) +{ + return ((Gmac *)hw)->TPQ.reg; +} + +static inline void hri_gmac_set_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpsf_reg_t hri_gmac_get_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TPSF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpsf_reg_t hri_gmac_read_TPSF_reg(const void *const hw) +{ + return ((Gmac *)hw)->TPSF.reg; +} + +static inline void hri_gmac_set_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rpsf_reg_t hri_gmac_get_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RPSF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rpsf_reg_t hri_gmac_read_RPSF_reg(const void *const hw) +{ + return ((Gmac *)hw)->RPSF.reg; +} + +static inline void hri_gmac_set_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rjfml_reg_t hri_gmac_get_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RJFML.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rjfml_reg_t hri_gmac_read_RJFML_reg(const void *const hw) +{ + return ((Gmac *)hw)->RJFML.reg; +} + +static inline void hri_gmac_set_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrb_reg_t hri_gmac_get_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->HRB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrb_reg_t hri_gmac_read_HRB_reg(const void *const hw) +{ + return ((Gmac *)hw)->HRB.reg; +} + +static inline void hri_gmac_set_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrt_reg_t hri_gmac_get_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->HRT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrt_reg_t hri_gmac_read_HRT_reg(const void *const hw) +{ + return ((Gmac *)hw)->HRT.reg; +} + +static inline void hri_gmac_set_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm_reg_t hri_gmac_get_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TIDM[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm_reg_t hri_gmac_read_TIDM_reg(const void *const hw, uint8_t index) +{ + return ((Gmac *)hw)->TIDM[index].reg; +} + +static inline void hri_gmac_set_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_wol_reg_t hri_gmac_get_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->WOL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_WOL_reg(const void *const hw, hri_gmac_wol_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_wol_reg_t hri_gmac_read_WOL_reg(const void *const hw) +{ + return ((Gmac *)hw)->WOL.reg; +} + +static inline void hri_gmac_set_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ipgs_reg_t hri_gmac_get_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->IPGS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ipgs_reg_t hri_gmac_read_IPGS_reg(const void *const hw) +{ + return ((Gmac *)hw)->IPGS.reg; +} + +static inline void hri_gmac_set_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_svlan_reg_t hri_gmac_get_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SVLAN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_svlan_reg_t hri_gmac_read_SVLAN_reg(const void *const hw) +{ + return ((Gmac *)hw)->SVLAN.reg; +} + +static inline void hri_gmac_set_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpfcp_reg_t hri_gmac_get_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TPFCP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpfcp_reg_t hri_gmac_read_TPFCP_reg(const void *const hw) +{ + return ((Gmac *)hw)->TPFCP.reg; +} + +static inline void hri_gmac_set_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samb1_reg_t hri_gmac_get_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SAMB1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samb1_reg_t hri_gmac_read_SAMB1_reg(const void *const hw) +{ + return ((Gmac *)hw)->SAMB1.reg; +} + +static inline void hri_gmac_set_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samt1_reg_t hri_gmac_get_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SAMT1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samt1_reg_t hri_gmac_read_SAMT1_reg(const void *const hw) +{ + return ((Gmac *)hw)->SAMT1.reg; +} + +static inline void hri_gmac_set_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_nsc_reg_t hri_gmac_get_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NSC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_nsc_reg_t hri_gmac_read_NSC_reg(const void *const hw) +{ + return ((Gmac *)hw)->NSC.reg; +} + +static inline void hri_gmac_set_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_scl_reg_t hri_gmac_get_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SCL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SCL_reg(const void *const hw, hri_gmac_scl_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_scl_reg_t hri_gmac_read_SCL_reg(const void *const hw) +{ + return ((Gmac *)hw)->SCL.reg; +} + +static inline void hri_gmac_set_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sch_reg_t hri_gmac_get_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SCH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SCH_reg(const void *const hw, hri_gmac_sch_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sch_reg_t hri_gmac_read_SCH_reg(const void *const hw) +{ + return ((Gmac *)hw)->SCH.reg; +} + +static inline void hri_gmac_set_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tisubn_reg_t hri_gmac_get_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TISUBN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tisubn_reg_t hri_gmac_read_TISUBN_reg(const void *const hw) +{ + return ((Gmac *)hw)->TISUBN.reg; +} + +static inline void hri_gmac_set_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsh_reg_t hri_gmac_get_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsh_reg_t hri_gmac_read_TSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSH.reg; +} + +static inline void hri_gmac_set_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsssl_reg_t hri_gmac_get_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSSSL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsssl_reg_t hri_gmac_read_TSSSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSSSL.reg; +} + +static inline void hri_gmac_set_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tssn_reg_t hri_gmac_get_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSSN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tssn_reg_t hri_gmac_read_TSSN_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSSN.reg; +} + +static inline void hri_gmac_set_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsl_reg_t hri_gmac_get_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsl_reg_t hri_gmac_read_TSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSL.reg; +} + +static inline void hri_gmac_set_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tn_reg_t hri_gmac_get_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TN_reg(const void *const hw, hri_gmac_tn_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tn_reg_t hri_gmac_read_TN_reg(const void *const hw) +{ + return ((Gmac *)hw)->TN.reg; +} + +static inline void hri_gmac_set_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_get_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TI.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TI_reg(const void *const hw, hri_gmac_ti_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_read_TI_reg(const void *const hw) +{ + return ((Gmac *)hw)->TI.reg; +} + +static inline void hri_gmac_write_TA_reg(const void *const hw, hri_gmac_ta_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TA.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GMAC_E54_H_INCLUDED */ +#endif /* _SAME54_GMAC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_hmatrixb_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_hmatrixb_e54.h new file mode 100644 index 0000000..2ef0684 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_hmatrixb_e54.h @@ -0,0 +1,237 @@ +/** + * \file + * + * \brief SAM HMATRIXB + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_HMATRIXB_COMPONENT_ +#ifndef _HRI_HMATRIXB_E54_H_INCLUDED_ +#define _HRI_HMATRIXB_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS) +#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define HMATRIXB_CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_hmatrixb_pras_reg_t; +typedef uint32_t hri_hmatrixb_prbs_reg_t; +typedef uint32_t hri_hmatrixbprs_pras_reg_t; +typedef uint32_t hri_hmatrixbprs_prbs_reg_t; + +static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRAS.reg; +} + +static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRBS.reg; +} + +static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; +} + +static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_HMATRIXB_E54_H_INCLUDED */ +#endif /* _SAME54_HMATRIXB_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_i2s_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_i2s_e54.h new file mode 100644 index 0000000..42b88dc --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_i2s_e54.h @@ -0,0 +1,3032 @@ +/** + * \file + * + * \brief SAM I2S + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_I2S_COMPONENT_ +#ifndef _HRI_I2S_E54_H_INCLUDED_ +#define _HRI_I2S_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_I2S_CRITICAL_SECTIONS) +#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define I2S_CRITICAL_SECTION_ENTER() +#define I2S_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_i2s_intenset_reg_t; +typedef uint16_t hri_i2s_intflag_reg_t; +typedef uint16_t hri_i2s_syncbusy_reg_t; +typedef uint32_t hri_i2s_clkctrl_reg_t; +typedef uint32_t hri_i2s_rxctrl_reg_t; +typedef uint32_t hri_i2s_rxdata_reg_t; +typedef uint32_t hri_i2s_txctrl_reg_t; +typedef uint32_t hri_i2s_txdata_reg_t; +typedef uint8_t hri_i2s_ctrla_reg_t; + +static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg) +{ + while (((I2s *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg) +{ + return ((I2s *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; +} + +static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; +} + +static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; +} + +static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; +} + +static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; +} + +static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; +} + +static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; +} + +static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; +} + +static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; +} + +static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; +} + +static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; +} + +static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; +} + +static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; +} + +static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; +} + +static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; +} + +static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; +} + +static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw) +{ + return ((I2s *)hw)->INTFLAG.reg; +} + +static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) +{ + ((I2s *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; +} + +static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos; +} + +static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; + } +} + +static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; +} + +static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; +} + +static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos; +} + +static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; + } +} + +static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; +} + +static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; +} + +static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos; +} + +static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; + } +} + +static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; +} + +static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; +} + +static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos; +} + +static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; + } +} + +static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; +} + +static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; +} + +static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos; +} + +static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; + } +} + +static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; +} + +static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; +} + +static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos; +} + +static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; + } +} + +static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; +} + +static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; +} + +static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos; +} + +static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; + } +} + +static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; +} + +static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; +} + +static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos; +} + +static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; + } +} + +static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; +} + +static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + ((I2s *)hw)->INTENSET.reg = mask; +} + +static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw) +{ + return ((I2s *)hw)->INTENSET.reg; +} + +static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data) +{ + ((I2s *)hw)->INTENSET.reg = data; + ((I2s *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + ((I2s *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_TXEN_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXEN) >> I2S_SYNCBUSY_TXEN_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_RXEN_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXEN) >> I2S_SYNCBUSY_RXEN_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_TXDATA_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXDATA) >> I2S_SYNCBUSY_TXDATA_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_RXDATA_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXDATA) >> I2S_SYNCBUSY_RXDATA_Pos; +} + +static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw) +{ + return ((I2s *)hw)->SYNCBUSY.reg; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_DATA_bf(const void *const hw, hri_i2s_rxdata_reg_t mask) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA(mask)) >> I2S_RXDATA_DATA_Pos; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_DATA_bf(const void *const hw) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA_Msk) >> I2S_RXDATA_DATA_Pos; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_reg(const void *const hw, hri_i2s_rxdata_reg_t mask) +{ + uint32_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->RXDATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_reg(const void *const hw) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + return ((I2s *)hw)->RXDATA.reg; +} + +static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_ENABLE; + tmp |= value << I2S_CTRLA_ENABLE_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_CKEN0; + tmp |= value << I2S_CTRLA_CKEN0_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_CKEN1; + tmp |= value << I2S_CTRLA_CKEN1_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_TXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_TXEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_TXEN) >> I2S_CTRLA_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_TXEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_TXEN; + tmp |= value << I2S_CTRLA_TXEN_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_TXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_TXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_RXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_RXEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_RXEN) >> I2S_CTRLA_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_RXEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_RXEN; + tmp |= value << I2S_CTRLA_RXEN_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_RXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_RXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= mask; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg = data; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~mask; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= mask; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + return ((I2s *)hw)->CTRLA.reg; +} + +static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_BITDELAY; + tmp |= value << I2S_CLKCTRL_BITDELAY_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSSEL; + tmp |= value << I2S_CLKCTRL_FSSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSINV; + tmp |= value << I2S_CLKCTRL_FSINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSOUTINV; + tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SCKSEL; + tmp |= value << I2S_CLKCTRL_SCKSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SCKOUTINV; + tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKSEL; + tmp |= value << I2S_CLKCTRL_MCKSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKEN; + tmp |= value << I2S_CLKCTRL_MCKEN_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKOUTINV; + tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk; + tmp |= I2S_CLKCTRL_SLOTSIZE(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk; + tmp |= I2S_CLKCTRL_NBSLOTS(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk; + tmp |= I2S_CLKCTRL_FSWIDTH(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKDIV_Msk; + tmp |= I2S_CLKCTRL_MCKDIV(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk; + tmp |= I2S_CLKCTRL_MCKOUTDIV(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index) +{ + return ((I2s *)hw)->CLKCTRL[index].reg; +} + +static inline void hri_i2s_set_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_TXSAME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXSAME) >> I2S_TXCTRL_TXSAME_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_TXSAME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_TXSAME; + tmp |= value << I2S_TXCTRL_TXSAME_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTADJ) >> I2S_TXCTRL_SLOTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTADJ; + tmp |= value << I2S_TXCTRL_SLOTADJ_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_WORDADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_WORDADJ) >> I2S_TXCTRL_WORDADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_WORDADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_WORDADJ; + tmp |= value << I2S_TXCTRL_WORDADJ_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_BITREV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_BITREV) >> I2S_TXCTRL_BITREV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_BITREV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_BITREV; + tmp |= value << I2S_TXCTRL_BITREV_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS0) >> I2S_TXCTRL_SLOTDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS0; + tmp |= value << I2S_TXCTRL_SLOTDIS0_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS1) >> I2S_TXCTRL_SLOTDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS1; + tmp |= value << I2S_TXCTRL_SLOTDIS1_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS2) >> I2S_TXCTRL_SLOTDIS2_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS2; + tmp |= value << I2S_TXCTRL_SLOTDIS2_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS3) >> I2S_TXCTRL_SLOTDIS3_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS3; + tmp |= value << I2S_TXCTRL_SLOTDIS3_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS4) >> I2S_TXCTRL_SLOTDIS4_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS4; + tmp |= value << I2S_TXCTRL_SLOTDIS4_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS5) >> I2S_TXCTRL_SLOTDIS5_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS5; + tmp |= value << I2S_TXCTRL_SLOTDIS5_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS6) >> I2S_TXCTRL_SLOTDIS6_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS6; + tmp |= value << I2S_TXCTRL_SLOTDIS6_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS7) >> I2S_TXCTRL_SLOTDIS7_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS7; + tmp |= value << I2S_TXCTRL_SLOTDIS7_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_MONO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_MONO) >> I2S_TXCTRL_MONO_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_MONO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_MONO; + tmp |= value << I2S_TXCTRL_MONO_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_DMA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DMA) >> I2S_TXCTRL_DMA_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_DMA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_DMA; + tmp |= value << I2S_TXCTRL_DMA_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXDEFAULT(mask)) >> I2S_TXCTRL_TXDEFAULT_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_TXDEFAULT_Msk; + tmp |= I2S_TXCTRL_TXDEFAULT(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_TXDEFAULT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXDEFAULT_Msk) >> I2S_TXCTRL_TXDEFAULT_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DATASIZE(mask)) >> I2S_TXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_DATASIZE_Msk; + tmp |= I2S_TXCTRL_DATASIZE(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_DATASIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DATASIZE_Msk) >> I2S_TXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_EXTEND(mask)) >> I2S_TXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_EXTEND_Msk; + tmp |= I2S_TXCTRL_EXTEND(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_EXTEND_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_EXTEND_Msk) >> I2S_TXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_reg(const void *const hw) +{ + return ((I2s *)hw)->TXCTRL.reg; +} + +static inline void hri_i2s_set_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_CLKSEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_CLKSEL) >> I2S_RXCTRL_CLKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_CLKSEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_CLKSEL; + tmp |= value << I2S_RXCTRL_CLKSEL_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTADJ) >> I2S_RXCTRL_SLOTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTADJ; + tmp |= value << I2S_RXCTRL_SLOTADJ_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_WORDADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_WORDADJ) >> I2S_RXCTRL_WORDADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_WORDADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_WORDADJ; + tmp |= value << I2S_RXCTRL_WORDADJ_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_BITREV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_BITREV) >> I2S_RXCTRL_BITREV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_BITREV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_BITREV; + tmp |= value << I2S_RXCTRL_BITREV_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS0) >> I2S_RXCTRL_SLOTDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS0; + tmp |= value << I2S_RXCTRL_SLOTDIS0_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS1) >> I2S_RXCTRL_SLOTDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS1; + tmp |= value << I2S_RXCTRL_SLOTDIS1_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS2) >> I2S_RXCTRL_SLOTDIS2_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS2; + tmp |= value << I2S_RXCTRL_SLOTDIS2_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS3) >> I2S_RXCTRL_SLOTDIS3_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS3; + tmp |= value << I2S_RXCTRL_SLOTDIS3_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS4) >> I2S_RXCTRL_SLOTDIS4_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS4; + tmp |= value << I2S_RXCTRL_SLOTDIS4_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS5) >> I2S_RXCTRL_SLOTDIS5_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS5; + tmp |= value << I2S_RXCTRL_SLOTDIS5_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS6) >> I2S_RXCTRL_SLOTDIS6_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS6; + tmp |= value << I2S_RXCTRL_SLOTDIS6_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS7) >> I2S_RXCTRL_SLOTDIS7_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS7; + tmp |= value << I2S_RXCTRL_SLOTDIS7_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_MONO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_MONO) >> I2S_RXCTRL_MONO_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_MONO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_MONO; + tmp |= value << I2S_RXCTRL_MONO_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_DMA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DMA) >> I2S_RXCTRL_DMA_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_DMA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_DMA; + tmp |= value << I2S_RXCTRL_DMA_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_RXLOOP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_RXLOOP) >> I2S_RXCTRL_RXLOOP_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_RXLOOP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_RXLOOP; + tmp |= value << I2S_RXCTRL_RXLOOP_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SERMODE(mask)) >> I2S_RXCTRL_SERMODE_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SERMODE_Msk; + tmp |= I2S_RXCTRL_SERMODE(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_SERMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SERMODE_Msk) >> I2S_RXCTRL_SERMODE_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DATASIZE(mask)) >> I2S_RXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_DATASIZE_Msk; + tmp |= I2S_RXCTRL_DATASIZE(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_DATASIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DATASIZE_Msk) >> I2S_RXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_EXTEND(mask)) >> I2S_RXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_EXTEND_Msk; + tmp |= I2S_RXCTRL_EXTEND(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_EXTEND_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_EXTEND_Msk) >> I2S_RXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_reg(const void *const hw) +{ + return ((I2s *)hw)->RXCTRL.reg; +} + +static inline void hri_i2s_write_TXDATA_reg(const void *const hw, hri_i2s_txdata_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXDATA.reg = data; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_I2S_E54_H_INCLUDED */ +#endif /* _SAME54_I2S_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_icm_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_icm_e54.h new file mode 100644 index 0000000..374caa4 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_icm_e54.h @@ -0,0 +1,761 @@ +/** + * \file + * + * \brief SAM ICM + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_ICM_COMPONENT_ +#ifndef _HRI_ICM_E54_H_INCLUDED_ +#define _HRI_ICM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ICM_CRITICAL_SECTIONS) +#define ICM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ICM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ICM_CRITICAL_SECTION_ENTER() +#define ICM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_icm_cfg_reg_t; +typedef uint32_t hri_icm_ctrl_reg_t; +typedef uint32_t hri_icm_dscr_reg_t; +typedef uint32_t hri_icm_hash_reg_t; +typedef uint32_t hri_icm_imr_reg_t; +typedef uint32_t hri_icm_isr_reg_t; +typedef uint32_t hri_icm_sr_reg_t; +typedef uint32_t hri_icm_uasr_reg_t; +typedef uint32_t hri_icm_uihval_reg_t; +typedef uint32_t hri_icmdescriptor_raddr_reg_t; +typedef uint32_t hri_icmdescriptor_rcfg_reg_t; +typedef uint32_t hri_icmdescriptor_rctrl_reg_t; +typedef uint32_t hri_icmdescriptor_rnext_reg_t; + +static inline void hri_icmdescriptor_set_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_get_RADDR_reg(const void *const hw, + hri_icmdescriptor_raddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_read_RADDR_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RADDR.reg; +} + +static inline void hri_icmdescriptor_set_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_get_RCFG_reg(const void *const hw, + hri_icmdescriptor_rcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_read_RCFG_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RCFG.reg; +} + +static inline void hri_icmdescriptor_set_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_get_RCTRL_reg(const void *const hw, + hri_icmdescriptor_rctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_read_RCTRL_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RCTRL.reg; +} + +static inline void hri_icmdescriptor_set_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_get_RNEXT_reg(const void *const hw, + hri_icmdescriptor_rnext_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RNEXT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_read_RNEXT_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RNEXT.reg; +} + +static inline void hri_icm_set_IMR_URAD_bit(const void *const hw) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_URAD; +} + +static inline bool hri_icm_get_IMR_URAD_bit(const void *const hw) +{ + return (((Icm *)hw)->IMR.reg & ICM_IMR_URAD) >> ICM_IMR_URAD_Pos; +} + +static inline void hri_icm_write_IMR_URAD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; + } else { + ((Icm *)hw)->IER.reg = ICM_IMR_URAD; + } +} + +static inline void hri_icm_clear_IMR_URAD_bit(const void *const hw) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; +} + +static inline void hri_icm_set_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RHC(mask)) >> ICM_IMR_RHC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RHC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RHC_Msk) >> ICM_IMR_RHC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RHC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RHC(data); +} + +static inline void hri_icm_clear_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RHC(mask); +} + +static inline void hri_icm_set_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RDM(mask)) >> ICM_IMR_RDM_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RDM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RDM_Msk) >> ICM_IMR_RDM_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RDM(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RDM(data); +} + +static inline void hri_icm_clear_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RDM(mask); +} + +static inline void hri_icm_set_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RBE(mask)) >> ICM_IMR_RBE_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RBE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RBE_Msk) >> ICM_IMR_RBE_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RBE(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RBE(data); +} + +static inline void hri_icm_clear_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RBE(mask); +} + +static inline void hri_icm_set_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RWC(mask)) >> ICM_IMR_RWC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RWC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RWC_Msk) >> ICM_IMR_RWC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RWC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RWC(data); +} + +static inline void hri_icm_clear_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RWC(mask); +} + +static inline void hri_icm_set_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_REC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_REC(mask)) >> ICM_IMR_REC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_REC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_REC_Msk) >> ICM_IMR_REC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_REC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_REC(data); +} + +static inline void hri_icm_clear_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_REC(mask); +} + +static inline void hri_icm_set_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RSU(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RSU(mask)) >> ICM_IMR_RSU_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RSU_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RSU_Msk) >> ICM_IMR_RSU_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RSU(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RSU(data); +} + +static inline void hri_icm_clear_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RSU(mask); +} + +static inline void hri_icm_set_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = mask; +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_reg(const void *const hw) +{ + return ((Icm *)hw)->IMR.reg; +} + +static inline void hri_icm_write_IMR_reg(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = data; + ((Icm *)hw)->IDR.reg = ~data; +} + +static inline void hri_icm_clear_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = mask; +} + +static inline bool hri_icm_get_SR_ENABLE_bit(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_ENABLE) >> ICM_SR_ENABLE_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_RAWRMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS(mask)) >> ICM_SR_RAWRMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_RAWRMDIS_bf(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS_Msk) >> ICM_SR_RAWRMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_RMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS(mask)) >> ICM_SR_RMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_RMDIS_bf(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS_Msk) >> ICM_SR_RMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_reg(const void *const hw, hri_icm_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->SR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_reg(const void *const hw) +{ + return ((Icm *)hw)->SR.reg; +} + +static inline bool hri_icm_get_ISR_URAD_bit(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_URAD) >> ICM_ISR_URAD_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RHC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC(mask)) >> ICM_ISR_RHC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RHC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC_Msk) >> ICM_ISR_RHC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RDM_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM(mask)) >> ICM_ISR_RDM_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RDM_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM_Msk) >> ICM_ISR_RDM_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RBE_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE(mask)) >> ICM_ISR_RBE_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RBE_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE_Msk) >> ICM_ISR_RBE_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RWC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC(mask)) >> ICM_ISR_RWC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RWC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC_Msk) >> ICM_ISR_RWC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_REC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_REC(mask)) >> ICM_ISR_REC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_REC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_REC_Msk) >> ICM_ISR_REC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RSU_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU(mask)) >> ICM_ISR_RSU_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RSU_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU_Msk) >> ICM_ISR_RSU_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_reg(const void *const hw, hri_icm_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_reg(const void *const hw) +{ + return ((Icm *)hw)->ISR.reg; +} + +static inline hri_icm_uasr_reg_t hri_icm_get_UASR_URAT_bf(const void *const hw, hri_icm_uasr_reg_t mask) +{ + return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT(mask)) >> ICM_UASR_URAT_Pos; +} + +static inline hri_icm_uasr_reg_t hri_icm_read_UASR_URAT_bf(const void *const hw) +{ + return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT_Msk) >> ICM_UASR_URAT_Pos; +} + +static inline hri_icm_uasr_reg_t hri_icm_get_UASR_reg(const void *const hw, hri_icm_uasr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->UASR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_uasr_reg_t hri_icm_read_UASR_reg(const void *const hw) +{ + return ((Icm *)hw)->UASR.reg; +} + +static inline void hri_icm_set_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_get_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_CFG_reg(const void *const hw, hri_icm_cfg_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_read_CFG_reg(const void *const hw) +{ + return ((Icm *)hw)->CFG.reg; +} + +static inline void hri_icm_set_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->DSCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_reg(const void *const hw) +{ + return ((Icm *)hw)->DSCR.reg; +} + +static inline void hri_icm_set_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_hash_reg_t hri_icm_get_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->HASH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_HASH_reg(const void *const hw, hri_icm_hash_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_hash_reg_t hri_icm_read_HASH_reg(const void *const hw) +{ + return ((Icm *)hw)->HASH.reg; +} + +static inline void hri_icm_write_CTRL_reg(const void *const hw, hri_icm_ctrl_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CTRL.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_write_UIHVAL_reg(const void *const hw, uint8_t index, hri_icm_uihval_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->UIHVAL[index].reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ICM_E54_H_INCLUDED */ +#endif /* _SAME54_ICM_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_mclk_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_mclk_e54.h new file mode 100644 index 0000000..7e3963b --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_mclk_e54.h @@ -0,0 +1,3556 @@ +/** + * \file + * + * \brief SAM MCLK + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_MCLK_COMPONENT_ +#ifndef _HRI_MCLK_E54_H_INCLUDED_ +#define _HRI_MCLK_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MCLK_CRITICAL_SECTIONS) +#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MCLK_CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mclk_ahbmask_reg_t; +typedef uint32_t hri_mclk_apbamask_reg_t; +typedef uint32_t hri_mclk_apbbmask_reg_t; +typedef uint32_t hri_mclk_apbcmask_reg_t; +typedef uint32_t hri_mclk_apbdmask_reg_t; +typedef uint8_t hri_mclk_cpudiv_reg_t; +typedef uint8_t hri_mclk_hsdiv_reg_t; +typedef uint8_t hri_mclk_intenset_reg_t; +typedef uint8_t hri_mclk_intflag_reg_t; + +static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTFLAG.reg; +} + +static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + ((Mclk *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; +} + +static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; +} + +static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; + } else { + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; + } +} + +static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; +} + +static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENSET.reg = mask; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTENSET.reg; +} + +static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data) +{ + ((Mclk *)hw)->INTENSET.reg = data; + ((Mclk *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENCLR.reg = mask; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_DIV_bf(const void *const hw, hri_mclk_hsdiv_reg_t mask) +{ + return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV(mask)) >> MCLK_HSDIV_DIV_Pos; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_DIV_bf(const void *const hw) +{ + return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV_Msk) >> MCLK_HSDIV_DIV_Pos; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_reg(const void *const hw, hri_mclk_hsdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->HSDIV.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->HSDIV.reg; +} + +static inline void hri_mclk_set_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_DIV(mask)) >> MCLK_CPUDIV_DIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= ~MCLK_CPUDIV_DIV_Msk; + tmp |= MCLK_CPUDIV_DIV(data); + ((Mclk *)hw)->CPUDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_DIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_DIV_Msk) >> MCLK_CPUDIV_DIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->CPUDIV.reg; +} + +static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB0; + tmp |= value << MCLK_AHBMASK_HPB0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB1; + tmp |= value << MCLK_AHBMASK_HPB1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB2; + tmp |= value << MCLK_AHBMASK_HPB2_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB3; + tmp |= value << MCLK_AHBMASK_HPB3_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DSU; + tmp |= value << MCLK_AHBMASK_DSU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HMATRIX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HMATRIX) >> MCLK_AHBMASK_HMATRIX_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HMATRIX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HMATRIX; + tmp |= value << MCLK_AHBMASK_HMATRIX_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL; + tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HSRAM; + tmp |= value << MCLK_AHBMASK_HSRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CMCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CMCC) >> MCLK_AHBMASK_CMCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CMCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CMCC; + tmp |= value << MCLK_AHBMASK_CMCC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DMAC; + tmp |= value << MCLK_AHBMASK_DMAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_USB; + tmp |= value << MCLK_AHBMASK_USB_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_BKUPRAM) >> MCLK_AHBMASK_BKUPRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_BKUPRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_BKUPRAM; + tmp |= value << MCLK_AHBMASK_BKUPRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PAC; + tmp |= value << MCLK_AHBMASK_PAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_QSPI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_QSPI) >> MCLK_AHBMASK_QSPI_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_QSPI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_QSPI; + tmp |= value << MCLK_AHBMASK_QSPI_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_GMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_GMAC) >> MCLK_AHBMASK_GMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_GMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_GMAC; + tmp |= value << MCLK_AHBMASK_GMAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_SDHC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_SDHC0) >> MCLK_AHBMASK_SDHC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_SDHC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_SDHC0; + tmp |= value << MCLK_AHBMASK_SDHC0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_SDHC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_SDHC1) >> MCLK_AHBMASK_SDHC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_SDHC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_SDHC1; + tmp |= value << MCLK_AHBMASK_SDHC1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CAN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CAN0) >> MCLK_AHBMASK_CAN0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CAN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CAN0; + tmp |= value << MCLK_AHBMASK_CAN0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CAN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CAN1) >> MCLK_AHBMASK_CAN1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CAN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CAN1; + tmp |= value << MCLK_AHBMASK_CAN1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_ICM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_ICM) >> MCLK_AHBMASK_ICM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_ICM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_ICM; + tmp |= value << MCLK_AHBMASK_ICM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PUKCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PUKCC) >> MCLK_AHBMASK_PUKCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PUKCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PUKCC; + tmp |= value << MCLK_AHBMASK_PUKCC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_QSPI_2X) >> MCLK_AHBMASK_QSPI_2X_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_QSPI_2X_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_QSPI_2X; + tmp |= value << MCLK_AHBMASK_QSPI_2X_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_SMEEPROM) >> MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; + tmp |= value << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_CACHE) >> MCLK_AHBMASK_NVMCTRL_CACHE_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_CACHE; + tmp |= value << MCLK_AHBMASK_NVMCTRL_CACHE_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->AHBMASK.reg; +} + +static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PAC; + tmp |= value << MCLK_APBAMASK_PAC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PM; + tmp |= value << MCLK_APBAMASK_PM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_MCLK; + tmp |= value << MCLK_APBAMASK_MCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RSTC; + tmp |= value << MCLK_APBAMASK_RSTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSCCTRL; + tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSC32KCTRL; + tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SUPC; + tmp |= value << MCLK_APBAMASK_SUPC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_GCLK; + tmp |= value << MCLK_APBAMASK_GCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_WDT; + tmp |= value << MCLK_APBAMASK_WDT_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RTC; + tmp |= value << MCLK_APBAMASK_RTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_EIC; + tmp |= value << MCLK_APBAMASK_EIC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_FREQM; + tmp |= value << MCLK_APBAMASK_FREQM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SERCOM0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SERCOM0) >> MCLK_APBAMASK_SERCOM0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SERCOM0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SERCOM0; + tmp |= value << MCLK_APBAMASK_SERCOM0_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SERCOM1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SERCOM1) >> MCLK_APBAMASK_SERCOM1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SERCOM1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SERCOM1; + tmp |= value << MCLK_APBAMASK_SERCOM1_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_TC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_TC0) >> MCLK_APBAMASK_TC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_TC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_TC0; + tmp |= value << MCLK_APBAMASK_TC0_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_TC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_TC1) >> MCLK_APBAMASK_TC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_TC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_TC1; + tmp |= value << MCLK_APBAMASK_TC1_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBAMASK.reg; +} + +static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_USB; + tmp |= value << MCLK_APBBMASK_USB_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_DSU; + tmp |= value << MCLK_APBBMASK_DSU_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_NVMCTRL; + tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_PORT; + tmp |= value << MCLK_APBBMASK_PORT_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_HMATRIX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_HMATRIX) >> MCLK_APBBMASK_HMATRIX_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_HMATRIX; + tmp |= value << MCLK_APBBMASK_HMATRIX_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_EVSYS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_EVSYS) >> MCLK_APBBMASK_EVSYS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_EVSYS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_EVSYS; + tmp |= value << MCLK_APBBMASK_EVSYS_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_SERCOM2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_SERCOM2) >> MCLK_APBBMASK_SERCOM2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_SERCOM2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_SERCOM2; + tmp |= value << MCLK_APBBMASK_SERCOM2_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_SERCOM3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_SERCOM3) >> MCLK_APBBMASK_SERCOM3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_SERCOM3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_SERCOM3; + tmp |= value << MCLK_APBBMASK_SERCOM3_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TCC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TCC0) >> MCLK_APBBMASK_TCC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TCC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TCC0; + tmp |= value << MCLK_APBBMASK_TCC0_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TCC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TCC1) >> MCLK_APBBMASK_TCC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TCC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TCC1; + tmp |= value << MCLK_APBBMASK_TCC1_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TC2) >> MCLK_APBBMASK_TC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TC2; + tmp |= value << MCLK_APBBMASK_TC2_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TC3) >> MCLK_APBBMASK_TC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TC3; + tmp |= value << MCLK_APBBMASK_TC3_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_RAMECC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_RAMECC) >> MCLK_APBBMASK_RAMECC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_RAMECC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_RAMECC; + tmp |= value << MCLK_APBBMASK_RAMECC_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBBMASK.reg; +} + +static inline void hri_mclk_set_APBCMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_GMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_GMAC) >> MCLK_APBCMASK_GMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_GMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_GMAC; + tmp |= value << MCLK_APBCMASK_GMAC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC2; + tmp |= value << MCLK_APBCMASK_TCC2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC3) >> MCLK_APBCMASK_TCC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC3; + tmp |= value << MCLK_APBCMASK_TCC3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC4; + tmp |= value << MCLK_APBCMASK_TC4_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC5) >> MCLK_APBCMASK_TC5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC5; + tmp |= value << MCLK_APBCMASK_TC5_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_PDEC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_PDEC) >> MCLK_APBCMASK_PDEC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_PDEC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_PDEC; + tmp |= value << MCLK_APBCMASK_PDEC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AC; + tmp |= value << MCLK_APBCMASK_AC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AES; + tmp |= value << MCLK_APBCMASK_AES_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TRNG; + tmp |= value << MCLK_APBCMASK_TRNG_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_ICM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_ICM) >> MCLK_APBCMASK_ICM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_ICM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_ICM; + tmp |= value << MCLK_APBCMASK_ICM_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_QSPI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_QSPI) >> MCLK_APBCMASK_QSPI_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_QSPI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_QSPI; + tmp |= value << MCLK_APBCMASK_QSPI_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_CCL; + tmp |= value << MCLK_APBCMASK_CCL_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBCMASK.reg; +} + +static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM4) >> MCLK_APBDMASK_SERCOM4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM4; + tmp |= value << MCLK_APBDMASK_SERCOM4_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM5; + tmp |= value << MCLK_APBDMASK_SERCOM5_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM6) >> MCLK_APBDMASK_SERCOM6_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM6; + tmp |= value << MCLK_APBDMASK_SERCOM6_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM7) >> MCLK_APBDMASK_SERCOM7_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM7; + tmp |= value << MCLK_APBDMASK_SERCOM7_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TCC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TCC4) >> MCLK_APBDMASK_TCC4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TCC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TCC4; + tmp |= value << MCLK_APBDMASK_TCC4_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TC6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TC6) >> MCLK_APBDMASK_TC6_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TC6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TC6; + tmp |= value << MCLK_APBDMASK_TC6_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TC7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TC7) >> MCLK_APBDMASK_TC7_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TC7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TC7; + tmp |= value << MCLK_APBDMASK_TC7_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_ADC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_ADC0) >> MCLK_APBDMASK_ADC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_ADC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_ADC0; + tmp |= value << MCLK_APBDMASK_ADC0_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_ADC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_ADC1) >> MCLK_APBDMASK_ADC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_ADC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_ADC1; + tmp |= value << MCLK_APBDMASK_ADC1_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_DAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_DAC) >> MCLK_APBDMASK_DAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_DAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_DAC; + tmp |= value << MCLK_APBDMASK_DAC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_I2S_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_I2S) >> MCLK_APBDMASK_I2S_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_I2S_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_I2S; + tmp |= value << MCLK_APBDMASK_I2S_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_PCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_PCC) >> MCLK_APBDMASK_PCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_PCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_PCC; + tmp |= value << MCLK_APBDMASK_PCC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBDMASK.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MCLK_E54_H_INCLUDED */ +#endif /* _SAME54_MCLK_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_nvmctrl_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_nvmctrl_e54.h new file mode 100644 index 0000000..12d4022 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_nvmctrl_e54.h @@ -0,0 +1,1618 @@ +/** + * \file + * + * \brief SAM NVMCTRL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_NVMCTRL_COMPONENT_ +#ifndef _HRI_NVMCTRL_E54_H_INCLUDED_ +#define _HRI_NVMCTRL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) +#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVMCTRL_CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_nvmctrl_ctrla_reg_t; +typedef uint16_t hri_nvmctrl_ctrlb_reg_t; +typedef uint16_t hri_nvmctrl_intenset_reg_t; +typedef uint16_t hri_nvmctrl_intflag_reg_t; +typedef uint16_t hri_nvmctrl_status_reg_t; +typedef uint32_t hri_nvmctrl_addr_reg_t; +typedef uint32_t hri_nvmctrl_eccerr_reg_t; +typedef uint32_t hri_nvmctrl_param_reg_t; +typedef uint32_t hri_nvmctrl_pbldata_reg_t; +typedef uint32_t hri_nvmctrl_runlock_reg_t; +typedef uint32_t hri_nvmctrl_seestat_reg_t; +typedef uint8_t hri_nvmctrl_dbgctrl_reg_t; +typedef uint8_t hri_nvmctrl_seecfg_reg_t; + +static inline bool hri_nvmctrl_get_INTFLAG_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; +} + +static inline bool hri_nvmctrl_get_interrupt_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; +} + +static inline bool hri_nvmctrl_get_interrupt_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; +} + +static inline bool hri_nvmctrl_get_interrupt_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; +} + +static inline bool hri_nvmctrl_get_interrupt_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; +} + +static inline bool hri_nvmctrl_get_interrupt_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; +} + +static inline bool hri_nvmctrl_get_interrupt_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; +} + +static inline bool hri_nvmctrl_get_interrupt_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; +} + +static inline bool hri_nvmctrl_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; +} + +static inline bool hri_nvmctrl_get_interrupt_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; +} + +static inline bool hri_nvmctrl_get_interrupt_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; +} + +static inline bool hri_nvmctrl_get_interrupt_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, + hri_nvmctrl_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_nvmctrl_set_INTEN_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; +} + +static inline bool hri_nvmctrl_get_INTEN_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_DONE) >> NVMCTRL_INTENSET_DONE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; +} + +static inline void hri_nvmctrl_set_INTEN_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; +} + +static inline bool hri_nvmctrl_get_INTEN_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ADDRE) >> NVMCTRL_INTENSET_ADDRE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ADDRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; +} + +static inline void hri_nvmctrl_set_INTEN_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; +} + +static inline bool hri_nvmctrl_get_INTEN_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_PROGE) >> NVMCTRL_INTENSET_PROGE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_PROGE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; +} + +static inline void hri_nvmctrl_set_INTEN_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; +} + +static inline bool hri_nvmctrl_get_INTEN_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_LOCKE) >> NVMCTRL_INTENSET_LOCKE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_LOCKE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; +} + +static inline void hri_nvmctrl_set_INTEN_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; +} + +static inline bool hri_nvmctrl_get_INTEN_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCSE) >> NVMCTRL_INTENSET_ECCSE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ECCSE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; +} + +static inline void hri_nvmctrl_set_INTEN_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; +} + +static inline bool hri_nvmctrl_get_INTEN_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCDE) >> NVMCTRL_INTENSET_ECCDE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ECCDE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; +} + +static inline void hri_nvmctrl_set_INTEN_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; +} + +static inline bool hri_nvmctrl_get_INTEN_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_NVME) >> NVMCTRL_INTENSET_NVME_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_NVME_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; + } +} + +static inline void hri_nvmctrl_clear_INTEN_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; +} + +static inline void hri_nvmctrl_set_INTEN_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; +} + +static inline bool hri_nvmctrl_get_INTEN_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SUSP) >> NVMCTRL_INTENSET_SUSP_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; +} + +static inline void hri_nvmctrl_set_INTEN_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; +} + +static inline bool hri_nvmctrl_get_INTEN_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESFULL) >> NVMCTRL_INTENSET_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEESFULL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; +} + +static inline void hri_nvmctrl_set_INTEN_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; +} + +static inline bool hri_nvmctrl_get_INTEN_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESOVF) >> NVMCTRL_INTENSET_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEESOVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; +} + +static inline void hri_nvmctrl_set_INTEN_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; +} + +static inline bool hri_nvmctrl_get_INTEN_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEEWRC) >> NVMCTRL_INTENSET_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEEWRC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; +} + +static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, + hri_nvmctrl_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTENSET.reg; +} + +static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) +{ + ((Nvmctrl *)hw)->INTENSET.reg = data; + ((Nvmctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_nvmctrl_get_PARAM_SEE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PARAM.reg; +} + +static inline bool hri_nvmctrl_get_STATUS_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_READY) >> NVMCTRL_STATUS_READY_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SUSP) >> NVMCTRL_STATUS_SUSP_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_AFIRST_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_AFIRST) >> NVMCTRL_STATUS_AFIRST_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_BPDIS_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BPDIS) >> NVMCTRL_STATUS_BPDIS_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_BOOTPROT_bf(const void *const hw, + hri_nvmctrl_status_reg_t mask) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT(mask)) >> NVMCTRL_STATUS_BOOTPROT_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_BOOTPROT_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT_Msk) >> NVMCTRL_STATUS_BOOTPROT_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->STATUS.reg; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_RUNLOCK_bf(const void *const hw, + hri_nvmctrl_runlock_reg_t mask) +{ + return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK(mask)) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_RUNLOCK_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK_Msk) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_reg(const void *const hw, + hri_nvmctrl_runlock_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->RUNLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->RUNLOCK.reg; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_DATA_bf(const void *const hw, uint8_t index, + hri_nvmctrl_pbldata_reg_t mask) +{ + return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA(mask)) >> NVMCTRL_PBLDATA_DATA_Pos; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_DATA_bf(const void *const hw, uint8_t index) +{ + return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA_Msk) >> NVMCTRL_PBLDATA_DATA_Pos; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_reg(const void *const hw, uint8_t index, + hri_nvmctrl_pbldata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PBLDATA[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_reg(const void *const hw, uint8_t index) +{ + return ((Nvmctrl *)hw)->PBLDATA[index].reg; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_ADDR_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR(mask)) >> NVMCTRL_ECCERR_ADDR_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_ADDR_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR_Msk) >> NVMCTRL_ECCERR_ADDR_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEL_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL(mask)) >> NVMCTRL_ECCERR_TYPEL_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEL_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL_Msk) >> NVMCTRL_ECCERR_TYPEL_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEH_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH(mask)) >> NVMCTRL_ECCERR_TYPEH_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEH_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH_Msk) >> NVMCTRL_ECCERR_TYPEH_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_reg(const void *const hw, hri_nvmctrl_eccerr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ECCERR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ECCERR.reg; +} + +static inline bool hri_nvmctrl_get_SEESTAT_ASEES_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_ASEES) >> NVMCTRL_SEESTAT_ASEES_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOAD) >> NVMCTRL_SEESTAT_LOAD_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_BUSY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_BUSY) >> NVMCTRL_SEESTAT_BUSY_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_LOCK_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOCK) >> NVMCTRL_SEESTAT_LOCK_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_RLOCK_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_RLOCK) >> NVMCTRL_SEESTAT_RLOCK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_SBLK_bf(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK(mask)) >> NVMCTRL_SEESTAT_SBLK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_SBLK_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK_Msk) >> NVMCTRL_SEESTAT_SBLK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_PSZ_bf(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ(mask)) >> NVMCTRL_SEESTAT_PSZ_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_PSZ_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ_Msk) >> NVMCTRL_SEESTAT_PSZ_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_reg(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->SEESTAT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->SEESTAT.reg; +} + +static inline void hri_nvmctrl_set_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AUTOWS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AUTOWS) >> NVMCTRL_CTRLA_AUTOWS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AUTOWS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AUTOWS; + tmp |= value << NVMCTRL_CTRLA_AUTOWS_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_SUSPEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_SUSPEN) >> NVMCTRL_CTRLA_SUSPEN_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_SUSPEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_SUSPEN; + tmp |= value << NVMCTRL_CTRLA_SUSPEN_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AHBNS0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AHBNS0) >> NVMCTRL_CTRLA_AHBNS0_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AHBNS0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AHBNS0; + tmp |= value << NVMCTRL_CTRLA_AHBNS0_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AHBNS1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AHBNS1) >> NVMCTRL_CTRLA_AHBNS1_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AHBNS1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AHBNS1; + tmp |= value << NVMCTRL_CTRLA_AHBNS1_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS0) >> NVMCTRL_CTRLA_CACHEDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CACHEDIS0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CACHEDIS0; + tmp |= value << NVMCTRL_CTRLA_CACHEDIS0_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS1) >> NVMCTRL_CTRLA_CACHEDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CACHEDIS1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CACHEDIS1; + tmp |= value << NVMCTRL_CTRLA_CACHEDIS1_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_WMODE(mask)) >> NVMCTRL_CTRLA_WMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_WMODE_Msk; + tmp |= NVMCTRL_CTRLA_WMODE(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_WMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_WMODE_Msk) >> NVMCTRL_CTRLA_WMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_PRM(mask)) >> NVMCTRL_CTRLA_PRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_PRM_Msk; + tmp |= NVMCTRL_CTRLA_PRM(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_PRM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_PRM_Msk) >> NVMCTRL_CTRLA_PRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_RWS(mask)) >> NVMCTRL_CTRLA_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_RWS_Msk; + tmp |= NVMCTRL_CTRLA_RWS(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_RWS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_RWS_Msk) >> NVMCTRL_CTRLA_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLA.reg; +} + +static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= ~NVMCTRL_ADDR_ADDR_Msk; + tmp |= NVMCTRL_ADDR_ADDR(data); + ((Nvmctrl *)hw)->ADDR.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ADDR.reg; +} + +static inline void hri_nvmctrl_set_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp = (tmp & NVMCTRL_DBGCTRL_ECCDIS) >> NVMCTRL_DBGCTRL_ECCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= ~NVMCTRL_DBGCTRL_ECCDIS; + tmp |= value << NVMCTRL_DBGCTRL_ECCDIS_Pos; + ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp = (tmp & NVMCTRL_DBGCTRL_ECCELOG) >> NVMCTRL_DBGCTRL_ECCELOG_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= ~NVMCTRL_DBGCTRL_ECCELOG; + tmp |= value << NVMCTRL_DBGCTRL_ECCELOG_Pos; + ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_get_DBGCTRL_reg(const void *const hw, + hri_nvmctrl_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_read_DBGCTRL_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->DBGCTRL.reg; +} + +static inline void hri_nvmctrl_set_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_SEECFG_WMODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp = (tmp & NVMCTRL_SEECFG_WMODE) >> NVMCTRL_SEECFG_WMODE_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_WMODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= ~NVMCTRL_SEECFG_WMODE; + tmp |= value << NVMCTRL_SEECFG_WMODE_Pos; + ((Nvmctrl *)hw)->SEECFG.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_SEECFG_APRDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp = (tmp & NVMCTRL_SEECFG_APRDIS) >> NVMCTRL_SEECFG_APRDIS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_APRDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= ~NVMCTRL_SEECFG_APRDIS; + tmp |= value << NVMCTRL_SEECFG_APRDIS_Pos; + ((Nvmctrl *)hw)->SEECFG.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_get_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_read_SEECFG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->SEECFG.reg; +} + +static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVMCTRL_E54_H_INCLUDED */ +#endif /* _SAME54_NVMCTRL_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_osc32kctrl_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_osc32kctrl_e54.h new file mode 100644 index 0000000..2eabbca --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_osc32kctrl_e54.h @@ -0,0 +1,1199 @@ +/** + * \file + * + * \brief SAM OSC32KCTRL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_OSC32KCTRL_COMPONENT_ +#ifndef _HRI_OSC32KCTRL_E54_H_INCLUDED_ +#define _HRI_OSC32KCTRL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_osc32kctrl_xosc32k_reg_t; +typedef uint32_t hri_osc32kctrl_intenset_reg_t; +typedef uint32_t hri_osc32kctrl_intflag_reg_t; +typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; +typedef uint32_t hri_osc32kctrl_status_reg_t; +typedef uint8_t hri_osc32kctrl_cfdctrl_reg_t; +typedef uint8_t hri_osc32kctrl_evctrl_reg_t; +typedef uint8_t hri_osc32kctrl_rtcctrl_reg_t; + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, + hri_osc32kctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KFAIL) >> OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KFAIL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; +} + +static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, + hri_osc32kctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTENSET.reg; +} + +static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = data; + ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KFAIL) >> OSC32KCTRL_STATUS_XOSC32KFAIL_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KSW_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KSW) >> OSC32KCTRL_STATUS_XOSC32KSW_Pos; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, + hri_osc32kctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->STATUS.reg; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; + tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); + ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->RTCCTRL.reg; +} + +static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; + tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; + tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN32K; + tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN1K; + tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; + tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_CGM_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_CGM(mask)) >> OSC32KCTRL_XOSC32K_CGM_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_CGM_Msk; + tmp |= OSC32KCTRL_XOSC32K_CGM(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_CGM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_CGM_Msk) >> OSC32KCTRL_XOSC32K_CGM_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->XOSC32K.reg; +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK; + tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const hw, + hri_osc32kctrl_cfdctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->CFDCTRL.reg; +} + +static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= ~OSC32KCTRL_EVCTRL_CFDEO; + tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos; + ((Osc32kctrl *)hw)->EVCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const hw, + hri_osc32kctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_EN32K; + tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_EN1K; + tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; + tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->OSCULP32K.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSC32KCTRL_E54_H_INCLUDED */ +#endif /* _SAME54_OSC32KCTRL_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_oscctrl_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_oscctrl_e54.h new file mode 100644 index 0000000..f331410 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_oscctrl_e54.h @@ -0,0 +1,4441 @@ +/** + * \file + * + * \brief SAM OSCCTRL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_OSCCTRL_COMPONENT_ +#ifndef _HRI_OSCCTRL_E54_H_INCLUDED_ +#define _HRI_OSCCTRL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) +#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSCCTRL_CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_oscctrl_dfllmul_reg_t; +typedef uint32_t hri_oscctrl_dfllval_reg_t; +typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrl_dpllratio_reg_t; +typedef uint32_t hri_oscctrl_dpllstatus_reg_t; +typedef uint32_t hri_oscctrl_dpllsyncbusy_reg_t; +typedef uint32_t hri_oscctrl_intenset_reg_t; +typedef uint32_t hri_oscctrl_intflag_reg_t; +typedef uint32_t hri_oscctrl_status_reg_t; +typedef uint32_t hri_oscctrl_xoscctrl_reg_t; +typedef uint32_t hri_oscctrldpll_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrldpll_dpllratio_reg_t; +typedef uint32_t hri_oscctrldpll_dpllstatus_reg_t; +typedef uint32_t hri_oscctrldpll_dpllsyncbusy_reg_t; +typedef uint8_t hri_oscctrl_dfllctrla_reg_t; +typedef uint8_t hri_oscctrl_dfllctrlb_reg_t; +typedef uint8_t hri_oscctrl_dfllsync_reg_t; +typedef uint8_t hri_oscctrl_dpllctrla_reg_t; +typedef uint8_t hri_oscctrl_evctrl_reg_t; +typedef uint8_t hri_oscctrldpll_dpllctrla_reg_t; + +static inline void hri_oscctrldpll_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + while (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrldpll_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg; +} + +static inline void hri_oscctrl_wait_for_sync(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrl_is_syncing(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg; +} + +static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) + >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_get_DPLLSYNCBUSY_reg(const void *const hw, + hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_read_DPLLSYNCBUSY_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrldpll_get_DPLLSTATUS_LOCK_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrldpll_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_get_DPLLSTATUS_reg(const void *const hw, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_read_DPLLSTATUS_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLSTATUS.reg; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_get_DPLLCTRLA_reg(const void *const hw, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = data; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_read_DPLLCTRLA_reg(const void *const hw) +{ + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((OscctrlDpll *)hw)->DPLLCTRLA.reg; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDR_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_reg(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = data; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_reg(const void *const hw) +{ + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((OscctrlDpll *)hw)->DPLLRATIO.reg; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_WUF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; + tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_FILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_FILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_REFCLK_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_REFCLK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_LTIME_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_LTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DIV_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_reg(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLCTRLB.reg; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) + >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) + >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t +hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) + >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) + >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index) +{ + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t +hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t +hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index) +{ + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; + tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, + hri_oscctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) +{ + ((Oscctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY0) >> OSCCTRL_INTENSET_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY1) >> OSCCTRL_INTENSET_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; +} + +static inline void hri_oscctrl_set_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL0) >> OSCCTRL_INTENSET_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCFAIL0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; +} + +static inline void hri_oscctrl_set_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL1) >> OSCCTRL_INTENSET_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCFAIL1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKR) >> OSCCTRL_INTENSET_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKF) >> OSCCTRL_INTENSET_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LTO) >> OSCCTRL_INTENSET_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LDRTO) >> OSCCTRL_INTENSET_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKR) >> OSCCTRL_INTENSET_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKF) >> OSCCTRL_INTENSET_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LTO) >> OSCCTRL_INTENSET_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LDRTO) >> OSCCTRL_INTENSET_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; +} + +static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, + hri_oscctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTENSET.reg; +} + +static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) +{ + ((Oscctrl *)hw)->INTENSET.reg = data; + ((Oscctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY0) >> OSCCTRL_STATUS_XOSCRDY0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY1) >> OSCCTRL_STATUS_XOSCRDY1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL0) >> OSCCTRL_STATUS_XOSCFAIL0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL1) >> OSCCTRL_STATUS_XOSCFAIL1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCCKSW0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW0) >> OSCCTRL_STATUS_XOSCCKSW0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCCKSW1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW1) >> OSCCTRL_STATUS_XOSCCKSW1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKR) >> OSCCTRL_STATUS_DPLL0LCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKF) >> OSCCTRL_STATUS_DPLL0LCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0TO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0TO) >> OSCCTRL_STATUS_DPLL0TO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LDRTO) >> OSCCTRL_STATUS_DPLL0LDRTO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKR) >> OSCCTRL_STATUS_DPLL1LCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKF) >> OSCCTRL_STATUS_DPLL1LCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1TO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1TO) >> OSCCTRL_STATUS_DPLL1TO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LDRTO) >> OSCCTRL_STATUS_DPLL1LDRTO_Pos; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->STATUS.reg; +} + +static inline void hri_oscctrl_set_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_EVCTRL_CFDEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSCCTRL_EVCTRL_CFDEO0) >> OSCCTRL_EVCTRL_CFDEO0_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_CFDEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= ~OSCCTRL_EVCTRL_CFDEO0; + tmp |= value << OSCCTRL_EVCTRL_CFDEO0_Pos; + ((Oscctrl *)hw)->EVCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_EVCTRL_CFDEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSCCTRL_EVCTRL_CFDEO1) >> OSCCTRL_EVCTRL_CFDEO1_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_CFDEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= ~OSCCTRL_EVCTRL_CFDEO1; + tmp |= value << OSCCTRL_EVCTRL_CFDEO1_Pos; + ((Oscctrl *)hw)->EVCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; + tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; + tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_LOWBUFGAIN) >> OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; + tmp |= value << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENALC) >> OSCCTRL_XOSCCTRL_ENALC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENALC; + tmp |= value << OSCCTRL_XOSCCTRL_ENALC_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_CFDEN; + tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_SWBEN; + tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT(mask)) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_IPTAT_Msk; + tmp |= OSCCTRL_XOSCCTRL_IPTAT(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT_Msk) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT(mask)) >> OSCCTRL_XOSCCTRL_IMULT_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_IMULT_Msk; + tmp |= OSCCTRL_XOSCCTRL_IMULT(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT_Msk) >> OSCCTRL_XOSCCTRL_IMULT_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; + tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC(mask)) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_CFDPRESC_Msk; + tmp |= OSCCTRL_XOSCCTRL_CFDPRESC(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC_Msk) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Oscctrl *)hw)->XOSCCTRL[index].reg; +} + +static inline void hri_oscctrl_set_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_ENABLE) >> OSCCTRL_DFLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DFLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_RUNSTDBY) >> OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_ONDEMAND) >> OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_get_DFLLCTRLA_reg(const void *const hw, + hri_oscctrl_dfllctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_read_DFLLCTRLA_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_MODE) >> OSCCTRL_DFLLCTRLB_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_MODE; + tmp |= value << OSCCTRL_DFLLCTRLB_MODE_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_STABLE) >> OSCCTRL_DFLLCTRLB_STABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_STABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_STABLE; + tmp |= value << OSCCTRL_DFLLCTRLB_STABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_LLAW) >> OSCCTRL_DFLLCTRLB_LLAW_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_LLAW_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_LLAW; + tmp |= value << OSCCTRL_DFLLCTRLB_LLAW_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_USBCRM) >> OSCCTRL_DFLLCTRLB_USBCRM_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_USBCRM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_USBCRM; + tmp |= value << OSCCTRL_DFLLCTRLB_USBCRM_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_CCDIS) >> OSCCTRL_DFLLCTRLB_CCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_CCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_CCDIS; + tmp |= value << OSCCTRL_DFLLCTRLB_CCDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_QLDIS) >> OSCCTRL_DFLLCTRLB_QLDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_QLDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_QLDIS; + tmp |= value << OSCCTRL_DFLLCTRLB_QLDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_BPLCKC) >> OSCCTRL_DFLLCTRLB_BPLCKC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_BPLCKC_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_BPLCKC; + tmp |= value << OSCCTRL_DFLLCTRLB_BPLCKC_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_WAITLOCK) >> OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_WAITLOCK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; + tmp |= value << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_get_DFLLCTRLB_reg(const void *const hw, + hri_oscctrl_dfllctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_read_DFLLCTRLB_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLCTRLB.reg; +} + +static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk; + tmp |= OSCCTRL_DFLLVAL_FINE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk; + tmp |= OSCCTRL_DFLLVAL_COARSE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk; + tmp |= OSCCTRL_DFLLVAL_DIFF(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLVAL.reg; +} + +static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk; + tmp |= OSCCTRL_DFLLMUL_MUL(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_FSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_CSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLMUL.reg; +} + +static inline void hri_oscctrl_set_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_ENABLE) >> OSCCTRL_DFLLSYNC_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_ENABLE; + tmp |= value << OSCCTRL_DFLLSYNC_ENABLE_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLCTRLB) >> OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLCTRLB_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLVAL) >> OSCCTRL_DFLLSYNC_DFLLVAL_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLVAL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLVAL; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLVAL_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLMUL) >> OSCCTRL_DFLLSYNC_DFLLMUL_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLMUL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLMUL; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLMUL_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const hw, + hri_oscctrl_dfllsync_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLSYNC.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSCCTRL_E54_H_INCLUDED */ +#endif /* _SAME54_OSCCTRL_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pac_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pac_e54.h new file mode 100644 index 0000000..8963135 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pac_e54.h @@ -0,0 +1,1514 @@ +/** + * \file + * + * \brief SAM PAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PAC_COMPONENT_ +#ifndef _HRI_PAC_E54_H_INCLUDED_ +#define _HRI_PAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PAC_CRITICAL_SECTIONS) +#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PAC_CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pac_intflaga_reg_t; +typedef uint32_t hri_pac_intflagahb_reg_t; +typedef uint32_t hri_pac_intflagb_reg_t; +typedef uint32_t hri_pac_intflagc_reg_t; +typedef uint32_t hri_pac_intflagd_reg_t; +typedef uint32_t hri_pac_statusa_reg_t; +typedef uint32_t hri_pac_statusb_reg_t; +typedef uint32_t hri_pac_statusc_reg_t; +typedef uint32_t hri_pac_statusd_reg_t; +typedef uint32_t hri_pac_wrctrl_reg_t; +typedef uint8_t hri_pac_evctrl_reg_t; +typedef uint8_t hri_pac_intenset_reg_t; + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; +} + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH_ALT) >> PAC_INTFLAGAHB_FLASH_ALT_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH_ALT; +} + +static inline bool hri_pac_get_INTFLAGAHB_SEEPROM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SEEPROM) >> PAC_INTFLAGAHB_SEEPROM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SEEPROM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SEEPROM; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMCM4S_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMCM4S) >> PAC_INTFLAGAHB_RAMCM4S_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMCM4S_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMCM4S; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMPPPDSU) >> PAC_INTFLAGAHB_RAMPPPDSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMPPPDSU; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMAWR) >> PAC_INTFLAGAHB_RAMDMAWR_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMAWR; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMACICM) >> PAC_INTFLAGAHB_RAMDMACICM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMACICM; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB3) >> PAC_INTFLAGAHB_HPB3_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB3; +} + +static inline bool hri_pac_get_INTFLAGAHB_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_PUKCC) >> PAC_INTFLAGAHB_PUKCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_PUKCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_PUKCC; +} + +static inline bool hri_pac_get_INTFLAGAHB_SDHC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC0) >> PAC_INTFLAGAHB_SDHC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SDHC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC0; +} + +static inline bool hri_pac_get_INTFLAGAHB_SDHC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC1) >> PAC_INTFLAGAHB_SDHC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SDHC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC1; +} + +static inline bool hri_pac_get_INTFLAGAHB_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_QSPI) >> PAC_INTFLAGAHB_QSPI_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_QSPI_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_QSPI; +} + +static inline bool hri_pac_get_INTFLAGAHB_BKUPRAM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_BKUPRAM) >> PAC_INTFLAGAHB_BKUPRAM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_BKUPRAM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_BKUPRAM; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGAHB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGAHB.reg; +} + +static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGAHB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC; +} + +static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; +} + +static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; +} + +static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; +} + +static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; +} + +static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; +} + +static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; +} + +static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; +} + +static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; +} + +static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM; +} + +static inline bool hri_pac_get_INTFLAGA_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM0) >> PAC_INTFLAGA_SERCOM0_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SERCOM0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM0; +} + +static inline bool hri_pac_get_INTFLAGA_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM1) >> PAC_INTFLAGA_SERCOM1_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SERCOM1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM1; +} + +static inline bool hri_pac_get_INTFLAGA_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC0) >> PAC_INTFLAGA_TC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_TC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC0; +} + +static inline bool hri_pac_get_INTFLAGA_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC1) >> PAC_INTFLAGA_TC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_TC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC1; +} + +static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGA.reg; +} + +static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + ((Pac *)hw)->INTFLAGA.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB; +} + +static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; +} + +static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; +} + +static inline bool hri_pac_get_INTFLAGB_CMCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_CMCC) >> PAC_INTFLAGB_CMCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_CMCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_CMCC; +} + +static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT; +} + +static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC; +} + +static inline bool hri_pac_get_INTFLAGB_HMATRIX_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_HMATRIX) >> PAC_INTFLAGB_HMATRIX_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_HMATRIX_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_HMATRIX; +} + +static inline bool hri_pac_get_INTFLAGB_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_EVSYS) >> PAC_INTFLAGB_EVSYS_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_EVSYS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_EVSYS; +} + +static inline bool hri_pac_get_INTFLAGB_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM2) >> PAC_INTFLAGB_SERCOM2_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_SERCOM2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM2; +} + +static inline bool hri_pac_get_INTFLAGB_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM3) >> PAC_INTFLAGB_SERCOM3_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_SERCOM3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM3; +} + +static inline bool hri_pac_get_INTFLAGB_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC0) >> PAC_INTFLAGB_TCC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TCC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC0; +} + +static inline bool hri_pac_get_INTFLAGB_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC1) >> PAC_INTFLAGB_TCC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TCC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC1; +} + +static inline bool hri_pac_get_INTFLAGB_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC2) >> PAC_INTFLAGB_TC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC2; +} + +static inline bool hri_pac_get_INTFLAGB_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC3) >> PAC_INTFLAGB_TC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC3; +} + +static inline bool hri_pac_get_INTFLAGB_RAMECC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_RAMECC) >> PAC_INTFLAGB_RAMECC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_RAMECC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_RAMECC; +} + +static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGB.reg; +} + +static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGC_CAN0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN0) >> PAC_INTFLAGC_CAN0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CAN0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN0; +} + +static inline bool hri_pac_get_INTFLAGC_CAN1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN1) >> PAC_INTFLAGC_CAN1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CAN1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN1; +} + +static inline bool hri_pac_get_INTFLAGC_GMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_GMAC) >> PAC_INTFLAGC_GMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_GMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_GMAC; +} + +static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2; +} + +static inline bool hri_pac_get_INTFLAGC_TCC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC3) >> PAC_INTFLAGC_TCC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC3; +} + +static inline bool hri_pac_get_INTFLAGC_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC4) >> PAC_INTFLAGC_TC4_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC4; +} + +static inline bool hri_pac_get_INTFLAGC_TC5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC5) >> PAC_INTFLAGC_TC5_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC5; +} + +static inline bool hri_pac_get_INTFLAGC_PDEC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PDEC) >> PAC_INTFLAGC_PDEC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_PDEC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PDEC; +} + +static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC; +} + +static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES; +} + +static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG; +} + +static inline bool hri_pac_get_INTFLAGC_ICM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ICM) >> PAC_INTFLAGC_ICM_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_ICM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ICM; +} + +static inline bool hri_pac_get_INTFLAGC_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PUKCC) >> PAC_INTFLAGC_PUKCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_PUKCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PUKCC; +} + +static inline bool hri_pac_get_INTFLAGC_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_QSPI) >> PAC_INTFLAGC_QSPI_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_QSPI_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_QSPI; +} + +static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL; +} + +static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGC.reg; +} + +static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + ((Pac *)hw)->INTFLAGC.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM4) >> PAC_INTFLAGD_SERCOM4_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM4; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM5) >> PAC_INTFLAGD_SERCOM5_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM5; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM6_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM6) >> PAC_INTFLAGD_SERCOM6_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM6_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM6; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM7_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM7) >> PAC_INTFLAGD_SERCOM7_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM7_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM7; +} + +static inline bool hri_pac_get_INTFLAGD_TCC4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TCC4) >> PAC_INTFLAGD_TCC4_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TCC4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TCC4; +} + +static inline bool hri_pac_get_INTFLAGD_TC6_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC6) >> PAC_INTFLAGD_TC6_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TC6_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC6; +} + +static inline bool hri_pac_get_INTFLAGD_TC7_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC7) >> PAC_INTFLAGD_TC7_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TC7_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC7; +} + +static inline bool hri_pac_get_INTFLAGD_ADC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC0) >> PAC_INTFLAGD_ADC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_ADC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC0; +} + +static inline bool hri_pac_get_INTFLAGD_ADC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC1) >> PAC_INTFLAGD_ADC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_ADC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC1; +} + +static inline bool hri_pac_get_INTFLAGD_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_DAC) >> PAC_INTFLAGD_DAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_DAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_DAC; +} + +static inline bool hri_pac_get_INTFLAGD_I2S_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_I2S) >> PAC_INTFLAGD_I2S_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_I2S_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_I2S; +} + +static inline bool hri_pac_get_INTFLAGD_PCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_PCC) >> PAC_INTFLAGD_PCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_PCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_PCC; +} + +static inline hri_pac_intflagd_reg_t hri_pac_get_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGD.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagd_reg_t hri_pac_read_INTFLAGD_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGD.reg; +} + +static inline void hri_pac_clear_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) +{ + ((Pac *)hw)->INTFLAGD.reg = mask; +} + +static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; +} + +static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; +} + +static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; + } else { + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; + } +} + +static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; +} + +static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENSET.reg = mask; +} + +static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) +{ + return ((Pac *)hw)->INTENSET.reg; +} + +static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) +{ + ((Pac *)hw)->INTENSET.reg = data; + ((Pac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos; +} + +static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; +} + +static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; +} + +static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; +} + +static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; +} + +static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos; +} + +static inline bool hri_pac_get_STATUSA_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM0) >> PAC_STATUSA_SERCOM0_Pos; +} + +static inline bool hri_pac_get_STATUSA_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM1) >> PAC_STATUSA_SERCOM1_Pos; +} + +static inline bool hri_pac_get_STATUSA_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC0) >> PAC_STATUSA_TC0_Pos; +} + +static inline bool hri_pac_get_STATUSA_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC1) >> PAC_STATUSA_TC1_Pos; +} + +static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSA.reg; +} + +static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos; +} + +static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; +} + +static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSB_CMCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_CMCC) >> PAC_STATUSB_CMCC_Pos; +} + +static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos; +} + +static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos; +} + +static inline bool hri_pac_get_STATUSB_HMATRIX_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_HMATRIX) >> PAC_STATUSB_HMATRIX_Pos; +} + +static inline bool hri_pac_get_STATUSB_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_EVSYS) >> PAC_STATUSB_EVSYS_Pos; +} + +static inline bool hri_pac_get_STATUSB_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM2) >> PAC_STATUSB_SERCOM2_Pos; +} + +static inline bool hri_pac_get_STATUSB_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM3) >> PAC_STATUSB_SERCOM3_Pos; +} + +static inline bool hri_pac_get_STATUSB_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC0) >> PAC_STATUSB_TCC0_Pos; +} + +static inline bool hri_pac_get_STATUSB_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC1) >> PAC_STATUSB_TCC1_Pos; +} + +static inline bool hri_pac_get_STATUSB_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC2) >> PAC_STATUSB_TC2_Pos; +} + +static inline bool hri_pac_get_STATUSB_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC3) >> PAC_STATUSB_TC3_Pos; +} + +static inline bool hri_pac_get_STATUSB_RAMECC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_RAMECC) >> PAC_STATUSB_RAMECC_Pos; +} + +static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSB.reg; +} + +static inline bool hri_pac_get_STATUSC_CAN0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN0) >> PAC_STATUSC_CAN0_Pos; +} + +static inline bool hri_pac_get_STATUSC_CAN1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN1) >> PAC_STATUSC_CAN1_Pos; +} + +static inline bool hri_pac_get_STATUSC_GMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_GMAC) >> PAC_STATUSC_GMAC_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC3) >> PAC_STATUSC_TCC3_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC4) >> PAC_STATUSC_TC4_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC5) >> PAC_STATUSC_TC5_Pos; +} + +static inline bool hri_pac_get_STATUSC_PDEC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PDEC) >> PAC_STATUSC_PDEC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos; +} + +static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos; +} + +static inline bool hri_pac_get_STATUSC_ICM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ICM) >> PAC_STATUSC_ICM_Pos; +} + +static inline bool hri_pac_get_STATUSC_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PUKCC) >> PAC_STATUSC_PUKCC_Pos; +} + +static inline bool hri_pac_get_STATUSC_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_QSPI) >> PAC_STATUSC_QSPI_Pos; +} + +static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos; +} + +static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSC.reg; +} + +static inline bool hri_pac_get_STATUSD_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM4) >> PAC_STATUSD_SERCOM4_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM5) >> PAC_STATUSD_SERCOM5_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM6_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM6) >> PAC_STATUSD_SERCOM6_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM7_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM7) >> PAC_STATUSD_SERCOM7_Pos; +} + +static inline bool hri_pac_get_STATUSD_TCC4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TCC4) >> PAC_STATUSD_TCC4_Pos; +} + +static inline bool hri_pac_get_STATUSD_TC6_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC6) >> PAC_STATUSD_TC6_Pos; +} + +static inline bool hri_pac_get_STATUSD_TC7_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC7) >> PAC_STATUSD_TC7_Pos; +} + +static inline bool hri_pac_get_STATUSD_ADC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC0) >> PAC_STATUSD_ADC0_Pos; +} + +static inline bool hri_pac_get_STATUSD_ADC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC1) >> PAC_STATUSD_ADC1_Pos; +} + +static inline bool hri_pac_get_STATUSD_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_DAC) >> PAC_STATUSD_DAC_Pos; +} + +static inline bool hri_pac_get_STATUSD_I2S_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_I2S) >> PAC_STATUSD_I2S_Pos; +} + +static inline bool hri_pac_get_STATUSD_PCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_PCC) >> PAC_STATUSD_PCC_Pos; +} + +static inline hri_pac_statusd_reg_t hri_pac_get_STATUSD_reg(const void *const hw, hri_pac_statusd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSD.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusd_reg_t hri_pac_read_STATUSD_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSD.reg; +} + +static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_PERID_Msk; + tmp |= PAC_WRCTRL_PERID(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_KEY_Msk; + tmp |= PAC_WRCTRL_KEY(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->WRCTRL.reg; +} + +static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= ~PAC_EVCTRL_ERREO; + tmp |= value << PAC_EVCTRL_ERREO_Pos; + ((Pac *)hw)->EVCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PAC_E54_H_INCLUDED */ +#endif /* _SAME54_PAC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pcc_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pcc_e54.h new file mode 100644 index 0000000..42a5600 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pcc_e54.h @@ -0,0 +1,298 @@ +/** + * \file + * + * \brief SAM PCC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PCC_COMPONENT_ +#ifndef _HRI_PCC_E54_H_INCLUDED_ +#define _HRI_PCC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PCC_CRITICAL_SECTIONS) +#define PCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PCC_CRITICAL_SECTION_ENTER() +#define PCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pcc_imr_reg_t; +typedef uint32_t hri_pcc_isr_reg_t; +typedef uint32_t hri_pcc_mr_reg_t; +typedef uint32_t hri_pcc_rhr_reg_t; +typedef uint32_t hri_pcc_wpmr_reg_t; +typedef uint32_t hri_pcc_wpsr_reg_t; + +static inline void hri_pcc_set_IMR_DRDY_bit(const void *const hw) +{ + ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; +} + +static inline bool hri_pcc_get_IMR_DRDY_bit(const void *const hw) +{ + return (((Pcc *)hw)->IMR.reg & PCC_IMR_DRDY) >> PCC_IMR_DRDY_Pos; +} + +static inline void hri_pcc_write_IMR_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; + } else { + ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; + } +} + +static inline void hri_pcc_clear_IMR_DRDY_bit(const void *const hw) +{ + ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; +} + +static inline void hri_pcc_set_IMR_OVRE_bit(const void *const hw) +{ + ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; +} + +static inline bool hri_pcc_get_IMR_OVRE_bit(const void *const hw) +{ + return (((Pcc *)hw)->IMR.reg & PCC_IMR_OVRE) >> PCC_IMR_OVRE_Pos; +} + +static inline void hri_pcc_write_IMR_OVRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; + } else { + ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; + } +} + +static inline void hri_pcc_clear_IMR_OVRE_bit(const void *const hw) +{ + ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; +} + +static inline void hri_pcc_set_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + ((Pcc *)hw)->IER.reg = mask; +} + +static inline hri_pcc_imr_reg_t hri_pcc_get_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->IMR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_imr_reg_t hri_pcc_read_IMR_reg(const void *const hw) +{ + return ((Pcc *)hw)->IMR.reg; +} + +static inline void hri_pcc_write_IMR_reg(const void *const hw, hri_pcc_imr_reg_t data) +{ + ((Pcc *)hw)->IER.reg = data; + ((Pcc *)hw)->IDR.reg = ~data; +} + +static inline void hri_pcc_clear_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + ((Pcc *)hw)->IDR.reg = mask; +} + +static inline bool hri_pcc_get_ISR_DRDY_bit(const void *const hw) +{ + return (((Pcc *)hw)->ISR.reg & PCC_ISR_DRDY) >> PCC_ISR_DRDY_Pos; +} + +static inline bool hri_pcc_get_ISR_OVRE_bit(const void *const hw) +{ + return (((Pcc *)hw)->ISR.reg & PCC_ISR_OVRE) >> PCC_ISR_OVRE_Pos; +} + +static inline hri_pcc_isr_reg_t hri_pcc_get_ISR_reg(const void *const hw, hri_pcc_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->ISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_isr_reg_t hri_pcc_read_ISR_reg(const void *const hw) +{ + return ((Pcc *)hw)->ISR.reg; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_RDATA_bf(const void *const hw, hri_pcc_rhr_reg_t mask) +{ + return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA(mask)) >> PCC_RHR_RDATA_Pos; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_RDATA_bf(const void *const hw) +{ + return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA_Msk) >> PCC_RHR_RDATA_Pos; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_reg(const void *const hw, hri_pcc_rhr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->RHR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_reg(const void *const hw) +{ + return ((Pcc *)hw)->RHR.reg; +} + +static inline bool hri_pcc_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVS) >> PCC_WPSR_WPVS_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_WPVSRC_bf(const void *const hw, hri_pcc_wpsr_reg_t mask) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC(mask)) >> PCC_WPSR_WPVSRC_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC_Msk) >> PCC_WPSR_WPVSRC_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_reg(const void *const hw, hri_pcc_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->WPSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_reg(const void *const hw) +{ + return ((Pcc *)hw)->WPSR.reg; +} + +static inline void hri_pcc_set_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg |= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_mr_reg_t hri_pcc_get_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->MR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pcc_write_MR_reg(const void *const hw, hri_pcc_mr_reg_t data) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg = data; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_clear_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg &= ~mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_toggle_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg ^= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_mr_reg_t hri_pcc_read_MR_reg(const void *const hw) +{ + return ((Pcc *)hw)->MR.reg; +} + +static inline void hri_pcc_set_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg |= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_wpmr_reg_t hri_pcc_get_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->WPMR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pcc_write_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t data) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg = data; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_clear_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg &= ~mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_toggle_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg ^= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_wpmr_reg_t hri_pcc_read_WPMR_reg(const void *const hw) +{ + return ((Pcc *)hw)->WPMR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PCC_E54_H_INCLUDED */ +#endif /* _SAME54_PCC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pdec_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pdec_e54.h new file mode 100644 index 0000000..ec7ce30 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pdec_e54.h @@ -0,0 +1,2684 @@ +/** + * \file + * + * \brief SAM PDEC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PDEC_COMPONENT_ +#ifndef _HRI_PDEC_E54_H_INCLUDED_ +#define _HRI_PDEC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PDEC_CRITICAL_SECTIONS) +#define PDEC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PDEC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PDEC_CRITICAL_SECTION_ENTER() +#define PDEC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_pdec_evctrl_reg_t; +typedef uint16_t hri_pdec_status_reg_t; +typedef uint32_t hri_pdec_cc_reg_t; +typedef uint32_t hri_pdec_ccbuf_reg_t; +typedef uint32_t hri_pdec_count_reg_t; +typedef uint32_t hri_pdec_ctrla_reg_t; +typedef uint32_t hri_pdec_syncbusy_reg_t; +typedef uint8_t hri_pdec_ctrlbset_reg_t; +typedef uint8_t hri_pdec_dbgctrl_reg_t; +typedef uint8_t hri_pdec_filter_reg_t; +typedef uint8_t hri_pdec_filterbuf_reg_t; +typedef uint8_t hri_pdec_intenset_reg_t; +typedef uint8_t hri_pdec_intflag_reg_t; +typedef uint8_t hri_pdec_presc_reg_t; +typedef uint8_t hri_pdec_prescbuf_reg_t; + +static inline void hri_pdec_wait_for_sync(const void *const hw, hri_pdec_syncbusy_reg_t reg) +{ + while (((Pdec *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_pdec_is_syncing(const void *const hw, hri_pdec_syncbusy_reg_t reg) +{ + return ((Pdec *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_pdec_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; +} + +static inline bool hri_pdec_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; +} + +static inline bool hri_pdec_get_INTFLAG_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; +} + +static inline bool hri_pdec_get_INTFLAG_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; +} + +static inline bool hri_pdec_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; +} + +static inline bool hri_pdec_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; +} + +static inline bool hri_pdec_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; +} + +static inline void hri_pdec_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; +} + +static inline bool hri_pdec_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; +} + +static inline void hri_pdec_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; +} + +static inline bool hri_pdec_get_interrupt_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; +} + +static inline void hri_pdec_clear_interrupt_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; +} + +static inline bool hri_pdec_get_interrupt_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; +} + +static inline void hri_pdec_clear_interrupt_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; +} + +static inline bool hri_pdec_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; +} + +static inline void hri_pdec_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; +} + +static inline bool hri_pdec_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; +} + +static inline void hri_pdec_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; +} + +static inline hri_pdec_intflag_reg_t hri_pdec_get_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_intflag_reg_t hri_pdec_read_INTFLAG_reg(const void *const hw) +{ + return ((Pdec *)hw)->INTFLAG.reg; +} + +static inline void hri_pdec_clear_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) +{ + ((Pdec *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_pdec_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; +} + +static inline bool hri_pdec_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Pdec *)hw)->CTRLBSET.reg & PDEC_CTRLBSET_LUPD) >> PDEC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_pdec_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; + } else { + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; + } +} + +static inline void hri_pdec_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; +} + +static inline void hri_pdec_set_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(mask); +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp = (tmp & PDEC_CTRLBSET_CMD(mask)) >> PDEC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp = (tmp & PDEC_CTRLBSET_CMD_Msk) >> PDEC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t data) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(data); + ((Pdec *)hw)->CTRLBCLR.reg = ~PDEC_CTRLBSET_CMD(data); +} + +static inline void hri_pdec_clear_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_CMD(mask); +} + +static inline void hri_pdec_set_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_reg(const void *const hw) +{ + return ((Pdec *)hw)->CTRLBSET.reg; +} + +static inline void hri_pdec_write_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t data) +{ + ((Pdec *)hw)->CTRLBSET.reg = data; + ((Pdec *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_pdec_clear_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_pdec_set_INTEN_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; +} + +static inline bool hri_pdec_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_OVF) >> PDEC_INTENSET_OVF_Pos; +} + +static inline void hri_pdec_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; + } +} + +static inline void hri_pdec_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; +} + +static inline void hri_pdec_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; +} + +static inline bool hri_pdec_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_ERR) >> PDEC_INTENSET_ERR_Pos; +} + +static inline void hri_pdec_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; + } +} + +static inline void hri_pdec_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; +} + +static inline void hri_pdec_set_INTEN_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; +} + +static inline bool hri_pdec_get_INTEN_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_DIR) >> PDEC_INTENSET_DIR_Pos; +} + +static inline void hri_pdec_write_INTEN_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; + } +} + +static inline void hri_pdec_clear_INTEN_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; +} + +static inline void hri_pdec_set_INTEN_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; +} + +static inline bool hri_pdec_get_INTEN_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_VLC) >> PDEC_INTENSET_VLC_Pos; +} + +static inline void hri_pdec_write_INTEN_VLC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; + } +} + +static inline void hri_pdec_clear_INTEN_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; +} + +static inline void hri_pdec_set_INTEN_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; +} + +static inline bool hri_pdec_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC0) >> PDEC_INTENSET_MC0_Pos; +} + +static inline void hri_pdec_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; + } +} + +static inline void hri_pdec_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; +} + +static inline void hri_pdec_set_INTEN_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; +} + +static inline bool hri_pdec_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC1) >> PDEC_INTENSET_MC1_Pos; +} + +static inline void hri_pdec_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; + } +} + +static inline void hri_pdec_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; +} + +static inline void hri_pdec_set_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + ((Pdec *)hw)->INTENSET.reg = mask; +} + +static inline hri_pdec_intenset_reg_t hri_pdec_get_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_intenset_reg_t hri_pdec_read_INTEN_reg(const void *const hw) +{ + return ((Pdec *)hw)->INTENSET.reg; +} + +static inline void hri_pdec_write_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t data) +{ + ((Pdec *)hw)->INTENSET.reg = data; + ((Pdec *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pdec_clear_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + ((Pdec *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pdec_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_SWRST) >> PDEC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_ENABLE) >> PDEC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CTRLB) >> PDEC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_STATUS) >> PDEC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_PRESC_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_PRESC) >> PDEC_SYNCBUSY_PRESC_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_FILTER_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_FILTER) >> PDEC_SYNCBUSY_FILTER_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_COUNT) >> PDEC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC0) >> PDEC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC1) >> PDEC_SYNCBUSY_CC1_Pos; +} + +static inline hri_pdec_syncbusy_reg_t hri_pdec_get_SYNCBUSY_reg(const void *const hw, hri_pdec_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_syncbusy_reg_t hri_pdec_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Pdec *)hw)->SYNCBUSY.reg; +} + +static inline void hri_pdec_set_CTRLA_SWRST_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWRST; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_SWRST) >> PDEC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_set_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ENABLE; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ENABLE) >> PDEC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ENABLE; + tmp |= value << PDEC_CTRLA_ENABLE_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ENABLE; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ENABLE; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_RUNSTDBY; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_RUNSTDBY) >> PDEC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_RUNSTDBY; + tmp |= value << PDEC_CTRLA_RUNSTDBY_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_RUNSTDBY; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_RUNSTDBY; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ALOCK; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ALOCK) >> PDEC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ALOCK; + tmp |= value << PDEC_CTRLA_ALOCK_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ALOCK; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ALOCK; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWAP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_SWAP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_SWAP) >> PDEC_CTRLA_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_SWAP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_SWAP; + tmp |= value << PDEC_CTRLA_SWAP_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_SWAP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_SWAP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PEREN; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PEREN) >> PDEC_CTRLA_PEREN_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PEREN; + tmp |= value << PDEC_CTRLA_PEREN_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PEREN; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PEREN; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN0) >> PDEC_CTRLA_PINEN0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN0; + tmp |= value << PDEC_CTRLA_PINEN0_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN1) >> PDEC_CTRLA_PINEN1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN1; + tmp |= value << PDEC_CTRLA_PINEN1_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN2) >> PDEC_CTRLA_PINEN2_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN2; + tmp |= value << PDEC_CTRLA_PINEN2_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN0) >> PDEC_CTRLA_PINVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN0; + tmp |= value << PDEC_CTRLA_PINVEN0_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN1) >> PDEC_CTRLA_PINVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN1; + tmp |= value << PDEC_CTRLA_PINVEN1_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN2) >> PDEC_CTRLA_PINVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN2; + tmp |= value << PDEC_CTRLA_PINVEN2_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MODE(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MODE(mask)) >> PDEC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_MODE_Msk; + tmp |= PDEC_CTRLA_MODE(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MODE(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MODE(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MODE_Msk) >> PDEC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_CONF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_CONF(mask)) >> PDEC_CTRLA_CONF_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_CONF_Msk; + tmp |= PDEC_CTRLA_CONF(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_CONF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_CONF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_CONF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_CONF_Msk) >> PDEC_CTRLA_CONF_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ANGULAR(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ANGULAR(mask)) >> PDEC_CTRLA_ANGULAR_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ANGULAR_Msk; + tmp |= PDEC_CTRLA_ANGULAR(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ANGULAR(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ANGULAR(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_ANGULAR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ANGULAR_Msk) >> PDEC_CTRLA_ANGULAR_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MAXCMP(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MAXCMP(mask)) >> PDEC_CTRLA_MAXCMP_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_MAXCMP_Msk; + tmp |= PDEC_CTRLA_MAXCMP(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MAXCMP(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MAXCMP(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MAXCMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MAXCMP_Msk) >> PDEC_CTRLA_MAXCMP_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + return ((Pdec *)hw)->CTRLA.reg; +} + +static inline void hri_pdec_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_OVFEO) >> PDEC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_OVFEO; + tmp |= value << PDEC_EVCTRL_OVFEO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_ERREO) >> PDEC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_ERREO; + tmp |= value << PDEC_EVCTRL_ERREO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_DIREO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_DIREO) >> PDEC_EVCTRL_DIREO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_DIREO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_DIREO; + tmp |= value << PDEC_EVCTRL_DIREO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_VLCEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_VLCEO) >> PDEC_EVCTRL_VLCEO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_VLCEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_VLCEO; + tmp |= value << PDEC_EVCTRL_VLCEO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_MCEO0) >> PDEC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_MCEO0; + tmp |= value << PDEC_EVCTRL_MCEO0_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_MCEO1) >> PDEC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_MCEO1; + tmp |= value << PDEC_EVCTRL_MCEO1_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVACT(mask)) >> PDEC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVACT_Msk; + tmp |= PDEC_EVCTRL_EVACT(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVACT_Msk) >> PDEC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVINV(mask)) >> PDEC_EVCTRL_EVINV_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVINV_Msk; + tmp |= PDEC_EVCTRL_EVINV(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVINV_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVINV_Msk) >> PDEC_EVCTRL_EVINV_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVEI(mask)) >> PDEC_EVCTRL_EVEI_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVEI_Msk; + tmp |= PDEC_EVCTRL_EVEI(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVEI_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVEI_Msk) >> PDEC_EVCTRL_EVEI_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_reg(const void *const hw) +{ + return ((Pdec *)hw)->EVCTRL.reg; +} + +static inline void hri_pdec_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg |= PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp = (tmp & PDEC_DBGCTRL_DBGRUN) >> PDEC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp &= ~PDEC_DBGCTRL_DBGRUN; + tmp |= value << PDEC_DBGCTRL_DBGRUN_Pos; + ((Pdec *)hw)->DBGCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg &= ~PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg ^= PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_dbgctrl_reg_t hri_pdec_get_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_dbgctrl_reg_t hri_pdec_read_DBGCTRL_reg(const void *const hw) +{ + return ((Pdec *)hw)->DBGCTRL.reg; +} + +static inline void hri_pdec_set_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg |= PDEC_PRESC_PRESC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp = (tmp & PDEC_PRESC_PRESC(mask)) >> PDEC_PRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_pdec_write_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp &= ~PDEC_PRESC_PRESC_Msk; + tmp |= PDEC_PRESC_PRESC(data); + ((Pdec *)hw)->PRESC.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg &= ~PDEC_PRESC_PRESC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg ^= PDEC_PRESC_PRESC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_PRESC_bf(const void *const hw) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp = (tmp & PDEC_PRESC_PRESC_Msk) >> PDEC_PRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_pdec_set_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + return ((Pdec *)hw)->PRESC.reg; +} + +static inline void hri_pdec_set_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg |= PDEC_FILTER_FILTER(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp = (tmp & PDEC_FILTER_FILTER(mask)) >> PDEC_FILTER_FILTER_Pos; + return tmp; +} + +static inline void hri_pdec_write_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp &= ~PDEC_FILTER_FILTER_Msk; + tmp |= PDEC_FILTER_FILTER(data); + ((Pdec *)hw)->FILTER.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg &= ~PDEC_FILTER_FILTER(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg ^= PDEC_FILTER_FILTER(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_FILTER_bf(const void *const hw) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp = (tmp & PDEC_FILTER_FILTER_Msk) >> PDEC_FILTER_FILTER_Pos; + return tmp; +} + +static inline void hri_pdec_set_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + return ((Pdec *)hw)->FILTER.reg; +} + +static inline void hri_pdec_set_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg |= PDEC_PRESCBUF_PRESCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_PRESCBUF_bf(const void *const hw, + hri_pdec_prescbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp = (tmp & PDEC_PRESCBUF_PRESCBUF(mask)) >> PDEC_PRESCBUF_PRESCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp &= ~PDEC_PRESCBUF_PRESCBUF_Msk; + tmp |= PDEC_PRESCBUF_PRESCBUF(data); + ((Pdec *)hw)->PRESCBUF.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg &= ~PDEC_PRESCBUF_PRESCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg ^= PDEC_PRESCBUF_PRESCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_PRESCBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp = (tmp & PDEC_PRESCBUF_PRESCBUF_Msk) >> PDEC_PRESCBUF_PRESCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->PRESCBUF.reg; +} + +static inline void hri_pdec_set_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg |= PDEC_FILTERBUF_FILTERBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_FILTERBUF_bf(const void *const hw, + hri_pdec_filterbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp = (tmp & PDEC_FILTERBUF_FILTERBUF(mask)) >> PDEC_FILTERBUF_FILTERBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp &= ~PDEC_FILTERBUF_FILTERBUF_Msk; + tmp |= PDEC_FILTERBUF_FILTERBUF(data); + ((Pdec *)hw)->FILTERBUF.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg &= ~PDEC_FILTERBUF_FILTERBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg ^= PDEC_FILTERBUF_FILTERBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_FILTERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp = (tmp & PDEC_FILTERBUF_FILTERBUF_Msk) >> PDEC_FILTERBUF_FILTERBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->FILTERBUF.reg; +} + +static inline void hri_pdec_set_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg |= PDEC_COUNT_COUNT(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp = (tmp & PDEC_COUNT_COUNT(mask)) >> PDEC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_pdec_write_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp &= ~PDEC_COUNT_COUNT_Msk; + tmp |= PDEC_COUNT_COUNT(data); + ((Pdec *)hw)->COUNT.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg &= ~PDEC_COUNT_COUNT(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg ^= PDEC_COUNT_COUNT(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp = (tmp & PDEC_COUNT_COUNT_Msk) >> PDEC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_pdec_set_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_COUNT_reg(const void *const hw, hri_pdec_count_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + return ((Pdec *)hw)->COUNT.reg; +} + +static inline void hri_pdec_set_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg |= PDEC_CC_CC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_get_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp = (tmp & PDEC_CC_CC(mask)) >> PDEC_CC_CC_Pos; + return tmp; +} + +static inline void hri_pdec_write_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp &= ~PDEC_CC_CC_Msk; + tmp |= PDEC_CC_CC(data); + ((Pdec *)hw)->CC[index].reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg &= ~PDEC_CC_CC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg ^= PDEC_CC_CC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp = (tmp & PDEC_CC_CC_Msk) >> PDEC_CC_CC_Pos; + return tmp; +} + +static inline void hri_pdec_set_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_get_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + return ((Pdec *)hw)->CC[index].reg; +} + +static inline void hri_pdec_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg |= PDEC_CCBUF_CCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_pdec_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp = (tmp & PDEC_CCBUF_CCBUF(mask)) >> PDEC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp &= ~PDEC_CCBUF_CCBUF_Msk; + tmp |= PDEC_CCBUF_CCBUF(data); + ((Pdec *)hw)->CCBUF[index].reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg &= ~PDEC_CCBUF_CCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg ^= PDEC_CCBUF_CCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp = (tmp & PDEC_CCBUF_CCBUF_Msk) >> PDEC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_pdec_ccbuf_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->CCBUF[index].reg; +} + +static inline bool hri_pdec_get_STATUS_QERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_QERR) >> PDEC_STATUS_QERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_QERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_QERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_IDXERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_IDXERR) >> PDEC_STATUS_IDXERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_IDXERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_IDXERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_MPERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_MPERR) >> PDEC_STATUS_MPERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_MPERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_MPERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_WINERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_WINERR) >> PDEC_STATUS_WINERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_WINERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_WINERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_HERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_HERR) >> PDEC_STATUS_HERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_HERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_HERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_STOP_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_STOP) >> PDEC_STATUS_STOP_Pos; +} + +static inline void hri_pdec_clear_STATUS_STOP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_STOP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_DIR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_DIR) >> PDEC_STATUS_DIR_Pos; +} + +static inline void hri_pdec_clear_STATUS_DIR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_DIR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_PRESCBUFV_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_PRESCBUFV) >> PDEC_STATUS_PRESCBUFV_Pos; +} + +static inline void hri_pdec_clear_STATUS_PRESCBUFV_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_PRESCBUFV; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_FILTERBUFV_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_FILTERBUFV) >> PDEC_STATUS_FILTERBUFV_Pos; +} + +static inline void hri_pdec_clear_STATUS_FILTERBUFV_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_FILTERBUFV; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV0) >> PDEC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_pdec_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV1) >> PDEC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_pdec_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_status_reg_t hri_pdec_get_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) +{ + uint16_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_clear_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_status_reg_t hri_pdec_read_STATUS_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PDEC_E54_H_INCLUDED */ +#endif /* _SAME54_PDEC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pm_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pm_e54.h new file mode 100644 index 0000000..0b91bee --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pm_e54.h @@ -0,0 +1,820 @@ +/** + * \file + * + * \brief SAM PM + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PM_COMPONENT_ +#ifndef _HRI_PM_E54_H_INCLUDED_ +#define _HRI_PM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PM_CRITICAL_SECTIONS) +#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PM_CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint8_t hri_pm_bkupcfg_reg_t; +typedef uint8_t hri_pm_ctrla_reg_t; +typedef uint8_t hri_pm_hibcfg_reg_t; +typedef uint8_t hri_pm_intenset_reg_t; +typedef uint8_t hri_pm_intflag_reg_t; +typedef uint8_t hri_pm_pwsakdly_reg_t; +typedef uint8_t hri_pm_sleepcfg_reg_t; +typedef uint8_t hri_pm_stdbycfg_reg_t; + +static inline bool hri_pm_get_INTFLAG_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; +} + +static inline void hri_pm_clear_INTFLAG_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; +} + +static inline bool hri_pm_get_interrupt_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; +} + +static inline void hri_pm_clear_interrupt_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; +} + +static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) +{ + return ((Pm *)hw)->INTFLAG.reg; +} + +static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + ((Pm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_pm_set_INTEN_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; +} + +static inline bool hri_pm_get_INTEN_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_SLEEPRDY) >> PM_INTENSET_SLEEPRDY_Pos; +} + +static inline void hri_pm_write_INTEN_SLEEPRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; + } else { + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; + } +} + +static inline void hri_pm_clear_INTEN_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; +} + +static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENSET.reg = mask; +} + +static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) +{ + return ((Pm *)hw)->INTENSET.reg; +} + +static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) +{ + ((Pm *)hw)->INTENSET.reg = data; + ((Pm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= ~PM_CTRLA_IORET; + tmp |= value << PM_CTRLA_IORET_Pos; + ((Pm *)hw)->CTRLA.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw) +{ + return ((Pm *)hw)->CTRLA.reg; +} + +static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; + tmp |= PM_SLEEPCFG_SLEEPMODE(data); + ((Pm *)hw)->SLEEPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->SLEEPCFG.reg; +} + +static inline void hri_pm_set_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_RAMCFG(mask)) >> PM_STDBYCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_RAMCFG_Msk; + tmp |= PM_STDBYCFG_RAMCFG(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_RAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_RAMCFG_Msk) >> PM_STDBYCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_FASTWKUP(mask)) >> PM_STDBYCFG_FASTWKUP_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_FASTWKUP_Msk; + tmp |= PM_STDBYCFG_FASTWKUP(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_FASTWKUP_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_FASTWKUP_Msk) >> PM_STDBYCFG_FASTWKUP_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->STDBYCFG.reg; +} + +static inline void hri_pm_set_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_RAMCFG(mask)) >> PM_HIBCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= ~PM_HIBCFG_RAMCFG_Msk; + tmp |= PM_HIBCFG_RAMCFG(data); + ((Pm *)hw)->HIBCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_RAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_RAMCFG_Msk) >> PM_HIBCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_BRAMCFG(mask)) >> PM_HIBCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= ~PM_HIBCFG_BRAMCFG_Msk; + tmp |= PM_HIBCFG_BRAMCFG(data); + ((Pm *)hw)->HIBCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_BRAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_BRAMCFG_Msk) >> PM_HIBCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->HIBCFG.reg; +} + +static inline void hri_pm_set_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg |= PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp = (tmp & PM_BKUPCFG_BRAMCFG(mask)) >> PM_BKUPCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp &= ~PM_BKUPCFG_BRAMCFG_Msk; + tmp |= PM_BKUPCFG_BRAMCFG(data); + ((Pm *)hw)->BKUPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg &= ~PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg ^= PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_BRAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp = (tmp & PM_BKUPCFG_BRAMCFG_Msk) >> PM_BKUPCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->BKUPCFG.reg; +} + +static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= ~PM_PWSAKDLY_IGNACK; + tmp |= value << PM_PWSAKDLY_IGNACK_Pos; + ((Pm *)hw)->PWSAKDLY.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos; + return tmp; +} + +static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= ~PM_PWSAKDLY_DLYVAL_Msk; + tmp |= PM_PWSAKDLY_DLYVAL(data); + ((Pm *)hw)->PWSAKDLY.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos; + return tmp; +} + +static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw) +{ + return ((Pm *)hw)->PWSAKDLY.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PM_E54_H_INCLUDED */ +#endif /* _SAME54_PM_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_port_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_port_e54.h new file mode 100644 index 0000000..261fcf5 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_port_e54.h @@ -0,0 +1,2528 @@ +/** + * \file + * + * \brief SAM PORT + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PORT_COMPONENT_ +#ifndef _HRI_PORT_E54_H_INCLUDED_ +#define _HRI_PORT_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PORT_CRITICAL_SECTIONS) +#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PORT_CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_port_ctrl_reg_t; +typedef uint32_t hri_port_dir_reg_t; +typedef uint32_t hri_port_evctrl_reg_t; +typedef uint32_t hri_port_in_reg_t; +typedef uint32_t hri_port_out_reg_t; +typedef uint32_t hri_port_wrconfig_reg_t; +typedef uint32_t hri_portgroup_ctrl_reg_t; +typedef uint32_t hri_portgroup_dir_reg_t; +typedef uint32_t hri_portgroup_evctrl_reg_t; +typedef uint32_t hri_portgroup_in_reg_t; +typedef uint32_t hri_portgroup_out_reg_t; +typedef uint32_t hri_portgroup_wrconfig_reg_t; +typedef uint8_t hri_port_pincfg_reg_t; +typedef uint8_t hri_port_pmux_reg_t; +typedef uint8_t hri_portgroup_pincfg_reg_t; +typedef uint8_t hri_portgroup_pmux_reg_t; + +static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data); + ((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) +{ + return ((PortGroup *)hw)->DIR.reg; +} + +static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = data; + ((PortGroup *)hw)->DIRCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = mask; +} + +static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data); + ((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) +{ + return ((PortGroup *)hw)->OUT.reg; +} + +static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = data; + ((PortGroup *)hw)->OUTCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) +{ + return ((PortGroup *)hw)->IN.reg; +} + +static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((PortGroup *)hw)->CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->CTRL.reg; +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->EVCTRL.reg; +} + +static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PMUX[index].reg; +} + +static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PINCFG[index].reg; +} + +static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data); + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].DIR.reg; +} + +static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; +} + +static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; +} + +static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; +} + +static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data); + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].OUT.reg; +} + +static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; +} + +static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; +} + +static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].IN.reg; +} + +static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].CTRL.reg; +} + +static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].EVCTRL.reg; +} + +static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; +} + +static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; +} + +static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, + hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PORT_E54_H_INCLUDED */ +#endif /* _SAME54_PORT_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_qspi_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_qspi_e54.h new file mode 100644 index 0000000..23742bc --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_qspi_e54.h @@ -0,0 +1,2058 @@ +/** + * \file + * + * \brief SAM QSPI + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_QSPI_COMPONENT_ +#ifndef _HRI_QSPI_E54_H_INCLUDED_ +#define _HRI_QSPI_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_QSPI_CRITICAL_SECTIONS) +#define QSPI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define QSPI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define QSPI_CRITICAL_SECTION_ENTER() +#define QSPI_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_qspi_baud_reg_t; +typedef uint32_t hri_qspi_ctrla_reg_t; +typedef uint32_t hri_qspi_ctrlb_reg_t; +typedef uint32_t hri_qspi_instraddr_reg_t; +typedef uint32_t hri_qspi_instrctrl_reg_t; +typedef uint32_t hri_qspi_instrframe_reg_t; +typedef uint32_t hri_qspi_intenset_reg_t; +typedef uint32_t hri_qspi_intflag_reg_t; +typedef uint32_t hri_qspi_rxdata_reg_t; +typedef uint32_t hri_qspi_scrambctrl_reg_t; +typedef uint32_t hri_qspi_scrambkey_reg_t; +typedef uint32_t hri_qspi_status_reg_t; +typedef uint32_t hri_qspi_txdata_reg_t; + +static inline bool hri_qspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; +} + +static inline bool hri_qspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; +} + +static inline bool hri_qspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; +} + +static inline bool hri_qspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; +} + +static inline bool hri_qspi_get_INTFLAG_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; +} + +static inline bool hri_qspi_get_INTFLAG_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; +} + +static inline bool hri_qspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; +} + +static inline void hri_qspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; +} + +static inline bool hri_qspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; +} + +static inline void hri_qspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; +} + +static inline bool hri_qspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; +} + +static inline void hri_qspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; +} + +static inline bool hri_qspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_qspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; +} + +static inline bool hri_qspi_get_interrupt_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; +} + +static inline void hri_qspi_clear_interrupt_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; +} + +static inline bool hri_qspi_get_interrupt_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; +} + +static inline void hri_qspi_clear_interrupt_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; +} + +static inline hri_qspi_intflag_reg_t hri_qspi_get_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_intflag_reg_t hri_qspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Qspi *)hw)->INTFLAG.reg; +} + +static inline void hri_qspi_clear_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) +{ + ((Qspi *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_qspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; +} + +static inline bool hri_qspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_RXC) >> QSPI_INTENSET_RXC_Pos; +} + +static inline void hri_qspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; + } +} + +static inline void hri_qspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; +} + +static inline void hri_qspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; +} + +static inline bool hri_qspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_DRE) >> QSPI_INTENSET_DRE_Pos; +} + +static inline void hri_qspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; + } +} + +static inline void hri_qspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; +} + +static inline void hri_qspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; +} + +static inline bool hri_qspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_TXC) >> QSPI_INTENSET_TXC_Pos; +} + +static inline void hri_qspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; + } +} + +static inline void hri_qspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; +} + +static inline void hri_qspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; +} + +static inline bool hri_qspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_ERROR) >> QSPI_INTENSET_ERROR_Pos; +} + +static inline void hri_qspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; + } +} + +static inline void hri_qspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; +} + +static inline void hri_qspi_set_INTEN_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; +} + +static inline bool hri_qspi_get_INTEN_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_CSRISE) >> QSPI_INTENSET_CSRISE_Pos; +} + +static inline void hri_qspi_write_INTEN_CSRISE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; + } +} + +static inline void hri_qspi_clear_INTEN_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; +} + +static inline void hri_qspi_set_INTEN_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; +} + +static inline bool hri_qspi_get_INTEN_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_INSTREND) >> QSPI_INTENSET_INSTREND_Pos; +} + +static inline void hri_qspi_write_INTEN_INSTREND_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; + } +} + +static inline void hri_qspi_clear_INTEN_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; +} + +static inline void hri_qspi_set_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + ((Qspi *)hw)->INTENSET.reg = mask; +} + +static inline hri_qspi_intenset_reg_t hri_qspi_get_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_intenset_reg_t hri_qspi_read_INTEN_reg(const void *const hw) +{ + return ((Qspi *)hw)->INTENSET.reg; +} + +static inline void hri_qspi_write_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t data) +{ + ((Qspi *)hw)->INTENSET.reg = data; + ((Qspi *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_qspi_clear_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + ((Qspi *)hw)->INTENCLR.reg = mask; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_DATA_bf(const void *const hw, hri_qspi_rxdata_reg_t mask) +{ + return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA(mask)) >> QSPI_RXDATA_DATA_Pos; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_DATA_bf(const void *const hw) +{ + return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA_Msk) >> QSPI_RXDATA_DATA_Pos; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_reg(const void *const hw, hri_qspi_rxdata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->RXDATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_reg(const void *const hw) +{ + return ((Qspi *)hw)->RXDATA.reg; +} + +static inline bool hri_qspi_get_STATUS_ENABLE_bit(const void *const hw) +{ + return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_ENABLE) >> QSPI_STATUS_ENABLE_Pos; +} + +static inline bool hri_qspi_get_STATUS_CSSTATUS_bit(const void *const hw) +{ + return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_CSSTATUS) >> QSPI_STATUS_CSSTATUS_Pos; +} + +static inline hri_qspi_status_reg_t hri_qspi_get_STATUS_reg(const void *const hw, hri_qspi_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_status_reg_t hri_qspi_read_STATUS_reg(const void *const hw) +{ + return ((Qspi *)hw)->STATUS.reg; +} + +static inline void hri_qspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_SWRST; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_SWRST) >> QSPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_ENABLE) >> QSPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= ~QSPI_CTRLA_ENABLE; + tmp |= value << QSPI_CTRLA_ENABLE_Pos; + ((Qspi *)hw)->CTRLA.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_LASTXFER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_LASTXFER) >> QSPI_CTRLA_LASTXFER_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLA_LASTXFER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= ~QSPI_CTRLA_LASTXFER; + tmp |= value << QSPI_CTRLA_LASTXFER_Pos; + ((Qspi *)hw)->CTRLA.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrla_reg_t hri_qspi_get_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrla_reg_t hri_qspi_read_CTRLA_reg(const void *const hw) +{ + return ((Qspi *)hw)->CTRLA.reg; +} + +static inline void hri_qspi_set_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_MODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_MODE) >> QSPI_CTRLB_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_MODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_MODE; + tmp |= value << QSPI_CTRLB_MODE_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_LOOPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_LOOPEN) >> QSPI_CTRLB_LOOPEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_LOOPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_LOOPEN; + tmp |= value << QSPI_CTRLB_LOOPEN_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_WDRBT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_WDRBT) >> QSPI_CTRLB_WDRBT_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_WDRBT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_WDRBT; + tmp |= value << QSPI_CTRLB_WDRBT_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_SMEMREG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_SMEMREG) >> QSPI_CTRLB_SMEMREG_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_SMEMREG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_SMEMREG; + tmp |= value << QSPI_CTRLB_SMEMREG_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_CSMODE(mask)) >> QSPI_CTRLB_CSMODE_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_CSMODE_Msk; + tmp |= QSPI_CTRLB_CSMODE(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_CSMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_CSMODE_Msk) >> QSPI_CTRLB_CSMODE_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DATALEN(mask)) >> QSPI_CTRLB_DATALEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DATALEN_Msk; + tmp |= QSPI_CTRLB_DATALEN(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DATALEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DATALEN_Msk) >> QSPI_CTRLB_DATALEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYBCT(mask)) >> QSPI_CTRLB_DLYBCT_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DLYBCT_Msk; + tmp |= QSPI_CTRLB_DLYBCT(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYBCT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYBCT_Msk) >> QSPI_CTRLB_DLYBCT_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYCS(mask)) >> QSPI_CTRLB_DLYCS_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DLYCS_Msk; + tmp |= QSPI_CTRLB_DLYCS(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYCS_Msk) >> QSPI_CTRLB_DLYCS_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_reg(const void *const hw) +{ + return ((Qspi *)hw)->CTRLB.reg; +} + +static inline void hri_qspi_set_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_BAUD_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_CPOL) >> QSPI_BAUD_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_BAUD_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_CPOL; + tmp |= value << QSPI_BAUD_CPOL_Pos; + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_BAUD_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_CPHA) >> QSPI_BAUD_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_BAUD_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_CPHA; + tmp |= value << QSPI_BAUD_CPHA_Pos; + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_BAUD(mask)) >> QSPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_qspi_write_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_BAUD_Msk; + tmp |= QSPI_BAUD_BAUD(data); + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_BAUD_Msk) >> QSPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_qspi_set_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_DLYBS(mask)) >> QSPI_BAUD_DLYBS_Pos; + return tmp; +} + +static inline void hri_qspi_write_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_DLYBS_Msk; + tmp |= QSPI_BAUD_DLYBS(data); + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_DLYBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_DLYBS_Msk) >> QSPI_BAUD_DLYBS_Pos; + return tmp; +} + +static inline void hri_qspi_set_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_reg(const void *const hw) +{ + return ((Qspi *)hw)->BAUD.reg; +} + +static inline void hri_qspi_set_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg |= QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_ADDR_bf(const void *const hw, + hri_qspi_instraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp = (tmp & QSPI_INSTRADDR_ADDR(mask)) >> QSPI_INSTRADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp &= ~QSPI_INSTRADDR_ADDR_Msk; + tmp |= QSPI_INSTRADDR_ADDR(data); + ((Qspi *)hw)->INSTRADDR.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg &= ~QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg ^= QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp = (tmp & QSPI_INSTRADDR_ADDR_Msk) >> QSPI_INSTRADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRADDR.reg; +} + +static inline void hri_qspi_set_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_INSTR_bf(const void *const hw, + hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_INSTR(mask)) >> QSPI_INSTRCTRL_INSTR_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= ~QSPI_INSTRCTRL_INSTR_Msk; + tmp |= QSPI_INSTRCTRL_INSTR(data); + ((Qspi *)hw)->INSTRCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_INSTR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_INSTR_Msk) >> QSPI_INSTRCTRL_INSTR_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_OPTCODE_bf(const void *const hw, + hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_OPTCODE(mask)) >> QSPI_INSTRCTRL_OPTCODE_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= ~QSPI_INSTRCTRL_OPTCODE_Msk; + tmp |= QSPI_INSTRCTRL_OPTCODE(data); + ((Qspi *)hw)->INSTRCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_OPTCODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_OPTCODE_Msk) >> QSPI_INSTRCTRL_OPTCODE_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRCTRL.reg; +} + +static inline void hri_qspi_set_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_INSTREN) >> QSPI_INSTRFRAME_INSTREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_INSTREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_INSTREN; + tmp |= value << QSPI_INSTRFRAME_INSTREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_ADDREN) >> QSPI_INSTRFRAME_ADDREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_ADDREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_ADDREN; + tmp |= value << QSPI_INSTRFRAME_ADDREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODEEN) >> QSPI_INSTRFRAME_OPTCODEEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_OPTCODEEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_OPTCODEEN; + tmp |= value << QSPI_INSTRFRAME_OPTCODEEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DATAEN) >> QSPI_INSTRFRAME_DATAEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DATAEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DATAEN; + tmp |= value << QSPI_INSTRFRAME_DATAEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_ADDRLEN) >> QSPI_INSTRFRAME_ADDRLEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_ADDRLEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_ADDRLEN; + tmp |= value << QSPI_INSTRFRAME_ADDRLEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_CRMODE) >> QSPI_INSTRFRAME_CRMODE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_CRMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_CRMODE; + tmp |= value << QSPI_INSTRFRAME_CRMODE_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_DDREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DDREN) >> QSPI_INSTRFRAME_DDREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DDREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DDREN; + tmp |= value << QSPI_INSTRFRAME_DDREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_WIDTH_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_WIDTH(mask)) >> QSPI_INSTRFRAME_WIDTH_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_WIDTH_Msk; + tmp |= QSPI_INSTRFRAME_WIDTH(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_WIDTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_WIDTH_Msk) >> QSPI_INSTRFRAME_WIDTH_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_OPTCODELEN_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN(mask)) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_OPTCODELEN_Msk; + tmp |= QSPI_INSTRFRAME_OPTCODELEN(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_OPTCODELEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN_Msk) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_TFRTYPE_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE(mask)) >> QSPI_INSTRFRAME_TFRTYPE_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_TFRTYPE_Msk; + tmp |= QSPI_INSTRFRAME_TFRTYPE(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_TFRTYPE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE_Msk) >> QSPI_INSTRFRAME_TFRTYPE_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_DUMMYLEN_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN(mask)) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DUMMYLEN_Msk; + tmp |= QSPI_INSTRFRAME_DUMMYLEN(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_DUMMYLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN_Msk) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_reg(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRFRAME.reg; +} + +static inline void hri_qspi_set_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp = (tmp & QSPI_SCRAMBCTRL_ENABLE) >> QSPI_SCRAMBCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= ~QSPI_SCRAMBCTRL_ENABLE; + tmp |= value << QSPI_SCRAMBCTRL_ENABLE_Pos; + ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp = (tmp & QSPI_SCRAMBCTRL_RANDOMDIS) >> QSPI_SCRAMBCTRL_RANDOMDIS_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= ~QSPI_SCRAMBCTRL_RANDOMDIS; + tmp |= value << QSPI_SCRAMBCTRL_RANDOMDIS_Pos; + ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scrambctrl_reg_t hri_qspi_get_SCRAMBCTRL_reg(const void *const hw, + hri_qspi_scrambctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scrambctrl_reg_t hri_qspi_read_SCRAMBCTRL_reg(const void *const hw) +{ + return ((Qspi *)hw)->SCRAMBCTRL.reg; +} + +static inline void hri_qspi_write_TXDATA_reg(const void *const hw, hri_qspi_txdata_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->TXDATA.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_write_SCRAMBKEY_reg(const void *const hw, hri_qspi_scrambkey_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBKEY.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_QSPI_E54_H_INCLUDED */ +#endif /* _SAME54_QSPI_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ramecc_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ramecc_e54.h new file mode 100644 index 0000000..6031cce --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ramecc_e54.h @@ -0,0 +1,362 @@ +/** + * \file + * + * \brief SAM RAMECC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_RAMECC_COMPONENT_ +#ifndef _HRI_RAMECC_E54_H_INCLUDED_ +#define _HRI_RAMECC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RAMECC_CRITICAL_SECTIONS) +#define RAMECC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RAMECC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RAMECC_CRITICAL_SECTION_ENTER() +#define RAMECC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ramecc_erraddr_reg_t; +typedef uint8_t hri_ramecc_dbgctrl_reg_t; +typedef uint8_t hri_ramecc_intenset_reg_t; +typedef uint8_t hri_ramecc_intflag_reg_t; +typedef uint8_t hri_ramecc_status_reg_t; + +static inline bool hri_ramecc_get_INTFLAG_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; +} + +static inline void hri_ramecc_clear_INTFLAG_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; +} + +static inline bool hri_ramecc_get_INTFLAG_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; +} + +static inline void hri_ramecc_clear_INTFLAG_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; +} + +static inline bool hri_ramecc_get_interrupt_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; +} + +static inline void hri_ramecc_clear_interrupt_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; +} + +static inline bool hri_ramecc_get_interrupt_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; +} + +static inline void hri_ramecc_clear_interrupt_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; +} + +static inline hri_ramecc_intflag_reg_t hri_ramecc_get_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw) +{ + return ((Ramecc *)hw)->INTFLAG.reg; +} + +static inline void hri_ramecc_clear_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) +{ + ((Ramecc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ramecc_set_INTEN_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; +} + +static inline bool hri_ramecc_get_INTEN_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_SINGLEE) >> RAMECC_INTENSET_SINGLEE_Pos; +} + +static inline void hri_ramecc_write_INTEN_SINGLEE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; + } else { + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; + } +} + +static inline void hri_ramecc_clear_INTEN_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; +} + +static inline void hri_ramecc_set_INTEN_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; +} + +static inline bool hri_ramecc_get_INTEN_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_DUALE) >> RAMECC_INTENSET_DUALE_Pos; +} + +static inline void hri_ramecc_write_INTEN_DUALE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; + } else { + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; + } +} + +static inline void hri_ramecc_clear_INTEN_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; +} + +static inline void hri_ramecc_set_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + ((Ramecc *)hw)->INTENSET.reg = mask; +} + +static inline hri_ramecc_intenset_reg_t hri_ramecc_get_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_intenset_reg_t hri_ramecc_read_INTEN_reg(const void *const hw) +{ + return ((Ramecc *)hw)->INTENSET.reg; +} + +static inline void hri_ramecc_write_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t data) +{ + ((Ramecc *)hw)->INTENSET.reg = data; + ((Ramecc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ramecc_clear_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + ((Ramecc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ramecc_get_STATUS_ECCDIS_bit(const void *const hw) +{ + return (((Ramecc *)hw)->STATUS.reg & RAMECC_STATUS_ECCDIS) >> RAMECC_STATUS_ECCDIS_Pos; +} + +static inline hri_ramecc_status_reg_t hri_ramecc_get_STATUS_reg(const void *const hw, hri_ramecc_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_status_reg_t hri_ramecc_read_STATUS_reg(const void *const hw) +{ + return ((Ramecc *)hw)->STATUS.reg; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_ERRADDR_bf(const void *const hw, + hri_ramecc_erraddr_reg_t mask) +{ + return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR(mask)) >> RAMECC_ERRADDR_ERRADDR_Pos; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_ERRADDR_bf(const void *const hw) +{ + return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR_Msk) >> RAMECC_ERRADDR_ERRADDR_Pos; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_reg(const void *const hw, hri_ramecc_erraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ramecc *)hw)->ERRADDR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw) +{ + return ((Ramecc *)hw)->ERRADDR.reg; +} + +static inline void hri_ramecc_set_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ramecc_get_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp = (tmp & RAMECC_DBGCTRL_ECCDIS) >> RAMECC_DBGCTRL_ECCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RAMECC_CRITICAL_SECTION_ENTER(); + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= ~RAMECC_DBGCTRL_ECCDIS; + tmp |= value << RAMECC_DBGCTRL_ECCDIS_Pos; + ((Ramecc *)hw)->DBGCTRL.reg = tmp; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_set_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ramecc_get_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp = (tmp & RAMECC_DBGCTRL_ECCELOG) >> RAMECC_DBGCTRL_ECCELOG_Pos; + return (bool)tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RAMECC_CRITICAL_SECTION_ENTER(); + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= ~RAMECC_DBGCTRL_ECCELOG; + tmp |= value << RAMECC_DBGCTRL_ECCELOG_Pos; + ((Ramecc *)hw)->DBGCTRL.reg = tmp; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_set_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_get_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t data) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg = data; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ramecc *)hw)->DBGCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RAMECC_E54_H_INCLUDED */ +#endif /* _SAME54_RAMECC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_rstc_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_rstc_e54.h new file mode 100644 index 0000000..bf5592a --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_rstc_e54.h @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief SAM RSTC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_RSTC_COMPONENT_ +#ifndef _HRI_RSTC_E54_H_INCLUDED_ +#define _HRI_RSTC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) +#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RSTC_CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint8_t hri_rstc_bkupexit_reg_t; +typedef uint8_t hri_rstc_rcause_reg_t; + +static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_NVM_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_NVM) >> RSTC_RCAUSE_NVM_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->RCAUSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw) +{ + return ((Rstc *)hw)->RCAUSE.reg; +} + +static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_HIB_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_HIB) >> RSTC_BKUPEXIT_HIB_Pos; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->BKUPEXIT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw) +{ + return ((Rstc *)hw)->BKUPEXIT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RSTC_E54_H_INCLUDED */ +#endif /* _SAME54_RSTC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_rtc_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_rtc_e54.h new file mode 100644 index 0000000..2f2fa3b --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_rtc_e54.h @@ -0,0 +1,10139 @@ +/** + * \file + * + * \brief SAM RTC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_RTC_COMPONENT_ +#ifndef _HRI_RTC_E54_H_INCLUDED_ +#define _HRI_RTC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RTC_CRITICAL_SECTIONS) +#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RTC_CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_rtcmode0_ctrla_reg_t; +typedef uint16_t hri_rtcmode0_ctrlb_reg_t; +typedef uint16_t hri_rtcmode0_intenset_reg_t; +typedef uint16_t hri_rtcmode0_intflag_reg_t; +typedef uint16_t hri_rtcmode1_comp_reg_t; +typedef uint16_t hri_rtcmode1_count_reg_t; +typedef uint16_t hri_rtcmode1_ctrla_reg_t; +typedef uint16_t hri_rtcmode1_ctrlb_reg_t; +typedef uint16_t hri_rtcmode1_intenset_reg_t; +typedef uint16_t hri_rtcmode1_intflag_reg_t; +typedef uint16_t hri_rtcmode1_per_reg_t; +typedef uint16_t hri_rtcmode2_ctrla_reg_t; +typedef uint16_t hri_rtcmode2_ctrlb_reg_t; +typedef uint16_t hri_rtcmode2_intenset_reg_t; +typedef uint16_t hri_rtcmode2_intflag_reg_t; +typedef uint32_t hri_rtc_bkup_reg_t; +typedef uint32_t hri_rtc_gp_reg_t; +typedef uint32_t hri_rtc_tampctrl_reg_t; +typedef uint32_t hri_rtc_tampid_reg_t; +typedef uint32_t hri_rtcalarm_alarm_reg_t; +typedef uint32_t hri_rtcmode0_comp_reg_t; +typedef uint32_t hri_rtcmode0_count_reg_t; +typedef uint32_t hri_rtcmode0_evctrl_reg_t; +typedef uint32_t hri_rtcmode0_syncbusy_reg_t; +typedef uint32_t hri_rtcmode0_timestamp_reg_t; +typedef uint32_t hri_rtcmode1_evctrl_reg_t; +typedef uint32_t hri_rtcmode1_syncbusy_reg_t; +typedef uint32_t hri_rtcmode1_timestamp_reg_t; +typedef uint32_t hri_rtcmode2_alarm_reg_t; +typedef uint32_t hri_rtcmode2_clock_reg_t; +typedef uint32_t hri_rtcmode2_evctrl_reg_t; +typedef uint32_t hri_rtcmode2_syncbusy_reg_t; +typedef uint32_t hri_rtcmode2_timestamp_reg_t; +typedef uint8_t hri_rtc_dbgctrl_reg_t; +typedef uint8_t hri_rtc_freqcorr_reg_t; +typedef uint8_t hri_rtcalarm_mask_reg_t; +typedef uint8_t hri_rtcmode2_mask_reg_t; + +static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; +} + +static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, + hri_rtcmode0_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTFLAG.reg; +} + +static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; +} + +static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, + hri_rtcmode1_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTFLAG.reg; +} + +static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; +} + +static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, + hri_rtcmode2_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTFLAG.reg; +} + +static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline void hri_rtcmode0_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP1) >> RTC_MODE0_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; +} + +static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; +} + +static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; + } +} + +static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = mask; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, + hri_rtcmode0_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTENSET.reg; +} + +static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = data; + ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline void hri_rtcmode1_set_INTEN_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP2) >> RTC_MODE1_INTENSET_CMP2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; +} + +static inline void hri_rtcmode1_set_INTEN_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP3) >> RTC_MODE1_INTENSET_CMP3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; +} + +static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; +} + +static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; + } +} + +static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = mask; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, + hri_rtcmode1_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTENSET.reg; +} + +static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = data; + ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM1) >> RTC_MODE2_INTENSET_ALARM1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; +} + +static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; +} + +static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; + } +} + +static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = mask; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, + hri_rtcmode2_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTENSET.reg; +} + +static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = data; + ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP1) >> RTC_MODE0_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP2) >> RTC_MODE0_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP3) >> RTC_MODE0_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode0_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP2) >> RTC_MODE1_SYNCBUSY_COMP2_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP3) >> RTC_MODE1_SYNCBUSY_COMP3_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP2) >> RTC_MODE1_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP3) >> RTC_MODE1_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode1_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM1) >> RTC_MODE2_SYNCBUSY_ALARM1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK1) >> RTC_MODE2_SYNCBUSY_MASK1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP2) >> RTC_MODE2_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP3) >> RTC_MODE2_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode2_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const hw, + hri_rtcmode0_timestamp_reg_t mask) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode0_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE0.TIMESTAMP.reg; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const hw, + hri_rtcmode1_timestamp_reg_t mask) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode1_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE1.TIMESTAMP.reg; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return ((Rtc *)hw)->MODE2.TIMESTAMP.reg; +} + +static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_ENABLE; + tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_BKTRST; + tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_GPTRST; + tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; + tmp |= RTC_MODE0_CTRLA_MODE(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE0_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE0.CTRLA.reg; +} + +static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_ENABLE; + tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_BKTRST; + tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_GPTRST; + tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; + tmp |= RTC_MODE1_CTRLA_MODE(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE1_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE1.CTRLA.reg; +} + +static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_ENABLE; + tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLKREP; + tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_BKTRST; + tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_GPTRST; + tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; + tmp |= RTC_MODE2_CTRLA_MODE(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE2_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + return ((Rtc *)hw)->MODE2.CTRLA.reg; +} + +static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_GP0EN; + tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_GP2EN) >> RTC_MODE0_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_GP2EN; + tmp |= value << RTC_MODE0_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_RTCOUT; + tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DMAEN; + tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk; + tmp |= RTC_MODE0_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk; + tmp |= RTC_MODE0_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.CTRLB.reg; +} + +static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_GP0EN; + tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_GP2EN) >> RTC_MODE1_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_GP2EN; + tmp |= value << RTC_MODE1_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_RTCOUT; + tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DMAEN; + tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk; + tmp |= RTC_MODE1_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk; + tmp |= RTC_MODE1_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.CTRLB.reg; +} + +static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_GP0EN; + tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_GP2EN) >> RTC_MODE2_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_GP2EN; + tmp |= value << RTC_MODE2_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_RTCOUT; + tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DMAEN; + tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk; + tmp |= RTC_MODE2_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk; + tmp |= RTC_MODE2_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.CTRLB.reg; +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO0; + tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO1; + tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO2; + tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO3; + tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO4; + tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO5; + tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO6; + tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO7; + tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO1) >> RTC_MODE0_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_OVFEO; + tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, + hri_rtcmode0_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.EVCTRL.reg; +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO0; + tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO1; + tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO2; + tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO3; + tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO4; + tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO5; + tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO6; + tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO7; + tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO2) >> RTC_MODE1_EVCTRL_CMPEO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO2; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO3) >> RTC_MODE1_EVCTRL_CMPEO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO3; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_OVFEO; + tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, + hri_rtcmode1_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.EVCTRL.reg; +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO0; + tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO1; + tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO2; + tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO3; + tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO4; + tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO5; + tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO6; + tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO7; + tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO1) >> RTC_MODE2_EVCTRL_ALARMEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO1; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_OVFEO; + tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, + hri_rtcmode2_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.EVCTRL.reg; +} + +static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.DBGCTRL.reg; +} + +static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + return ((Rtc *)hw)->MODE0.FREQCORR.reg; +} + +static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; + tmp |= RTC_MODE0_COUNT_COUNT(data); + ((Rtc *)hw)->MODE0.COUNT.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE0.COUNT.reg; +} + +static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; + tmp |= RTC_MODE1_COUNT_COUNT(data); + ((Rtc *)hw)->MODE1.COUNT.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE1.COUNT.reg; +} + +static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; + tmp |= RTC_MODE2_CLOCK_SECOND(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; + tmp |= RTC_MODE2_CLOCK_MINUTE(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; + tmp |= RTC_MODE2_CLOCK_HOUR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; + tmp |= RTC_MODE2_CLOCK_DAY(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; + tmp |= RTC_MODE2_CLOCK_MONTH(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; + tmp |= RTC_MODE2_CLOCK_YEAR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return ((Rtc *)hw)->MODE2.CLOCK.reg; +} + +static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= ~RTC_MODE1_PER_PER_Msk; + tmp |= RTC_MODE1_PER_PER(data); + ((Rtc *)hw)->MODE1.PER.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + return ((Rtc *)hw)->MODE1.PER.reg; +} + +static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= ~RTC_MODE0_COMP_COMP_Msk; + tmp |= RTC_MODE0_COMP_COMP(data); + ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + return ((Rtc *)hw)->MODE0.COMP[index].reg; +} + +static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= ~RTC_MODE1_COMP_COMP_Msk; + tmp |= RTC_MODE1_COMP_COMP(data); + ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg = data; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + return ((Rtc *)hw)->MODE1.COMP[index].reg; +} + +static inline void hri_rtc_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_get_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtc_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp &= ~RTC_GP_GP_Msk; + tmp |= RTC_GP_GP(data); + ((Rtc *)hw)->MODE0.GP[index].reg = tmp; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_read_GP_GP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg |= mask; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg = data; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg &= ~mask; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg ^= mask; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + return ((Rtc *)hw)->MODE0.GP[index].reg; +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL0; + tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL1; + tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL2; + tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL3; + tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL4; + tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC0; + tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC1; + tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC2; + tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC3; + tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC4; + tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; + tmp |= RTC_TAMPCTRL_IN0ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN0ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; + tmp |= RTC_TAMPCTRL_IN1ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN1ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; + tmp |= RTC_TAMPCTRL_IN2ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN2ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; + tmp |= RTC_TAMPCTRL_IN3ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN3ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; + tmp |= RTC_TAMPCTRL_IN4ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN4ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.TAMPCTRL.reg; +} + +static inline void hri_rtc_set_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID0; + tmp |= value << RTC_TAMPID_TAMPID0_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID1; + tmp |= value << RTC_TAMPID_TAMPID1_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID2; + tmp |= value << RTC_TAMPID_TAMPID2_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID3; + tmp |= value << RTC_TAMPID_TAMPID3_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID4; + tmp |= value << RTC_TAMPID_TAMPID4_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPEVT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPEVT; + tmp |= value << RTC_TAMPID_TAMPEVT_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampid_reg_t hri_rtc_get_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampid_reg_t hri_rtc_read_TAMPID_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.TAMPID.reg; +} + +static inline void hri_rtc_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtc_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp &= ~RTC_BKUP_BKUP_Msk; + tmp |= RTC_BKUP_BKUP(data); + ((Rtc *)hw)->MODE0.BKUP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtc_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE0.BKUP[index].reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode2_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode2_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode2_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode2_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode2_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode2_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode2_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode2_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode2_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode2_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode2_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode2_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode2_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode2_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) +#define hri_rtcmode2_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) +#define hri_rtcmode2_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) +#define hri_rtcmode2_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) +#define hri_rtcmode2_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) +#define hri_rtcmode2_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) +#define hri_rtcmode2_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode2_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode2_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode2_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode2_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode2_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) +#define hri_rtcmode2_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) +#define hri_rtcmode2_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) +#define hri_rtcmode2_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) +#define hri_rtcmode2_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) +#define hri_rtcmode2_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) +#define hri_rtcmode2_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) +#define hri_rtcmode2_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) +#define hri_rtcmode2_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) +#define hri_rtcmode2_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) +#define hri_rtcmode2_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) +#define hri_rtcmode2_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) +#define hri_rtcmode2_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) +#define hri_rtcmode2_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) +#define hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode0_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode0_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode0_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode0_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode0_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode0_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode0_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode0_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode0_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode0_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode0_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode0_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode0_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode0_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) +#define hri_rtcmode0_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) +#define hri_rtcmode0_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) +#define hri_rtcmode0_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) +#define hri_rtcmode0_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) +#define hri_rtcmode0_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) +#define hri_rtcmode0_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode0_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode0_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode0_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode0_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode0_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) +#define hri_rtcmode0_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) +#define hri_rtcmode0_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) +#define hri_rtcmode0_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) +#define hri_rtcmode0_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) +#define hri_rtcmode0_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) +#define hri_rtcmode0_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) +#define hri_rtcmode0_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) +#define hri_rtcmode0_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) +#define hri_rtcmode0_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) +#define hri_rtcmode0_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) +#define hri_rtcmode0_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) +#define hri_rtcmode0_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) +#define hri_rtcmode0_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) +#define hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode1_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode1_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode1_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode1_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode1_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode1_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode1_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode1_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode1_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode1_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode1_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode1_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode1_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode1_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) +#define hri_rtcmode1_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) +#define hri_rtcmode1_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) +#define hri_rtcmode1_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) +#define hri_rtcmode1_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) +#define hri_rtcmode1_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) +#define hri_rtcmode1_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode1_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode1_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode1_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode1_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode1_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) +#define hri_rtcmode1_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) +#define hri_rtcmode1_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) +#define hri_rtcmode1_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) +#define hri_rtcmode1_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) +#define hri_rtcmode1_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) +#define hri_rtcmode1_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) +#define hri_rtcmode1_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) +#define hri_rtcmode1_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) +#define hri_rtcmode1_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) +#define hri_rtcmode1_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) +#define hri_rtcmode1_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) +#define hri_rtcmode1_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) +#define hri_rtcmode1_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RTC_E54_H_INCLUDED */ +#endif /* _SAME54_RTC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_sdhc_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_sdhc_e54.h new file mode 100644 index 0000000..0b7f609 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_sdhc_e54.h @@ -0,0 +1,7477 @@ +/** + * \file + * + * \brief SAM SDHC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_SDHC_COMPONENT_ +#ifndef _HRI_SDHC_E54_H_INCLUDED_ +#define _HRI_SDHC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SDHC_CRITICAL_SECTIONS) +#define SDHC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SDHC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SDHC_CRITICAL_SECTION_ENTER() +#define SDHC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sdhc_acesr_reg_t; +typedef uint16_t hri_sdhc_bcr_reg_t; +typedef uint16_t hri_sdhc_bsr_reg_t; +typedef uint16_t hri_sdhc_ccr_reg_t; +typedef uint16_t hri_sdhc_cr_reg_t; +typedef uint16_t hri_sdhc_eisier_reg_t; +typedef uint16_t hri_sdhc_eister_reg_t; +typedef uint16_t hri_sdhc_eistr_reg_t; +typedef uint16_t hri_sdhc_feraces_reg_t; +typedef uint16_t hri_sdhc_fereis_reg_t; +typedef uint16_t hri_sdhc_hc2r_reg_t; +typedef uint16_t hri_sdhc_hcvr_reg_t; +typedef uint16_t hri_sdhc_nisier_reg_t; +typedef uint16_t hri_sdhc_nister_reg_t; +typedef uint16_t hri_sdhc_nistr_reg_t; +typedef uint16_t hri_sdhc_pvr_reg_t; +typedef uint16_t hri_sdhc_sisr_reg_t; +typedef uint16_t hri_sdhc_tmr_reg_t; +typedef uint32_t hri_sdhc_acr_reg_t; +typedef uint32_t hri_sdhc_arg1r_reg_t; +typedef uint32_t hri_sdhc_asar_reg_t; +typedef uint32_t hri_sdhc_bdpr_reg_t; +typedef uint32_t hri_sdhc_ca0r_reg_t; +typedef uint32_t hri_sdhc_ca1r_reg_t; +typedef uint32_t hri_sdhc_cacr_reg_t; +typedef uint32_t hri_sdhc_cc2r_reg_t; +typedef uint32_t hri_sdhc_mccar_reg_t; +typedef uint32_t hri_sdhc_psr_reg_t; +typedef uint32_t hri_sdhc_rr_reg_t; +typedef uint32_t hri_sdhc_ssar_reg_t; +typedef uint8_t hri_sdhc_aesr_reg_t; +typedef uint8_t hri_sdhc_bgcr_reg_t; +typedef uint8_t hri_sdhc_dbgr_reg_t; +typedef uint8_t hri_sdhc_hc1r_reg_t; +typedef uint8_t hri_sdhc_mc1r_reg_t; +typedef uint8_t hri_sdhc_mc2r_reg_t; +typedef uint8_t hri_sdhc_pcr_reg_t; +typedef uint8_t hri_sdhc_srr_reg_t; +typedef uint8_t hri_sdhc_tcr_reg_t; +typedef uint8_t hri_sdhc_wcr_reg_t; + +static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_CMDRESP_bf(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) +{ + return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP(mask)) >> SDHC_RR_CMDRESP_Pos; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_CMDRESP_bf(const void *const hw, uint8_t index) +{ + return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP_Msk) >> SDHC_RR_CMDRESP_Pos; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_reg(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->RR[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->RR[index].reg; +} + +static inline bool hri_sdhc_get_PSR_CMDINHC_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHC) >> SDHC_PSR_CMDINHC_Pos; +} + +static inline bool hri_sdhc_get_PSR_CMDINHD_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHD) >> SDHC_PSR_CMDINHD_Pos; +} + +static inline bool hri_sdhc_get_PSR_DLACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DLACT) >> SDHC_PSR_DLACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_RTREQ_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTREQ) >> SDHC_PSR_RTREQ_Pos; +} + +static inline bool hri_sdhc_get_PSR_WTACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WTACT) >> SDHC_PSR_WTACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_RTACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTACT) >> SDHC_PSR_RTACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_BUFWREN_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFWREN) >> SDHC_PSR_BUFWREN_Pos; +} + +static inline bool hri_sdhc_get_PSR_BUFRDEN_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFRDEN) >> SDHC_PSR_BUFRDEN_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDINS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDINS) >> SDHC_PSR_CARDINS_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDSS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDSS) >> SDHC_PSR_CARDSS_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDDPL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDDPL) >> SDHC_PSR_CARDDPL_Pos; +} + +static inline bool hri_sdhc_get_PSR_WRPPL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WRPPL) >> SDHC_PSR_WRPPL_Pos; +} + +static inline bool hri_sdhc_get_PSR_CMDLL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDLL) >> SDHC_PSR_CMDLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_DATLL_bf(const void *const hw, hri_sdhc_psr_reg_t mask) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL(mask)) >> SDHC_PSR_DATLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_DATLL_bf(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL_Msk) >> SDHC_PSR_DATLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_reg(const void *const hw, hri_sdhc_psr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->PSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->PSR.reg; +} + +static inline bool hri_sdhc_get_ACESR_ACMD12NE_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMD12NE) >> SDHC_ACESR_ACMD12NE_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDTEO_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDTEO) >> SDHC_ACESR_ACMDTEO_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDCRC_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDCRC) >> SDHC_ACESR_ACMDCRC_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDEND_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDEND) >> SDHC_ACESR_ACMDEND_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDIDX_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDIDX) >> SDHC_ACESR_ACMDIDX_Pos; +} + +static inline bool hri_sdhc_get_ACESR_CMDNI_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_CMDNI) >> SDHC_ACESR_CMDNI_Pos; +} + +static inline hri_sdhc_acesr_reg_t hri_sdhc_get_ACESR_reg(const void *const hw, hri_sdhc_acesr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->ACESR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_acesr_reg_t hri_sdhc_read_ACESR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ACESR.reg; +} + +static inline bool hri_sdhc_get_CA0R_TEOCLKU_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKU) >> SDHC_CA0R_TEOCLKU_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ED8SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ED8SUP) >> SDHC_CA0R_ED8SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ADMA2SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ADMA2SUP) >> SDHC_CA0R_ADMA2SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_HSSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_HSSUP) >> SDHC_CA0R_HSSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SDMASUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SDMASUP) >> SDHC_CA0R_SDMASUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SRSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SRSUP) >> SDHC_CA0R_SRSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V33VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V33VSUP) >> SDHC_CA0R_V33VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V30VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V30VSUP) >> SDHC_CA0R_V30VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V18VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V18VSUP) >> SDHC_CA0R_V18VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SB64SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SB64SUP) >> SDHC_CA0R_SB64SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ASINTSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ASINTSUP) >> SDHC_CA0R_ASINTSUP_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_TEOCLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF(mask)) >> SDHC_CA0R_TEOCLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_TEOCLKF_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF_Msk) >> SDHC_CA0R_TEOCLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_BASECLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF(mask)) >> SDHC_CA0R_BASECLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_BASECLKF_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF_Msk) >> SDHC_CA0R_BASECLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_MAXBLKL_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL(mask)) >> SDHC_CA0R_MAXBLKL_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_MAXBLKL_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL_Msk) >> SDHC_CA0R_MAXBLKL_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_SLTYPE_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE(mask)) >> SDHC_CA0R_SLTYPE_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_SLTYPE_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE_Msk) >> SDHC_CA0R_SLTYPE_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_reg(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CA0R.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CA0R.reg; +} + +static inline bool hri_sdhc_get_CA1R_SDR50SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR50SUP) >> SDHC_CA1R_SDR50SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_SDR104SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR104SUP) >> SDHC_CA1R_SDR104SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DDR50SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DDR50SUP) >> SDHC_CA1R_DDR50SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVASUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVASUP) >> SDHC_CA1R_DRVASUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVCSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVCSUP) >> SDHC_CA1R_DRVCSUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVDSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVDSUP) >> SDHC_CA1R_DRVDSUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_TSDR50_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TSDR50) >> SDHC_CA1R_TSDR50_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_TCNTRT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT(mask)) >> SDHC_CA1R_TCNTRT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_TCNTRT_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT_Msk) >> SDHC_CA1R_TCNTRT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_CLKMULT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT(mask)) >> SDHC_CA1R_CLKMULT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_CLKMULT_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT_Msk) >> SDHC_CA1R_CLKMULT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_reg(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CA1R.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CA1R.reg; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR33V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V(mask)) >> SDHC_MCCAR_MAXCUR33V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR33V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V_Msk) >> SDHC_MCCAR_MAXCUR33V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR30V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V(mask)) >> SDHC_MCCAR_MAXCUR30V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR30V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V_Msk) >> SDHC_MCCAR_MAXCUR30V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR18V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V(mask)) >> SDHC_MCCAR_MAXCUR18V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR18V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V_Msk) >> SDHC_MCCAR_MAXCUR18V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_reg(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->MCCAR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->MCCAR.reg; +} + +static inline bool hri_sdhc_get_AESR_LMIS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_LMIS) >> SDHC_AESR_LMIS_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_ERRST_bf(const void *const hw, hri_sdhc_aesr_reg_t mask) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST(mask)) >> SDHC_AESR_ERRST_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_ERRST_bf(const void *const hw) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST_Msk) >> SDHC_AESR_ERRST_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_reg(const void *const hw, hri_sdhc_aesr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->AESR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->AESR.reg; +} + +static inline bool hri_sdhc_get_SISR_INTSSL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->SISR.reg & SDHC_SISR_INTSSL_Msk) >> SDHC_SISR_INTSSL_Pos; +} + +static inline hri_sdhc_sisr_reg_t hri_sdhc_get_SISR_reg(const void *const hw, hri_sdhc_sisr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->SISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_sisr_reg_t hri_sdhc_read_SISR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SISR.reg; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_SVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER(mask)) >> SDHC_HCVR_SVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_SVER_bf(const void *const hw) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER_Msk) >> SDHC_HCVR_SVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_VVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER(mask)) >> SDHC_HCVR_VVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_VVER_bf(const void *const hw) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER_Msk) >> SDHC_HCVR_VVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_reg(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HCVR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HCVR.reg; +} + +static inline void hri_sdhc_set_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_ADDR(mask)) >> SDHC_SSAR_ADDR_Pos; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= ~SDHC_SSAR_ADDR_Msk; + tmp |= SDHC_SSAR_ADDR(data); + ((Sdhc *)hw)->SSAR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_ADDR_Msk) >> SDHC_SSAR_ADDR_Pos; + return tmp; +} + +static inline void hri_sdhc_set_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_CMD23_ARG2(mask)) >> SDHC_SSAR_CMD23_ARG2_Pos; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= ~SDHC_SSAR_CMD23_ARG2_Msk; + tmp |= SDHC_SSAR_CMD23_ARG2(data); + ((Sdhc *)hw)->SSAR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_CMD23_ARG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_CMD23_ARG2_Msk) >> SDHC_SSAR_CMD23_ARG2_Pos; + return tmp; +} + +static inline void hri_sdhc_set_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SSAR.reg; +} + +static inline void hri_sdhc_set_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BLOCKSIZE(mask)) >> SDHC_BSR_BLOCKSIZE_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= ~SDHC_BSR_BLOCKSIZE_Msk; + tmp |= SDHC_BSR_BLOCKSIZE(data); + ((Sdhc *)hw)->BSR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BLOCKSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BLOCKSIZE_Msk) >> SDHC_BSR_BLOCKSIZE_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BOUNDARY(mask)) >> SDHC_BSR_BOUNDARY_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= ~SDHC_BSR_BOUNDARY_Msk; + tmp |= SDHC_BSR_BOUNDARY(data); + ((Sdhc *)hw)->BSR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BOUNDARY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BOUNDARY_Msk) >> SDHC_BSR_BOUNDARY_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BSR.reg; +} + +static inline void hri_sdhc_set_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg |= SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp = (tmp & SDHC_BCR_BCNT(mask)) >> SDHC_BCR_BCNT_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BCR.reg; + tmp &= ~SDHC_BCR_BCNT_Msk; + tmp |= SDHC_BCR_BCNT(data); + ((Sdhc *)hw)->BCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg &= ~SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg ^= SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_BCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp = (tmp & SDHC_BCR_BCNT_Msk) >> SDHC_BCR_BCNT_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BCR.reg; +} + +static inline void hri_sdhc_set_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg |= SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp = (tmp & SDHC_ARG1R_ARG(mask)) >> SDHC_ARG1R_ARG_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp &= ~SDHC_ARG1R_ARG_Msk; + tmp |= SDHC_ARG1R_ARG(data); + ((Sdhc *)hw)->ARG1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg &= ~SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg ^= SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_ARG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp = (tmp & SDHC_ARG1R_ARG_Msk) >> SDHC_ARG1R_ARG_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ARG1R.reg; +} + +static inline void hri_sdhc_set_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_DMAEN) >> SDHC_TMR_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_DMAEN; + tmp |= value << SDHC_TMR_DMAEN_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_BCEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_BCEN) >> SDHC_TMR_BCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_BCEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_BCEN; + tmp |= value << SDHC_TMR_BCEN_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_DTDSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_DTDSEL) >> SDHC_TMR_DTDSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_DTDSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_DTDSEL; + tmp |= value << SDHC_TMR_DTDSEL_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_MSBSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_MSBSEL) >> SDHC_TMR_MSBSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_MSBSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_MSBSEL; + tmp |= value << SDHC_TMR_MSBSEL_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_ACMDEN(mask)) >> SDHC_TMR_ACMDEN_Pos; + return tmp; +} + +static inline void hri_sdhc_write_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_ACMDEN_Msk; + tmp |= SDHC_TMR_ACMDEN(data); + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_ACMDEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_ACMDEN_Msk) >> SDHC_TMR_ACMDEN_Pos; + return tmp; +} + +static inline void hri_sdhc_set_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->TMR.reg; +} + +static inline void hri_sdhc_set_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_CMDCCEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDCCEN) >> SDHC_CR_CMDCCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_CMDCCEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDCCEN; + tmp |= value << SDHC_CR_CMDCCEN_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_CMDICEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDICEN) >> SDHC_CR_CMDICEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_CMDICEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDICEN; + tmp |= value << SDHC_CR_CMDICEN_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_DPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_DPSEL) >> SDHC_CR_DPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_DPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_DPSEL; + tmp |= value << SDHC_CR_DPSEL_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_RESPTYP(mask)) >> SDHC_CR_RESPTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_RESPTYP_Msk; + tmp |= SDHC_CR_RESPTYP(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_RESPTYP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_RESPTYP_Msk) >> SDHC_CR_RESPTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDTYP(mask)) >> SDHC_CR_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDTYP_Msk; + tmp |= SDHC_CR_CMDTYP(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDTYP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDTYP_Msk) >> SDHC_CR_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDIDX(mask)) >> SDHC_CR_CMDIDX_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDIDX_Msk; + tmp |= SDHC_CR_CMDIDX(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDIDX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDIDX_Msk) >> SDHC_CR_CMDIDX_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CR_reg(const void *const hw, hri_sdhc_cr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CR.reg; +} + +static inline void hri_sdhc_set_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg |= SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp = (tmp & SDHC_BDPR_BUFDATA(mask)) >> SDHC_BDPR_BUFDATA_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp &= ~SDHC_BDPR_BUFDATA_Msk; + tmp |= SDHC_BDPR_BUFDATA(data); + ((Sdhc *)hw)->BDPR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg &= ~SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg ^= SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_BUFDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp = (tmp & SDHC_BDPR_BUFDATA_Msk) >> SDHC_BDPR_BUFDATA_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BDPR.reg; +} + +static inline void hri_sdhc_set_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_LEDCTRL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_LEDCTRL) >> SDHC_HC1R_LEDCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_LEDCTRL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_LEDCTRL; + tmp |= value << SDHC_HC1R_LEDCTRL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_DW_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DW) >> SDHC_HC1R_DW_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_DW_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_DW; + tmp |= value << SDHC_HC1R_DW_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_HSEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_HSEN) >> SDHC_HC1R_HSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_HSEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_HSEN; + tmp |= value << SDHC_HC1R_HSEN_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_CARDDTL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_CARDDTL) >> SDHC_HC1R_CARDDTL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_CARDDTL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_CARDDTL; + tmp |= value << SDHC_HC1R_CARDDTL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_CARDDSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_CARDDSEL) >> SDHC_HC1R_CARDDSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_CARDDSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_CARDDSEL; + tmp |= value << SDHC_HC1R_CARDDSEL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DMASEL(mask)) >> SDHC_HC1R_DMASEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_DMASEL_Msk; + tmp |= SDHC_HC1R_DMASEL(data); + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_DMASEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DMASEL_Msk) >> SDHC_HC1R_DMASEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HC1R.reg; +} + +static inline void hri_sdhc_set_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_PCR_SDBPWR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBPWR) >> SDHC_PCR_SDBPWR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_PCR_SDBPWR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= ~SDHC_PCR_SDBPWR; + tmp |= value << SDHC_PCR_SDBPWR_Pos; + ((Sdhc *)hw)->PCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBVSEL(mask)) >> SDHC_PCR_SDBVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= ~SDHC_PCR_SDBVSEL_Msk; + tmp |= SDHC_PCR_SDBVSEL(data); + ((Sdhc *)hw)->PCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_SDBVSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBVSEL_Msk) >> SDHC_PCR_SDBVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->PCR.reg; +} + +static inline void hri_sdhc_set_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_STPBGR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_STPBGR) >> SDHC_BGCR_STPBGR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_STPBGR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_STPBGR; + tmp |= value << SDHC_BGCR_STPBGR_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_CONTR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_CONTR) >> SDHC_BGCR_CONTR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_CONTR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_CONTR; + tmp |= value << SDHC_BGCR_CONTR_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_RWCTRL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_RWCTRL) >> SDHC_BGCR_RWCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_RWCTRL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_RWCTRL; + tmp |= value << SDHC_BGCR_RWCTRL_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_INTBG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_INTBG) >> SDHC_BGCR_INTBG_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_INTBG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_INTBG; + tmp |= value << SDHC_BGCR_INTBG_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bgcr_reg_t hri_sdhc_get_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bgcr_reg_t hri_sdhc_read_BGCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BGCR.reg; +} + +static inline void hri_sdhc_set_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCINT_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCINT) >> SDHC_WCR_WKENCINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCINT_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCINT; + tmp |= value << SDHC_WCR_WKENCINT_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCINS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCINS) >> SDHC_WCR_WKENCINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCINS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCINS; + tmp |= value << SDHC_WCR_WKENCINS_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCREM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCREM) >> SDHC_WCR_WKENCREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCREM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCREM; + tmp |= value << SDHC_WCR_WKENCREM_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_wcr_reg_t hri_sdhc_get_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_wcr_reg_t hri_sdhc_read_WCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->WCR.reg; +} + +static inline void hri_sdhc_set_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_INTCLKEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_INTCLKEN) >> SDHC_CCR_INTCLKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_INTCLKEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_INTCLKEN; + tmp |= value << SDHC_CCR_INTCLKEN_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_INTCLKS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_INTCLKS) >> SDHC_CCR_INTCLKS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_INTCLKS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_INTCLKS; + tmp |= value << SDHC_CCR_INTCLKS_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_SDCLKEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKEN) >> SDHC_CCR_SDCLKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_SDCLKEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_SDCLKEN; + tmp |= value << SDHC_CCR_SDCLKEN_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_CLKGSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_CLKGSEL) >> SDHC_CCR_CLKGSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_CLKGSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_CLKGSEL; + tmp |= value << SDHC_CCR_CLKGSEL_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_USDCLKFSEL(mask)) >> SDHC_CCR_USDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_USDCLKFSEL_Msk; + tmp |= SDHC_CCR_USDCLKFSEL(data); + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_USDCLKFSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_USDCLKFSEL_Msk) >> SDHC_CCR_USDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKFSEL(mask)) >> SDHC_CCR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_SDCLKFSEL_Msk; + tmp |= SDHC_CCR_SDCLKFSEL(data); + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_SDCLKFSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKFSEL_Msk) >> SDHC_CCR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CCR.reg; +} + +static inline void hri_sdhc_set_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg |= SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp = (tmp & SDHC_TCR_DTCVAL(mask)) >> SDHC_TCR_DTCVAL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TCR.reg; + tmp &= ~SDHC_TCR_DTCVAL_Msk; + tmp |= SDHC_TCR_DTCVAL(data); + ((Sdhc *)hw)->TCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg &= ~SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg ^= SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_DTCVAL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp = (tmp & SDHC_TCR_DTCVAL_Msk) >> SDHC_TCR_DTCVAL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->TCR.reg; +} + +static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTALL) >> SDHC_SRR_SWRSTALL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTALL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTALL; + tmp |= value << SDHC_SRR_SWRSTALL_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTCMD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTCMD) >> SDHC_SRR_SWRSTCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTCMD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTCMD; + tmp |= value << SDHC_SRR_SWRSTCMD_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTDAT_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTDAT) >> SDHC_SRR_SWRSTDAT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTDAT_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTDAT; + tmp |= value << SDHC_SRR_SWRSTDAT_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_srr_reg_t hri_sdhc_get_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_srr_reg_t hri_sdhc_read_SRR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SRR.reg; +} + +static inline void hri_sdhc_set_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CMDC) >> SDHC_NISTR_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CMDC; + tmp |= value << SDHC_NISTR_CMDC_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_TRFC) >> SDHC_NISTR_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_TRFC; + tmp |= value << SDHC_NISTR_TRFC_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BLKGE) >> SDHC_NISTR_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BLKGE; + tmp |= value << SDHC_NISTR_BLKGE_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_DMAINT) >> SDHC_NISTR_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_DMAINT; + tmp |= value << SDHC_NISTR_DMAINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BWRRDY) >> SDHC_NISTR_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BWRRDY; + tmp |= value << SDHC_NISTR_BWRRDY_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BRDRDY) >> SDHC_NISTR_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BRDRDY; + tmp |= value << SDHC_NISTR_BRDRDY_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CINS) >> SDHC_NISTR_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CINS; + tmp |= value << SDHC_NISTR_CINS_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CREM) >> SDHC_NISTR_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CREM; + tmp |= value << SDHC_NISTR_CREM_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CINT) >> SDHC_NISTR_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CINT; + tmp |= value << SDHC_NISTR_CINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_EMMC_BOOTAR) >> SDHC_NISTR_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_EMMC_BOOTAR; + tmp |= value << SDHC_NISTR_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_ERRINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_ERRINT) >> SDHC_NISTR_ERRINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_ERRINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_ERRINT; + tmp |= value << SDHC_NISTR_ERRINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nistr_reg_t hri_sdhc_get_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nistr_reg_t hri_sdhc_read_NISTR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISTR.reg; +} + +static inline void hri_sdhc_set_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDTEO) >> SDHC_EISTR_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDTEO; + tmp |= value << SDHC_EISTR_CMDTEO_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDCRC) >> SDHC_EISTR_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDCRC; + tmp |= value << SDHC_EISTR_CMDCRC_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDEND) >> SDHC_EISTR_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDEND; + tmp |= value << SDHC_EISTR_CMDEND_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDIDX) >> SDHC_EISTR_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDIDX; + tmp |= value << SDHC_EISTR_CMDIDX_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATTEO) >> SDHC_EISTR_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATTEO; + tmp |= value << SDHC_EISTR_DATTEO_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATCRC) >> SDHC_EISTR_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATCRC; + tmp |= value << SDHC_EISTR_DATCRC_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATEND) >> SDHC_EISTR_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATEND; + tmp |= value << SDHC_EISTR_DATEND_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CURLIM) >> SDHC_EISTR_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CURLIM; + tmp |= value << SDHC_EISTR_CURLIM_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_ACMD) >> SDHC_EISTR_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_ACMD; + tmp |= value << SDHC_EISTR_ACMD_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_ADMA) >> SDHC_EISTR_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_ADMA; + tmp |= value << SDHC_EISTR_ADMA_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_BOOTAE) >> SDHC_EISTR_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_BOOTAE; + tmp |= value << SDHC_EISTR_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eistr_reg_t hri_sdhc_get_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eistr_reg_t hri_sdhc_read_EISTR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISTR.reg; +} + +static inline void hri_sdhc_set_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CMDC) >> SDHC_NISTER_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CMDC; + tmp |= value << SDHC_NISTER_CMDC_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_TRFC) >> SDHC_NISTER_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_TRFC; + tmp |= value << SDHC_NISTER_TRFC_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BLKGE) >> SDHC_NISTER_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BLKGE; + tmp |= value << SDHC_NISTER_BLKGE_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_DMAINT) >> SDHC_NISTER_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_DMAINT; + tmp |= value << SDHC_NISTER_DMAINT_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BWRRDY) >> SDHC_NISTER_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BWRRDY; + tmp |= value << SDHC_NISTER_BWRRDY_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BRDRDY) >> SDHC_NISTER_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BRDRDY; + tmp |= value << SDHC_NISTER_BRDRDY_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CINS) >> SDHC_NISTER_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CINS; + tmp |= value << SDHC_NISTER_CINS_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CREM) >> SDHC_NISTER_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CREM; + tmp |= value << SDHC_NISTER_CREM_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CINT) >> SDHC_NISTER_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CINT; + tmp |= value << SDHC_NISTER_CINT_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_EMMC_BOOTAR) >> SDHC_NISTER_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_EMMC_BOOTAR; + tmp |= value << SDHC_NISTER_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nister_reg_t hri_sdhc_get_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nister_reg_t hri_sdhc_read_NISTER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISTER.reg; +} + +static inline void hri_sdhc_set_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDTEO) >> SDHC_EISTER_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDTEO; + tmp |= value << SDHC_EISTER_CMDTEO_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDCRC) >> SDHC_EISTER_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDCRC; + tmp |= value << SDHC_EISTER_CMDCRC_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDEND) >> SDHC_EISTER_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDEND; + tmp |= value << SDHC_EISTER_CMDEND_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDIDX) >> SDHC_EISTER_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDIDX; + tmp |= value << SDHC_EISTER_CMDIDX_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATTEO) >> SDHC_EISTER_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATTEO; + tmp |= value << SDHC_EISTER_DATTEO_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATCRC) >> SDHC_EISTER_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATCRC; + tmp |= value << SDHC_EISTER_DATCRC_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATEND) >> SDHC_EISTER_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATEND; + tmp |= value << SDHC_EISTER_DATEND_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CURLIM) >> SDHC_EISTER_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CURLIM; + tmp |= value << SDHC_EISTER_CURLIM_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_ACMD) >> SDHC_EISTER_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_ACMD; + tmp |= value << SDHC_EISTER_ACMD_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_ADMA) >> SDHC_EISTER_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_ADMA; + tmp |= value << SDHC_EISTER_ADMA_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_BOOTAE) >> SDHC_EISTER_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_BOOTAE; + tmp |= value << SDHC_EISTER_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eister_reg_t hri_sdhc_get_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eister_reg_t hri_sdhc_read_EISTER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISTER.reg; +} + +static inline void hri_sdhc_set_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CMDC) >> SDHC_NISIER_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CMDC; + tmp |= value << SDHC_NISIER_CMDC_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_TRFC) >> SDHC_NISIER_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_TRFC; + tmp |= value << SDHC_NISIER_TRFC_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BLKGE) >> SDHC_NISIER_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BLKGE; + tmp |= value << SDHC_NISIER_BLKGE_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_DMAINT) >> SDHC_NISIER_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_DMAINT; + tmp |= value << SDHC_NISIER_DMAINT_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BWRRDY) >> SDHC_NISIER_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BWRRDY; + tmp |= value << SDHC_NISIER_BWRRDY_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BRDRDY) >> SDHC_NISIER_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BRDRDY; + tmp |= value << SDHC_NISIER_BRDRDY_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CINS) >> SDHC_NISIER_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CINS; + tmp |= value << SDHC_NISIER_CINS_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CREM) >> SDHC_NISIER_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CREM; + tmp |= value << SDHC_NISIER_CREM_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CINT) >> SDHC_NISIER_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CINT; + tmp |= value << SDHC_NISIER_CINT_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_EMMC_BOOTAR) >> SDHC_NISIER_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_EMMC_BOOTAR; + tmp |= value << SDHC_NISIER_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nisier_reg_t hri_sdhc_get_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nisier_reg_t hri_sdhc_read_NISIER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISIER.reg; +} + +static inline void hri_sdhc_set_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDTEO) >> SDHC_EISIER_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDTEO; + tmp |= value << SDHC_EISIER_CMDTEO_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDCRC) >> SDHC_EISIER_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDCRC; + tmp |= value << SDHC_EISIER_CMDCRC_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDEND) >> SDHC_EISIER_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDEND; + tmp |= value << SDHC_EISIER_CMDEND_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDIDX) >> SDHC_EISIER_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDIDX; + tmp |= value << SDHC_EISIER_CMDIDX_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATTEO) >> SDHC_EISIER_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATTEO; + tmp |= value << SDHC_EISIER_DATTEO_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATCRC) >> SDHC_EISIER_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATCRC; + tmp |= value << SDHC_EISIER_DATCRC_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATEND) >> SDHC_EISIER_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATEND; + tmp |= value << SDHC_EISIER_DATEND_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CURLIM) >> SDHC_EISIER_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CURLIM; + tmp |= value << SDHC_EISIER_CURLIM_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_ACMD) >> SDHC_EISIER_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_ACMD; + tmp |= value << SDHC_EISIER_ACMD_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_ADMA) >> SDHC_EISIER_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_ADMA; + tmp |= value << SDHC_EISIER_ADMA_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_BOOTAE) >> SDHC_EISIER_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_BOOTAE; + tmp |= value << SDHC_EISIER_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eisier_reg_t hri_sdhc_get_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eisier_reg_t hri_sdhc_read_EISIER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISIER.reg; +} + +static inline void hri_sdhc_set_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_VS18EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_VS18EN) >> SDHC_HC2R_VS18EN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_VS18EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_VS18EN; + tmp |= value << SDHC_HC2R_VS18EN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_EXTUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EXTUN) >> SDHC_HC2R_EXTUN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_EXTUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_EXTUN; + tmp |= value << SDHC_HC2R_EXTUN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_SLCKSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_SLCKSEL) >> SDHC_HC2R_SLCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_SLCKSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_SLCKSEL; + tmp |= value << SDHC_HC2R_SLCKSEL_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_ASINTEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_ASINTEN) >> SDHC_HC2R_ASINTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_ASINTEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_ASINTEN; + tmp |= value << SDHC_HC2R_ASINTEN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_PVALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_PVALEN) >> SDHC_HC2R_PVALEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_PVALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_PVALEN; + tmp |= value << SDHC_HC2R_PVALEN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_UHSMS(mask)) >> SDHC_HC2R_UHSMS_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_UHSMS_Msk; + tmp |= SDHC_HC2R_UHSMS(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_UHSMS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_UHSMS_Msk) >> SDHC_HC2R_UHSMS_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_HS200EN(mask)) >> SDHC_HC2R_EMMC_HS200EN_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_EMMC_HS200EN_Msk; + tmp |= SDHC_HC2R_EMMC_HS200EN(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_HS200EN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_HS200EN_Msk) >> SDHC_HC2R_EMMC_HS200EN_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_DRVSEL(mask)) >> SDHC_HC2R_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_DRVSEL_Msk; + tmp |= SDHC_HC2R_DRVSEL(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_DRVSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_DRVSEL_Msk) >> SDHC_HC2R_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HC2R.reg; +} + +static inline void hri_sdhc_set_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg |= SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_ADMASA_bf(const void *const hw, uint8_t index, + hri_sdhc_asar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp = (tmp & SDHC_ASAR_ADMASA(mask)) >> SDHC_ASAR_ADMASA_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp &= ~SDHC_ASAR_ADMASA_Msk; + tmp |= SDHC_ASAR_ADMASA(data); + ((Sdhc *)hw)->ASAR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg &= ~SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg ^= SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_ADMASA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp = (tmp & SDHC_ASAR_ADMASA_Msk) >> SDHC_ASAR_ADMASA_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->ASAR[index].reg; +} + +static inline void hri_sdhc_set_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_CLKGSEL) >> SDHC_PVR_CLKGSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_PVR_CLKGSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_CLKGSEL; + tmp |= value << SDHC_PVR_CLKGSEL_Pos; + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, + hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_SDCLKFSEL(mask)) >> SDHC_PVR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_SDCLKFSEL_Msk; + tmp |= SDHC_PVR_SDCLKFSEL(data); + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_SDCLKFSEL_Msk) >> SDHC_PVR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_DRVSEL_bf(const void *const hw, uint8_t index, + hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_DRVSEL(mask)) >> SDHC_PVR_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_DRVSEL_Msk; + tmp |= SDHC_PVR_DRVSEL(data); + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_DRVSEL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_DRVSEL_Msk) >> SDHC_PVR_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->PVR[index].reg; +} + +static inline void hri_sdhc_set_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_DDR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_DDR) >> SDHC_MC1R_DDR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_DDR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_DDR; + tmp |= value << SDHC_MC1R_DDR_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_OPD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_OPD) >> SDHC_MC1R_OPD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_OPD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_OPD; + tmp |= value << SDHC_MC1R_OPD_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_BOOTA_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_BOOTA) >> SDHC_MC1R_BOOTA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_BOOTA_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_BOOTA; + tmp |= value << SDHC_MC1R_BOOTA_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_RSTN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_RSTN) >> SDHC_MC1R_RSTN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_RSTN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_RSTN; + tmp |= value << SDHC_MC1R_RSTN_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_FCD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_FCD) >> SDHC_MC1R_FCD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_FCD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_FCD; + tmp |= value << SDHC_MC1R_FCD_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_CMDTYP(mask)) >> SDHC_MC1R_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_CMDTYP_Msk; + tmp |= SDHC_MC1R_CMDTYP(data); + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_CMDTYP_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_CMDTYP_Msk) >> SDHC_MC1R_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->MC1R.reg; +} + +static inline void hri_sdhc_set_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg |= SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp = (tmp & SDHC_ACR_BMAX(mask)) >> SDHC_ACR_BMAX_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ACR.reg; + tmp &= ~SDHC_ACR_BMAX_Msk; + tmp |= SDHC_ACR_BMAX(data); + ((Sdhc *)hw)->ACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg &= ~SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg ^= SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_BMAX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp = (tmp & SDHC_ACR_BMAX_Msk) >> SDHC_ACR_BMAX_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ACR.reg; +} + +static inline void hri_sdhc_set_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg |= SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CC2R_FSDCLKD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp = (tmp & SDHC_CC2R_FSDCLKD) >> SDHC_CC2R_FSDCLKD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CC2R_FSDCLKD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp &= ~SDHC_CC2R_FSDCLKD; + tmp |= value << SDHC_CC2R_FSDCLKD_Pos; + ((Sdhc *)hw)->CC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg &= ~SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg ^= SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cc2r_reg_t hri_sdhc_get_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cc2r_reg_t hri_sdhc_read_CC2R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CC2R.reg; +} + +static inline void hri_sdhc_set_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CACR_CAPWREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_CAPWREN) >> SDHC_CACR_CAPWREN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CACR_CAPWREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= ~SDHC_CACR_CAPWREN; + tmp |= value << SDHC_CACR_CAPWREN_Pos; + ((Sdhc *)hw)->CACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_KEY(mask)) >> SDHC_CACR_KEY_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= ~SDHC_CACR_KEY_Msk; + tmp |= SDHC_CACR_KEY(data); + ((Sdhc *)hw)->CACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_KEY_Msk) >> SDHC_CACR_KEY_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CACR.reg; +} + +static inline void hri_sdhc_set_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg |= SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_DBGR_NIDBG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp = (tmp & SDHC_DBGR_NIDBG) >> SDHC_DBGR_NIDBG_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_DBGR_NIDBG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp &= ~SDHC_DBGR_NIDBG; + tmp |= value << SDHC_DBGR_NIDBG_Pos; + ((Sdhc *)hw)->DBGR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg &= ~SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg ^= SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_dbgr_reg_t hri_sdhc_get_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_dbgr_reg_t hri_sdhc_read_DBGR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->DBGR.reg; +} + +static inline void hri_sdhc_write_FERACES_reg(const void *const hw, hri_sdhc_feraces_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->FERACES.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_write_FEREIS_reg(const void *const hw, hri_sdhc_fereis_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->FEREIS.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_write_MC2R_reg(const void *const hw, hri_sdhc_mc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_sdhc_set_SSAR_CMD23_reg(a, b) hri_sdhc_set_SSAR_reg(a, b) +#define hri_sdhc_get_SSAR_CMD23_reg(a, b) hri_sdhc_get_SSAR_reg(a, b) +#define hri_sdhc_write_SSAR_CMD23_reg(a, b) hri_sdhc_write_SSAR_reg(a, b) +#define hri_sdhc_clear_SSAR_CMD23_reg(a, b) hri_sdhc_clear_SSAR_reg(a, b) +#define hri_sdhc_toggle_SSAR_CMD23_reg(a, b) hri_sdhc_toggle_SSAR_reg(a, b) +#define hri_sdhc_read_SSAR_CMD23_reg(a) hri_sdhc_read_SSAR_reg(a) +#define hri_sdhc_set_HC1R_EMMC_DW_bit(a) hri_sdhc_set_HC1R_DW_bit(a) +#define hri_sdhc_get_HC1R_EMMC_DW_bit(a) hri_sdhc_get_HC1R_DW_bit(a) +#define hri_sdhc_write_HC1R_EMMC_DW_bit(a, b) hri_sdhc_write_HC1R_DW_bit(a, b) +#define hri_sdhc_clear_HC1R_EMMC_DW_bit(a) hri_sdhc_clear_HC1R_DW_bit(a) +#define hri_sdhc_toggle_HC1R_EMMC_DW_bit(a) hri_sdhc_toggle_HC1R_DW_bit(a) +#define hri_sdhc_set_HC1R_EMMC_HSEN_bit(a) hri_sdhc_set_HC1R_HSEN_bit(a) +#define hri_sdhc_get_HC1R_EMMC_HSEN_bit(a) hri_sdhc_get_HC1R_HSEN_bit(a) +#define hri_sdhc_write_HC1R_EMMC_HSEN_bit(a, b) hri_sdhc_write_HC1R_HSEN_bit(a, b) +#define hri_sdhc_clear_HC1R_EMMC_HSEN_bit(a) hri_sdhc_clear_HC1R_HSEN_bit(a) +#define hri_sdhc_toggle_HC1R_EMMC_HSEN_bit(a) hri_sdhc_toggle_HC1R_HSEN_bit(a) +#define hri_sdhc_set_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_set_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_get_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_get_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_write_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_write_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_clear_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_clear_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_toggle_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_toggle_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_read_HC1R_EMMC_DMASEL_bf(a) hri_sdhc_read_HC1R_DMASEL_bf(a) +#define hri_sdhc_set_HC1R_EMMC_reg(a, b) hri_sdhc_set_HC1R_reg(a, b) +#define hri_sdhc_get_HC1R_EMMC_reg(a, b) hri_sdhc_get_HC1R_reg(a, b) +#define hri_sdhc_write_HC1R_EMMC_reg(a, b) hri_sdhc_write_HC1R_reg(a, b) +#define hri_sdhc_clear_HC1R_EMMC_reg(a, b) hri_sdhc_clear_HC1R_reg(a, b) +#define hri_sdhc_toggle_HC1R_EMMC_reg(a, b) hri_sdhc_toggle_HC1R_reg(a, b) +#define hri_sdhc_read_HC1R_EMMC_reg(a) hri_sdhc_read_HC1R_reg(a) +#define hri_sdhc_set_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_set_BGCR_STPBGR_bit(a) +#define hri_sdhc_get_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_get_BGCR_STPBGR_bit(a) +#define hri_sdhc_write_BGCR_EMMC_STPBGR_bit(a, b) hri_sdhc_write_BGCR_STPBGR_bit(a, b) +#define hri_sdhc_clear_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_clear_BGCR_STPBGR_bit(a) +#define hri_sdhc_toggle_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_toggle_BGCR_STPBGR_bit(a) +#define hri_sdhc_set_BGCR_EMMC_CONTR_bit(a) hri_sdhc_set_BGCR_CONTR_bit(a) +#define hri_sdhc_get_BGCR_EMMC_CONTR_bit(a) hri_sdhc_get_BGCR_CONTR_bit(a) +#define hri_sdhc_write_BGCR_EMMC_CONTR_bit(a, b) hri_sdhc_write_BGCR_CONTR_bit(a, b) +#define hri_sdhc_clear_BGCR_EMMC_CONTR_bit(a) hri_sdhc_clear_BGCR_CONTR_bit(a) +#define hri_sdhc_toggle_BGCR_EMMC_CONTR_bit(a) hri_sdhc_toggle_BGCR_CONTR_bit(a) +#define hri_sdhc_set_BGCR_EMMC_reg(a, b) hri_sdhc_set_BGCR_reg(a, b) +#define hri_sdhc_get_BGCR_EMMC_reg(a, b) hri_sdhc_get_BGCR_reg(a, b) +#define hri_sdhc_write_BGCR_EMMC_reg(a, b) hri_sdhc_write_BGCR_reg(a, b) +#define hri_sdhc_clear_BGCR_EMMC_reg(a, b) hri_sdhc_clear_BGCR_reg(a, b) +#define hri_sdhc_toggle_BGCR_EMMC_reg(a, b) hri_sdhc_toggle_BGCR_reg(a, b) +#define hri_sdhc_read_BGCR_EMMC_reg(a) hri_sdhc_read_BGCR_reg(a) +#define hri_sdhc_set_NISTR_EMMC_CMDC_bit(a) hri_sdhc_set_NISTR_CMDC_bit(a) +#define hri_sdhc_get_NISTR_EMMC_CMDC_bit(a) hri_sdhc_get_NISTR_CMDC_bit(a) +#define hri_sdhc_write_NISTR_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTR_CMDC_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTR_CMDC_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTR_CMDC_bit(a) +#define hri_sdhc_set_NISTR_EMMC_TRFC_bit(a) hri_sdhc_set_NISTR_TRFC_bit(a) +#define hri_sdhc_get_NISTR_EMMC_TRFC_bit(a) hri_sdhc_get_NISTR_TRFC_bit(a) +#define hri_sdhc_write_NISTR_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTR_TRFC_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTR_TRFC_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTR_TRFC_bit(a) +#define hri_sdhc_set_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTR_BLKGE_bit(a) +#define hri_sdhc_get_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTR_BLKGE_bit(a) +#define hri_sdhc_write_NISTR_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTR_BLKGE_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTR_BLKGE_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTR_BLKGE_bit(a) +#define hri_sdhc_set_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTR_DMAINT_bit(a) +#define hri_sdhc_get_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTR_DMAINT_bit(a) +#define hri_sdhc_write_NISTR_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTR_DMAINT_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTR_DMAINT_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTR_DMAINT_bit(a) +#define hri_sdhc_set_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTR_BWRRDY_bit(a) +#define hri_sdhc_get_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTR_BWRRDY_bit(a) +#define hri_sdhc_write_NISTR_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTR_BWRRDY_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTR_BWRRDY_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTR_BWRRDY_bit(a) +#define hri_sdhc_set_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTR_BRDRDY_bit(a) +#define hri_sdhc_get_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTR_BRDRDY_bit(a) +#define hri_sdhc_write_NISTR_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTR_BRDRDY_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTR_BRDRDY_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTR_BRDRDY_bit(a) +#define hri_sdhc_set_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_set_NISTR_ERRINT_bit(a) +#define hri_sdhc_get_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_get_NISTR_ERRINT_bit(a) +#define hri_sdhc_write_NISTR_EMMC_ERRINT_bit(a, b) hri_sdhc_write_NISTR_ERRINT_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_clear_NISTR_ERRINT_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_toggle_NISTR_ERRINT_bit(a) +#define hri_sdhc_set_NISTR_EMMC_reg(a, b) hri_sdhc_set_NISTR_reg(a, b) +#define hri_sdhc_get_NISTR_EMMC_reg(a, b) hri_sdhc_get_NISTR_reg(a, b) +#define hri_sdhc_write_NISTR_EMMC_reg(a, b) hri_sdhc_write_NISTR_reg(a, b) +#define hri_sdhc_clear_NISTR_EMMC_reg(a, b) hri_sdhc_clear_NISTR_reg(a, b) +#define hri_sdhc_toggle_NISTR_EMMC_reg(a, b) hri_sdhc_toggle_NISTR_reg(a, b) +#define hri_sdhc_read_NISTR_EMMC_reg(a) hri_sdhc_read_NISTR_reg(a) +#define hri_sdhc_set_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTR_CMDTEO_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTR_CMDTEO_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTR_CMDTEO_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTR_CMDTEO_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTR_CMDTEO_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTR_CMDCRC_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTR_CMDCRC_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTR_CMDCRC_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTR_CMDCRC_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTR_CMDCRC_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTR_CMDEND_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTR_CMDEND_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTR_CMDEND_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTR_CMDEND_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTR_CMDEND_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTR_CMDIDX_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTR_CMDIDX_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTR_CMDIDX_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTR_CMDIDX_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTR_CMDIDX_bit(a) +#define hri_sdhc_set_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTR_DATTEO_bit(a) +#define hri_sdhc_get_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTR_DATTEO_bit(a) +#define hri_sdhc_write_EISTR_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTR_DATTEO_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTR_DATTEO_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTR_DATTEO_bit(a) +#define hri_sdhc_set_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTR_DATCRC_bit(a) +#define hri_sdhc_get_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTR_DATCRC_bit(a) +#define hri_sdhc_write_EISTR_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTR_DATCRC_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTR_DATCRC_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTR_DATCRC_bit(a) +#define hri_sdhc_set_EISTR_EMMC_DATEND_bit(a) hri_sdhc_set_EISTR_DATEND_bit(a) +#define hri_sdhc_get_EISTR_EMMC_DATEND_bit(a) hri_sdhc_get_EISTR_DATEND_bit(a) +#define hri_sdhc_write_EISTR_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTR_DATEND_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTR_DATEND_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTR_DATEND_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTR_CURLIM_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTR_CURLIM_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTR_CURLIM_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTR_CURLIM_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTR_CURLIM_bit(a) +#define hri_sdhc_set_EISTR_EMMC_ACMD_bit(a) hri_sdhc_set_EISTR_ACMD_bit(a) +#define hri_sdhc_get_EISTR_EMMC_ACMD_bit(a) hri_sdhc_get_EISTR_ACMD_bit(a) +#define hri_sdhc_write_EISTR_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTR_ACMD_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTR_ACMD_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTR_ACMD_bit(a) +#define hri_sdhc_set_EISTR_EMMC_ADMA_bit(a) hri_sdhc_set_EISTR_ADMA_bit(a) +#define hri_sdhc_get_EISTR_EMMC_ADMA_bit(a) hri_sdhc_get_EISTR_ADMA_bit(a) +#define hri_sdhc_write_EISTR_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTR_ADMA_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTR_ADMA_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTR_ADMA_bit(a) +#define hri_sdhc_set_EISTR_EMMC_reg(a, b) hri_sdhc_set_EISTR_reg(a, b) +#define hri_sdhc_get_EISTR_EMMC_reg(a, b) hri_sdhc_get_EISTR_reg(a, b) +#define hri_sdhc_write_EISTR_EMMC_reg(a, b) hri_sdhc_write_EISTR_reg(a, b) +#define hri_sdhc_clear_EISTR_EMMC_reg(a, b) hri_sdhc_clear_EISTR_reg(a, b) +#define hri_sdhc_toggle_EISTR_EMMC_reg(a, b) hri_sdhc_toggle_EISTR_reg(a, b) +#define hri_sdhc_read_EISTR_EMMC_reg(a) hri_sdhc_read_EISTR_reg(a) +#define hri_sdhc_set_NISTER_EMMC_CMDC_bit(a) hri_sdhc_set_NISTER_CMDC_bit(a) +#define hri_sdhc_get_NISTER_EMMC_CMDC_bit(a) hri_sdhc_get_NISTER_CMDC_bit(a) +#define hri_sdhc_write_NISTER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTER_CMDC_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTER_CMDC_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTER_CMDC_bit(a) +#define hri_sdhc_set_NISTER_EMMC_TRFC_bit(a) hri_sdhc_set_NISTER_TRFC_bit(a) +#define hri_sdhc_get_NISTER_EMMC_TRFC_bit(a) hri_sdhc_get_NISTER_TRFC_bit(a) +#define hri_sdhc_write_NISTER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTER_TRFC_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTER_TRFC_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTER_TRFC_bit(a) +#define hri_sdhc_set_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTER_BLKGE_bit(a) +#define hri_sdhc_get_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTER_BLKGE_bit(a) +#define hri_sdhc_write_NISTER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTER_BLKGE_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTER_BLKGE_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTER_BLKGE_bit(a) +#define hri_sdhc_set_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTER_DMAINT_bit(a) +#define hri_sdhc_get_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTER_DMAINT_bit(a) +#define hri_sdhc_write_NISTER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTER_DMAINT_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTER_DMAINT_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTER_DMAINT_bit(a) +#define hri_sdhc_set_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTER_BWRRDY_bit(a) +#define hri_sdhc_get_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTER_BWRRDY_bit(a) +#define hri_sdhc_write_NISTER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTER_BWRRDY_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTER_BWRRDY_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTER_BWRRDY_bit(a) +#define hri_sdhc_set_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTER_BRDRDY_bit(a) +#define hri_sdhc_get_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTER_BRDRDY_bit(a) +#define hri_sdhc_write_NISTER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTER_BRDRDY_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTER_BRDRDY_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTER_BRDRDY_bit(a) +#define hri_sdhc_set_NISTER_EMMC_reg(a, b) hri_sdhc_set_NISTER_reg(a, b) +#define hri_sdhc_get_NISTER_EMMC_reg(a, b) hri_sdhc_get_NISTER_reg(a, b) +#define hri_sdhc_write_NISTER_EMMC_reg(a, b) hri_sdhc_write_NISTER_reg(a, b) +#define hri_sdhc_clear_NISTER_EMMC_reg(a, b) hri_sdhc_clear_NISTER_reg(a, b) +#define hri_sdhc_toggle_NISTER_EMMC_reg(a, b) hri_sdhc_toggle_NISTER_reg(a, b) +#define hri_sdhc_read_NISTER_EMMC_reg(a) hri_sdhc_read_NISTER_reg(a) +#define hri_sdhc_set_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTER_CMDTEO_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTER_CMDTEO_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTER_CMDTEO_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTER_CMDTEO_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTER_CMDTEO_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTER_CMDCRC_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTER_CMDCRC_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTER_CMDCRC_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTER_CMDCRC_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTER_CMDCRC_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTER_CMDEND_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTER_CMDEND_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTER_CMDEND_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTER_CMDEND_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTER_CMDEND_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTER_CMDIDX_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTER_CMDIDX_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTER_CMDIDX_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTER_CMDIDX_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTER_CMDIDX_bit(a) +#define hri_sdhc_set_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTER_DATTEO_bit(a) +#define hri_sdhc_get_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTER_DATTEO_bit(a) +#define hri_sdhc_write_EISTER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTER_DATTEO_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTER_DATTEO_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTER_DATTEO_bit(a) +#define hri_sdhc_set_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTER_DATCRC_bit(a) +#define hri_sdhc_get_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTER_DATCRC_bit(a) +#define hri_sdhc_write_EISTER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTER_DATCRC_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTER_DATCRC_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTER_DATCRC_bit(a) +#define hri_sdhc_set_EISTER_EMMC_DATEND_bit(a) hri_sdhc_set_EISTER_DATEND_bit(a) +#define hri_sdhc_get_EISTER_EMMC_DATEND_bit(a) hri_sdhc_get_EISTER_DATEND_bit(a) +#define hri_sdhc_write_EISTER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTER_DATEND_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTER_DATEND_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTER_DATEND_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTER_CURLIM_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTER_CURLIM_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTER_CURLIM_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTER_CURLIM_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTER_CURLIM_bit(a) +#define hri_sdhc_set_EISTER_EMMC_ACMD_bit(a) hri_sdhc_set_EISTER_ACMD_bit(a) +#define hri_sdhc_get_EISTER_EMMC_ACMD_bit(a) hri_sdhc_get_EISTER_ACMD_bit(a) +#define hri_sdhc_write_EISTER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTER_ACMD_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTER_ACMD_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTER_ACMD_bit(a) +#define hri_sdhc_set_EISTER_EMMC_ADMA_bit(a) hri_sdhc_set_EISTER_ADMA_bit(a) +#define hri_sdhc_get_EISTER_EMMC_ADMA_bit(a) hri_sdhc_get_EISTER_ADMA_bit(a) +#define hri_sdhc_write_EISTER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTER_ADMA_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTER_ADMA_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTER_ADMA_bit(a) +#define hri_sdhc_set_EISTER_EMMC_reg(a, b) hri_sdhc_set_EISTER_reg(a, b) +#define hri_sdhc_get_EISTER_EMMC_reg(a, b) hri_sdhc_get_EISTER_reg(a, b) +#define hri_sdhc_write_EISTER_EMMC_reg(a, b) hri_sdhc_write_EISTER_reg(a, b) +#define hri_sdhc_clear_EISTER_EMMC_reg(a, b) hri_sdhc_clear_EISTER_reg(a, b) +#define hri_sdhc_toggle_EISTER_EMMC_reg(a, b) hri_sdhc_toggle_EISTER_reg(a, b) +#define hri_sdhc_read_EISTER_EMMC_reg(a) hri_sdhc_read_EISTER_reg(a) +#define hri_sdhc_set_NISIER_EMMC_CMDC_bit(a) hri_sdhc_set_NISIER_CMDC_bit(a) +#define hri_sdhc_get_NISIER_EMMC_CMDC_bit(a) hri_sdhc_get_NISIER_CMDC_bit(a) +#define hri_sdhc_write_NISIER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISIER_CMDC_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISIER_CMDC_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISIER_CMDC_bit(a) +#define hri_sdhc_set_NISIER_EMMC_TRFC_bit(a) hri_sdhc_set_NISIER_TRFC_bit(a) +#define hri_sdhc_get_NISIER_EMMC_TRFC_bit(a) hri_sdhc_get_NISIER_TRFC_bit(a) +#define hri_sdhc_write_NISIER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISIER_TRFC_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISIER_TRFC_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISIER_TRFC_bit(a) +#define hri_sdhc_set_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISIER_BLKGE_bit(a) +#define hri_sdhc_get_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISIER_BLKGE_bit(a) +#define hri_sdhc_write_NISIER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISIER_BLKGE_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISIER_BLKGE_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISIER_BLKGE_bit(a) +#define hri_sdhc_set_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISIER_DMAINT_bit(a) +#define hri_sdhc_get_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISIER_DMAINT_bit(a) +#define hri_sdhc_write_NISIER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISIER_DMAINT_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISIER_DMAINT_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISIER_DMAINT_bit(a) +#define hri_sdhc_set_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISIER_BWRRDY_bit(a) +#define hri_sdhc_get_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISIER_BWRRDY_bit(a) +#define hri_sdhc_write_NISIER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISIER_BWRRDY_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISIER_BWRRDY_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISIER_BWRRDY_bit(a) +#define hri_sdhc_set_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISIER_BRDRDY_bit(a) +#define hri_sdhc_get_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISIER_BRDRDY_bit(a) +#define hri_sdhc_write_NISIER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISIER_BRDRDY_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISIER_BRDRDY_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISIER_BRDRDY_bit(a) +#define hri_sdhc_set_NISIER_EMMC_reg(a, b) hri_sdhc_set_NISIER_reg(a, b) +#define hri_sdhc_get_NISIER_EMMC_reg(a, b) hri_sdhc_get_NISIER_reg(a, b) +#define hri_sdhc_write_NISIER_EMMC_reg(a, b) hri_sdhc_write_NISIER_reg(a, b) +#define hri_sdhc_clear_NISIER_EMMC_reg(a, b) hri_sdhc_clear_NISIER_reg(a, b) +#define hri_sdhc_toggle_NISIER_EMMC_reg(a, b) hri_sdhc_toggle_NISIER_reg(a, b) +#define hri_sdhc_read_NISIER_EMMC_reg(a) hri_sdhc_read_NISIER_reg(a) +#define hri_sdhc_set_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISIER_CMDTEO_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISIER_CMDTEO_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISIER_CMDTEO_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISIER_CMDTEO_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISIER_CMDTEO_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISIER_CMDCRC_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISIER_CMDCRC_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISIER_CMDCRC_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISIER_CMDCRC_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISIER_CMDCRC_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISIER_CMDEND_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISIER_CMDEND_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISIER_CMDEND_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISIER_CMDEND_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISIER_CMDEND_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISIER_CMDIDX_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISIER_CMDIDX_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISIER_CMDIDX_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISIER_CMDIDX_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISIER_CMDIDX_bit(a) +#define hri_sdhc_set_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISIER_DATTEO_bit(a) +#define hri_sdhc_get_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISIER_DATTEO_bit(a) +#define hri_sdhc_write_EISIER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISIER_DATTEO_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISIER_DATTEO_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISIER_DATTEO_bit(a) +#define hri_sdhc_set_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISIER_DATCRC_bit(a) +#define hri_sdhc_get_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISIER_DATCRC_bit(a) +#define hri_sdhc_write_EISIER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISIER_DATCRC_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISIER_DATCRC_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISIER_DATCRC_bit(a) +#define hri_sdhc_set_EISIER_EMMC_DATEND_bit(a) hri_sdhc_set_EISIER_DATEND_bit(a) +#define hri_sdhc_get_EISIER_EMMC_DATEND_bit(a) hri_sdhc_get_EISIER_DATEND_bit(a) +#define hri_sdhc_write_EISIER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISIER_DATEND_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISIER_DATEND_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISIER_DATEND_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISIER_CURLIM_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISIER_CURLIM_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISIER_CURLIM_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISIER_CURLIM_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISIER_CURLIM_bit(a) +#define hri_sdhc_set_EISIER_EMMC_ACMD_bit(a) hri_sdhc_set_EISIER_ACMD_bit(a) +#define hri_sdhc_get_EISIER_EMMC_ACMD_bit(a) hri_sdhc_get_EISIER_ACMD_bit(a) +#define hri_sdhc_write_EISIER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISIER_ACMD_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISIER_ACMD_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISIER_ACMD_bit(a) +#define hri_sdhc_set_EISIER_EMMC_ADMA_bit(a) hri_sdhc_set_EISIER_ADMA_bit(a) +#define hri_sdhc_get_EISIER_EMMC_ADMA_bit(a) hri_sdhc_get_EISIER_ADMA_bit(a) +#define hri_sdhc_write_EISIER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISIER_ADMA_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISIER_ADMA_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISIER_ADMA_bit(a) +#define hri_sdhc_set_EISIER_EMMC_reg(a, b) hri_sdhc_set_EISIER_reg(a, b) +#define hri_sdhc_get_EISIER_EMMC_reg(a, b) hri_sdhc_get_EISIER_reg(a, b) +#define hri_sdhc_write_EISIER_EMMC_reg(a, b) hri_sdhc_write_EISIER_reg(a, b) +#define hri_sdhc_clear_EISIER_EMMC_reg(a, b) hri_sdhc_clear_EISIER_reg(a, b) +#define hri_sdhc_toggle_EISIER_EMMC_reg(a, b) hri_sdhc_toggle_EISIER_reg(a, b) +#define hri_sdhc_read_EISIER_EMMC_reg(a) hri_sdhc_read_EISIER_reg(a) +#define hri_sdhc_set_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_set_HC2R_EXTUN_bit(a) +#define hri_sdhc_get_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_get_HC2R_EXTUN_bit(a) +#define hri_sdhc_write_HC2R_EMMC_EXTUN_bit(a, b) hri_sdhc_write_HC2R_EXTUN_bit(a, b) +#define hri_sdhc_clear_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_clear_HC2R_EXTUN_bit(a) +#define hri_sdhc_toggle_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_toggle_HC2R_EXTUN_bit(a) +#define hri_sdhc_set_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_set_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_get_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_get_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_write_HC2R_EMMC_SLCKSEL_bit(a, b) hri_sdhc_write_HC2R_SLCKSEL_bit(a, b) +#define hri_sdhc_clear_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_clear_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_toggle_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_toggle_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_set_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_set_HC2R_PVALEN_bit(a) +#define hri_sdhc_get_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_get_HC2R_PVALEN_bit(a) +#define hri_sdhc_write_HC2R_EMMC_PVALEN_bit(a, b) hri_sdhc_write_HC2R_PVALEN_bit(a, b) +#define hri_sdhc_clear_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_clear_HC2R_PVALEN_bit(a) +#define hri_sdhc_toggle_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_toggle_HC2R_PVALEN_bit(a) +#define hri_sdhc_set_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_set_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_get_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_get_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_write_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_write_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_clear_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_clear_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_toggle_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_toggle_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_read_HC2R_EMMC_DRVSEL_bf(a) hri_sdhc_read_HC2R_DRVSEL_bf(a) +#define hri_sdhc_set_HC2R_EMMC_reg(a, b) hri_sdhc_set_HC2R_reg(a, b) +#define hri_sdhc_get_HC2R_EMMC_reg(a, b) hri_sdhc_get_HC2R_reg(a, b) +#define hri_sdhc_write_HC2R_EMMC_reg(a, b) hri_sdhc_write_HC2R_reg(a, b) +#define hri_sdhc_clear_HC2R_EMMC_reg(a, b) hri_sdhc_clear_HC2R_reg(a, b) +#define hri_sdhc_toggle_HC2R_EMMC_reg(a, b) hri_sdhc_toggle_HC2R_reg(a, b) +#define hri_sdhc_read_HC2R_EMMC_reg(a) hri_sdhc_read_HC2R_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SDHC_E54_H_INCLUDED */ +#endif /* _SAME54_SDHC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_sercom_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_sercom_e54.h new file mode 100644 index 0000000..fed00ff --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_sercom_e54.h @@ -0,0 +1,8892 @@ +/** + * \file + * + * \brief SAM SERCOM + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_SERCOM_COMPONENT_ +#ifndef _HRI_SERCOM_E54_H_INCLUDED_ +#define _HRI_SERCOM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) +#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SERCOM_CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sercomi2cm_status_reg_t; +typedef uint16_t hri_sercomi2cs_length_reg_t; +typedef uint16_t hri_sercomi2cs_status_reg_t; +typedef uint16_t hri_sercomspi_length_reg_t; +typedef uint16_t hri_sercomspi_status_reg_t; +typedef uint16_t hri_sercomusart_baud_reg_t; +typedef uint16_t hri_sercomusart_length_reg_t; +typedef uint16_t hri_sercomusart_status_reg_t; +typedef uint32_t hri_sercomi2cm_addr_reg_t; +typedef uint32_t hri_sercomi2cm_baud_reg_t; +typedef uint32_t hri_sercomi2cm_ctrla_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlc_reg_t; +typedef uint32_t hri_sercomi2cm_data_reg_t; +typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; +typedef uint32_t hri_sercomi2cs_addr_reg_t; +typedef uint32_t hri_sercomi2cs_ctrla_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlc_reg_t; +typedef uint32_t hri_sercomi2cs_data_reg_t; +typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; +typedef uint32_t hri_sercomspi_addr_reg_t; +typedef uint32_t hri_sercomspi_ctrla_reg_t; +typedef uint32_t hri_sercomspi_ctrlb_reg_t; +typedef uint32_t hri_sercomspi_ctrlc_reg_t; +typedef uint32_t hri_sercomspi_data_reg_t; +typedef uint32_t hri_sercomspi_syncbusy_reg_t; +typedef uint32_t hri_sercomusart_ctrla_reg_t; +typedef uint32_t hri_sercomusart_ctrlb_reg_t; +typedef uint32_t hri_sercomusart_ctrlc_reg_t; +typedef uint32_t hri_sercomusart_data_reg_t; +typedef uint32_t hri_sercomusart_syncbusy_reg_t; +typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; +typedef uint8_t hri_sercomi2cm_intenset_reg_t; +typedef uint8_t hri_sercomi2cm_intflag_reg_t; +typedef uint8_t hri_sercomi2cs_intenset_reg_t; +typedef uint8_t hri_sercomi2cs_intflag_reg_t; +typedef uint8_t hri_sercomspi_baud_reg_t; +typedef uint8_t hri_sercomspi_dbgctrl_reg_t; +typedef uint8_t hri_sercomspi_intenset_reg_t; +typedef uint8_t hri_sercomspi_intflag_reg_t; +typedef uint8_t hri_sercomusart_dbgctrl_reg_t; +typedef uint8_t hri_sercomusart_intenset_reg_t; +typedef uint8_t hri_sercomusart_intflag_reg_t; +typedef uint8_t hri_sercomusart_rxerrcnt_reg_t; +typedef uint8_t hri_sercomusart_rxpl_reg_t; + +static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTFLAG.reg; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cs_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTFLAG.reg; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; +} + +static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, + hri_sercomspi_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTFLAG.reg; +} + +static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = mask; +} + +static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, + hri_sercomusart_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTFLAG.reg; +} + +static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = mask; +} + +static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = mask; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, + hri_sercomi2cm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTENSET.reg; +} + +static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = data; + ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; +} + +static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = mask; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, + hri_sercomi2cs_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTENSET.reg; +} + +static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = data; + ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; +} + +static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; +} + +static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; + } +} + +static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; +} + +static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; + } +} + +static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; + } +} + +static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = mask; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, + hri_sercomspi_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTENSET.reg; +} + +static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = data; + ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; +} + +static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = mask; +} + +static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; +} + +static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; + } +} + +static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; + } +} + +static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; + } +} + +static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENSET.reg = mask; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, + hri_sercomusart_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTENSET.reg; +} + +static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) +{ + ((Sercom *)hw)->USART.INTENSET.reg = data; + ((Sercom *)hw)->USART.INTENCLR.reg = ~data; +} + +static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = mask; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_LENGTH) >> SERCOM_I2CM_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_LENGTH) >> SERCOM_I2CS_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cs_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_LENGTH) >> SERCOM_SPI_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, + hri_sercomspi_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_RXERRCNT_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_RXERRCNT) >> SERCOM_USART_SYNCBUSY_RXERRCNT_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_LENGTH) >> SERCOM_USART_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, + hri_sercomusart_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg; +} + +static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const hw, + hri_sercomusart_rxerrcnt_reg_t mask) +{ + uint8_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.RXERRCNT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.RXERRCNT.reg; +} + +static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CM_CTRLA_MODE(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CM_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; + tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->I2CM.CTRLA.reg; +} + +static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CS_CTRLA_MODE(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CS_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg = data; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->I2CS.CTRLA.reg; +} + +static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_ENABLE; + tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_IBON; + tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPHA; + tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPOL; + tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DORD; + tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; + tmp |= SERCOM_SPI_CTRLA_MODE(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DOPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DIPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; + tmp |= SERCOM_SPI_CTRLA_FORM(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->SPI.CTRLA.reg; +} + +static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_ENABLE; + tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_IBON; + tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXINV; + tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXINV; + tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CMODE; + tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CPOL; + tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_DORD; + tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; + tmp |= SERCOM_USART_CTRLA_MODE(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPR(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; + tmp |= SERCOM_USART_CTRLA_TXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; + tmp |= SERCOM_USART_CTRLA_RXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPA(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; + tmp |= SERCOM_USART_CTRLA_FORM(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->USART.CTRLA.reg; +} + +static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_SMEN; + tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_QCEN; + tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CM_CTRLB_CMD(data); + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.CTRLB.reg; +} + +static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_SMEN; + tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_GCMD; + tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; + tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; + tmp |= SERCOM_I2CS_CTRLB_AMODE(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CS_CTRLB_CMD(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLB.reg; +} + +static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; + tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_SSDE; + tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_MSSEN; + tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_RXEN; + tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; + tmp |= SERCOM_SPI_CTRLB_AMODE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + return ((Sercom *)hw)->SPI.CTRLB.reg; +} + +static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SBMODE; + tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_COLDEN; + tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SFDE; + tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_ENC; + tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_PMODE; + tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_TXEN; + tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_RXEN; + tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_USART_CTRLB_CHSIZE(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_LINCMD_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_LINCMD(mask)) >> SERCOM_USART_CTRLB_LINCMD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_LINCMD_Msk; + tmp |= SERCOM_USART_CTRLB_LINCMD(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_LINCMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_LINCMD_Msk) >> SERCOM_USART_CTRLB_LINCMD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.CTRLB.reg; +} + +static inline void hri_sercomi2cm_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg |= SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp = (tmp & SERCOM_I2CM_CTRLC_DATA32B) >> SERCOM_I2CM_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp &= ~SERCOM_I2CM_CTRLC_DATA32B; + tmp |= value << SERCOM_I2CM_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->I2CM.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg &= ~SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg ^= SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_get_CTRLC_reg(const void *const hw, + hri_sercomi2cm_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.CTRLC.reg; +} + +static inline void hri_sercomi2cs_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_DATA32B) >> SERCOM_I2CS_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= ~SERCOM_I2CS_CTRLC_DATA32B; + tmp |= value << SERCOM_I2CS_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_SDASETUP_bf(const void *const hw, + hri_sercomi2cs_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP(mask)) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= ~SERCOM_I2CS_CTRLC_SDASETUP_Msk; + tmp |= SERCOM_I2CS_CTRLC_SDASETUP(data); + ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_SDASETUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP_Msk) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_reg(const void *const hw, + hri_sercomi2cs_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLC.reg; +} + +static inline void hri_sercomspi_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_DATA32B) >> SERCOM_SPI_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= ~SERCOM_SPI_CTRLC_DATA32B; + tmp |= value << SERCOM_SPI_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->SPI.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_ICSPACE_bf(const void *const hw, + hri_sercomspi_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE(mask)) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= ~SERCOM_SPI_CTRLC_ICSPACE_Msk; + tmp |= SERCOM_SPI_CTRLC_ICSPACE(data); + ((Sercom *)hw)->SPI.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_ICSPACE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE_Msk) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_reg(const void *const hw, + hri_sercomspi_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.CTRLC.reg; +} + +static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_INACK; + tmp |= value << SERCOM_USART_CTRLC_INACK_Pos; + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_DSNACK; + tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos; + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk; + tmp |= SERCOM_USART_CTRLC_GTIME(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_BRKLEN_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN(mask)) >> SERCOM_USART_CTRLC_BRKLEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_BRKLEN_Msk; + tmp |= SERCOM_USART_CTRLC_BRKLEN(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_BRKLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN_Msk) >> SERCOM_USART_CTRLC_BRKLEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_HDRDLY_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY(mask)) >> SERCOM_USART_CTRLC_HDRDLY_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_HDRDLY_Msk; + tmp |= SERCOM_USART_CTRLC_HDRDLY(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_HDRDLY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY_Msk) >> SERCOM_USART_CTRLC_HDRDLY_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk; + tmp |= SERCOM_USART_CTRLC_MAXITER(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_DATA32B_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DATA32B(mask)) >> SERCOM_USART_CTRLC_DATA32B_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_DATA32B_Msk; + tmp |= SERCOM_USART_CTRLC_DATA32B(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_DATA32B_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DATA32B_Msk) >> SERCOM_USART_CTRLC_DATA32B_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.CTRLC.reg; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.BAUD.reg; +} + +static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; + tmp |= SERCOM_SPI_BAUD_BAUD(data); + ((Sercom *)hw)->SPI.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRAC_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; + tmp |= SERCOM_USART_RXPL_RXPL(data); + ((Sercom *)hw)->USART.RXPL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.RXPL.reg; +} + +static inline void hri_sercomi2cs_set_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LENEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_LENGTH_LENEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LENEN) >> SERCOM_I2CS_LENGTH_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_LENEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= ~SERCOM_I2CS_LENGTH_LENEN; + tmp |= value << SERCOM_I2CS_LENGTH_LENEN_Pos; + ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LENEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LENEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LEN(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomi2cs_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LEN(mask)) >> SERCOM_I2CS_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= ~SERCOM_I2CS_LENGTH_LEN_Msk; + tmp |= SERCOM_I2CS_LENGTH_LEN(data); + ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LEN(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LEN(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LEN_Msk) >> SERCOM_I2CS_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_reg(const void *const hw, + hri_sercomi2cs_length_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg = data; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_reg(const void *const hw) +{ + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + return ((Sercom *)hw)->I2CS.LENGTH.reg; +} + +static inline void hri_sercomspi_set_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LENEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_LENGTH_LENEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LENEN) >> SERCOM_SPI_LENGTH_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_LENGTH_LENEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= ~SERCOM_SPI_LENGTH_LENEN; + tmp |= value << SERCOM_SPI_LENGTH_LENEN_Pos; + ((Sercom *)hw)->SPI.LENGTH.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LENEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LENEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LEN(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomspi_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LEN(mask)) >> SERCOM_SPI_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= ~SERCOM_SPI_LENGTH_LEN_Msk; + tmp |= SERCOM_SPI_LENGTH_LEN(data); + ((Sercom *)hw)->SPI.LENGTH.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LEN(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LEN(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LEN_Msk) >> SERCOM_SPI_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_reg(const void *const hw, + hri_sercomspi_length_reg_t mask) +{ + uint16_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + return ((Sercom *)hw)->SPI.LENGTH.reg; +} + +static inline void hri_sercomusart_set_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LEN(mask)) >> SERCOM_USART_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= ~SERCOM_USART_LENGTH_LEN_Msk; + tmp |= SERCOM_USART_LENGTH_LEN(data); + ((Sercom *)hw)->USART.LENGTH.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LEN_Msk) >> SERCOM_USART_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LENEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LENEN_bf(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LENEN(mask)) >> SERCOM_USART_LENGTH_LENEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= ~SERCOM_USART_LENGTH_LENEN_Msk; + tmp |= SERCOM_USART_LENGTH_LENEN(data); + ((Sercom *)hw)->USART.LENGTH.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LENEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LENEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LENEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LENEN_Msk) >> SERCOM_USART_LENGTH_LENEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_reg(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.LENGTH.reg; +} + +static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LENEN; + tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_HS; + tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CM_ADDR_ADDR(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; + tmp |= SERCOM_I2CM_ADDR_LEN(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.ADDR.reg; +} + +static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_GENCEN; + tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDR(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.ADDR.reg; +} + +static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; + tmp |= SERCOM_SPI_ADDR_ADDR(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.ADDR.reg; +} + +static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; + tmp |= SERCOM_I2CM_DATA_DATA(data); + ((Sercom *)hw)->I2CM.DATA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.DATA.reg; +} + +static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; + tmp |= SERCOM_I2CS_DATA_DATA(data); + ((Sercom *)hw)->I2CS.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.DATA.reg; +} + +static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const hw, + hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= ~SERCOM_SPI_DATA_DATA_Msk; + tmp |= SERCOM_SPI_DATA_DATA(data); + ((Sercom *)hw)->SPI.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DATA.reg; +} + +static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= ~SERCOM_USART_DATA_DATA_Msk; + tmp |= SERCOM_USART_DATA_DATA(data); + ((Sercom *)hw)->USART.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DATA.reg; +} + +static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, + hri_sercomi2cm_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.DBGCTRL.reg; +} + +static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, + hri_sercomspi_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DBGCTRL.reg; +} + +static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, + hri_sercomusart_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DBGCTRL.reg; +} + +static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LENERR) >> SERCOM_I2CS_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, + hri_sercomi2cs_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.STATUS.reg; +} + +static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_LENERR) >> SERCOM_SPI_STATUS_LENERR_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, + hri_sercomspi_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.STATUS.reg; +} + +static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, + hri_sercomusart_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.STATUS.reg; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSERR; + tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; + tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_RXNACK; + tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; + tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; + tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LENERR; + tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; + tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg |= mask; +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.STATUS.reg; +} + +static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + ((Sercom *)hw)->I2CM.STATUS.reg = data; +} + +static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; +} + +static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_sercomusart_set_BAUD_FRAC_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRAC_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRAC_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRAC_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRAC_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRAC_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_FRACFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRACFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRACFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRACFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRACFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRACFP_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_USARTFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_USARTFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_USARTFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_USARTFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_USARTFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_USARTFP_reg(a) hri_sercomusart_read_BAUD_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SERCOM_E54_H_INCLUDED */ +#endif /* _SAME54_SERCOM_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_supc_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_supc_e54.h new file mode 100644 index 0000000..501c36f --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_supc_e54.h @@ -0,0 +1,1769 @@ +/** + * \file + * + * \brief SAM SUPC + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_SUPC_COMPONENT_ +#ifndef _HRI_SUPC_E54_H_INCLUDED_ +#define _HRI_SUPC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) +#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SUPC_CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_supc_bbps_reg_t; +typedef uint32_t hri_supc_bkin_reg_t; +typedef uint32_t hri_supc_bkout_reg_t; +typedef uint32_t hri_supc_bod33_reg_t; +typedef uint32_t hri_supc_intenset_reg_t; +typedef uint32_t hri_supc_intflag_reg_t; +typedef uint32_t hri_supc_status_reg_t; +typedef uint32_t hri_supc_vref_reg_t; +typedef uint32_t hri_supc_vreg_reg_t; + +static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) +{ + return ((Supc *)hw)->INTFLAG.reg; +} + +static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + ((Supc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; + } +} + +static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; +} + +static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; + } +} + +static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; +} + +static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; +} + +static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; +} + +static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; + } +} + +static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; +} + +static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; +} + +static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos; +} + +static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; + } +} + +static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; +} + +static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; +} + +static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos; +} + +static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; + } +} + +static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; +} + +static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENSET.reg = mask; +} + +static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) +{ + return ((Supc *)hw)->INTENSET.reg; +} + +static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) +{ + ((Supc *)hw)->INTENSET.reg = data; + ((Supc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos; +} + +static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos; +} + +static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) +{ + return ((Supc *)hw)->STATUS.reg; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKIN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw) +{ + return ((Supc *)hw)->BKIN.reg; +} + +static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ENABLE; + tmp |= value << SUPC_BOD33_ENABLE_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_STDBYCFG; + tmp |= value << SUPC_BOD33_STDBYCFG_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNSTDBY; + tmp |= value << SUPC_BOD33_RUNSTDBY_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNHIB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNHIB) >> SUPC_BOD33_RUNHIB_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNHIB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNHIB; + tmp |= value << SUPC_BOD33_RUNHIB_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNBKUP; + tmp |= value << SUPC_BOD33_RUNBKUP_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ACTION_Msk; + tmp |= SUPC_BOD33_ACTION(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_HYST(mask)) >> SUPC_BOD33_HYST_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_HYST_Msk; + tmp |= SUPC_BOD33_HYST(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_HYST_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_HYST_Msk) >> SUPC_BOD33_HYST_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_PSEL_Msk; + tmp |= SUPC_BOD33_PSEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_LEVEL_Msk; + tmp |= SUPC_BOD33_LEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_VBATLEVEL(mask)) >> SUPC_BOD33_VBATLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_VBATLEVEL_Msk; + tmp |= SUPC_BOD33_VBATLEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_VBATLEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_VBATLEVEL_Msk) >> SUPC_BOD33_VBATLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) +{ + return ((Supc *)hw)->BOD33.reg; +} + +static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_ENABLE; + tmp |= value << SUPC_VREG_ENABLE_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_SEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_SEL) >> SUPC_VREG_SEL_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_SEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_SEL; + tmp |= value << SUPC_VREG_SEL_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_RUNBKUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_RUNBKUP) >> SUPC_VREG_RUNBKUP_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_RUNBKUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_RUNBKUP; + tmp |= value << SUPC_VREG_RUNBKUP_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_VSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSEN) >> SUPC_VREG_VSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_VSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSEN; + tmp |= value << SUPC_VREG_VSEN_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSPER_Msk; + tmp |= SUPC_VREG_VSPER(data); + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) +{ + return ((Supc *)hw)->VREG.reg; +} + +static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSEN; + tmp |= value << SUPC_VREF_TSEN_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_VREFOE; + tmp |= value << SUPC_VREF_VREFOE_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSSEL; + tmp |= value << SUPC_VREF_TSSEL_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_RUNSTDBY; + tmp |= value << SUPC_VREF_RUNSTDBY_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_ONDEMAND; + tmp |= value << SUPC_VREF_ONDEMAND_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_SEL_Msk; + tmp |= SUPC_VREF_SEL(data); + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) +{ + return ((Supc *)hw)->VREF.reg; +} + +static inline void hri_supc_set_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_CONF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_CONF) >> SUPC_BBPS_CONF_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_CONF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_CONF; + tmp |= value << SUPC_BBPS_CONF_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_WAKEEN; + tmp |= value << SUPC_BBPS_WAKEEN_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw) +{ + return ((Supc *)hw)->BBPS.reg; +} + +static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_EN_Msk; + tmp |= SUPC_BKOUT_EN(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_CLR_Msk; + tmp |= SUPC_BKOUT_CLR(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_SET_Msk; + tmp |= SUPC_BKOUT_SET(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_RTCTGL_Msk; + tmp |= SUPC_BKOUT_RTCTGL(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw) +{ + return ((Supc *)hw)->BKOUT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SUPC_E54_H_INCLUDED */ +#endif /* _SAME54_SUPC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_tc_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_tc_e54.h new file mode 100644 index 0000000..a31cb2c --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_tc_e54.h @@ -0,0 +1,3003 @@ +/** + * \file + * + * \brief SAM TC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_TC_COMPONENT_ +#ifndef _HRI_TC_E54_H_INCLUDED_ +#define _HRI_TC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TC_CRITICAL_SECTIONS) +#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TC_CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tc_evctrl_reg_t; +typedef uint16_t hri_tccount16_cc_reg_t; +typedef uint16_t hri_tccount16_ccbuf_reg_t; +typedef uint16_t hri_tccount16_count_reg_t; +typedef uint32_t hri_tc_ctrla_reg_t; +typedef uint32_t hri_tc_syncbusy_reg_t; +typedef uint32_t hri_tccount32_cc_reg_t; +typedef uint32_t hri_tccount32_ccbuf_reg_t; +typedef uint32_t hri_tccount32_count_reg_t; +typedef uint8_t hri_tc_ctrlbset_reg_t; +typedef uint8_t hri_tc_dbgctrl_reg_t; +typedef uint8_t hri_tc_drvctrl_reg_t; +typedef uint8_t hri_tc_intenset_reg_t; +typedef uint8_t hri_tc_intflag_reg_t; +typedef uint8_t hri_tc_status_reg_t; +typedef uint8_t hri_tc_wave_reg_t; +typedef uint8_t hri_tccount8_cc_reg_t; +typedef uint8_t hri_tccount8_ccbuf_reg_t; +typedef uint8_t hri_tccount8_count_reg_t; +typedef uint8_t hri_tccount8_per_reg_t; +typedef uint8_t hri_tccount8_perbuf_reg_t; + +static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; +} + +static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTFLAG.reg; +} + +static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = mask; +} + +static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; +} + +static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; + } +} + +static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; +} + +static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; +} + +static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; + } +} + +static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; +} + +static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; +} + +static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data); + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); +} + +static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); +} + +static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = mask; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.CTRLBSET.reg; +} + +static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = data; + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data; +} + +static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask; +} + +static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; +} + +static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; +} + +static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; + } +} + +static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; +} + +static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; +} + +static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; +} + +static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; + } +} + +static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; +} + +static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; +} + +static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; +} + +static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; + } +} + +static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; +} + +static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; +} + +static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; +} + +static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; + } +} + +static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; +} + +static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = mask; +} + +static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTENSET.reg; +} + +static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = data; + ((Tc *)hw)->COUNT16.INTENCLR.reg = ~data; +} + +static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = mask; +} + +static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.SYNCBUSY.reg; +} + +static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ENABLE; + tmp |= value << TC_CTRLA_ENABLE_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_RUNSTDBY; + tmp |= value << TC_CTRLA_RUNSTDBY_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ONDEMAND; + tmp |= value << TC_CTRLA_ONDEMAND_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ALOCK; + tmp |= value << TC_CTRLA_ALOCK_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN0; + tmp |= value << TC_CTRLA_CAPTEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN1; + tmp |= value << TC_CTRLA_CAPTEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN0; + tmp |= value << TC_CTRLA_COPEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN1; + tmp |= value << TC_CTRLA_COPEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_MODE_Msk; + tmp |= TC_CTRLA_MODE(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCSYNC_Msk; + tmp |= TC_CTRLA_PRESCSYNC(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCALER_Msk; + tmp |= TC_CTRLA_PRESCALER(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE0(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE0(mask)) >> TC_CTRLA_CAPTMODE0_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTMODE0_Msk; + tmp |= TC_CTRLA_CAPTMODE0(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE0(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE0(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE0_Msk) >> TC_CTRLA_CAPTMODE0_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE1(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE1(mask)) >> TC_CTRLA_CAPTMODE1_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTMODE1_Msk; + tmp |= TC_CTRLA_CAPTMODE1(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE1(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE1(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE1_Msk) >> TC_CTRLA_CAPTMODE1_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + return ((Tc *)hw)->COUNT16.CTRLA.reg; +} + +static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCINV; + tmp |= value << TC_EVCTRL_TCINV_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCEI; + tmp |= value << TC_EVCTRL_TCEI_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_OVFEO; + tmp |= value << TC_EVCTRL_OVFEO_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO0; + tmp |= value << TC_EVCTRL_MCEO0_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO1; + tmp |= value << TC_EVCTRL_MCEO1_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_EVACT_Msk; + tmp |= TC_EVCTRL_EVACT(data); + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.EVCTRL.reg; +} + +static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= ~TC_WAVE_WAVEGEN_Msk; + tmp |= TC_WAVE_WAVEGEN(data); + ((Tc *)hw)->COUNT16.WAVE.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.WAVE.reg; +} + +static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN0; + tmp |= value << TC_DRVCTRL_INVEN0_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN1; + tmp |= value << TC_DRVCTRL_INVEN1_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DRVCTRL.reg; +} + +static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= ~TC_DBGCTRL_DBGRUN; + tmp |= value << TC_DBGCTRL_DBGRUN_Pos; + ((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DBGCTRL.reg; +} + +static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; + tmp |= TC_COUNT8_COUNT_COUNT(data); + ((Tc *)hw)->COUNT8.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT8.COUNT.reg; +} + +static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; + tmp |= TC_COUNT16_COUNT_COUNT(data); + ((Tc *)hw)->COUNT16.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT16.COUNT.reg; +} + +static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; + tmp |= TC_COUNT32_COUNT_COUNT(data); + ((Tc *)hw)->COUNT32.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT32.COUNT.reg; +} + +static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= ~TC_COUNT8_PER_PER_Msk; + tmp |= TC_COUNT8_PER_PER(data); + ((Tc *)hw)->COUNT8.PER.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + return ((Tc *)hw)->COUNT8.PER.reg; +} + +static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= ~TC_COUNT8_CC_CC_Msk; + tmp |= TC_COUNT8_CC_CC(data); + ((Tc *)hw)->COUNT8.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT8.CC[index].reg; +} + +static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= ~TC_COUNT16_CC_CC_Msk; + tmp |= TC_COUNT16_CC_CC(data); + ((Tc *)hw)->COUNT16.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT16.CC[index].reg; +} + +static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= ~TC_COUNT32_CC_CC_Msk; + tmp |= TC_COUNT32_CC_CC(data); + ((Tc *)hw)->COUNT32.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT32.CC[index].reg; +} + +static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; + tmp |= TC_COUNT8_PERBUF_PERBUF(data); + ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.PERBUF.reg; +} + +static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT8_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.CCBUF[index].reg; +} + +static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT16_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.CCBUF[index].reg; +} + +static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT32_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT32.CCBUF[index].reg; +} + +static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; +} + +static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; +} + +static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b) +#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b) +#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b) +#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b) +#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b) +#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a) +#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b) +#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b) +#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b) +#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b) +#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b) +#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a) +#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b) +#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b) +#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b) +#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b) +#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b) +#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a) +#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b) +#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b) +#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b) +#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b) +#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b) +#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TC_E54_H_INCLUDED */ +#endif /* _SAME54_TC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_tcc_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_tcc_e54.h new file mode 100644 index 0000000..55f46bd --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_tcc_e54.h @@ -0,0 +1,9992 @@ +/** + * \file + * + * \brief SAM TCC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_TCC_COMPONENT_ +#ifndef _HRI_TCC_E54_H_INCLUDED_ +#define _HRI_TCC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TCC_CRITICAL_SECTIONS) +#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TCC_CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tcc_patt_reg_t; +typedef uint16_t hri_tcc_pattbuf_reg_t; +typedef uint32_t hri_tcc_cc_reg_t; +typedef uint32_t hri_tcc_ccbuf_reg_t; +typedef uint32_t hri_tcc_count_reg_t; +typedef uint32_t hri_tcc_ctrla_reg_t; +typedef uint32_t hri_tcc_drvctrl_reg_t; +typedef uint32_t hri_tcc_evctrl_reg_t; +typedef uint32_t hri_tcc_fctrla_reg_t; +typedef uint32_t hri_tcc_fctrlb_reg_t; +typedef uint32_t hri_tcc_intenset_reg_t; +typedef uint32_t hri_tcc_intflag_reg_t; +typedef uint32_t hri_tcc_per_reg_t; +typedef uint32_t hri_tcc_perbuf_reg_t; +typedef uint32_t hri_tcc_status_reg_t; +typedef uint32_t hri_tcc_syncbusy_reg_t; +typedef uint32_t hri_tcc_wave_reg_t; +typedef uint32_t hri_tcc_wexctrl_reg_t; +typedef uint8_t hri_tcc_ctrlbset_reg_t; +typedef uint8_t hri_tcc_dbgctrl_reg_t; + +static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + while (((Tcc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + return ((Tcc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_INTFLAG_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; +} + +static inline bool hri_tcc_get_INTFLAG_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; +} + +static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_interrupt_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; +} + +static inline bool hri_tcc_get_interrupt_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTFLAG.reg; +} + +static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + ((Tcc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; +} + +static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; + } +} + +static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; +} + +static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; +} + +static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; + } +} + +static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; +} + +static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); +} + +static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); +} + +static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->CTRLBSET.reg; +} + +static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = data; + ((Tcc *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; +} + +static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; +} + +static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; + } +} + +static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; +} + +static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; +} + +static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; +} + +static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; + } +} + +static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; +} + +static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; +} + +static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; +} + +static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; + } +} + +static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; +} + +static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; +} + +static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; +} + +static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; + } +} + +static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; +} + +static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; +} + +static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos; +} + +static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; + } +} + +static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; +} + +static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; +} + +static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; +} + +static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; + } +} + +static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; +} + +static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; +} + +static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; +} + +static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; +} + +static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; +} + +static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; +} + +static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; +} + +static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; +} + +static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; +} + +static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; +} + +static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; +} + +static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; + } +} + +static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; +} + +static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; +} + +static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; +} + +static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; + } +} + +static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; +} + +static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; +} + +static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; +} + +static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; + } +} + +static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; +} + +static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; +} + +static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; +} + +static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; + } +} + +static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; +} + +static inline void hri_tcc_set_INTEN_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; +} + +static inline bool hri_tcc_get_INTEN_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC4) >> TCC_INTENSET_MC4_Pos; +} + +static inline void hri_tcc_write_INTEN_MC4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; + } +} + +static inline void hri_tcc_clear_INTEN_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; +} + +static inline void hri_tcc_set_INTEN_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; +} + +static inline bool hri_tcc_get_INTEN_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC5) >> TCC_INTENSET_MC5_Pos; +} + +static inline void hri_tcc_write_INTEN_MC5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; + } +} + +static inline void hri_tcc_clear_INTEN_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; +} + +static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENSET.reg = mask; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTENSET.reg; +} + +static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) +{ + ((Tcc *)hw)->INTENSET.reg = data; + ((Tcc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC4) >> TCC_SYNCBUSY_CC4_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC5) >> TCC_SYNCBUSY_CC5_Pos; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tcc *)hw)->SYNCBUSY.reg; +} + +static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ENABLE; + tmp |= value << TCC_CTRLA_ENABLE_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RUNSTDBY; + tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ALOCK; + tmp |= value << TCC_CTRLA_ALOCK_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_MSYNC; + tmp |= value << TCC_CTRLA_MSYNC_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_DMAOS; + tmp |= value << TCC_CTRLA_DMAOS_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN0; + tmp |= value << TCC_CTRLA_CPTEN0_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN1; + tmp |= value << TCC_CTRLA_CPTEN1_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN2; + tmp |= value << TCC_CTRLA_CPTEN2_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN3; + tmp |= value << TCC_CTRLA_CPTEN3_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN4) >> TCC_CTRLA_CPTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN4; + tmp |= value << TCC_CTRLA_CPTEN4_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN5) >> TCC_CTRLA_CPTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN5; + tmp |= value << TCC_CTRLA_CPTEN5_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RESOLUTION_Msk; + tmp |= TCC_CTRLA_RESOLUTION(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCALER_Msk; + tmp |= TCC_CTRLA_PRESCALER(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; + tmp |= TCC_CTRLA_PRESCSYNC(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + return ((Tcc *)hw)->CTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_KEEP; + tmp |= value << TCC_FCTRLA_KEEP_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_QUAL; + tmp |= value << TCC_FCTRLA_QUAL_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_RESTART; + tmp |= value << TCC_FCTRLA_RESTART_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKPRESC; + tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_SRC_Msk; + tmp |= TCC_FCTRLA_SRC(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANK_Msk; + tmp |= TCC_FCTRLA_BLANK(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_HALT_Msk; + tmp |= TCC_FCTRLA_HALT(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CHSEL_Msk; + tmp |= TCC_FCTRLA_CHSEL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CAPTURE_Msk; + tmp |= TCC_FCTRLA_CAPTURE(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; + tmp |= TCC_FCTRLA_BLANKVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; + tmp |= TCC_FCTRLA_FILTERVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_KEEP; + tmp |= value << TCC_FCTRLB_KEEP_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_QUAL; + tmp |= value << TCC_FCTRLB_QUAL_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_RESTART; + tmp |= value << TCC_FCTRLB_RESTART_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKPRESC; + tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_SRC_Msk; + tmp |= TCC_FCTRLB_SRC(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANK_Msk; + tmp |= TCC_FCTRLB_BLANK(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_HALT_Msk; + tmp |= TCC_FCTRLB_HALT(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CHSEL_Msk; + tmp |= TCC_FCTRLB_CHSEL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CAPTURE_Msk; + tmp |= TCC_FCTRLB_CAPTURE(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; + tmp |= TCC_FCTRLB_BLANKVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; + tmp |= TCC_FCTRLB_FILTERVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLB.reg; +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN0; + tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN1; + tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN2; + tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN3; + tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_OTMX_Msk; + tmp |= TCC_WEXCTRL_OTMX(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTLS_Msk; + tmp |= TCC_WEXCTRL_DTLS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTHS_Msk; + tmp |= TCC_WEXCTRL_DTHS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->WEXCTRL.reg; +} + +static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE0; + tmp |= value << TCC_DRVCTRL_NRE0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE1; + tmp |= value << TCC_DRVCTRL_NRE1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE2; + tmp |= value << TCC_DRVCTRL_NRE2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE3; + tmp |= value << TCC_DRVCTRL_NRE3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE4; + tmp |= value << TCC_DRVCTRL_NRE4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE5; + tmp |= value << TCC_DRVCTRL_NRE5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE6; + tmp |= value << TCC_DRVCTRL_NRE6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE7; + tmp |= value << TCC_DRVCTRL_NRE7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV0; + tmp |= value << TCC_DRVCTRL_NRV0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV1; + tmp |= value << TCC_DRVCTRL_NRV1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV2; + tmp |= value << TCC_DRVCTRL_NRV2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV3; + tmp |= value << TCC_DRVCTRL_NRV3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV4; + tmp |= value << TCC_DRVCTRL_NRV4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV5; + tmp |= value << TCC_DRVCTRL_NRV5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV6; + tmp |= value << TCC_DRVCTRL_NRV6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV7; + tmp |= value << TCC_DRVCTRL_NRV7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN0; + tmp |= value << TCC_DRVCTRL_INVEN0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN1; + tmp |= value << TCC_DRVCTRL_INVEN1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN2; + tmp |= value << TCC_DRVCTRL_INVEN2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN3; + tmp |= value << TCC_DRVCTRL_INVEN3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN4; + tmp |= value << TCC_DRVCTRL_INVEN4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN5; + tmp |= value << TCC_DRVCTRL_INVEN5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN6; + tmp |= value << TCC_DRVCTRL_INVEN6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN7; + tmp |= value << TCC_DRVCTRL_INVEN7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL0(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL1(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DRVCTRL.reg; +} + +static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_DBGRUN; + tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_FDDBD; + tmp |= value << TCC_DBGCTRL_FDDBD_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DBGCTRL.reg; +} + +static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_OVFEO; + tmp |= value << TCC_EVCTRL_OVFEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TRGEO; + tmp |= value << TCC_EVCTRL_TRGEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTEO; + tmp |= value << TCC_EVCTRL_CNTEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV0; + tmp |= value << TCC_EVCTRL_TCINV0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV1; + tmp |= value << TCC_EVCTRL_TCINV1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI0; + tmp |= value << TCC_EVCTRL_TCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI1; + tmp |= value << TCC_EVCTRL_TCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI0; + tmp |= value << TCC_EVCTRL_MCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI1; + tmp |= value << TCC_EVCTRL_MCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI2; + tmp |= value << TCC_EVCTRL_MCEI2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI3; + tmp |= value << TCC_EVCTRL_MCEI3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI4) >> TCC_EVCTRL_MCEI4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI4; + tmp |= value << TCC_EVCTRL_MCEI4_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI5) >> TCC_EVCTRL_MCEI5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI5; + tmp |= value << TCC_EVCTRL_MCEI5_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO0; + tmp |= value << TCC_EVCTRL_MCEO0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO1; + tmp |= value << TCC_EVCTRL_MCEO1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO2; + tmp |= value << TCC_EVCTRL_MCEO2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO3; + tmp |= value << TCC_EVCTRL_MCEO3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO4) >> TCC_EVCTRL_MCEO4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO4; + tmp |= value << TCC_EVCTRL_MCEO4_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO5) >> TCC_EVCTRL_MCEO5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO5; + tmp |= value << TCC_EVCTRL_MCEO5_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT0_Msk; + tmp |= TCC_EVCTRL_EVACT0(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT1_Msk; + tmp |= TCC_EVCTRL_EVACT1(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTSEL_Msk; + tmp |= TCC_EVCTRL_CNTSEL(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->EVCTRL.reg; +} + +static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE0; + tmp |= value << TCC_PATT_PGE0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE1; + tmp |= value << TCC_PATT_PGE1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE2; + tmp |= value << TCC_PATT_PGE2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE3; + tmp |= value << TCC_PATT_PGE3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE4; + tmp |= value << TCC_PATT_PGE4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE5; + tmp |= value << TCC_PATT_PGE5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE6; + tmp |= value << TCC_PATT_PGE6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE7; + tmp |= value << TCC_PATT_PGE7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV0; + tmp |= value << TCC_PATT_PGV0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV1; + tmp |= value << TCC_PATT_PGV1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV2; + tmp |= value << TCC_PATT_PGV2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV3; + tmp |= value << TCC_PATT_PGV3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV4; + tmp |= value << TCC_PATT_PGV4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV5; + tmp |= value << TCC_PATT_PGV5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV6; + tmp |= value << TCC_PATT_PGV6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV7; + tmp |= value << TCC_PATT_PGV7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + uint16_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->PATT.reg; +} + +static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CIPEREN; + tmp |= value << TCC_WAVE_CIPEREN_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN0; + tmp |= value << TCC_WAVE_CICCEN0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN1; + tmp |= value << TCC_WAVE_CICCEN1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN2; + tmp |= value << TCC_WAVE_CICCEN2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN3; + tmp |= value << TCC_WAVE_CICCEN3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL0; + tmp |= value << TCC_WAVE_POL0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL1; + tmp |= value << TCC_WAVE_POL1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL2; + tmp |= value << TCC_WAVE_POL2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL3; + tmp |= value << TCC_WAVE_POL3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL4) >> TCC_WAVE_POL4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL4; + tmp |= value << TCC_WAVE_POL4_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL5) >> TCC_WAVE_POL5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL5; + tmp |= value << TCC_WAVE_POL5_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP0; + tmp |= value << TCC_WAVE_SWAP0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP1; + tmp |= value << TCC_WAVE_SWAP1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP2; + tmp |= value << TCC_WAVE_SWAP2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP3; + tmp |= value << TCC_WAVE_SWAP3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_WAVEGEN_Msk; + tmp |= TCC_WAVE_WAVEGEN(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_RAMP_Msk; + tmp |= TCC_WAVE_RAMP(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->WAVE.reg; +} + +static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH4_DITHER_Msk; + tmp |= TCC_PER_DITH4_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH5_DITHER_Msk; + tmp |= TCC_PER_DITH5_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH6_DITHER_Msk; + tmp |= TCC_PER_DITH6_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH4_DITHER_Msk; + tmp |= TCC_CC_DITH4_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH5_DITHER_Msk; + tmp |= TCC_CC_DITH5_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH6_DITHER_Msk; + tmp |= TCC_CC_DITH6_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB0; + tmp |= value << TCC_PATTBUF_PGEB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB1; + tmp |= value << TCC_PATTBUF_PGEB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB2; + tmp |= value << TCC_PATTBUF_PGEB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB3; + tmp |= value << TCC_PATTBUF_PGEB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB4; + tmp |= value << TCC_PATTBUF_PGEB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB5; + tmp |= value << TCC_PATTBUF_PGEB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB6; + tmp |= value << TCC_PATTBUF_PGEB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB7; + tmp |= value << TCC_PATTBUF_PGEB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB0; + tmp |= value << TCC_PATTBUF_PGVB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB1; + tmp |= value << TCC_PATTBUF_PGVB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB2; + tmp |= value << TCC_PATTBUF_PGVB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB3; + tmp |= value << TCC_PATTBUF_PGVB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB4; + tmp |= value << TCC_PATTBUF_PGVB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB5; + tmp |= value << TCC_PATTBUF_PGVB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB6; + tmp |= value << TCC_PATTBUF_PGVB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB7; + tmp |= value << TCC_PATTBUF_PGVB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PATTBUF.reg; +} + +static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERBUF.reg; +} + +static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCBUF[index].reg; +} + +static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; +} + +static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; +} + +static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; +} + +static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV4_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV4) >> TCC_STATUS_CCBUFV4_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV5_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV5) >> TCC_STATUS_CCBUFV5_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP4_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP4) >> TCC_STATUS_CMP4_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP5_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP5) >> TCC_STATUS_CMP5_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TCC_E54_H_INCLUDED */ +#endif /* _SAME54_TCC_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_trng_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_trng_e54.h new file mode 100644 index 0000000..e42caab --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_trng_e54.h @@ -0,0 +1,380 @@ +/** + * \file + * + * \brief SAM TRNG + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_TRNG_COMPONENT_ +#ifndef _HRI_TRNG_E54_H_INCLUDED_ +#define _HRI_TRNG_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TRNG_CRITICAL_SECTIONS) +#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TRNG_CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_trng_data_reg_t; +typedef uint8_t hri_trng_ctrla_reg_t; +typedef uint8_t hri_trng_evctrl_reg_t; +typedef uint8_t hri_trng_intenset_reg_t; +typedef uint8_t hri_trng_intflag_reg_t; + +static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw) +{ + return ((Trng *)hw)->INTFLAG.reg; +} + +static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + ((Trng *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; +} + +static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos; +} + +static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; + } else { + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; + } +} + +static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; +} + +static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENSET.reg = mask; +} + +static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw) +{ + return ((Trng *)hw)->INTENSET.reg; +} + +static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data) +{ + ((Trng *)hw)->INTENSET.reg = data; + ((Trng *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENCLR.reg = mask; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Trng *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw) +{ + return ((Trng *)hw)->DATA.reg; +} + +static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_ENABLE; + tmp |= value << TRNG_CTRLA_ENABLE_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_RUNSTDBY; + tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw) +{ + return ((Trng *)hw)->CTRLA.reg; +} + +static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= ~TRNG_EVCTRL_DATARDYEO; + tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos; + ((Trng *)hw)->EVCTRL.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw) +{ + return ((Trng *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TRNG_E54_H_INCLUDED */ +#endif /* _SAME54_TRNG_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_usb_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_usb_e54.h new file mode 100644 index 0000000..34b5e02 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_usb_e54.h @@ -0,0 +1,9335 @@ +/** + * \file + * + * \brief SAM USB + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_USB_COMPONENT_ +#ifndef _HRI_USB_E54_H_INCLUDED_ +#define _HRI_USB_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_USB_CRITICAL_SECTIONS) +#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define USB_CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_usb_padcal_reg_t; +typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t; +typedef uint16_t hri_usbdesc_bank_extreg_reg_t; +typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t; +typedef uint16_t hri_usbdescriptordevice_extreg_reg_t; +typedef uint16_t hri_usbdescriptorhost_ctrl_pipe_reg_t; +typedef uint16_t hri_usbdescriptorhost_extreg_reg_t; +typedef uint16_t hri_usbdescriptorhost_status_pipe_reg_t; +typedef uint16_t hri_usbdevice_ctrlb_reg_t; +typedef uint16_t hri_usbdevice_epintsmry_reg_t; +typedef uint16_t hri_usbdevice_fnum_reg_t; +typedef uint16_t hri_usbdevice_intenset_reg_t; +typedef uint16_t hri_usbdevice_intflag_reg_t; +typedef uint16_t hri_usbhost_ctrlb_reg_t; +typedef uint16_t hri_usbhost_fnum_reg_t; +typedef uint16_t hri_usbhost_intenset_reg_t; +typedef uint16_t hri_usbhost_intflag_reg_t; +typedef uint16_t hri_usbhost_pintsmry_reg_t; +typedef uint32_t hri_usb_descadd_reg_t; +typedef uint32_t hri_usbdesc_bank_addr_reg_t; +typedef uint32_t hri_usbdesc_bank_pcksize_reg_t; +typedef uint32_t hri_usbdescriptordevice_addr_reg_t; +typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t; +typedef uint32_t hri_usbdescriptorhost_addr_reg_t; +typedef uint32_t hri_usbdescriptorhost_pcksize_reg_t; +typedef uint8_t hri_usb_ctrla_reg_t; +typedef uint8_t hri_usb_fsmstatus_reg_t; +typedef uint8_t hri_usb_qosctrl_reg_t; +typedef uint8_t hri_usb_syncbusy_reg_t; +typedef uint8_t hri_usbdesc_bank_status_bk_reg_t; +typedef uint8_t hri_usbdescriptordevice_status_bk_reg_t; +typedef uint8_t hri_usbdescriptorhost_status_bk_reg_t; +typedef uint8_t hri_usbdevice_dadd_reg_t; +typedef uint8_t hri_usbdevice_epcfg_reg_t; +typedef uint8_t hri_usbdevice_epintenset_reg_t; +typedef uint8_t hri_usbdevice_epintflag_reg_t; +typedef uint8_t hri_usbdevice_epstatus_reg_t; +typedef uint8_t hri_usbdevice_status_reg_t; +typedef uint8_t hri_usbendpoint_epcfg_reg_t; +typedef uint8_t hri_usbendpoint_epintenset_reg_t; +typedef uint8_t hri_usbendpoint_epintflag_reg_t; +typedef uint8_t hri_usbendpoint_epstatus_reg_t; +typedef uint8_t hri_usbhost_binterval_reg_t; +typedef uint8_t hri_usbhost_flenhigh_reg_t; +typedef uint8_t hri_usbhost_hsofc_reg_t; +typedef uint8_t hri_usbhost_pcfg_reg_t; +typedef uint8_t hri_usbhost_pintenset_reg_t; +typedef uint8_t hri_usbhost_pintflag_reg_t; +typedef uint8_t hri_usbhost_pstatus_reg_t; +typedef uint8_t hri_usbhost_status_reg_t; +typedef uint8_t hri_usbpipe_binterval_reg_t; +typedef uint8_t hri_usbpipe_pcfg_reg_t; +typedef uint8_t hri_usbpipe_pintenset_reg_t; +typedef uint8_t hri_usbpipe_pintflag_reg_t; +typedef uint8_t hri_usbpipe_pstatus_reg_t; + +static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg) +{ + while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg) +{ + return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->EXTREG.reg; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_BK.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; +} + +static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t +hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t +hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, hri_usbdescriptorhost_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) + >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) + >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_bk_reg_t +hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) + >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) + >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) + >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbendpoint_epintflag_reg_t +hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintflag_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbendpoint_epstatus_reg_t +hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbendpoint_epintenset_reg_t +hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbdevice_epintflag_reg_t +hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbdevice_epintenset_reg_t +hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const hw, + hri_usbdevice_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTFLAG.reg; +} + +static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = mask; +} + +static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const hw, + hri_usbhost_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTFLAG.reg; +} + +static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; + } +} + +static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; + } +} + +static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; + } +} + +static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = mask; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const hw, + hri_usbdevice_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTENSET.reg; +} + +static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = data; + ((Usb *)hw)->DEVICE.INTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = mask; +} + +static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; +} + +static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos; +} + +static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; + } +} + +static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; +} + +static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; +} + +static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos; +} + +static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; + } +} + +static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; +} + +static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; + } +} + +static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; + } +} + +static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; +} + +static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos; +} + +static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; + } +} + +static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; +} + +static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; +} + +static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos; +} + +static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; + } +} + +static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; +} + +static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENSET.reg = mask; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const hw, + hri_usbhost_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTENSET.reg; +} + +static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data) +{ + ((Usb *)hw)->HOST.INTENSET.reg = data; + ((Usb *)hw)->HOST.INTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = mask; +} + +static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.SYNCBUSY.reg; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.STATUS.reg; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, + hri_usb_fsmstatus_reg_t mask) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FSMSTATUS.reg; +} + +static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.FNUM.reg; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FLENHIGH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FLENHIGH.reg; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const hw, + hri_usbdevice_epintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.EPINTSMRY.reg; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const hw, + hri_usbhost_pintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PINTSMRY.reg; +} + +static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_ENABLE; + tmp |= value << USB_CTRLA_ENABLE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_RUNSTDBY; + tmp |= value << USB_CTRLA_RUNSTDBY_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_MODE; + tmp |= value << USB_CTRLA_MODE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg = data; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw) +{ + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + return ((Usb *)hw)->HOST.CTRLA.reg; +} + +static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_CQOS_Msk; + tmp |= USB_QOSCTRL_CQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_DQOS_Msk; + tmp |= USB_QOSCTRL_DQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.QOSCTRL.reg; +} + +static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_DETACH; + tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_UPRSM; + tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_NREPLY; + tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTJ; + tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTK; + tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTPCKT; + tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_OPMODE2; + tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_GNAK; + tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk; + tmp |= USB_DEVICE_CTRLB_SPDCONF(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk; + tmp |= USB_DEVICE_CTRLB_LPMHDSK(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.CTRLB.reg; +} + +static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_RESUME; + tmp |= value << USB_HOST_CTRLB_RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_AUTORESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_AUTORESUME) >> USB_HOST_CTRLB_AUTORESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_AUTORESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_AUTORESUME; + tmp |= value << USB_HOST_CTRLB_AUTORESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTJ; + tmp |= value << USB_HOST_CTRLB_TSTJ_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTK; + tmp |= value << USB_HOST_CTRLB_TSTK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SOFE; + tmp |= value << USB_HOST_CTRLB_SOFE_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_BUSRESET; + tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_VBUSOK; + tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_L1RESUME; + tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk; + tmp |= USB_HOST_CTRLB_SPDCONF(data); + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.CTRLB.reg; +} + +static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_ADDEN; + tmp |= value << USB_DEVICE_DADD_ADDEN_Pos; + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const hw, + hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_DADD_Msk; + tmp |= USB_DEVICE_DADD_DADD(data); + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.DADD.reg; +} + +static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENCE; + tmp |= value << USB_HOST_HSOFC_FLENCE_Pos; + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENC_Msk; + tmp |= USB_HOST_HSOFC_FLENC(data); + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.HSOFC.reg; +} + +static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_MFNUM_Msk; + tmp |= USB_HOST_FNUM_MFNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_FNUM_Msk; + tmp |= USB_HOST_FNUM_FNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FNUM.reg; +} + +static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= ~USB_DESCADD_DESCADD_Msk; + tmp |= USB_DESCADD_DESCADD(data); + ((Usb *)hw)->HOST.DESCADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.DESCADD.reg; +} + +static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSP_Msk; + tmp |= USB_PADCAL_TRANSP(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSN_Msk; + tmp |= USB_PADCAL_TRANSN(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRIM_Msk; + tmp |= USB_PADCAL_TRIM(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PADCAL.reg; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.STATUS.reg; +} + +static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->EXTREG.reg; +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const hw, + hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void +hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) + >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_status_bk_reg_t +hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_status_bk_reg_t +hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) +#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b) +#define hri_usbhost_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) +#define hri_usbhost_is_syncing(a, b) hri_usb_is_syncing(a, b) +#define hri_usbhost_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) +#define hri_usbhost_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) +#define hri_usbhost_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) +#define hri_usbhost_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) +#define hri_usbhost_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) +#define hri_usbhost_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) +#define hri_usbhost_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) +#define hri_usbhost_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) +#define hri_usbhost_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) +#define hri_usbhost_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) +#define hri_usbhost_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) +#define hri_usbhost_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) +#define hri_usbhost_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) +#define hri_usbhost_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) +#define hri_usbhost_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) +#define hri_usbhost_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) +#define hri_usbhost_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) +#define hri_usbhost_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) +#define hri_usbhost_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) +#define hri_usbhost_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) +#define hri_usbhost_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) +#define hri_usbhost_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) +#define hri_usbhost_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) +#define hri_usbhost_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) +#define hri_usbhost_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) +#define hri_usbhost_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) +#define hri_usbhost_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) +#define hri_usbhost_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) +#define hri_usbhost_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) +#define hri_usbhost_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) +#define hri_usbhost_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) +#define hri_usbhost_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) +#define hri_usbhost_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) +#define hri_usbhost_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) +#define hri_usbhost_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) +#define hri_usbhost_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) +#define hri_usbhost_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) +#define hri_usbhost_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) +#define hri_usbhost_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) +#define hri_usbhost_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) +#define hri_usbhost_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) +#define hri_usbhost_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) +#define hri_usbhost_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) +#define hri_usbhost_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) +#define hri_usbhost_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) +#define hri_usbhost_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) +#define hri_usbhost_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) +#define hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) +#define hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) +#define hri_usbhost_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) +#define hri_usbhost_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) +#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) +#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) +#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) +#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) +#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) +#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) +#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) +#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) +#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) +#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) +#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) +#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) +#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) +#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) +#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) +#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) +#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) +#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) +#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) +#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) +#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) +#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) +#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) +#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) +#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) +#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) +#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) +#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) +#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) +#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) +#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) +#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) +#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) +#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) +#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) +#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) +#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) +#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) +#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) +#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) +#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) +#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) +#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) +#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) +#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) +#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) +#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_USB_E54_H_INCLUDED */ +#endif /* _SAME54_USB_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_wdt_e54.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_wdt_e54.h new file mode 100644 index 0000000..3549e2f --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_wdt_e54.h @@ -0,0 +1,617 @@ +/** + * \file + * + * \brief SAM WDT + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_WDT_COMPONENT_ +#ifndef _HRI_WDT_E54_H_INCLUDED_ +#define _HRI_WDT_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_WDT_CRITICAL_SECTIONS) +#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define WDT_CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_wdt_syncbusy_reg_t; +typedef uint8_t hri_wdt_clear_reg_t; +typedef uint8_t hri_wdt_config_reg_t; +typedef uint8_t hri_wdt_ctrla_reg_t; +typedef uint8_t hri_wdt_ewctrl_reg_t; +typedef uint8_t hri_wdt_intenset_reg_t; +typedef uint8_t hri_wdt_intflag_reg_t; + +static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + while (((Wdt *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + return ((Wdt *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTFLAG.reg; +} + +static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + ((Wdt *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; +} + +static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; +} + +static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; + } else { + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; + } +} + +static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; +} + +static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENSET.reg = mask; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTENSET.reg; +} + +static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) +{ + ((Wdt *)hw)->INTENSET.reg = data; + ((Wdt *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Wdt *)hw)->SYNCBUSY.reg; +} + +static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ENABLE; + tmp |= value << WDT_CTRLA_ENABLE_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_WEN; + tmp |= value << WDT_CTRLA_WEN_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ALWAYSON; + tmp |= value << WDT_CTRLA_ALWAYSON_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) +{ + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + return ((Wdt *)hw)->CTRLA.reg; +} + +static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_PER_Msk; + tmp |= WDT_CONFIG_PER(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_WINDOW_Msk; + tmp |= WDT_CONFIG_WINDOW(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) +{ + return ((Wdt *)hw)->CONFIG.reg; +} + +static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; + tmp |= WDT_EWCTRL_EWOFFSET(data); + ((Wdt *)hw)->EWCTRL.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) +{ + return ((Wdt *)hw)->EWCTRL.reg; +} + +static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CLEAR.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR); + WDT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_WDT_E54_H_INCLUDED */ +#endif /* _SAME54_WDT_COMPONENT_ */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c new file mode 100644 index 0000000..c6750db --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c @@ -0,0 +1,134 @@ +#include +#include "spi_slave_dma_config.h" +#include "A1335.h" +#include "AS5048.h" + +/* Buffer length to transfer/receive */ +#define BUFFER_LEN (6) + +/* DMA channel Descriptor */ +extern DmacDescriptor _descriptor_section[DMAC_CH_NUM]; +extern DmacDescriptor _write_back_section[DMAC_CH_NUM]; + +/* IO descriptor for SPI master */ +struct io_descriptor *io_spi_master; + +volatile uint8_t spi_master_tx_complete = 0; +volatile uint8_t spi_master_rx_complete = 0; +volatile uint8_t cs_pulled_high = 0; +volatile uint8_t received_data_len = 0; + +static uint8_t rx_buffer[BUFFER_LEN] = {0}; +static uint8_t tx_buffer[BUFFER_LEN] = "Hell0"; + +static struct timer_task TIMER_0_task1; + +static void task1_cb(const struct timer_task *const timer_task) +{ + volatile int i = 0; + //a1335_State_Machine(&A1); + as5048a_State_Machine(&AS_1); + +} + +void TIMER_0_init(void) +{ + TIMER_0_task1.interval = 100; + TIMER_0_task1.cb = task1_cb; + TIMER_0_task1.mode = TIMER_TASK_REPEAT; + timer_add_task(&TIMER_0, &TIMER_0_task1); + timer_start(&TIMER_0); +} + + +/* DMA Transfer complete callback for SPI master TX */ +static void spi_master_tx_complete_cb(struct _dma_resource *resource) +{ + /* Transfer completed */ + delay_us(CONF_DELAY_US); + gpio_set_pin_level(SPI_CS, true); + spi_master_tx_complete = true; +} + +/* DMA Transfer complete callback for SPI master RX */ +static void spi_master_rx_complete_cb(struct _dma_resource *resource) +{ + /* Transfer completed */ + gpio_set_pin_level(SPI_CS, true); + spi_master_rx_complete = true; +} + +/* Start SPI master data transfer */ +void spi_master_tx(uint8_t *buffer, uint8_t length) +{ + //spi_m_dma_enable(&SPI_0); + gpio_set_pin_level(SPI_CS, false); + //io_write(io_spi_master, buffer, length); + spi_m_dma_transfer(&SPI_0,tx_buffer,rx_buffer,BUFFER_LEN); + +} + +/* Start SPI master data Reception from Slave */ +void spi_master_rx(uint8_t *buffer, uint8_t length) +{ + spi_m_dma_enable(&SPI_0); + gpio_set_pin_level(SPI_CS, false); + io_read(io_spi_master, buffer, length); +} + +/* SPI master IO and Callback Initialization */ +void spi_master_init(void) +{ + spi_m_dma_get_io_descriptor(&SPI_0, &io_spi_master); + spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_TX_DONE, spi_master_tx_complete_cb); + spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_RX_DONE, spi_master_rx_complete_cb); +} + + +int main(void) +{ + /* Initializes MCU, drivers and middleware */ + atmel_start_init(); + /* Initialize SPI master IO and Callback */ + //spi_master_init(); + //a1335_init(&SPI_1, &A1); + as5048a_init(&SPI_1, &AS_1); + TIMER_0_init(); + + //spi_m_dma_enable(&SPI_0); + + /* Start SPI Master data transfer using DMA */ + //spi_master_rx(rx_buffer, BUFFER_LEN); + //spi_master_tx(tx_buffer, BUFFER_LEN); + /* Start SPI Master data reception using DMA */ + //spi_master_rx(tx_buffer, BUFFER_LEN); + printf("Init Complete\n\r"); + /* Replace with your application code */ + while (1) { + //delay_ms(1000); + //tx_buffer[4] = tx_buffer[4]+1; + ////spi_master_rx(rx_buffer, BUFFER_LEN); + //spi_master_tx(tx_buffer, BUFFER_LEN); + // + //if (spi_master_tx_complete) { + //spi_master_rx_complete = false; + //printf("Master Sent DATA = "); + ///* Print Received data by SPI Master from SPI Slave on Console */ + //for (int i = 0; i < BUFFER_LEN; i++) { + //printf("%c", tx_buffer[i]); + //} + //printf("\n\r"); + // + //} + ///* Check for SPI Master is received data from SPI Slave */ + //if (spi_master_rx_complete) { + //spi_master_rx_complete = false; + //printf("Master Recieved DATA = "); + ///* Print Received data by SPI Master from SPI Slave on Console */ + //for (int i = 0; i < BUFFER_LEN; i++) { + //printf("%c", rx_buffer[i]); + //} + //printf("\n\r"); + //} + } +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/gcc/read.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/gcc/read.c new file mode 100644 index 0000000..90e4618 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/gcc/read.c @@ -0,0 +1,53 @@ +/** + * \file + * + * \brief STDIO redirection + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +int __attribute__((weak)) _read(int file, char *ptr, int len); /* Remove GCC compiler warning */ + +int __attribute__((weak)) _read(int file, char *ptr, int len) +{ + int n = 0; + + if (file != 0) { + return -1; + } + + n = stdio_io_read((uint8_t *)ptr, len); + if (n < 0) { + return -1; + } + + return n; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/gcc/write.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/gcc/write.c new file mode 100644 index 0000000..44fa815 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/gcc/write.c @@ -0,0 +1,53 @@ +/** + * \file + * + * \brief STDIO redirection + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +int __attribute__((weak)) _write(int file, char *ptr, int len); /* Remove GCC compiler warning */ + +int __attribute__((weak)) _write(int file, char *ptr, int len) +{ + int n = 0; + + if ((file != 1) && (file != 2) && (file != 3)) { + return -1; + } + + n = stdio_io_write((const uint8_t *)ptr, len); + if (n < 0) { + return -1; + } + + return n; +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/stdio_io.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/stdio_io.c new file mode 100644 index 0000000..7659f3d --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/stdio_io.c @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief STDIO redirection terminal + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** IO descriptor for STDIO access. */ +static struct io_descriptor *stdio_io = NULL; + +void stdio_io_init(struct io_descriptor *io) +{ +#if defined(__GNUC__) + /* Specify that stdout and stdin should not be buffered. */ + setbuf(stdout, NULL); + setbuf(stdin, NULL); + /* Note: Already the case in IAR's Normal DLIB default configuration + * and AVR GCC library: + * - printf() emits one character at a time. + * - getchar() requests only 1 byte to exit. + */ +#endif + stdio_io = io; +} + +void stdio_io_set_io(struct io_descriptor *io) +{ + stdio_io = io; +} + +int32_t stdio_io_read(uint8_t *buf, const int32_t len) +{ + if (stdio_io == NULL) { + return 0; + } + return io_read(stdio_io, buf, len); +} + +int32_t stdio_io_write(const uint8_t *buf, const int32_t len) +{ + if (stdio_io == NULL) { + return 0; + } + return io_write(stdio_io, buf, len); +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/stdio_io.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/stdio_io.h new file mode 100644 index 0000000..973adad --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/stdio_io.h @@ -0,0 +1,81 @@ +/** + * \file + * + * \brief STDIO redirection terminal + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _STDIO_IO_H_INCLUDED +#define _STDIO_IO_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * \brief Initialize STDIO access + * \param[in] io Pointer to IO descriptor, + * NULL to discard R/W without any error. + */ +void stdio_io_init(struct io_descriptor *io); + +/** + * \brief Change IO descriptor for terminal to R/W data + * \param[in] io Pointer to IO descriptor, + * NULL to discard R/W without any error. + */ +void stdio_io_set_io(struct io_descriptor *io); + +/** + * \brief Read through specified terminal + * \param[out] buf Pointer to buffer to place read data + * \param[in] len Data length in number of bytes + * \return status + * \retval >=0 number of bytes read + * \retval <0 error + */ +int32_t stdio_io_read(uint8_t *buf, const int32_t len); + +/** + * \brief Write through specified terminal + * \param[in] buf Pointer to buffer to place data to write + * \param[in] len Data length in number of bytes + * \return status + * \retval >=0 number of bytes read + * \retval <0 error + */ +int32_t stdio_io_write(const uint8_t *buf, const int32_t len); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _STDIO_IO_H_INCLUDED */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_start.c b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_start.c new file mode 100644 index 0000000..db8d362 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_start.c @@ -0,0 +1,23 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file or main.c + * to avoid loosing it when reconfiguring. + */ + +#include "atmel_start.h" +#include "stdio_start.h" + +void STDIO_REDIRECT_0_example(void) +{ + /* Print welcome message */ + printf("\r\nHello ATMEL World!\r\n"); +} + +void stdio_redirect_init(void) +{ + + usart_sync_enable(&TARGET_IO); + stdio_io_init(&TARGET_IO.io); +} diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_start.h b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_start.h new file mode 100644 index 0000000..bee5325 --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_start.h @@ -0,0 +1,31 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file or main.c + * to avoid loosing it when reconfiguring. + */ +#ifndef STDIO_MAIN_H +#define STDIO_MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include + +#include +#include + +void STDIO_REDIRECT_0_example(void); + +/** + * \brief Initialize STDIO Redirect + */ +void stdio_redirect_init(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STDIO_MAIN_H */ diff --git a/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_Test_Master.atsln b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_Test_Master.atsln new file mode 100644 index 0000000..4268b6e --- /dev/null +++ b/Examples/Angle Sensor Reading/Master_Slave_IF_Test_Master/Master_Slave_IF_Test_Master.atsln @@ -0,0 +1,22 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Atmel Studio Solution File, Format Version 11.00 +VisualStudioVersion = 14.0.23107.0 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "Master_Slave_IF_TestMaster", "Master_Slave_IF_TestMaster\Master_Slave_IF_TestMaster.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|ARM = Debug|ARM + Release|ARM = Release|ARM + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Master/Board_to_Board_Coms.atsln b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Master/Board_to_Board_Coms.atsln new file mode 100644 index 0000000..f0b63c3 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Master/Board_to_Board_Coms.atsln @@ -0,0 +1,22 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Atmel Studio Solution File, Format Version 11.00 +VisualStudioVersion = 14.0.23107.0 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "Board_to_Board_Coms", "Board_to_Board_Coms\Board_to_Board_Coms.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|ARM = Debug|ARM + Release|ARM = Release|ARM + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Master/Board_to_Board_Coms/.atmelstart/AtmelStart.env_conf b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Master/Board_to_Board_Coms/.atmelstart/AtmelStart.env_conf new file mode 100644 index 0000000..2033451 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Master/Board_to_Board_Coms/.atmelstart/AtmelStart.env_conf @@ -0,0 +1,6 @@ + + + + + + diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Master/Board_to_Board_Coms/.atmelstart/AtmelStart.gpdsc b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Master/Board_to_Board_Coms/.atmelstart/AtmelStart.gpdsc new file mode 100644 index 0000000..a72465d --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Master/Board_to_Board_Coms/.atmelstart/AtmelStart.gpdsc @@ -0,0 +1,236 @@ + + Atmel + My Project + Project generated by Atmel Start + http://start.atmel.com/ + + Initial version + + + Configuration Files generated by Atmel Start + + + + Atmel Start + + http://start.atmel.com/ + + + + + + + + + Dependency on CMSIS core and Device Startup components + + + + + + + + + + + + + + + + + + + + + + + + + Atmel Start Framework + #define ATMEL_START + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/.atmelstart/atmel_start_config.atstart b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/.atmelstart/atmel_start_config.atstart new file mode 100644 index 0000000..fe082ff --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/.atmelstart/atmel_start_config.atstart @@ -0,0 +1,723 @@ +format_version: '2' +name: My Project +versions: + api: '1.0' + backend: 1.8.580 + commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c + content: unknown + content_pack_name: unknown + format: '2' + frontend: 1.8.580 + packs_version_avr8: 1.0.1463 + packs_version_qtouch: unknown + packs_version_sam: 1.0.1726 + version_backend: 1.8.580 + version_frontend: '' +board: + identifier: SAMC21XplainedPro + device: SAMC21J18A-AN +details: null +application: null +middlewares: + STDIO_REDIRECT_0: + user_label: STDIO_REDIRECT_0 + configuration: {} + definition: Atmel:STDIO_redirect:0.0.1::STDIO_Redirect + functionality: STDIO_Redirect + api: STDIO:Redirect:IO + dependencies: + Target IO: TARGET_IO +drivers: + DMAC: + user_label: DMAC + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + functionality: System + api: HAL:HPL:DMAC + configuration: + dmac_beatsize_0: 8-bit bus transfer + dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_10: 8-bit bus transfer + dmac_beatsize_11: 8-bit bus transfer + dmac_beatsize_12: 8-bit bus transfer + dmac_beatsize_13: 8-bit bus transfer + dmac_beatsize_14: 8-bit bus transfer + dmac_beatsize_15: 8-bit bus transfer + dmac_beatsize_2: 8-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer + dmac_beatsize_4: 8-bit bus transfer + dmac_beatsize_5: 8-bit bus transfer + dmac_beatsize_6: 8-bit bus transfer + dmac_beatsize_7: 8-bit bus transfer + dmac_beatsize_8: 8-bit bus transfer + dmac_beatsize_9: 8-bit bus transfer + dmac_blockact_0: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_1: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_10: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_11: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_12: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_13: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_14: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_15: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_2: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_3: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_4: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_5: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_6: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_7: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_8: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_9: Channel will be disabled if it is the last block transfer in + the transaction + dmac_channel_0_settings: true + dmac_channel_10_settings: false + dmac_channel_11_settings: false + dmac_channel_12_settings: false + dmac_channel_13_settings: false + dmac_channel_14_settings: false + dmac_channel_15_settings: false + dmac_channel_1_settings: true + dmac_channel_2_settings: false + dmac_channel_3_settings: false + dmac_channel_4_settings: false + dmac_channel_5_settings: false + dmac_channel_6_settings: false + dmac_channel_7_settings: false + dmac_channel_8_settings: false + dmac_channel_9_settings: false + dmac_dbgrun: false + dmac_dqos: Background (no sensitive operation) + dmac_dstinc_0: true + dmac_dstinc_1: false + dmac_dstinc_10: false + dmac_dstinc_11: false + dmac_dstinc_12: false + dmac_dstinc_13: false + dmac_dstinc_14: false + dmac_dstinc_15: false + dmac_dstinc_2: false + dmac_dstinc_3: false + dmac_dstinc_4: false + dmac_dstinc_5: false + dmac_dstinc_6: false + dmac_dstinc_7: false + dmac_dstinc_8: false + dmac_dstinc_9: false + dmac_enable: true + dmac_enable_0: true + dmac_enable_1: true + dmac_enable_10: false + dmac_enable_11: false + dmac_enable_12: false + dmac_enable_13: false + dmac_enable_14: false + dmac_enable_15: false + dmac_enable_2: false + dmac_enable_3: false + dmac_enable_4: false + dmac_enable_5: false + dmac_enable_6: false + dmac_enable_7: false + dmac_enable_8: false + dmac_enable_9: false + dmac_evact_0: No action + dmac_evact_1: No action + dmac_evact_10: No action + dmac_evact_11: No action + dmac_evact_12: No action + dmac_evact_13: No action + dmac_evact_14: No action + dmac_evact_15: No action + dmac_evact_2: No action + dmac_evact_3: No action + dmac_evact_4: No action + dmac_evact_5: No action + dmac_evact_6: No action + dmac_evact_7: No action + dmac_evact_8: No action + dmac_evact_9: No action + dmac_evie_0: false + dmac_evie_1: false + dmac_evie_10: false + dmac_evie_11: false + dmac_evie_12: false + dmac_evie_13: false + dmac_evie_14: false + dmac_evie_15: false + dmac_evie_2: false + dmac_evie_3: false + dmac_evie_4: false + dmac_evie_5: false + dmac_evie_6: false + dmac_evie_7: false + dmac_evie_8: false + dmac_evie_9: false + dmac_evoe_0: false + dmac_evoe_1: false + dmac_evoe_10: false + dmac_evoe_11: false + dmac_evoe_12: false + dmac_evoe_13: false + dmac_evoe_14: false + dmac_evoe_15: false + dmac_evoe_2: false + dmac_evoe_3: false + dmac_evoe_4: false + dmac_evoe_5: false + dmac_evoe_6: false + dmac_evoe_7: false + dmac_evoe_8: false + dmac_evoe_9: false + dmac_evosel_0: Event generation disabled + dmac_evosel_1: Event generation disabled + dmac_evosel_10: Event generation disabled + dmac_evosel_11: Event generation disabled + dmac_evosel_12: Event generation disabled + dmac_evosel_13: Event generation disabled + dmac_evosel_14: Event generation disabled + dmac_evosel_15: Event generation disabled + dmac_evosel_2: Event generation disabled + dmac_evosel_3: Event generation disabled + dmac_evosel_4: Event generation disabled + dmac_evosel_5: Event generation disabled + dmac_evosel_6: Event generation disabled + dmac_evosel_7: Event generation disabled + dmac_evosel_8: Event generation disabled + dmac_evosel_9: Event generation disabled + dmac_fqos: Background (no sensitive operation) + dmac_lvl_0: Channel priority 0 + dmac_lvl_1: Channel priority 0 + dmac_lvl_10: Channel priority 0 + dmac_lvl_11: Channel priority 0 + dmac_lvl_12: Channel priority 0 + dmac_lvl_13: Channel priority 0 + dmac_lvl_14: Channel priority 0 + dmac_lvl_15: Channel priority 0 + dmac_lvl_2: Channel priority 0 + dmac_lvl_3: Channel priority 0 + dmac_lvl_4: Channel priority 0 + dmac_lvl_5: Channel priority 0 + dmac_lvl_6: Channel priority 0 + dmac_lvl_7: Channel priority 0 + dmac_lvl_8: Channel priority 0 + dmac_lvl_9: Channel priority 0 + dmac_lvlen0: true + dmac_lvlen1: true + dmac_lvlen2: false + dmac_lvlen3: false + dmac_lvlpri0: 0 + dmac_lvlpri1: 0 + dmac_lvlpri2: 0 + dmac_lvlpri3: 0 + dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 + dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 + dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 + dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 + dmac_runstdby_0: false + dmac_runstdby_1: false + dmac_runstdby_10: false + dmac_runstdby_11: false + dmac_runstdby_12: false + dmac_runstdby_13: false + dmac_runstdby_14: false + dmac_runstdby_15: false + dmac_runstdby_2: false + dmac_runstdby_3: false + dmac_runstdby_4: false + dmac_runstdby_5: false + dmac_runstdby_6: false + dmac_runstdby_7: false + dmac_runstdby_8: false + dmac_runstdby_9: false + dmac_srcinc_0: false + dmac_srcinc_1: true + dmac_srcinc_10: false + dmac_srcinc_11: false + dmac_srcinc_12: false + dmac_srcinc_13: false + dmac_srcinc_14: false + dmac_srcinc_15: false + dmac_srcinc_2: false + dmac_srcinc_3: false + dmac_srcinc_4: false + dmac_srcinc_5: false + dmac_srcinc_6: false + dmac_srcinc_7: false + dmac_srcinc_8: false + dmac_srcinc_9: false + dmac_stepsel_0: Step size settings apply to the destination address + dmac_stepsel_1: Step size settings apply to the source address + dmac_stepsel_10: Step size settings apply to the destination address + dmac_stepsel_11: Step size settings apply to the destination address + dmac_stepsel_12: Step size settings apply to the destination address + dmac_stepsel_13: Step size settings apply to the destination address + dmac_stepsel_14: Step size settings apply to the destination address + dmac_stepsel_15: Step size settings apply to the destination address + dmac_stepsel_2: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_4: Step size settings apply to the destination address + dmac_stepsel_5: Step size settings apply to the destination address + dmac_stepsel_6: Step size settings apply to the destination address + dmac_stepsel_7: Step size settings apply to the destination address + dmac_stepsel_8: Step size settings apply to the destination address + dmac_stepsel_9: Step size settings apply to the destination address + dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_trifsrc_0: SERCOM5 RX Trigger + dmac_trifsrc_1: SERCOM5 TX Trigger + dmac_trifsrc_10: Only software/event triggers + dmac_trifsrc_11: Only software/event triggers + dmac_trifsrc_12: Only software/event triggers + dmac_trifsrc_13: Only software/event triggers + dmac_trifsrc_14: Only software/event triggers + dmac_trifsrc_15: Only software/event triggers + dmac_trifsrc_2: Only software/event triggers + dmac_trifsrc_3: Only software/event triggers + dmac_trifsrc_4: Only software/event triggers + dmac_trifsrc_5: Only software/event triggers + dmac_trifsrc_6: Only software/event triggers + dmac_trifsrc_7: Only software/event triggers + dmac_trifsrc_8: Only software/event triggers + dmac_trifsrc_9: Only software/event triggers + dmac_trigact_0: One trigger required for each beat transfer + dmac_trigact_1: One trigger required for each beat transfer + dmac_trigact_10: One trigger required for each block transfer + dmac_trigact_11: One trigger required for each block transfer + dmac_trigact_12: One trigger required for each block transfer + dmac_trigact_13: One trigger required for each block transfer + dmac_trigact_14: One trigger required for each block transfer + dmac_trigact_15: One trigger required for each block transfer + dmac_trigact_2: One trigger required for each block transfer + dmac_trigact_3: One trigger required for each block transfer + dmac_trigact_4: One trigger required for each block transfer + dmac_trigact_5: One trigger required for each block transfer + dmac_trigact_6: One trigger required for each block transfer + dmac_trigact_7: One trigger required for each block transfer + dmac_trigact_8: One trigger required for each block transfer + dmac_trigact_9: One trigger required for each block transfer + dmac_wrbqos: Background (no sensitive operation) + optional_signals: [] + variant: null + clocks: + domain_group: null + GCLK: + user_label: GCLK + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + functionality: System + api: HAL:HPL:GCLK + configuration: + $input: 400000 + $input_id: External Crystal Oscillator 0.4-32MHz (XOSC) + RESERVED_InputFreq: 400000 + RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC) + _$freq_output_Generic clock generator 0: 24000000 + _$freq_output_Generic clock generator 1: 400000 + _$freq_output_Generic clock generator 2: 400000 + _$freq_output_Generic clock generator 3: 400000 + _$freq_output_Generic clock generator 4: 400000 + _$freq_output_Generic clock generator 5: 400000 + _$freq_output_Generic clock generator 6: 400000 + _$freq_output_Generic clock generator 7: 400000 + enable_gclk_gen_0: true + enable_gclk_gen_0__externalclock: 1000000 + enable_gclk_gen_1: false + enable_gclk_gen_1__externalclock: 1000000 + enable_gclk_gen_2: false + enable_gclk_gen_2__externalclock: 1000000 + enable_gclk_gen_3: false + enable_gclk_gen_3__externalclock: 1000000 + enable_gclk_gen_4: false + enable_gclk_gen_4__externalclock: 1000000 + enable_gclk_gen_5: false + enable_gclk_gen_5__externalclock: 1000000 + enable_gclk_gen_6: false + enable_gclk_gen_6__externalclock: 1000000 + enable_gclk_gen_7: false + enable_gclk_gen_7__externalclock: 1000000 + gclk_arch_gen_0_enable: true + gclk_arch_gen_0_idc: false + gclk_arch_gen_0_oe: false + gclk_arch_gen_0_oov: false + gclk_arch_gen_0_runstdby: false + gclk_arch_gen_1_enable: false + gclk_arch_gen_1_idc: false + gclk_arch_gen_1_oe: false + gclk_arch_gen_1_oov: false + gclk_arch_gen_1_runstdby: false + gclk_arch_gen_2_enable: false + gclk_arch_gen_2_idc: false + gclk_arch_gen_2_oe: false + gclk_arch_gen_2_oov: false + gclk_arch_gen_2_runstdby: false + gclk_arch_gen_3_enable: false + gclk_arch_gen_3_idc: false + gclk_arch_gen_3_oe: false + gclk_arch_gen_3_oov: false + gclk_arch_gen_3_runstdby: false + gclk_arch_gen_4_enable: false + gclk_arch_gen_4_idc: false + gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oov: false + gclk_arch_gen_4_runstdby: false + gclk_arch_gen_5_enable: false + gclk_arch_gen_5_idc: false + gclk_arch_gen_5_oe: false + gclk_arch_gen_5_oov: false + gclk_arch_gen_5_runstdby: false + gclk_arch_gen_6_enable: false + gclk_arch_gen_6_idc: false + gclk_arch_gen_6_oe: false + gclk_arch_gen_6_oov: false + gclk_arch_gen_6_runstdby: false + gclk_arch_gen_7_enable: false + gclk_arch_gen_7_idc: false + gclk_arch_gen_7_oe: false + gclk_arch_gen_7_oov: false + gclk_arch_gen_7_runstdby: false + gclk_gen_0_div: 1 + gclk_gen_0_div_sel: false + gclk_gen_0_oscillator: 48MHz Internal Oscillator (OSC48M) + gclk_gen_1_div: 1 + gclk_gen_1_div_sel: false + gclk_gen_1_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_2_div: 1 + gclk_gen_2_div_sel: false + gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_3_div: 1 + gclk_gen_3_div_sel: false + gclk_gen_3_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_4_div: 1 + gclk_gen_4_div_sel: false + gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_5_div: 1 + gclk_gen_5_div_sel: false + gclk_gen_5_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_6_div: 1 + gclk_gen_6_div_sel: false + gclk_gen_6_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_7_div: 1 + gclk_gen_7_div_sel: false + gclk_gen_7_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + optional_signals: [] + variant: null + clocks: + domain_group: null + MCLK: + user_label: MCLK + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + functionality: System + api: HAL:HPL:MCLK + configuration: + $input: 24000000 + $input_id: Generic clock generator 0 + RESERVED_InputFreq: 24000000 + RESERVED_InputFreq_id: Generic clock generator 0 + _$freq_output_CPU: 24000000 + cpu_clock_source: Generic clock generator 0 + cpu_div: '1' + enable_cpu_clock: true + nvm_wait_states: '0' + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: CPU + input: CPU + external: false + external_frequency: 0 + configuration: {} + OSC32KCTRL: + user_label: OSC32KCTRL + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + functionality: System + api: HAL:HPL:OSC32KCTRL + configuration: + $input: 32768 + $input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + RESERVED_InputFreq: 32768 + RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + _$freq_output_RTC source: 32768 + enable_osc32k: false + enable_osculp32k: true + enable_rtc_source: false + enable_xosc32k: false + osc32k_arch_calib: 0 + osc32k_arch_calib_enable: false + osc32k_arch_en1k: false + osc32k_arch_en32k: false + osc32k_arch_enable: false + osc32k_arch_ondemand: false + osc32k_arch_runstdby: false + osc32k_arch_startup: 92us + osculp32k_calib: 0 + osculp32k_calib_enable: false + rtc_1khz_selection: false + rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + xosc32k_arch_cfden: false + xosc32k_arch_cfdeo: false + xosc32k_arch_en1k: false + xosc32k_arch_en32k: false + xosc32k_arch_enable: false + xosc32k_arch_ondemand: true + xosc32k_arch_runstdby: false + xosc32k_arch_startup: 122us + xosc32k_arch_swben: false + xosc32k_arch_xtalen: true + optional_signals: [] + variant: null + clocks: + domain_group: null + OSCCTRL: + user_label: OSCCTRL + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + functionality: System + api: HAL:HPL:OSCCTRL + configuration: + $input: 32768 + $input_id: 32kHz External Crystal Oscillator (XOSC32K) + RESERVED_InputFreq: 32768 + RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K) + _$freq_output_48MHz Internal Oscillator (OSC48M): 24000000 + _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000 + _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 47998976 + enable_fdpll96m: false + enable_osc48m: true + enable_xosc: false + fdpll96m_arch_enable: false + fdpll96m_arch_filter: Default filter mode + fdpll96m_arch_lbypass: false + fdpll96m_arch_lpen: false + fdpll96m_arch_ltime: No time-out, automatic lock + fdpll96m_arch_ondemand: true + fdpll96m_arch_runstdby: false + fdpll96m_arch_wuf: false + fdpll96m_clock_div: 0 + fdpll96m_ldr: 1463 + fdpll96m_ldrfrac: 13 + fdpll96m_presc: '1' + fdpll96m_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + osc48m_arch_enable: true + osc48m_arch_ondemand: true + osc48m_arch_runstdby: false + osc48m_arch_startup: 21.333us + osc48m_div: 1 + xosc_arch_ampgc: false + xosc_arch_cfden: false + xosc_arch_cfdeo: false + xosc_arch_enable: false + xosc_arch_gain: 2MHz + xosc_arch_ondemand: true + xosc_arch_runstdby: false + xosc_arch_startup: 31us + xosc_arch_swben: false + xosc_arch_xtalen: false + xosc_frequency: 400000 + optional_signals: [] + variant: null + clocks: + domain_group: null + PORT: + user_label: PORT + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::PORT::driver_config_definition::PORT::HAL:HPL:PORT + functionality: System + api: HAL:HPL:PORT + configuration: + enable_port_input_event_0: false + enable_port_input_event_1: false + enable_port_input_event_2: false + enable_port_input_event_3: false + porta_event_action_0: Output register of pin will be set to level of event + porta_event_action_1: Output register of pin will be set to level of event + porta_event_action_2: Output register of pin will be set to level of event + porta_event_action_3: Output register of pin will be set to level of event + porta_event_pin_identifier_0: 0 + porta_event_pin_identifier_1: 0 + porta_event_pin_identifier_2: 0 + porta_event_pin_identifier_3: 0 + porta_input_event_enable_0: false + porta_input_event_enable_1: false + porta_input_event_enable_2: false + porta_input_event_enable_3: false + portb_event_action_0: Output register of pin will be set to level of event + portb_event_action_1: Output register of pin will be set to level of event + portb_event_action_2: Output register of pin will be set to level of event + portb_event_action_3: Output register of pin will be set to level of event + portb_event_pin_identifier_0: 0 + portb_event_pin_identifier_1: 0 + portb_event_pin_identifier_2: 0 + portb_event_pin_identifier_3: 0 + portb_input_event_enable_0: false + portb_input_event_enable_1: false + portb_input_event_enable_2: false + portb_input_event_enable_3: false + optional_signals: [] + variant: null + clocks: + domain_group: null + TARGET_IO: + user_label: TARGET_IO + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::SERCOM4::driver_config_definition::UART::HAL:Driver:USART.Sync + functionality: USART + api: HAL:Driver:USART_Sync + configuration: + usart_advanced: false + usart_arch_clock_mode: USART with internal clock + usart_arch_cloden: false + usart_arch_dbgstop: Keep running + usart_arch_dord: LSB is transmitted first + usart_arch_enc: No encoding + usart_arch_fractional: 0 + usart_arch_ibon: false + usart_arch_lin_slave_enable: Disable + usart_arch_runstdby: false + usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) + usart_arch_sampr: 16x arithmetic + usart_arch_sfde: false + usart_baud_rate: 19200 + usart_character_size: 8 bits + usart_parity: No parity + usart_rx_enable: true + usart_stop_bit: One stop bit + usart_tx_enable: true + optional_signals: [] + variant: + specification: TXPO=1, RXPO=3, CMODE=0 + required_signals: + - name: SERCOM4/PAD/2 + pad: PB10 + label: TX + - name: SERCOM4/PAD/3 + pad: PB11 + label: RX + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + SPI_0: + user_label: SPI_0 + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::SERCOM5::driver_config_definition::SPI.Slave::HAL:Driver:SPI.Slave.Sync + functionality: SPI + api: HAL:Driver:SPI_Slave_Sync + configuration: + spi_slave_advanced: true + spi_slave_arch_addr: 0 + spi_slave_arch_addrmask: 0 + spi_slave_arch_amode: Address mask + spi_slave_arch_amode_en: false + spi_slave_arch_cpha: Sample input on leading edge + spi_slave_arch_cpol: SCK is low when idle + spi_slave_arch_dbgstop: Keep running + spi_slave_arch_dord: MSB first + spi_slave_arch_ibon: In data stream + spi_slave_arch_ploaden: true + spi_slave_arch_runstdby: false + spi_slave_arch_ssde: true + spi_slave_character_size: 8 bits + spi_slave_rx_enable: true + optional_signals: [] + variant: + specification: TXPO=3, RXPO=2 + required_signals: + - name: SERCOM5/PAD/0 + pad: PB02 + label: MISO + - name: SERCOM5/PAD/1 + pad: PB03 + label: _SS + - name: SERCOM5/PAD/2 + pad: PB00 + label: MOSI + - name: SERCOM5/PAD/3 + pad: PB01 + label: SCK + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 +pads: + PB10: + name: PB10 + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB10 + mode: Peripheral IO + user_label: PB10 + configuration: null + PB11: + name: PB11 + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB11 + mode: Peripheral IO + user_label: PB11 + configuration: null + PB00: + name: PB00 + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB00 + mode: Digital input + user_label: PB00 + configuration: null + PB01: + name: PB01 + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB01 + mode: Digital output + user_label: PB01 + configuration: null + PB02: + name: PB02 + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB02 + mode: Digital output + user_label: PB02 + configuration: null + SPI_CS: + name: PB03 + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB03 + mode: Digital input + user_label: SPI_CS + configuration: null +toolchain_options: [] +static_files: [] diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave.componentinfo.xml b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave.componentinfo.xml new file mode 100644 index 0000000..cfec504 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave.componentinfo.xml @@ -0,0 +1,169 @@ + + + + + + + CMSIS + CORE + + + ARM + 5.1.2 + C:/Program Files (x86)\Atmel\Studio\7.0\Packs + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Documentation\Core\html\index.html + + doc + + + + CMSIS/Documentation/Core/html/index.html + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + + include + + + + CMSIS/Core/Include/ + + + + + CMSIS + C:/Program Files (x86)/Atmel/Studio/7.0/Packs/arm/CMSIS/5.4.0/ARM.CMSIS.pdsc + 5.4.0 + true + ARMv6_7_8-M Device + + + + Resolved + Fixed + true + + + + + Device + Startup + + + Atmel + 1.2.0 + C:/Program Files (x86)\Atmel\Studio\7.0\Packs + + + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMC21_DFP\1.2.176\samc21\include + + include + C + + + samc21/include + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMC21_DFP\1.2.176\samc21\include\sam.h + + header + C + 2Rk75rgdSdFbgPkrL7+Wow== + + samc21/include/sam.h + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMC21_DFP\1.2.176\samc21\templates\main.c + template + source + C Exe + xuIJiMguVw2V0blzqcbuXg== + + samc21/templates/main.c + Main file (.c) + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMC21_DFP\1.2.176\samc21\templates\main.cpp + template + source + C Exe + nU+WlKcYaWh0AWBBS+WVpA== + + samc21/templates/main.cpp + Main file (.cpp) + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMC21_DFP\1.2.176\samc21\gcc\system_samc21.c + config + source + GCC Exe + iZApSPlKT5sFShfs2MMw3A== + + samc21/gcc/system_samc21.c + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMC21_DFP\1.2.176\samc21\gcc\gcc\startup_samc21.c + config + source + GCC Exe + bpsG10hjzf37y3bP6vwBHA== + + samc21/gcc/gcc/startup_samc21.c + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMC21_DFP\1.2.176\samc21\gcc\gcc\samc21j18a_flash.ld + config + linkerScript + GCC Exe + yu/XahV2/buVFCoG75gBZA== + + samc21/gcc/gcc/samc21j18a_flash.ld + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMC21_DFP\1.2.176\samc21\gcc\gcc\samc21j18a_sram.ld + config + other + GCC Exe + jV8QDkxtU5u901fos+wrpg== + + samc21/gcc/gcc/samc21j18a_sram.ld + + + + + SAMC21_DFP + C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/SAMC21_DFP/1.2.176/Atmel.SAMC21_DFP.pdsc + 1.2.176 + true + ATSAMC21J18A + + + + Resolved + Fixed + true + + + \ No newline at end of file diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave.cproj b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave.cproj new file mode 100644 index 0000000..2deaef8 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave.cproj @@ -0,0 +1,835 @@ + + + + 2.0 + 7.0 + com.Atmel.ARMGCC.C + dce6c7e3-ee26-4d79-826b-08594b9ad897 + ATSAMC21J18A + none + Executable + C + $(MSBuildProjectName) + .elf + $(MSBuildProjectDirectory)\$(Configuration) + Board_to_Board_Coms_Slave + Board_to_Board_Coms_Slave + Board_to_Board_Coms_Slave + Native + true + false + true + true + + + true + + 2 + 0 + 0 + + + + + + + + + + + + + + gcc + .atmelstart\atmel_start_config.atstart + .atmelstart\AtmelStart.gpdsc + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + True + True + True + True + True + + + NDEBUG + + + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/divas + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + ../stdio_redirect + %24(PackRepoDir)\atmel\SAMC21_DFP\1.2.176\samc21\include + + + Optimize for size (-Os) + True + True + True + + + libm + + + + + %24(ProjectDir)\Device_Startup + + + True + -Tsamc21j18a_flash.ld + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/divas + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + ../stdio_redirect + %24(PackRepoDir)\atmel\SAMC21_DFP\1.2.176\samc21\include + + + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/divas + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + ../stdio_redirect + %24(PackRepoDir)\atmel\SAMC21_DFP\1.2.176\samc21\include + + + + + + + + + True + True + True + True + True + + + DEBUG + + + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/divas + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + ../stdio_redirect + %24(PackRepoDir)\atmel\SAMC21_DFP\1.2.176\samc21\include + + + Optimize debugging experience (-Og) + True + Maximum (-g3) + True + True + + + libm + + + + + %24(ProjectDir)\Device_Startup + + + True + -Tsamc21j18a_flash.ld + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/divas + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + ../stdio_redirect + %24(PackRepoDir)\atmel\SAMC21_DFP\1.2.176\samc21\include + + + Default (-g) + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/divas + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + ../stdio_redirect + %24(PackRepoDir)\atmel\SAMC21_DFP\1.2.176\samc21\include + + + Default (-Wa,-g) + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + + \ No newline at end of file diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Default.xml b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Default.xml new file mode 100644 index 0000000..dbc30fc --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Default.xml @@ -0,0 +1,475 @@ + + + + + + + DebugLevel + None + + + IncludePaths + NDEBUG + + + MiscellaneousSettings + -std=gnu99 + + + OptimizationLevel + Optimize for size (-Os) + + + SymbolDefines + NDEBUG + + + SymbolUndefines + + + + Verbose + False + + + WarningsAsErrors + False + + + armgcc.compiler.general.CLanguageExp + True + + + armgcc.compiler.general.ChangeDefaultCharTypeUnsigned + False + + + armgcc.compiler.general.ChangeDefaultBitFieldUnsigned + False + + + armgcc.compiler.general.processormode + + + + armgcc.compiler.preprocessor.DoNotSearchSystemDirectories + False + + + armgcc.compiler.preprocessor.PreprocessOnly + False + + + armgcc.compiler.symbols.Default + + + + armgcc.compiler.directories.DefaultIncludePath + True + + + armgcc.compiler.optimization.OtherFlags + + + + armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection + True + + + armgcc.compiler.optimization.PrepareDataForGarbageCollection + False + + + armgcc.compiler.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.compiler.optimization.EnableFastMath + False + + + armgcc.compiler.optimization.GeneratePositionIndependentCode + False + + + armgcc.compiler.optimization.EnableLongCalls + True + + + armgcc.compiler.optimization.OtherDebuggingFlags + + + + armgcc.compiler.optimization.GenerateGprofInformation + False + + + armgcc.compiler.optimization.GenerateProfInformation + False + + + armgcc.compiler.warnings.AllWarnings + True + + + armgcc.compiler.warnings.ExtraWarnings + False + + + armgcc.compiler.warnings.Undefined + False + + + armgcc.compiler.warnings.CheckSyntaxOnly + False + + + armgcc.compiler.warnings.Pedantic + False + + + armgcc.compiler.warnings.PedanticWarningsAsErrors + False + + + armgcc.compiler.warnings.InhibitAllWarnings + False + + + armgcc.compiler.miscellaneous.Device + True + + + armgcc.compiler.miscellaneous.CompileOnly + True + + + armgcc.compiler.miscellaneous.SupportAnsiPrograms + False + + + armgcc.compiler.miscellaneous.MakeFileDependent + True + + + + + Libraries + libm + + + LibrarySearchPath + $(ProjectDir)\Device_Startup + + + MiscellaneousSettings + -Tsamc21j18a_flash.ld + + + armgcc.linker.general.DoNotUseStandardStartFiles + False + + + armgcc.linker.general.DoNotUseDefaultLibraries + False + + + armgcc.linker.general.NoStartupOrDefaultLibs + False + + + armgcc.linker.general.OmitAllSymbolInformation + False + + + armgcc.linker.general.NoSharedLibraries + False + + + armgcc.linker.general.GenerateMAPFile + True + + + armgcc.linker.general.UseNewlibNano + False + + + armgcc.linker.general.AdditionalSpecs + None + + + armgcc.linker.optimization.GarbageCollectUnusedSections + True + + + armgcc.linker.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.linker.optimization.EnableFastMath + False + + + armgcc.linker.optimization.GeneratePositionIndependentCode + False + + + armgcc.linker.memorysettings.Flash + + + + armgcc.linker.memorysettings.Sram + + + + armgcc.linker.memorysettings.ExternalRAM + + + + armgcc.linker.miscellaneous.OtherOptions + + + + armgcc.linker.miscellaneous.OtherObjects + + + + Release + + + + + DebugLevel + Maximum (-g3) + + + IncludePaths + DEBUG + + + MiscellaneousSettings + -std=gnu99 + + + OptimizationLevel + Optimize debugging experience (-Og) + + + SymbolDefines + DEBUG + + + SymbolUndefines + + + + Verbose + False + + + WarningsAsErrors + False + + + armgcc.compiler.general.CLanguageExp + True + + + armgcc.compiler.general.ChangeDefaultCharTypeUnsigned + False + + + armgcc.compiler.general.ChangeDefaultBitFieldUnsigned + False + + + armgcc.compiler.general.processormode + + + + armgcc.compiler.preprocessor.DoNotSearchSystemDirectories + False + + + armgcc.compiler.preprocessor.PreprocessOnly + False + + + armgcc.compiler.symbols.Default + + + + armgcc.compiler.directories.DefaultIncludePath + True + + + armgcc.compiler.optimization.OtherFlags + + + + armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection + True + + + armgcc.compiler.optimization.PrepareDataForGarbageCollection + False + + + armgcc.compiler.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.compiler.optimization.EnableFastMath + False + + + armgcc.compiler.optimization.GeneratePositionIndependentCode + False + + + armgcc.compiler.optimization.EnableLongCalls + True + + + armgcc.compiler.optimization.OtherDebuggingFlags + + + + armgcc.compiler.optimization.GenerateGprofInformation + False + + + armgcc.compiler.optimization.GenerateProfInformation + False + + + armgcc.compiler.warnings.AllWarnings + True + + + armgcc.compiler.warnings.ExtraWarnings + False + + + armgcc.compiler.warnings.Undefined + False + + + armgcc.compiler.warnings.CheckSyntaxOnly + False + + + armgcc.compiler.warnings.Pedantic + False + + + armgcc.compiler.warnings.PedanticWarningsAsErrors + False + + + armgcc.compiler.warnings.InhibitAllWarnings + False + + + armgcc.compiler.miscellaneous.Device + True + + + armgcc.compiler.miscellaneous.CompileOnly + True + + + armgcc.compiler.miscellaneous.SupportAnsiPrograms + False + + + armgcc.compiler.miscellaneous.MakeFileDependent + True + + + + + Libraries + libm + + + LibrarySearchPath + $(ProjectDir)\Device_Startup + + + MiscellaneousSettings + -Tsamc21j18a_flash.ld + + + armgcc.linker.general.DoNotUseStandardStartFiles + False + + + armgcc.linker.general.DoNotUseDefaultLibraries + False + + + armgcc.linker.general.NoStartupOrDefaultLibs + False + + + armgcc.linker.general.OmitAllSymbolInformation + False + + + armgcc.linker.general.NoSharedLibraries + False + + + armgcc.linker.general.GenerateMAPFile + True + + + armgcc.linker.general.UseNewlibNano + False + + + armgcc.linker.general.AdditionalSpecs + None + + + armgcc.linker.optimization.GarbageCollectUnusedSections + True + + + armgcc.linker.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.linker.optimization.EnableFastMath + False + + + armgcc.linker.optimization.GeneratePositionIndependentCode + False + + + armgcc.linker.memorysettings.Flash + + + + armgcc.linker.memorysettings.Sram + + + + armgcc.linker.memorysettings.ExternalRAM + + + + armgcc.linker.miscellaneous.OtherOptions + + + + armgcc.linker.miscellaneous.OtherObjects + + + + Debug + + + \ No newline at end of file diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Device_Startup/samc21j18a_flash.ld b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Device_Startup/samc21j18a_flash.ld new file mode 100644 index 0000000..85a624a --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Device_Startup/samc21j18a_flash.ld @@ -0,0 +1,143 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMC21J18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Device_Startup/samc21j18a_sram.ld b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Device_Startup/samc21j18a_sram.ld new file mode 100644 index 0000000..7ba753b --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Device_Startup/samc21j18a_sram.ld @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMC21J18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Device_Startup/startup_samc21.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Device_Startup/startup_samc21.c new file mode 100644 index 0000000..d88eb29 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Device_Startup/startup_samc21.c @@ -0,0 +1,271 @@ +/** + * \file + * + * \brief gcc starttup file for SAMC21 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "samc21.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M0+ core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* MCLK, OSC32KCTRL, OSCCTRL, PAC, PM, SUPC, TAL */ +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_TSENS +void TSENS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_SERCOM4 +void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SERCOM5 +void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_CAN0 +void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_CAN1 +void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_TCC1 +void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TCC2 +void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_ADC0 +void ADC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_ADC1 +void ADC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_AC +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_DAC +void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SDADC +void SDADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_PTC +void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pvReservedM12 = (void*) (0UL), /* Reserved */ + .pvReservedM11 = (void*) (0UL), /* Reserved */ + .pvReservedM10 = (void*) (0UL), /* Reserved */ + .pvReservedM9 = (void*) (0UL), /* Reserved */ + .pvReservedM8 = (void*) (0UL), /* Reserved */ + .pvReservedM7 = (void*) (0UL), /* Reserved */ + .pvReservedM6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pvReservedM4 = (void*) (0UL), /* Reserved */ + .pvReservedM3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSYSTEM_Handler = (void*) SYSTEM_Handler, /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 1 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-Time Counter */ + .pfnEIC_Handler = (void*) EIC_Handler, /* 3 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 4 Frequency Meter */ +#ifdef ID_TSENS + .pfnTSENS_Handler = (void*) TSENS_Handler, /* 5 Temperature Sensor */ +#else + .pvReserved5 = (void*) (0UL), /* 5 Reserved */ +#endif + .pfnNVMCTRL_Handler = (void*) NVMCTRL_Handler, /* 6 Non-Volatile Memory Controller */ + .pfnDMAC_Handler = (void*) DMAC_Handler, /* 7 Direct Memory Access Controller */ + .pfnEVSYS_Handler = (void*) EVSYS_Handler, /* 8 Event System Interface */ + .pfnSERCOM0_Handler = (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ + .pfnSERCOM1_Handler = (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ + .pfnSERCOM2_Handler = (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ + .pfnSERCOM3_Handler = (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ +#ifdef ID_SERCOM4 + .pfnSERCOM4_Handler = (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ +#else + .pvReserved13 = (void*) (0UL), /* 13 Reserved */ +#endif +#ifdef ID_SERCOM5 + .pfnSERCOM5_Handler = (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ +#else + .pvReserved14 = (void*) (0UL), /* 14 Reserved */ +#endif +#ifdef ID_CAN0 + .pfnCAN0_Handler = (void*) CAN0_Handler, /* 15 Control Area Network 0 */ +#else + .pvReserved15 = (void*) (0UL), /* 15 Reserved */ +#endif +#ifdef ID_CAN1 + .pfnCAN1_Handler = (void*) CAN1_Handler, /* 16 Control Area Network 1 */ +#else + .pvReserved16 = (void*) (0UL), /* 16 Reserved */ +#endif + .pfnTCC0_Handler = (void*) TCC0_Handler, /* 17 Timer Counter Control 0 */ +#ifdef ID_TCC1 + .pfnTCC1_Handler = (void*) TCC1_Handler, /* 18 Timer Counter Control 1 */ +#else + .pvReserved18 = (void*) (0UL), /* 18 Reserved */ +#endif +#ifdef ID_TCC2 + .pfnTCC2_Handler = (void*) TCC2_Handler, /* 19 Timer Counter Control 2 */ +#else + .pvReserved19 = (void*) (0UL), /* 19 Reserved */ +#endif + .pfnTC0_Handler = (void*) TC0_Handler, /* 20 Basic Timer Counter 0 */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 21 Basic Timer Counter 1 */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 22 Basic Timer Counter 2 */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 23 Basic Timer Counter 3 */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 24 Basic Timer Counter 4 */ +#ifdef ID_ADC0 + .pfnADC0_Handler = (void*) ADC0_Handler, /* 25 Analog Digital Converter 0 */ +#else + .pvReserved25 = (void*) (0UL), /* 25 Reserved */ +#endif +#ifdef ID_ADC1 + .pfnADC1_Handler = (void*) ADC1_Handler, /* 26 Analog Digital Converter 1 */ +#else + .pvReserved26 = (void*) (0UL), /* 26 Reserved */ +#endif +#ifdef ID_AC + .pfnAC_Handler = (void*) AC_Handler, /* 27 Analog Comparators */ +#else + .pvReserved27 = (void*) (0UL), /* 27 Reserved */ +#endif +#ifdef ID_DAC + .pfnDAC_Handler = (void*) DAC_Handler, /* 28 Digital Analog Converter */ +#else + .pvReserved28 = (void*) (0UL), /* 28 Reserved */ +#endif +#ifdef ID_SDADC + .pfnSDADC_Handler = (void*) SDADC_Handler, /* 29 Sigma-Delta Analog Digital Converter */ +#else + .pvReserved29 = (void*) (0UL), /* 29 Reserved */ +#endif +#ifdef ID_PTC + .pfnPTC_Handler = (void*) PTC_Handler /* 30 Peripheral Touch Controller */ +#else + .pvReserved30 = (void*) (0UL) /* 30 Reserved */ +#endif +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Device_Startup/system_samc21.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Device_Startup/system_samc21.c new file mode 100644 index 0000000..06e7f02 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Device_Startup/system_samc21.c @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "samc21.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (4000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/atmel_start.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/atmel_start.c new file mode 100644 index 0000000..12895d0 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/atmel_start.c @@ -0,0 +1,10 @@ +#include + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void) +{ + system_init(); + stdio_redirect_init(); +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/atmel_start.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/atmel_start.h new file mode 100644 index 0000000..ace35cf --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/atmel_start.h @@ -0,0 +1,19 @@ +#ifndef ATMEL_START_H_INCLUDED +#define ATMEL_START_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "driver_init.h" +#include "stdio_start.h" + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/atmel_start_pins.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/atmel_start_pins.h new file mode 100644 index 0000000..e793bd7 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/atmel_start_pins.h @@ -0,0 +1,32 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef ATMEL_START_PINS_H_INCLUDED +#define ATMEL_START_PINS_H_INCLUDED + +#include + +// SAMC21 has 9 pin functions + +#define GPIO_PIN_FUNCTION_A 0 +#define GPIO_PIN_FUNCTION_B 1 +#define GPIO_PIN_FUNCTION_C 2 +#define GPIO_PIN_FUNCTION_D 3 +#define GPIO_PIN_FUNCTION_E 4 +#define GPIO_PIN_FUNCTION_F 5 +#define GPIO_PIN_FUNCTION_G 6 +#define GPIO_PIN_FUNCTION_H 7 +#define GPIO_PIN_FUNCTION_I 8 + +#define PB00 GPIO(GPIO_PORTB, 0) +#define PB01 GPIO(GPIO_PORTB, 1) +#define PB02 GPIO(GPIO_PORTB, 2) +#define SPI_CS GPIO(GPIO_PORTB, 3) +#define PB10 GPIO(GPIO_PORTB, 10) +#define PB11 GPIO(GPIO_PORTB, 11) + +#endif // ATMEL_START_PINS_H_INCLUDED diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/RTE_Components.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/RTE_Components.h new file mode 100644 index 0000000..55002b7 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/RTE_Components.h @@ -0,0 +1,54 @@ + /** + * \file + * + * \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME) + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \acme_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \acme_license_stop + * + * Project: Board_to_Board_Coms_Slave + * Target: ATSAMC21J18A + * + **/ + + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +#define ATMEL_START + +#endif /* RTE_COMPONENTS_H */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_divas_config.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_divas_config.h new file mode 100644 index 0000000..ff6392e --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_divas_config.h @@ -0,0 +1,13 @@ + +// Advanced settings + +// Disable Leading Zero Optimization +// Leading zero optimization makes division faster but cycles to take varias according to input values +// With leading zero optimization the clock cycles are 2-8 for 16-bit and 2-16 for 32-bit +// Disable leading zero optimization will force the division to take a fixed time of maximum number of cycles +// divas_arch_dlz +#ifndef CONF_DIVAS_DLZ +#define CONF_DIVAS_DLZ 0 +#endif + +// diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_dmac_config.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_dmac_config.h new file mode 100644 index 0000000..6a79400 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_dmac_config.h @@ -0,0 +1,3474 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 1 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 1 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif + +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 1 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif + +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 0 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif + +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 0 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif + +// Data Transfer Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the data transfer operation +// dmac_dqos +#ifndef CONF_DMAC_DQOS +#define CONF_DMAC_DQOS 0 +#endif + +// Fetch Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the fetch operation +// dmac_fqos +#ifndef CONF_DMAC_FQOS +#define CONF_DMAC_FQOS 0 +#endif + +// Write-Back Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the write-back operation +// dmac_wrbqos +#ifndef CONF_DMAC_WRBQOS +#define CONF_DMAC_WRBQOS 0 +#endif + +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 1 +#endif + +// Channel Enable +// Indicates whether channel 0 is enabled or not +// dmac_enable_0 +#ifndef CONF_DMAC_ENABLE_0 +#define CONF_DMAC_ENABLE_0 1 +#endif + +// Channel Run in Standby +// Indicates whether channel 0 is running in standby mode or not +// dmac_runstdby_0 +#ifndef CONF_DMAC_RUNSTDBY_0 +#define CONF_DMAC_RUNSTDBY_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 2 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 12 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 1 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 1 +#endif + +// Channel Enable +// Indicates whether channel 1 is enabled or not +// dmac_enable_1 +#ifndef CONF_DMAC_ENABLE_1 +#define CONF_DMAC_ENABLE_1 1 +#endif + +// Channel Run in Standby +// Indicates whether channel 1 is running in standby mode or not +// dmac_runstdby_1 +#ifndef CONF_DMAC_RUNSTDBY_1 +#define CONF_DMAC_RUNSTDBY_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 2 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 13 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 1 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 1 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 2 is enabled or not +// dmac_enable_2 +#ifndef CONF_DMAC_ENABLE_2 +#define CONF_DMAC_ENABLE_2 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 2 is running in standby mode or not +// dmac_runstdby_2 +#ifndef CONF_DMAC_RUNSTDBY_2 +#define CONF_DMAC_RUNSTDBY_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 3 is enabled or not +// dmac_enable_3 +#ifndef CONF_DMAC_ENABLE_3 +#define CONF_DMAC_ENABLE_3 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 3 is running in standby mode or not +// dmac_runstdby_3 +#ifndef CONF_DMAC_RUNSTDBY_3 +#define CONF_DMAC_RUNSTDBY_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 4 is enabled or not +// dmac_enable_4 +#ifndef CONF_DMAC_ENABLE_4 +#define CONF_DMAC_ENABLE_4 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 4 is running in standby mode or not +// dmac_runstdby_4 +#ifndef CONF_DMAC_RUNSTDBY_4 +#define CONF_DMAC_RUNSTDBY_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 5 is enabled or not +// dmac_enable_5 +#ifndef CONF_DMAC_ENABLE_5 +#define CONF_DMAC_ENABLE_5 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 5 is running in standby mode or not +// dmac_runstdby_5 +#ifndef CONF_DMAC_RUNSTDBY_5 +#define CONF_DMAC_RUNSTDBY_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 6 is enabled or not +// dmac_enable_6 +#ifndef CONF_DMAC_ENABLE_6 +#define CONF_DMAC_ENABLE_6 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 6 is running in standby mode or not +// dmac_runstdby_6 +#ifndef CONF_DMAC_RUNSTDBY_6 +#define CONF_DMAC_RUNSTDBY_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 7 is enabled or not +// dmac_enable_7 +#ifndef CONF_DMAC_ENABLE_7 +#define CONF_DMAC_ENABLE_7 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 7 is running in standby mode or not +// dmac_runstdby_7 +#ifndef CONF_DMAC_RUNSTDBY_7 +#define CONF_DMAC_RUNSTDBY_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 8 is enabled or not +// dmac_enable_8 +#ifndef CONF_DMAC_ENABLE_8 +#define CONF_DMAC_ENABLE_8 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 8 is running in standby mode or not +// dmac_runstdby_8 +#ifndef CONF_DMAC_RUNSTDBY_8 +#define CONF_DMAC_RUNSTDBY_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 9 is enabled or not +// dmac_enable_9 +#ifndef CONF_DMAC_ENABLE_9 +#define CONF_DMAC_ENABLE_9 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 9 is running in standby mode or not +// dmac_runstdby_9 +#ifndef CONF_DMAC_RUNSTDBY_9 +#define CONF_DMAC_RUNSTDBY_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 10 is enabled or not +// dmac_enable_10 +#ifndef CONF_DMAC_ENABLE_10 +#define CONF_DMAC_ENABLE_10 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 10 is running in standby mode or not +// dmac_runstdby_10 +#ifndef CONF_DMAC_RUNSTDBY_10 +#define CONF_DMAC_RUNSTDBY_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 11 is enabled or not +// dmac_enable_11 +#ifndef CONF_DMAC_ENABLE_11 +#define CONF_DMAC_ENABLE_11 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 11 is running in standby mode or not +// dmac_runstdby_11 +#ifndef CONF_DMAC_RUNSTDBY_11 +#define CONF_DMAC_RUNSTDBY_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 12 is enabled or not +// dmac_enable_12 +#ifndef CONF_DMAC_ENABLE_12 +#define CONF_DMAC_ENABLE_12 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 12 is running in standby mode or not +// dmac_runstdby_12 +#ifndef CONF_DMAC_RUNSTDBY_12 +#define CONF_DMAC_RUNSTDBY_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 13 is enabled or not +// dmac_enable_13 +#ifndef CONF_DMAC_ENABLE_13 +#define CONF_DMAC_ENABLE_13 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 13 is running in standby mode or not +// dmac_runstdby_13 +#ifndef CONF_DMAC_RUNSTDBY_13 +#define CONF_DMAC_RUNSTDBY_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 14 is enabled or not +// dmac_enable_14 +#ifndef CONF_DMAC_ENABLE_14 +#define CONF_DMAC_ENABLE_14 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 14 is running in standby mode or not +// dmac_runstdby_14 +#ifndef CONF_DMAC_RUNSTDBY_14 +#define CONF_DMAC_RUNSTDBY_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 15 is enabled or not +// dmac_enable_15 +#ifndef CONF_DMAC_ENABLE_15 +#define CONF_DMAC_ENABLE_15 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 15 is running in standby mode or not +// dmac_runstdby_15 +#ifndef CONF_DMAC_RUNSTDBY_15 +#define CONF_DMAC_RUNSTDBY_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_gclk_config.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_gclk_config.h new file mode 100644 index 0000000..460b7eb --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_gclk_config.h @@ -0,0 +1,608 @@ +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 0 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SOURCE +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_OSC48M +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_runstdby +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif +// +// + +// Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 1 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SOURCE +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_runstdby +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif +// +// + +// Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 2 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SOURCE +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_runstdby +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 1 +#endif +// +// + +// Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 3 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SOURCE +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_runstdby +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif +// +// + +// Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 4 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SOURCE +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_runstdby +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif +// +// + +// Generic clock generator 5 configuration +// Indicates whether generic clock 5 configuration is enabled or not +// enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 5 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 5 +// gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SOURCE +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_5_runstdby +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> +// gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 1 +#endif +// +// + +// Generic clock generator 6 configuration +// Indicates whether generic clock 6 configuration is enabled or not +// enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 6 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 6 +// gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SOURCE +#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_6_runstdby +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> +// gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 1 +#endif +// +// + +// Generic clock generator 7 configuration +// Indicates whether generic clock 7 configuration is enabled or not +// enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 7 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 7 +// gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SOURCE +#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_7_runstdby +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> +// gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_mclk_config.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_mclk_config.h new file mode 100644 index 0000000..1e351fa --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_mclk_config.h @@ -0,0 +1,72 @@ +/* Auto-generated config file hpl_mclk_config.h */ +#ifndef HPL_MCLK_CONFIG_H +#define HPL_MCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Basic settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// CPU Clock Division Factor +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for CPU clock +// cpu_div +#ifndef CONF_MCLK_CPUDIV +#define CONF_MCLK_CPUDIV MCLK_CPUDIV_CPUDIV_DIV1_Val +#endif + +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 0 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_MCLK_CONFIG_H diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_osc32kctrl_config.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_osc32kctrl_config.h new file mode 100644 index 0000000..e9bfb5e --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_osc32kctrl_config.h @@ -0,0 +1,229 @@ +/* Auto-generated config file hpl_osc32kctrl_config.h */ +#ifndef HPL_OSC32KCTRL_CONFIG_H +#define HPL_OSC32KCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RTC Source configuration +// enable_rtc_source +#ifndef CONF_RTCCTRL_CONFIG +#define CONF_RTCCTRL_CONFIG 0 +#endif + +// RTC source control +// RTC Clock Source Selection +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// This defines the clock source for RTC +// rtc_source_oscillator +#ifndef CONF_RTCCTRL_SRC +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// Use 1 kHz output +// rtc_1khz_selection +#ifndef CONF_RTCCTRL_1KHZ + +#define CONF_RTCCTRL_1KHZ 0 + +#endif + +#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) +#else +#error unexpected CONF_RTCCTRL_SRC +#endif + +// +// +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 0 +#endif + +// 32kHz External Crystal Oscillator Control +// Oscillator enable +// Indicates whether 32kHz External Crystal Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>122us +// <0x1=>1068us +// <0x2=>62592us +// <0x3=>125092us +// <0x4=>500092us +// <0x5=>1000092us +// <0x6=>2000092us +// <0x7=>4000092us// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc32k_arch_swben +#ifndef CONF_XOSC32K_SWBEN +#define CONF_XOSC32K_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc32k_arch_cfden +#ifndef CONF_XOSC32K_CFDEN +#define CONF_XOSC32K_CFDEN 0 +#endif + +// Clock Failure Detector Event Out +// Indicates whether Clock Failure Detector Event Out is enabled or not +// xosc32k_arch_cfdeo +#ifndef CONF_XOSC32K_CFDEO +#define CONF_XOSC32K_CFDEO 0 +#endif + +// Crystal connected to XIN32/XOUT32 Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 1 +#endif + +// +// +// 32kHz Internal Oscillator Configuration +// Indicates whether configuration for OSC32K is enabled or not +// enable_osc32k +#ifndef CONF_OSC32K_CONFIG +#define CONF_OSC32K_CONFIG 0 +#endif + +// 32kHz Internal Oscillator Control +// Enable +// Indicates whether 32kHz Internal Oscillator is enabled or not +// osc32k_arch_enable +#ifndef CONF_OSC32K_ENABLE +#define CONF_OSC32K_ENABLE 0 +#endif + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osc32k_arch_calib_enable +#ifndef CONF_OSC32K_CALIB_ENABLE +#define CONF_OSC32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x7F> +// osc32k_arch_calib +#ifndef CONF_OSC32K_CALIB +#define CONF_OSC32K_CALIB 0x0 +#endif + +// Start-Up Time +// <0x0=>92us +// <0x1=>122us +// <0x2=>183us +// <0x3=>305us +// <0x4=>549us +// <0x5=>1038us +// <0x6=>2014us +// <0x7=>3967us +// osc32k_arch_startup +#ifndef CONF_OSC32K_STARTUP +#define CONF_OSC32K_STARTUP 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// osc32k_arch_ondemand +#ifndef CONF_OSC32K_ONDEMAND +#define CONF_OSC32K_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// osc32k_arch_runstdby +#ifndef CONF_OSC32K_RUNSTDBY +#define CONF_OSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// osc32k_arch_en1k +#ifndef CONF_OSC32K_EN1K +#define CONF_OSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// osc32k_arch_en32k +#ifndef CONF_OSC32K_EN32K +#define CONF_OSC32K_EN32K 0 +#endif +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator Control + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osculp32k_calib_enable +#ifndef CONF_OSCULP32K_CALIB_ENABLE +#define CONF_OSCULP32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x1F> +// osculp32k_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_oscctrl_config.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_oscctrl_config.h new file mode 100644 index 0000000..494aaee --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_oscctrl_config.h @@ -0,0 +1,308 @@ +/* Auto-generated config file hpl_oscctrl_config.h */ +#ifndef HPL_OSCCTRL_CONFIG_H +#define HPL_OSCCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC is enabled or not +// enable_xosc +#ifndef CONF_XOSC_CONFIG +#define CONF_XOSC_CONFIG 0 +#endif + +// Frequency <400000-32000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC_FREQUENCY 400000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc_arch_enable +#ifndef CONF_XOSC_ENABLE +#define CONF_XOSC_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc_arch_startup +#ifndef CONF_XOSC_STARTUP +#define CONF_XOSC_STARTUP 0x0 +#endif + +// Automatic Amplitude Gain Control +// Indicates whether Automatic Amplitude Gain Control is enabled or not +// xosc_arch_ampgc +#ifndef CONF_XOSC_AMPGC +#define CONF_XOSC_AMPGC 0 +#endif + +// External Multipurpose Crystal Oscillator Gain +// <0x0=>2MHz +// <0x1=>4MHz +// <0x2=>8MHz +// <0x3=>16MHz +// <0x4=>30MHz +// xosc_arch_gain +#ifndef CONF_XOSC_GAIN +#define CONF_XOSC_GAIN 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc_arch_ondemand +#ifndef CONF_XOSC_ONDEMAND +#define CONF_XOSC_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc_arch_runstdby +#ifndef CONF_XOSC_RUNSTDBY +#define CONF_XOSC_RUNSTDBY 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc_arch_swben +#ifndef CONF_XOSC_SWBEN +#define CONF_XOSC_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc_arch_cfden +#ifndef CONF_XOSC_CFDEN +#define CONF_XOSC_CFDEN 0 +#endif + +// Clock Failure Detector Event Out +// Indicates whether Clock Failure Detector Event Out is enabled or not +// xosc_arch_cfdeo +#ifndef CONF_XOSC_CFDEO +#define CONF_XOSC_CFDEO 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc_arch_xtalen +#ifndef CONF_XOSC_XTALEN +#define CONF_XOSC_XTALEN 0 +#endif +// +// + +// 48MHz Internal Oscillator Configuration +// Indicates whether configuration for OSC48M is enabled or not +// enable_osc48m +#ifndef CONF_OSC48M_CONFIG +#define CONF_OSC48M_CONFIG 1 +#endif + +// 48MHz Internal Oscillator Control +// Enable +// Indicates whether 48MHz Internal Oscillator is enabled or not +// osc48m_arch_enable +#ifndef CONF_OSC48M_ENABLE +#define CONF_OSC48M_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// osc48m_arch_ondemand +#ifndef CONF_OSC48M_ONDEMAND +#define CONF_OSC48M_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// osc48m_arch_runstdby +#ifndef CONF_OSC48M_RUNSTDBY +#define CONF_OSC48M_RUNSTDBY 0 +#endif + +// Oscillator Division Selection <0x0-0xF> +// Indicates OSC48M division value +// osc48m_div +#ifndef CONF_OSC48M_DIV +#define CONF_OSC48M_DIV 1 +#endif + +// Start-Up Time +// <0x0=> 166ns +// <0x1=> 333ns +// <0x2=> 667ns +// <0x3=> 1.333us +// <0x4=> 2.667us +// <0x5=> 5.333us +// <0x6=> 10.667us +// <0x7=> 21.333us +// osc48m_arch_startup +#ifndef CONF_OSC48M_STARTUP +#define CONF_OSC48M_STARTUP 0x7 +#endif + +// +// + +// DPLL Configuration +// Indicates whether configuration for DPLL is enabled or not +// enable_fdpll96m +#ifndef CONF_DPLL_CONFIG +#define CONF_DPLL_CONFIG 0 +#endif + +#define CONF_OSCCTRL_DPLL_REFCLK_XOSC32K 0 +#define CONF_OSCCTRL_DPLL_REFCLK_XOSC 1 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK 2 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK0 CONF_OSCCTRL_DPLL_REFCLK_GCLK +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK1 3 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK2 4 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK3 5 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK4 6 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK5 7 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK6 8 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK7 9 + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Select the clock source. +// fdpll96m_ref_clock +#ifndef CONF_DPLL_REFCLK_VAL +#define CONF_DPLL_REFCLK_VAL CONF_OSCCTRL_DPLL_REFCLK_XOSC32K +#endif + +#if (CONF_DPLL_REFCLK_VAL <= CONF_OSCCTRL_DPLL_REFCLK_GCLK0) +#define CONF_DPLL_REFCLK CONF_DPLL_REFCLK_VAL +#endif +#if (CONF_DPLL_REFCLK_VAL > CONF_OSCCTRL_DPLL_REFCLK_GCLK0) +#define CONF_DPLL_REFCLK CONF_OSCCTRL_DPLL_REFCLK_GCLK +#define CONF_DPLL_GCLK (CONF_DPLL_REFCLK_VAL - CONF_OSCCTRL_DPLL_REFCLK_GCLK0) +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll96m_arch_enable +#ifndef CONF_DPLL_ENABLE +#define CONF_DPLL_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll96m_arch_ondemand +#ifndef CONF_DPLL_ONDEMAND +#define CONF_DPLL_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll96m_arch_runstdby +#ifndef CONF_DPLL_RUNSTDBY +#define CONF_DPLL_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0xF> +// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/16)/(2^presc) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll96m_ldrfrac +#ifndef CONF_DPLL_LDRFRAC +#define CONF_DPLL_LDRFRAC 0xd +#endif + +// Loop Divider Ratio Integer Part <0x0-0xFFF> +// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/16)/(2^presc) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll96m_ldr +#ifndef CONF_DPLL_LDR +#define CONF_DPLL_LDR 0x5b7 +#endif + +// Clock Divider <0x0-0x3FF> +// This Clock divider is only for XOSC clock input to DPLL +// fdpll96m_clock_div +#ifndef CONF_DPLL_DIV +#define CONF_DPLL_DIV 0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll96m_arch_lbypass +#ifndef CONF_DPLL_LBYPASS +#define CONF_DPLL_LBYPASS 0 +#endif + +// Lock Time +// <0=>No time-out, automatic lock +// <4=>The Time-out if no lock within 8 ms +// <5=>The Time-out if no lock within 9 ms +// <6=>The Time-out if no lock within 10 ms +// <7=>The Time-out if no lock within 11 ms +// fdpll96m_arch_ltime +#ifndef CONF_DPLL_LTIME +#define CONF_DPLL_LTIME 0 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll96m_arch_wuf +#ifndef CONF_DPLL_WUF +#define CONF_DPLL_WUF 0 +#endif + +// Low-Power Enable +// Indicates whether Low-Power Enable is enabled or not +// fdpll96m_arch_lpen +#ifndef CONF_DPLL_LPEN +#define CONF_DPLL_LPEN 0 +#endif + +// Reference Clock Selection +// <0x0=>Default filter mode +// <0x1=>Low bandwidth filter +// <0x2=>High bandwidth filter +// <0x3=>High damping filter +// fdpll96m_arch_filter +#ifndef CONF_DPLL_FILTER +#define CONF_DPLL_FILTER 0 +#endif + +// Output Clock Prescaler +// 1 +// 2 +// 4 +// fdpll96m_presc +#ifndef CONF_DPLL_PRESC +#define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSCCTRL_CONFIG_H diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_port_config.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_port_config.h new file mode 100644 index 0000000..1efce33 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_port_config.h @@ -0,0 +1,284 @@ +/* Auto-generated config file hpl_port_config.h */ +#ifndef HPL_PORT_CONFIG_H +#define HPL_PORT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// PORT Input Event 0 configuration +// enable_port_input_event_0 +#ifndef CONF_PORT_EVCTRL_PORT_0 +#define CONF_PORT_EVCTRL_PORT_0 0 +#endif + +// PORT Input Event 0 configuration on PORT A + +// PORTA Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled +// porta_input_event_enable_0 +#ifndef CONF_PORTA_EVCTRL_PORTEI_0 +#define CONF_PORTA_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTA Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_0 +#ifndef CONF_PORTA_EVCTRL_PID_0 +#define CONF_PORTA_EVCTRL_PID_0 0x0 +#endif + +// PORTA Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 0 +// porta_event_action_0 +#ifndef CONF_PORTA_EVCTRL_EVACT_0 +#define CONF_PORTA_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT B + +// PORTB Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled +// portb_input_event_enable_0 +#ifndef CONF_PORTB_EVCTRL_PORTEI_0 +#define CONF_PORTB_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTB Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_0 +#ifndef CONF_PORTB_EVCTRL_PID_0 +#define CONF_PORTB_EVCTRL_PID_0 0x0 +#endif + +// PORTB Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 0 +// portb_event_action_0 +#ifndef CONF_PORTB_EVCTRL_EVACT_0 +#define CONF_PORTB_EVCTRL_EVACT_0 0 +#endif + +// + +// + +// PORT Input Event 1 configuration +// enable_port_input_event_1 +#ifndef CONF_PORT_EVCTRL_PORT_1 +#define CONF_PORT_EVCTRL_PORT_1 0 +#endif + +// PORT Input Event 1 configuration on PORT A + +// PORTA Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled +// porta_input_event_enable_1 +#ifndef CONF_PORTA_EVCTRL_PORTEI_1 +#define CONF_PORTA_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTA Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_1 +#ifndef CONF_PORTA_EVCTRL_PID_1 +#define CONF_PORTA_EVCTRL_PID_1 0x0 +#endif + +// PORTA Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 1 +// porta_event_action_1 +#ifndef CONF_PORTA_EVCTRL_EVACT_1 +#define CONF_PORTA_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT B + +// PORTB Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled +// portb_input_event_enable_1 +#ifndef CONF_PORTB_EVCTRL_PORTEI_1 +#define CONF_PORTB_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTB Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_1 +#ifndef CONF_PORTB_EVCTRL_PID_1 +#define CONF_PORTB_EVCTRL_PID_1 0x0 +#endif + +// PORTB Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 1 +// portb_event_action_1 +#ifndef CONF_PORTB_EVCTRL_EVACT_1 +#define CONF_PORTB_EVCTRL_EVACT_1 0 +#endif + +// + +// + +// PORT Input Event 2 configuration +// enable_port_input_event_2 +#ifndef CONF_PORT_EVCTRL_PORT_2 +#define CONF_PORT_EVCTRL_PORT_2 0 +#endif + +// PORT Input Event 2 configuration on PORT A + +// PORTA Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled +// porta_input_event_enable_2 +#ifndef CONF_PORTA_EVCTRL_PORTEI_2 +#define CONF_PORTA_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTA Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_2 +#ifndef CONF_PORTA_EVCTRL_PID_2 +#define CONF_PORTA_EVCTRL_PID_2 0x0 +#endif + +// PORTA Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 2 +// porta_event_action_2 +#ifndef CONF_PORTA_EVCTRL_EVACT_2 +#define CONF_PORTA_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT B + +// PORTB Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled +// portb_input_event_enable_2 +#ifndef CONF_PORTB_EVCTRL_PORTEI_2 +#define CONF_PORTB_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTB Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_2 +#ifndef CONF_PORTB_EVCTRL_PID_2 +#define CONF_PORTB_EVCTRL_PID_2 0x0 +#endif + +// PORTB Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 2 +// portb_event_action_2 +#ifndef CONF_PORTB_EVCTRL_EVACT_2 +#define CONF_PORTB_EVCTRL_EVACT_2 0 +#endif + +// + +// + +// PORT Input Event 3 configuration +// enable_port_input_event_3 +#ifndef CONF_PORT_EVCTRL_PORT_3 +#define CONF_PORT_EVCTRL_PORT_3 0 +#endif + +// PORT Input Event 3 configuration on PORT A + +// PORTA Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled +// porta_input_event_enable_3 +#ifndef CONF_PORTA_EVCTRL_PORTEI_3 +#define CONF_PORTA_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTA Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_3 +#ifndef CONF_PORTA_EVCTRL_PID_3 +#define CONF_PORTA_EVCTRL_PID_3 0x0 +#endif + +// PORTA Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 3 +// porta_event_action_3 +#ifndef CONF_PORTA_EVCTRL_EVACT_3 +#define CONF_PORTA_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT B + +// PORTB Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled +// portb_input_event_enable_3 +#ifndef CONF_PORTB_EVCTRL_PORTEI_3 +#define CONF_PORTB_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTB Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_3 +#ifndef CONF_PORTB_EVCTRL_PID_3 +#define CONF_PORTB_EVCTRL_PID_3 0x0 +#endif + +// PORTB Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 3 +// portb_event_action_3 +#ifndef CONF_PORTB_EVCTRL_EVACT_3 +#define CONF_PORTB_EVCTRL_EVACT_3 0 +#endif + +// + +// + +#define CONF_PORTA_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ + | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ + | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) +#define CONF_PORTB_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ + | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ + | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) + +// <<< end of configuration section >>> + +#endif // HPL_PORT_CONFIG_H diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_sercom_config.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_sercom_config.h new file mode 100644 index 0000000..a0924c1 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/hpl_sercom_config.h @@ -0,0 +1,427 @@ +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_SERCOM_4_USART_ENABLE +#define CONF_SERCOM_4_USART_ENABLE 1 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable input buffer in SERCOM module +// usart_rx_enable +#ifndef CONF_SERCOM_4_USART_RXEN +#define CONF_SERCOM_4_USART_RXEN 1 +#endif + +// Transmitt buffer enable +// Enable output buffer in SERCOM module +// usart_tx_enable +#ifndef CONF_SERCOM_4_USART_TXEN +#define CONF_SERCOM_4_USART_TXEN 1 +#endif + +// Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_SERCOM_4_USART_PARITY +#define CONF_SERCOM_4_USART_PARITY 0x0 +#endif + +// Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_SERCOM_4_USART_CHSIZE +#define CONF_SERCOM_4_USART_CHSIZE 0x0 +#endif + +// Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_SERCOM_4_USART_SBMODE +#define CONF_SERCOM_4_USART_SBMODE 0 +#endif + +// Baud rate <1-3000000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_SERCOM_4_USART_BAUD +#define CONF_SERCOM_4_USART_BAUD 19200 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_SERCOM_4_USART_ADVANCED_CONFIG +#define CONF_SERCOM_4_USART_ADVANCED_CONFIG 0 +#endif + +// Run in stand-by +// Keep the module running in standby sleep mode +// usart_arch_runstdby +#ifndef CONF_SERCOM_4_USART_RUNSTDBY +#define CONF_SERCOM_4_USART_RUNSTDBY 0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when the BUFOVF status bit is asserted +// usart_arch_ibon +#ifndef CONF_SERCOM_4_USART_IBON +#define CONF_SERCOM_4_USART_IBON 0 +#endif + +// Start of Frame Detection Enable +// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// usart_arch_sfde +#ifndef CONF_SERCOM_4_USART_SFDE +#define CONF_SERCOM_4_USART_SFDE 0 +#endif + +// Collision Detection Enable +// Collision detection enable +// usart_arch_cloden +#ifndef CONF_SERCOM_4_USART_CLODEN +#define CONF_SERCOM_4_USART_CLODEN 0 +#endif + +// Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// usart_arch_clock_mode +#ifndef CONF_SERCOM_4_USART_MODE +#define CONF_SERCOM_4_USART_MODE 0x1 +#endif + +// Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x4=>3x arithmetic +// How many over-sampling bits used when sampling data state +// usart_arch_sampr +#ifndef CONF_SERCOM_4_USART_SAMPR +#define CONF_SERCOM_4_USART_SAMPR 0x0 +#endif + +// Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// Adjust which samples to use for data sampling in asynchronous mode +// usart_arch_sampa +#ifndef CONF_SERCOM_4_USART_SAMPA +#define CONF_SERCOM_4_USART_SAMPA 0x0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_SERCOM_4_USART_FRACTIONAL +#define CONF_SERCOM_4_USART_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_dord +#ifndef CONF_SERCOM_4_USART_DORD +#define CONF_SERCOM_4_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_4_USART_CPOL 0 + +// Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// usart_arch_enc +#ifndef CONF_SERCOM_4_USART_ENC +#define CONF_SERCOM_4_USART_ENC 0 +#endif + +// LIN Slave Enable +// Break Character Detection and Auto-Baud/LIN Slave Enable. +// Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). +// <0=>Disable +// <1=>Enable +// usart_arch_lin_slave_enable +#ifndef CONF_SERCOM_4_USART_LIN_SLAVE_ENABLE +#define CONF_SERCOM_4_USART_LIN_SLAVE_ENABLE 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// usart_arch_dbgstop +#ifndef CONF_SERCOM_4_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_4_USART_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_4_USART_CMODE +#define CONF_SERCOM_4_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_4_USART_RXPO +#define CONF_SERCOM_4_USART_RXPO 3 /* RX is on PIN_PB11 */ +#endif + +#ifndef CONF_SERCOM_4_USART_TXPO +#define CONF_SERCOM_4_USART_TXPO 1 /* TX is on PIN_PB10 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_4_USART_LIN_SLAVE_ENABLE == 1 +#if CONF_SERCOM_4_USART_PARITY == 0 +#define CONF_SERCOM_4_USART_PMODE 0 +#define CONF_SERCOM_4_USART_FORM 4 +#else +#define CONF_SERCOM_4_USART_PMODE CONF_SERCOM_4_USART_PARITY - 1 +#define CONF_SERCOM_4_USART_FORM 5 +#endif +#else /* #if CONF_SERCOM_4_USART_LIN_SLAVE_ENABLE == 0 */ +#if CONF_SERCOM_4_USART_PARITY == 0 +#define CONF_SERCOM_4_USART_PMODE 0 +#define CONF_SERCOM_4_USART_FORM 0 +#else +#define CONF_SERCOM_4_USART_PMODE CONF_SERCOM_4_USART_PARITY - 1 +#define CONF_SERCOM_4_USART_FORM 1 +#endif +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_4_USART_SAMPR == 0 +#ifndef CONF_SERCOM_4_USART_BAUD_RATE +#define CONF_SERCOM_4_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_4_USART_SAMPR == 1 +#ifndef CONF_SERCOM_4_USART_BAUD_RATE +#define CONF_SERCOM_4_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM4_CORE_FREQUENCY) / (CONF_SERCOM_4_USART_BAUD * 16)) - (CONF_SERCOM_4_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_4_USART_SAMPR == 2 +#ifndef CONF_SERCOM_4_USART_BAUD_RATE +#define CONF_SERCOM_4_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_4_USART_SAMPR == 3 +#ifndef CONF_SERCOM_4_USART_BAUD_RATE +#define CONF_SERCOM_4_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM4_CORE_FREQUENCY) / (CONF_SERCOM_4_USART_BAUD * 8)) - (CONF_SERCOM_4_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_4_USART_SAMPR == 4 +#ifndef CONF_SERCOM_4_USART_BAUD_RATE +#define CONF_SERCOM_4_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +// Enable configuration of module +#ifndef CONF_SERCOM_5_SPI_ENABLE +#define CONF_SERCOM_5_SPI_ENABLE 1 +#endif + +// Set module in SPI Slave mode +#ifndef CONF_SERCOM_5_SPI_MODE +#define CONF_SERCOM_5_SPI_MODE 0x02 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable receive buffer to receive data from slave. (RXEN) +// spi_slave_rx_enable +#ifndef CONF_SERCOM_5_SPI_RXEN +#define CONF_SERCOM_5_SPI_RXEN 0x1 +#endif + +// Character Size +// Bit size for all characters sent over the SPI bus. (CHSIZE) +// <0x0=>8 bits +// <0x1=>9 bits +// spi_slave_character_size +#ifndef CONF_SERCOM_5_SPI_CHSIZE +#define CONF_SERCOM_5_SPI_CHSIZE 0x0 +#endif + +// + +// Advanced Configuration +// spi_slave_advanced +#ifndef CONF_SERCOM_5_SPI_ADVANCED +#define CONF_SERCOM_5_SPI_ADVANCED 1 +#endif + +// Data Order +// <0=>MSB first +// <1=>LSB first +// I least significant or most significant bit is shifted out first. (DORD) +// spi_slave_arch_dord +#ifndef CONF_SERCOM_5_SPI_DORD +#define CONF_SERCOM_5_SPI_DORD 0x0 +#endif + +// Clock Polarity +// <0=>SCK is low when idle +// <1=>SCK is high when idle +// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) +// spi_slave_arch_cpol +#ifndef CONF_SERCOM_5_SPI_CPOL +#define CONF_SERCOM_5_SPI_CPOL 0x0 +#endif + +// Clock Phase +// <0x0=>Sample input on leading edge +// <0x1=>Sample input on trailing edge +// Determines if input data is sampled on leading or trailing SCK edge. (CPHA) +// spi_slave_arch_cpha +#ifndef CONF_SERCOM_5_SPI_CPHA +#define CONF_SERCOM_5_SPI_CPHA 0x0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when OVF is asserted. (IBON) +// <0x0=>In data stream +// <0x1=>On buffer overflow +// spi_slave_arch_ibon +#ifndef CONF_SERCOM_5_SPI_IBON +#define CONF_SERCOM_5_SPI_IBON 0x0 +#endif + +// Slave Select Low Detect Enable +// This bit enables wake up when the slave select (_SS) pin transitions from high to low. (SSDE) +// spi_slave_arch_ssde +#ifndef CONF_SERCOM_5_SPI_SSDE +#define CONF_SERCOM_5_SPI_SSDE 1 +#endif + +// Slave Detect Preload Enable +// Setting this bit will enable preloading of the slave shift register when there is no transfer in progress. (PLOADEN) +// spi_slave_arch_ploaden +#ifndef CONF_SERCOM_5_SPI_PLOADEN +#define CONF_SERCOM_5_SPI_PLOADEN 1 +#endif + +// Enable SPI address mode +// This will enable SPI frames with address, first received character is treated as address. (FORM=SPI_ADDR) +// spi_slave_arch_amode_en +#ifndef CONF_SERCOM_5_SPI_AMODE_EN +#define CONF_SERCOM_5_SPI_AMODE_EN 0 +#endif + +// Address Mode +// <0x0=>Address mask +// <0x1=>Two unique addresses +// <0x2=>Address range +// These bits set the slave addressing mode when the frame format with address is used. (AMODE) +// spi_slave_arch_amode +#ifndef CONF_SERCOM_5_SPI_AMODE +#define CONF_SERCOM_5_SPI_AMODE 0 +#endif + +// Address <0-255> +// These bits hold the address when SPI address modes is enabled. (ADDR) +// spi_slave_arch_addr +#ifndef CONF_SERCOM_5_SPI_ADDR +#define CONF_SERCOM_5_SPI_ADDR 0 +#endif + +// Address mask <0-255> +// These bits hold the address mask when SPI address mode is enabled. (ADDRMASK) +// spi_slave_arch_addrmask +#ifndef CONF_SERCOM_5_SPI_ADDRMASK +#define CONF_SERCOM_5_SPI_ADDRMASK 0 +#endif + +// Run in stand-by +// Module stays active in stand-by sleep mode. (RUNSTDBY) +// spi_slave_arch_runstdby +#ifndef CONF_SERCOM_5_SPI_RUNSTDBY +#define CONF_SERCOM_5_SPI_RUNSTDBY 0x0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) +// <0=>Keep running +// <1=>Halt +// spi_slave_arch_dbgstop +#ifndef CONF_SERCOM_5_SPI_DBGSTOP +#define CONF_SERCOM_5_SPI_DBGSTOP 0 +#endif + +// + +// This bit is not applicable in slave mode +#ifndef CONF_SERCOM_5_SPI_MSSEN +#define CONF_SERCOM_5_SPI_MSSEN 0x0 +#endif + +// Receive Data Pinout +// <0x0=>PAD[0] +// <0x1=>PAD[1] +// <0x2=>PAD[2] +// <0x3=>PAD[3] +// spi_slave_rxpo +#ifndef CONF_SERCOM_5_SPI_RXPO +#define CONF_SERCOM_5_SPI_RXPO 2 +#endif + +// Transmit Data Pinout +// <0x0=>PAD[0,1]_DO_SCK +// <0x1=>PAD[2,3]_DO_SCK +// <0x2=>PAD[3,1]_DO_SCK +// <0x3=>PAD[0,3]_DO_SCK +// spi_slave_txpo +#ifndef CONF_SERCOM_5_SPI_TXPO +#define CONF_SERCOM_5_SPI_TXPO 3 +#endif + +#ifndef CONF_SERCOM_5_SPI_BAUD_RATE +#define CONF_SERCOM_5_SPI_BAUD_RATE 0 +#endif + +#ifndef CONF_SERCOM_5_SPI_DUMMYBYTE +#define CONF_SERCOM_5_SPI_DUMMYBYTE 0x0 +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/peripheral_clk_config.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/peripheral_clk_config.h new file mode 100644 index 0000000..ab23f8a --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/peripheral_clk_config.h @@ -0,0 +1,145 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 24000000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM4_CORE_SRC +#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM4_SLOW_SRC +#define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM4_CORE_FREQUENCY + * \brief SERCOM4's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY +#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 24000000 +#endif + +/** + * \def CONF_GCLK_SERCOM4_SLOW_FREQUENCY + * \brief SERCOM4's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM4_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 400000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM5_CORE_SRC +#define CONF_GCLK_SERCOM5_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM5_SLOW_SRC +#define CONF_GCLK_SERCOM5_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM5_CORE_FREQUENCY + * \brief SERCOM5's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY +#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 24000000 +#endif + +/** + * \def CONF_GCLK_SERCOM5_SLOW_FREQUENCY + * \brief SERCOM5's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM5_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM5_SLOW_FREQUENCY 400000 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/stdio_redirect_config.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/stdio_redirect_config.h new file mode 100644 index 0000000..3515c0c --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/config/stdio_redirect_config.h @@ -0,0 +1,9 @@ +/* Auto-generated config file stdio_redirect_config.h */ +#ifndef STDIO_REDIRECT_CONFIG_H +#define STDIO_REDIRECT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <<< end of configuration section >>> + +#endif // STDIO_REDIRECT_CONFIG_H diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/documentation/stdio.rst b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/documentation/stdio.rst new file mode 100644 index 0000000..2864b49 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/documentation/stdio.rst @@ -0,0 +1,34 @@ +STDIO redirection +================= + +The STDIO redirection provides means to redirect standard input/output to HAL +IO. + +On initialization, the HAL IO descriptor is assigned so that all input and +output is redirected to access it. The IO descriptor can also be changed +through stdio_io_set_io(). All stdin or stdout access is redirected to the +IO descriptor. When the IO descriptor is set to NULL, all input and output +are discarded. + +For GCC redirection, the stdout and stdin buffer are turned off, the +standard _read() and _write() are overridden. + +For IAR redirection, the __read() and __write() are overridden. + +For Keil redirection, the Retarget.c are modified to override fputc(), fgetc(), +etc. + +Features +-------- + +* Standard input/output redirection (e.g., printf to EDBG COM port) + +Dependencies +------------ + +* HAL IO driver + +Limitations +----------- + +* IO read/write operation should be synchronous diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/driver_init.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/driver_init.c new file mode 100644 index 0000000..73e9a54 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/driver_init.c @@ -0,0 +1,115 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_init.h" +#include +#include +#include + +struct usart_sync_descriptor TARGET_IO; + +struct spi_s_sync_descriptor SPI_0; + +void TARGET_IO_PORT_init(void) +{ + + gpio_set_pin_function(PB10, PINMUX_PB10D_SERCOM4_PAD2); + + gpio_set_pin_function(PB11, PINMUX_PB11D_SERCOM4_PAD3); +} + +void TARGET_IO_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_mclk_set_APBCMASK_SERCOM4_bit(MCLK); +} + +void TARGET_IO_init(void) +{ + TARGET_IO_CLOCK_init(); + usart_sync_init(&TARGET_IO, SERCOM4, (void *)NULL); + TARGET_IO_PORT_init(); +} + +void SPI_0_PORT_init(void) +{ + + gpio_set_pin_level(PB02, + // Initial level + // pad_initial_level + // Low + // High + false); + + // Set pin direction to output + gpio_set_pin_direction(PB02, GPIO_DIRECTION_OUT); + + gpio_set_pin_function(PB02, PINMUX_PB02D_SERCOM5_PAD0); + + // Set pin direction to input + gpio_set_pin_direction(SPI_CS, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(SPI_CS, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(SPI_CS, PINMUX_PB03D_SERCOM5_PAD1); + + // Set pin direction to input + gpio_set_pin_direction(PB00, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PB00, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PB00, PINMUX_PB00D_SERCOM5_PAD2); + + gpio_set_pin_level(PB01, + // Initial level + // pad_initial_level + // Low + // High + false); + + // Set pin direction to output + gpio_set_pin_direction(PB01, GPIO_DIRECTION_OUT); + + gpio_set_pin_function(PB01, PINMUX_PB01D_SERCOM5_PAD3); +} + +void SPI_0_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_CORE, CONF_GCLK_SERCOM5_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_SLOW, CONF_GCLK_SERCOM5_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_mclk_set_APBCMASK_SERCOM5_bit(MCLK); +} + +void SPI_0_init(void) +{ + SPI_0_CLOCK_init(); + spi_s_sync_init(&SPI_0, SERCOM5); + SPI_0_PORT_init(); +} + +void system_init(void) +{ + init_mcu(); + + TARGET_IO_init(); + + SPI_0_init(); +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/driver_init.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/driver_init.h new file mode 100644 index 0000000..7d0ee52 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/driver_init.h @@ -0,0 +1,50 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_INIT_INCLUDED +#define DRIVER_INIT_INCLUDED + +#include "atmel_start_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#include + +#include + +extern struct usart_sync_descriptor TARGET_IO; + +extern struct spi_s_sync_descriptor SPI_0; + +void TARGET_IO_PORT_init(void); +void TARGET_IO_CLOCK_init(void); +void TARGET_IO_init(void); + +void SPI_0_PORT_init(void); +void SPI_0_CLOCK_init(void); +void SPI_0_init(void); +void SPI_0_example(void); + +/** + * \brief Perform system initialization, initialize pins and clocks for + * peripherals + */ +void system_init(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_INIT_INCLUDED diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/examples/driver_examples.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/examples/driver_examples.c new file mode 100644 index 0000000..6b79848 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/examples/driver_examples.c @@ -0,0 +1,37 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_examples.h" +#include "driver_init.h" +#include "utils.h" + +/** + * Example of using TARGET_IO to write "Hello World" using the IO abstraction. + */ +void TARGET_IO_example(void) +{ + struct io_descriptor *io; + usart_sync_get_io_descriptor(&TARGET_IO, &io); + usart_sync_enable(&TARGET_IO); + + io_write(io, (uint8_t *)"Hello World!", 12); +} + +/** + * Example of using SPI_0 to write "Hello World" using the IO abstraction. + */ +static uint8_t example_SPI_0[12] = "Hello World!"; + +void SPI_0_example(void) +{ + struct io_descriptor *io; + spi_s_sync_get_io_descriptor(&SPI_0, &io); + + spi_s_sync_enable(&SPI_0); + io_write(io, example_SPI_0, 12); +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/examples/driver_examples.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/examples/driver_examples.h new file mode 100644 index 0000000..745c3df --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/examples/driver_examples.h @@ -0,0 +1,20 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_EXAMPLES_H_INCLUDED +#define DRIVER_EXAMPLES_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void TARGET_IO_example(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_EXAMPLES_H_INCLUDED diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/documentation/spi_slave_sync.rst b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/documentation/spi_slave_sync.rst new file mode 100644 index 0000000..226eb8a --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/documentation/spi_slave_sync.rst @@ -0,0 +1,60 @@ +The SPI Slave Synchronous Driver +================================ + +The serial peripheral interface (SPI) is a synchronous serial communication +interface. + +SPI devices communicate in full duplex mode using a master-slave +architecture with a single master. The slave device uses the control signal +and clocks from master for reading and writing. Slave device is selected through +slave select (SS) line. + +When data is read or written through the I/O writing function, the driver keeps +polling until amount of characters achieved. Also it's possible to perform +full-duplex read and write through transfer function, which process read and +write at the same time. + +When SS detection is considered, a "break on SS detection" option can be enabled +to make it possible to terminate the read/write/transfer on SS desertion. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * SPI mode + * Character size + * Data order +* Data transfer: transmission, reception and full-duplex + +Applications +------------ + +* SPI to I2C bridge that bridges SPI commands to I2C interface. + +Dependencies +------------ + +SPI slave capable hardware + +Concurrency +----------- + +N/A + +Limitations +----------- + +N/A + +Known issues and workarounds +---------------------------- + +When writing data through SPI slave, the time that the data appears on data line +depends on the SPI hardware, and previous writing state, since there can be +data in output fifo filled by previous broken transmitting. The number of such +dummy/broken characters is limited by hardware. Whether these dummy/broken +characters can be flushed is also limited by hardware. + diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/documentation/usart_sync.rst b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/documentation/usart_sync.rst new file mode 100644 index 0000000..15e4b13 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/documentation/usart_sync.rst @@ -0,0 +1,58 @@ +The USART Synchronous Driver +============================ + +The universal synchronous and asynchronous receiver and transmitter +(USART) is usually used to transfer data from one device to the other. + +User can set action for flow control pins by function usart_set_flow_control, +if the flow control is enabled. All the available states are defined in union +usart_flow_control_state. + +Note that user can set state of flow control pins only if automatic support of +the flow control is not supported by the hardware. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * UART or USRT communication mode + * Character size + * Data order + * Flow control +* Data transfer: transmission, reception + +Applications +------------ + +They are commonly used in a terminal application or low-speed communication +between devices. + +Dependencies +------------ + +USART capable hardware. + +Concurrency +----------- + +Write buffer should not be changed while data is being sent. + + +Limitations +----------- + +* The driver does not support 9-bit character size. +* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. + And the SCK pin can't be set directly. Application can use a GCLK output PIN + to generate SCK. For example to communicate with a SMARTCARD with ISO7816 + (F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be + config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_atomic.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_atomic.h new file mode 100644 index 0000000..82151fc --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_atomic.h @@ -0,0 +1,120 @@ +/** + * \file + * + * \brief Critical sections related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ATOMIC_H_INCLUDED +#define _HAL_ATOMIC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_atomic + * + *@{ + */ + +/** + * \brief Type for the register holding global interrupt enable flag + */ +typedef uint32_t hal_atomic_t; + +/** + * \brief Helper macro for entering critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_enterCritical() function to enter critical + * sections. No semicolon is required after the macro. + * + * \section atomic_usage Usage Example + * \code + * CRITICAL_SECTION_ENTER() + * Critical code + * CRITICAL_SECTION_LEAVE() + * \endcode + */ +#define CRITICAL_SECTION_ENTER() \ + { \ + volatile hal_atomic_t __atomic; \ + atomic_enter_critical(&__atomic); + +/** + * \brief Helper macro for leaving critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_leaveCritical() function to leave critical + * sections. No semicolon is required after the macro. + */ +#define CRITICAL_SECTION_LEAVE() \ + atomic_leave_critical(&__atomic); \ + } + +/** + * \brief Disable interrupts, enter critical section + * + * Disables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[out] atomic The pointer to a variable to store the value of global + * interrupt enable flag + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Exit atomic section + * + * Enables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[in] atomic The pointer to a variable, which stores the latest stored + * value of the global interrupt enable flag + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t atomic_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_delay.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_delay.h new file mode 100644 index 0000000..9d4aa5c --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_delay.h @@ -0,0 +1,89 @@ +/** + * \file + * + * \brief HAL delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#ifndef _HAL_DELAY_H_INCLUDED +#define _HAL_DELAY_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_delay Delay Driver + * + *@{ + */ + +/** + * \brief Initialize Delay driver + * + * \param[in] hw The pointer to hardware instance + */ +void delay_init(void *const hw); + +/** + * \brief Perform delay in us + * + * This function performs delay for the given amount of microseconds. + * + * \param[in] us The amount delay in us + */ +void delay_us(const uint16_t us); + +/** + * \brief Perform delay in ms + * + * This function performs delay for the given amount of milliseconds. + * + * \param[in] ms The amount delay in ms + */ +void delay_ms(const uint16_t ms); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t delay_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_gpio.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_gpio.h new file mode 100644 index 0000000..fbfa2d4 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_gpio.h @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ +#ifndef _HAL_GPIO_INCLUDED_ +#define _HAL_GPIO_INCLUDED_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set gpio pull mode + * + * Set pin pull mode, non existing pull modes throws an fatal assert + * + * \param[in] pin The pin number for device + * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor + * GPIO_PULL_UP = Pull pin high with internal resistor + * GPIO_PULL_OFF = Disable pin pull mode + */ +static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) +{ + _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); +} + +/** + * \brief Set pin function + * + * Select which function a pin will be used for + * + * \param[in] pin The pin number for device + * \param[in] function The pin function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) +{ + _gpio_set_pin_function(pin, function); +} + +/** + * \brief Set port data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + _gpio_set_direction(port, mask, direction); +} + +/** + * \brief Set gpio data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] pin The pin number for device + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) +{ + _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); +} + +/** + * \brief Set port level + * + * Sets output level on the pins defined by the bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply port level to the corresponding + * pin + * \param[in] level true = Pin levels set to "high" state + * false = Pin levels set to "low" state + */ +static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + _gpio_set_level(port, mask, level); +} + +/** + * \brief Set gpio level + * + * Sets output level on a pin + * + * \param[in] pin The pin number for device + * \param[in] level true = Pin level set to "high" state + * false = Pin level set to "low" state + */ +static inline void gpio_set_pin_level(const uint8_t pin, const bool level) +{ + _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); +} + +/** + * \brief Toggle out level on pins + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding + * pin + */ +static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) +{ + _gpio_toggle_level(port, mask); +} + +/** + * \brief Toggle output level on pin + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] pin The pin number for device + */ +static inline void gpio_toggle_pin_level(const uint8_t pin) +{ + _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); +} + +/** + * \brief Get input level on pins + * + * Read the input level on pins connected to a port + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t gpio_get_port_level(const enum gpio_port port) +{ + return _gpio_get_level(port); +} + +/** + * \brief Get level on pin + * + * Reads the level on pins connected to a port + * + * \param[in] pin The pin number for device + */ +static inline bool gpio_get_pin_level(const uint8_t pin) +{ + return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); +} +/** + * \brief Get current driver version + */ +uint32_t gpio_get_version(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_init.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_init.h new file mode 100644 index 0000000..d7bc6fe --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_init.h @@ -0,0 +1,72 @@ +/** + * \file + * + * \brief HAL initialization related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_INIT_H_INCLUDED +#define _HAL_INIT_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_init Init Driver + * + *@{ + */ + +/** + * \brief Initialize the hardware abstraction layer + * + * This function calls the various initialization functions. + * Currently the following initialization functions are supported: + * - System clock initialization + */ +static inline void init_mcu(void) +{ + _init_chip(); +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t init_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_io.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_io.h new file mode 100644 index 0000000..f50401d --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_io.h @@ -0,0 +1,110 @@ +/** + * \file + * + * \brief I/O related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_IO_INCLUDED +#define _HAL_IO_INCLUDED + +/** + * \addtogroup doc_driver_hal_helper_io I/O Driver + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I/O descriptor + * + * The I/O descriptor forward declaration. + */ +struct io_descriptor; + +/** + * \brief I/O write function pointer type + */ +typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read function pointer type + */ +typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O descriptor + */ +struct io_descriptor { + io_write_t write; /*! The write function pointer. */ + io_read_t read; /*! The read function pointer. */ +}; + +/** + * \brief I/O write interface + * + * This function writes up to \p length of bytes to a given I/O descriptor. + * It returns the number of bytes actually write. + * + * \param[in] descr An I/O descriptor to write + * \param[in] buf The buffer pointer to story the write data + * \param[in] length The number of bytes to write + * + * \return The number of bytes written + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read interface + * + * This function reads up to \p length bytes from a given I/O descriptor, and + * stores it in the buffer pointed to by \p buf. It returns the number of bytes + * actually read. + * + * \param[in] descr An I/O descriptor to read + * \param[in] buf The buffer pointer to story the read data + * \param[in] length The number of bytes to read + * + * \return The number of bytes actually read. This number can be less than the + * requested length. E.g., in a driver that uses ring buffer for + * reception, it may depend on the availability of data in the + * ring buffer. + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_IO_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_sleep.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_sleep.h new file mode 100644 index 0000000..b90ef6a --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_sleep.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SLEEP_H_INCLUDED +#define _HAL_SLEEP_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_sleep + * + *@{ + */ + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t sleep_get_version(void); +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_spi_s_sync.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_spi_s_sync.h new file mode 100644 index 0000000..2cdc43d --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_spi_s_sync.h @@ -0,0 +1,204 @@ +/** + * \file + * + * \brief SPI Slave functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SPI_S_SYNC_H_INCLUDED +#define _HAL_SPI_S_SYNC_H_INCLUDED + +#include "hpl_spi_s_sync.h" +#include "utils.h" +#include "hal_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_spi_slave_sync + * + * @{ + */ + +/** \brief SPI Slave HAL driver struct for synchronous access + */ +struct spi_s_sync_descriptor { + struct _spi_s_sync_hpl_interface *func; + /** SPI device instance */ + struct _spi_sync_dev dev; + /** I/O read/write */ + struct io_descriptor io; + /** Break on SS desert detection. */ + uint8_t break_on_ss_det; +}; + +/** \brief Set the SPI HAL instance function pointer for HPL APIs. + * + * Set SPI HAL instance function pointer for HPL APIs. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] func Pointer to the HPL api structure. + * + */ +void spi_s_sync_set_func_ptr(struct spi_s_sync_descriptor *spi, void *const func); + +/** \brief Initialize the SPI Slave HAL instance and hardware + * + * Initialize SPI Slave HAL with polling mode. + * + * \param[in, out] spi Pointer to the SPI Slave HAL instance. + * \param[in] hw Pointer to the hardware base. + * + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error. + */ +int32_t spi_s_sync_init(struct spi_s_sync_descriptor *spi, void *const hw); + +/** \brief Deinitialize the SPI HAL instance + * + * Disable and reset SPI, de-init software. + * + * \param[in,out] spi Pointer to the SPI Slave HAL instance. + */ +void spi_s_sync_deinit(struct spi_s_sync_descriptor *spi); + +/** \brief Enable SPI + * + * \param[in,out] spi Pointer to the SPI Slave HAL instance. + */ +void spi_s_sync_enable(struct spi_s_sync_descriptor *spi); + +/** \brief Disable SPI + * + * \param[in,out] spi Pointer to the SPI Slave HAL instance. + */ +void spi_s_sync_disable(struct spi_s_sync_descriptor *spi); + +/** \brief Set SPI mode + * + * Set the SPI transfer mode (\ref spi_transfer_mode_t), + * which controls the clock polarity and clock phase: + * - Mode 0: leading edge is rising edge, data sample on leading edge. + * - Mode 1: leading edge is rising edge, data sample on trailing edge. + * - Mode 2: leading edge is falling edge, data sample on leading edge. + * - Mode 3: leading edge is falling edge, data sample on trailing edge. + * Note that SPI must be disabled to change mode. + * + * \param[in,out] spi Pointer to the HAL SPI instance. + * \param[in] mode The mode (\ref spi_transfer_mode_t). + * + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error. + */ +int32_t spi_s_sync_set_mode(struct spi_s_sync_descriptor *spi, const enum spi_transfer_mode mode); + +/** \brief Set SPI transfer character size in number of bits + * + * The character size (\ref spi_char_size_t) influence the way the data is + * sent/received. + * For char size <= 8-bit, data is stored byte by byte. + * For char size between 9-bit ~ 16-bit, data is stored in 2-byte length. + * Note that the default and recommended char size is 8-bit since it's + * supported by all system. + * Note that the SPI must be disabled to change character size. Also it affects + * buffer accessing, the ring buffer should be flushed before changing it to + * avoid conflicts. + * + * \param[in,out] spi Pointer to the HAL SPI instance. + * \param[in] char_size The char size (~32, recommended 8). + * + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error. + */ +int32_t spi_s_sync_set_char_size(struct spi_s_sync_descriptor *spi, const enum spi_char_size char_size); + +/** \brief Set SPI transfer data order + * + * Note that the SPI must be disabled to change data order. + * + * \param[in,out] spi Pointer to the HAL SPI instance. + * \param[in] dord The data order: send LSB/MSB first. + * + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error. + */ +int32_t spi_s_sync_set_data_order(struct spi_s_sync_descriptor *spi, const enum spi_data_order dord); + +/** \brief Enable/disable break on SS desert detection + * + * \param[in,out] spi Pointer to the HAL SPI instance. + * \param[in] enable Set to \c true to break R/W loop on SS desert. + */ +void spi_s_sync_break_on_ss_detect(struct spi_s_sync_descriptor *spi, const bool enable); + +/** \brief Write/read at the same time + * + * \param[in,out] spi Pointer to the HAL SPI instance. + * \param[in] xfer Pointer to the transfer information (\ref spi_xfer). + * + * \return Operation result. + * \retval <0 Error. + * \retval >=0 Number of characters transferred. + */ +int32_t spi_s_sync_transfer(struct spi_s_sync_descriptor *spi, const struct spi_xfer *xfer); + +/** + * \brief Return I/O descriptor for this SPI instance + * + * This function will return an I/O instance for this SPI driver instance + * + * \param[in] spi An SPI slave descriptor, which is used to communicate through + * SPI + * \param[in] io A pointer to an I/O descriptor pointer type + * + * \return Error code. + * \retval 0 No error detected + * \retval <0 Error code + */ +int32_t spi_s_sync_get_io_descriptor(struct spi_s_sync_descriptor *spi, struct io_descriptor **io); + +/** \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t spi_s_sync_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_SPI_S_SYNC_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_usart_sync.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_usart_sync.h new file mode 100644 index 0000000..1ef22fc --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hal_usart_sync.h @@ -0,0 +1,247 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SYNC_USART_H_INCLUDED +#define _HAL_SYNC_USART_H_INCLUDED + +#include "hal_io.h" +#include + +/** + * \addtogroup doc_driver_hal_usart_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Synchronous USART descriptor + */ +struct usart_sync_descriptor { + struct io_descriptor io; + struct _usart_sync_device device; +}; + +/** + * \brief Initialize USART interface + * + * This function initializes the given I/O descriptor to be used + * as USART interface descriptor. + * It checks if the given hardware is not initialized and + * if the given hardware is permitted to be initialized. + * + * \param[out] descr A USART descriptor which is used to communicate via USART + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to as set of functions pointers + * + * \return Initialization status. + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); + +/** + * \brief Deinitialize USART interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and + * if the given hardware is permitted to be deinitialized. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return De-initialization status. + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); + +/** + * \brief Enable USART interface + * + * Enables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Enabling status. + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); + +/** + * \brief Disable USART interface + * + * Disables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Disabling status. + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve I/O descriptor + * + * This function retrieves the I/O descriptor of the given USART descriptor. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] io An I/O descriptor to retrieve + * + * \return The status of the I/O descriptor retrieving. + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); + +/** + * \brief Specify action for flow control pins + * + * This function sets the action (or state) for the flow control pins + * if the flow control is enabled. + * It sets the state of flow control pins only if the automatic support of + * the flow control is not supported by the hardware. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] state A state to set the flow control pins + * + * \return The status of flow control action setup. + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state); + +/** + * \brief Set USART baud rate + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] baud_rate A baud rate to set + * + * \return The status of baud rate setting. + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); + +/** + * \brief Set USART data order + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] data_order A data order to set + * + * \return The status of data order setting. + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); + +/** + * \brief Set USART mode + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] mode A mode to set + * + * \return The status of mode setting. + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); + +/** + * \brief Set USART parity + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] parity A parity to set + * + * \return The status of parity setting. + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); + +/** + * \brief Set USART stop bits + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] stop_bits Stop bits to set + * + * \return The status of stop bits setting. + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); + +/** + * \brief Set USART character size + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] size A character size to set + * + * \return The status of character size setting. + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins + * if the flow control is enabled. + * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case + * if the flow control is done by the hardware + * and the pins state cannot be read out. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] state The state of flow control pins + * + * \return The status of flow control state reading. + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state); + +/** + * \brief Check if the USART transmitter is empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART TX empty checking. + * \retval 0 The USART transmitter is not empty + * \retval 1 The USART transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Check if the USART receiver is not empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART RX empty checking. + * \retval 1 The USART receiver is not empty + * \retval 0 The USART receiver is empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usart_sync_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_core.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_core.h new file mode 100644 index 0000000..9324c43 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_core.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief CPU core related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_H_INCLUDED +#define _HPL_CORE_H_INCLUDED + +/** + * \addtogroup HPL Core + * + * \section hpl_core_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_core_port.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_delay.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_delay.h new file mode 100644 index 0000000..a0f1ac8 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_delay.h @@ -0,0 +1,97 @@ +/** + * \file + * + * \brief Delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DELAY_H_INCLUDED +#define _HPL_DELAY_H_INCLUDED + +/** + * \addtogroup HPL Delay + * + * \section hpl_delay_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Initialize delay functionality + * + * \param[in] hw The pointer to hardware instance + */ +void _delay_init(void *const hw); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + * + * \param[in] us The amount of us to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_us(const uint16_t us); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + * + * \param[in] ms The amount of ms to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_ms(const uint16_t ms); + +/** + * \brief Delay loop to delay n number of cycles + * + * \param[in] hw The pointer to hardware instance + * \param[in] cycles The amount of cycles to delay for + */ +void _delay_cycles(void *const hw, uint32_t cycles); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_div.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_div.h new file mode 100644 index 0000000..f45f794 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_div.h @@ -0,0 +1,59 @@ +/** + * \file + * + * \brief Division operation related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DIV_H_INCLUDED +#define _HPL_DIV_H_INCLUDED + +/** + * \addtogroup HPL Div + * + * \section hpl_div_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Initialize hardware for division operation + */ +void _div_init(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_DIV_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_dma.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_dma.h new file mode 100644 index 0000000..1e08434 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_dma.h @@ -0,0 +1,176 @@ +/** + * \file + * + * \brief DMA related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DMA_H_INCLUDED +#define _HPL_DMA_H_INCLUDED + +/** + * \addtogroup HPL DMA + * + * \section hpl_dma_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct _dma_resource; + +/** + * \brief DMA callback types + */ +enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; + +/** + * \brief DMA interrupt callbacks + */ +struct _dma_callbacks { + void (*transfer_done)(struct _dma_resource *resource); + void (*error)(struct _dma_resource *resource); +}; + +/** + * \brief DMA resource structure + */ +struct _dma_resource { + struct _dma_callbacks dma_cb; + void * back; +}; + +/** + * \brief Initialize DMA + * + * This function does low level DMA configuration. + * + * \return initialize status + */ +int32_t _dma_init(void); + +/** + * \brief Set destination address + * + * \param[in] channel DMA channel to set destination address for + * \param[in] dst Destination address + * + * \return setting status + */ +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); + +/** + * \brief Set source address + * + * \param[in] channel DMA channel to set source address for + * \param[in] src Source address + * + * \return setting status + */ +int32_t _dma_set_source_address(const uint8_t channel, const void *const src); + +/** + * \brief Set next descriptor address + * + * \param[in] current_channel Current DMA channel to set next descriptor address + * \param[in] next_channel Next DMA channel used as next descriptor + * + * \return setting status + */ +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel); + +/** + * \brief Enable/disable source address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set source address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); + +/** + * \brief Enable/disable Destination address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set destination address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable); +/** + * \brief Set the amount of data to be transfered per transaction + * + * \param[in] channel DMA channel to set data amount for + * \param[in] amount Data amount + * + * \return status of operation + */ +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); + +/** + * \brief Trigger DMA transaction on the given channel + * + * \param[in] channel DMA channel to trigger transaction on + * + * \return status of operation + */ +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); + +/** + * \brief Retrieves DMA resource structure + * + * \param[out] resource The resource to be retrieved + * \param[in] channel DMA channel to retrieve structure for + * + * \return status of operation + */ +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); + +/** + * \brief Enable/disable DMA interrupt + * + * \param[in] channel DMA channel to enable/disable interrupt for + * \param[in] type The type of interrupt to disable/enable if applicable + * \param[in] state Enable or disable + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_DMA_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_gpio.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_gpio.h new file mode 100644 index 0000000..5cdd387 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_gpio.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief Port related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GPIO_H_INCLUDED +#define _HPL_GPIO_H_INCLUDED + +/** + * \addtogroup HPL Port + * + * \section hpl_port_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \brief Macros for the pin and port group, lower 5 + * bits stands for pin number in the group, higher 3 + * bits stands for port group + */ +#define GPIO_PIN(n) (((n)&0x1Fu) << 0) +#define GPIO_PORT(n) ((n) >> 5) +#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) +#define GPIO_PIN_FUNCTION_OFF 0xffffffff + +/** + * \brief PORT pull mode settings + */ +enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; + +/** + * \brief PORT direction settins + */ +enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; + +/** + * \brief PORT group abstraction + */ + +enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Port initialization function + * + * Port initialization function should setup the port module based + * on a static configuration file, this function should normally + * not be called directly, but is a part of hal_init() + */ +void _gpio_init(void); + +/** + * \brief Set direction on port with mask + * + * Set data direction for each pin, or disable the pin + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input + * and disable input buffer to disable the pin + * GPIO_DIRECTION_IN = set pin direction to input + * and enable input buffer to enable the pin + * GPIO_DIRECTION_OUT = set pin direction to output + * and disable input buffer + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction); + +/** + * \brief Set output level on port with mask + * + * Sets output state on pin to high or low with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + * \param[in] level true = pin level is set to 1 + * false = pin level is set to 0 + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); + +/** + * \brief Change output level to the opposite with mask + * + * Change pin output level to the opposite with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); + +/** + * \brief Get input levels on all port pins + * + * Get input level on all port pins, will read IN register if configured to + * input and OUT register if configured as output + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port); + +/** + * \brief Set pin pull mode + * + * Set pull mode on a single pin + * + * \notice This function will automatically change pin direction to input + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] pin The pin in the group that pull mode should be selected + * for + * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled + * GPIO_PULL_DOWN = pull resistor on pin will pull pin + * level to ground level + * GPIO_PULL_UP = pull resistor on pin will pull pin + * level to VCC + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode); + +/** + * \brief Set gpio function + * + * Select which function a gpio is used for + * + * \param[in] gpio The gpio to set function for + * \param[in] function The gpio function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); + +#include +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_i2c_m_async.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_i2c_m_async.h new file mode 100644 index 0000000..8a9491d --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_i2c_m_async.h @@ -0,0 +1,205 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED +#define _HPL_I2C_M_ASYNC_H_INCLUDED + +#include "hpl_i2c_m_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c master callback names + */ +enum _i2c_m_async_callback_type { + I2C_M_ASYNC_DEVICE_ERROR, + I2C_M_ASYNC_DEVICE_TX_COMPLETE, + I2C_M_ASYNC_DEVICE_RX_COMPLETE +}; + +struct _i2c_m_async_device; + +typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); +typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); + +/** + * \brief i2c callback pointers structure + */ +struct _i2c_m_async_callback { + _i2c_error_cb_t error; + _i2c_complete_cb_t tx_complete; + _i2c_complete_cb_t rx_complete; +}; + +/** + * \brief i2c device structure + */ +struct _i2c_m_async_device { + struct _i2c_m_service service; + void * hw; + struct _i2c_m_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C in interrupt mode + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c interrupt device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C in interrupt mode + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Register callback to I2C + * + * This function does low level I2C callback register. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] cb_type The callback type request + * \param[in] func The callback function pointer + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, + FUNC_PTR func); + +/** + * \brief Generate stop condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Operation status + * \retval 0 Operation executed successfully + * \retval <0 Operation failed + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Returns the number of bytes left or not used in the I2C message buffer + * + * This function will return the number of bytes left (not written to the bus) or still free + * (not received from the bus) in the message buffer, depending on direction of transmission. + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Number of bytes or error code + * \retval >0 Positive number indicating bytes left + * \retval 0 Buffer is full/empty depending on direction + * \retval <0 Error code + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable/disable I2C master interrupt + * + * param[in] device The pointer to I2C master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_i2c_m_sync.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_i2c_m_sync.h new file mode 100644 index 0000000..ce173ae --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_i2c_m_sync.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_SYNC_H_INCLUDED +#define _HPL_I2C_M_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c flags + */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_BUSY 0x0100 +#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ +#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ +#define I2C_M_FAIL 0x1000 +#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ + +/** + * \brief i2c Return codes + */ +#define I2C_OK 0 /* Operation successful */ +#define I2C_ACK -1 /* Received ACK from device on I2C bus */ +#define I2C_NACK -2 /* Received NACK from device on I2C bus */ +#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ +#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ +#define I2C_ERR_BUS -5 /* Bus error */ +#define I2C_ERR_BUSY -6 /* Device busy */ +#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ + +/** + * \brief i2c I2C Modes + */ +#define I2C_STANDARD_MODE 0x00 +#define I2C_FASTMODE 0x01 +#define I2C_HIGHSPEED_MODE 0x02 + +/** + * \brief i2c master message structure + */ +struct _i2c_m_msg { + uint16_t addr; + volatile uint16_t flags; + int32_t len; + uint8_t * buffer; +}; + +/** + * \brief i2c master service + */ +struct _i2c_m_service { + struct _i2c_m_msg msg; + uint16_t mode; + uint16_t trise; +}; + +/** + * \brief i2c sync master device structure + */ +struct _i2c_m_sync_device { + struct _i2c_m_service service; + void * hw; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Send send condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_dev The pointer to i2c device struct + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_i2c_s_async.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_i2c_s_async.h new file mode 100644 index 0000000..92a5765 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_i2c_s_async.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED +#define _HPL_I2C_S_ASYNC_H_INCLUDED + +#include "hpl_i2c_s_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c callback types + */ +enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; + +/** + * \brief Forward declaration of I2C Slave device + */ +struct _i2c_s_async_device; + +/** + * \brief i2c slave callback function type + */ +typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); + +/** + * \brief i2c slave callback pointers structure + */ +struct _i2c_s_async_callback { + void (*error)(struct _i2c_s_async_device *const device); + void (*tx)(struct _i2c_s_async_device *const device); + void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); +}; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_async_device { + void * hw; + struct _i2c_s_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize asynchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c interrupt device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); + +/** + * \brief Deinitialize asynchronous I2C in interrupt mode + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); + +/** + * \brief Abort data transmission + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); + +/** + * \brief Enable/disable I2C slave interrupt + * + * param[in] device The pointer to I2C slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool disable); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_i2c_s_sync.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_i2c_s_sync.h new file mode 100644 index 0000000..93b5934 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_i2c_s_sync.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_SYNC_H_INCLUDED +#define _HPL_I2C_S_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I2C Slave status type + */ +typedef uint32_t i2c_s_status_t; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_sync_device { + void *hw; +}; + +#include + +/** + * \name HPL functions + */ + +/** + * \brief Initialize synchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize synchronous I2C slave + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); + +/** + * \brief Clear the Data Ready interrupt flag + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device); + +/** + * \brief Read a byte from the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Data received via I2C interface. + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if I2C is ready to send next byte + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the ready check. + * \retval true if the I2C is ready to send next byte + * \retval false if the I2C is not ready to send next byte + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if there is data received by I2C + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the data received check. + * \retval true if the I2C has received a byte + * \retval false if the I2C has not received a byte + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_init.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_init.h new file mode 100644 index 0000000..71bf49c --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_init.h @@ -0,0 +1,124 @@ +/** + * \file + * + * \brief Init related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_INIT_H_INCLUDED +#define _HPL_INIT_H_INCLUDED + +/** + * \addtogroup HPL Init + * + * \section hpl_init_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initializes clock sources + */ +void _sysctrl_init_sources(void); + +/** + * \brief Initializes Power Manager + */ +void _pm_init(void); + +/** + * \brief Initialize generators + */ +void _gclk_init_generators(void); + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void); + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _sysctrl_init_referenced_generators(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _oscctrl_init_referenced_generators(void); + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void); + +/** + * \brief Initialize clock generator + */ +void _lpmcu_misc_regs_init(void); + +/** + * \brief Initialize clock generator + */ +void _pmc_init(void); + +/** + * \brief Set performance level + * + * \param[in] level The performance level to set + */ +void _set_performance_level(const uint8_t level); + +/** + * \brief Initialize the chip + */ +void _init_chip(void); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_irq.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_irq.h new file mode 100644 index 0000000..2894944 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_irq.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief IRQ related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_IRQ_H_INCLUDED +#define _HPL_IRQ_H_INCLUDED + +/** + * \addtogroup HPL IRQ + * + * \section hpl_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief IRQ descriptor + */ +struct _irq_descriptor { + void (*handler)(void *parameter); + void *parameter; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve current IRQ number + * + * \return The current IRQ number + */ +uint8_t _irq_get_current(void); + +/** + * \brief Disable the given IRQ + * + * \param[in] n The number of IRQ to disable + */ +void _irq_disable(uint8_t n); + +/** + * \brief Set the given IRQ + * + * \param[in] n The number of IRQ to set + */ +void _irq_set(uint8_t n); + +/** + * \brief Clear the given IRQ + * + * \param[in] n The number of IRQ to clear + */ +void _irq_clear(uint8_t n); + +/** + * \brief Enable the given IRQ + * + * \param[in] n The number of IRQ to enable + */ +void _irq_enable(uint8_t n); + +/** + * \brief Register IRQ handler + * + * \param[in] number The number registered IRQ + * \param[in] irq The pointer to irq handler to register + * + * \return The status of IRQ handler registering + * \retval -1 Passed parameters were invalid + * \retval 0 The registering is completed successfully + */ +void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_missing_features.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_missing_features.h new file mode 100644 index 0000000..7071db2 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_missing_features.h @@ -0,0 +1,37 @@ +/** + * \file + * + * \brief Family-dependent missing features expected by HAL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_MISSING_FEATURES +#define _HPL_MISSING_FEATURES + +#endif /* _HPL_MISSING_FEATURES */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_reset.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_reset.h new file mode 100644 index 0000000..28e4c96 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_reset.h @@ -0,0 +1,92 @@ +/** + * \file + * + * \brief Reset related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RESET_H_INCLUDED +#define _HPL_RESET_H_INCLUDED + +/** + * \addtogroup HPL Reset + * + * \section hpl_reset_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Reset reason enumeration + * + * The list of possible reset reasons. + */ +enum reset_reason { + + RESET_REASON_POR = 1, + RESET_REASON_BODCORE = 2, + RESET_REASON_BODVDD = 4, + RESET_REASON_EXT = 16, + RESET_REASON_WDT = 32, + RESET_REASON_SYST = 64 +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve the reset reason + * + * Retrieves the reset reason of the last MCU reset. + * + *\return An enum value indicating the reason of the last reset. + */ +enum reset_reason _get_reset_reason(void); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_sleep.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_sleep.h new file mode 100644 index 0000000..6731ec3 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_sleep.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SLEEP_H_INCLUDED +#define _HPL_SLEEP_H_INCLUDED + +/** + * \addtogroup HPL Sleep + * + * \section hpl_sleep_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Set the sleep mode for the device + * + * This function sets the sleep mode for the device. + * For an overview of which systems are disabled in sleep for the different + * sleep modes see datasheet. + * + * \param[in] mode Sleep mode to use + * + * \return the status of a sleep request + * \retval -1 The requested sleep mode was invalid + * \retval 0 The operation completed successfully, sleep mode is set + */ +int32_t _set_sleep_mode(const uint8_t mode); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi.h new file mode 100644 index 0000000..a5652e5 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi.h @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_H_INCLUDED +#define _HPL_SPI_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SPI Dummy char is used when reading data from the SPI slave + */ +#define SPI_DUMMY_CHAR 0x1ff + +/** + * \brief SPI message to let driver to process + */ +//@{ +struct spi_msg { + /** Pointer to the output data buffer */ + uint8_t *txbuf; + /** Pointer to the input data buffer */ + uint8_t *rxbuf; + /** Size of the message data in SPI characters */ + uint32_t size; +}; +//@} + +/** + * \brief SPI transfer modes + * SPI transfer mode controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + */ +enum spi_transfer_mode { + /** Leading edge is rising edge, data sample on leading edge. */ + SPI_MODE_0, + /** Leading edge is rising edge, data sample on trailing edge. */ + SPI_MODE_1, + /** Leading edge is falling edge, data sample on leading edge. */ + SPI_MODE_2, + /** Leading edge is falling edge, data sample on trailing edge. */ + SPI_MODE_3 +}; + +/** + * \brief SPI character sizes + * The character size influence the way the data is sent/received. + * For char size <= 8 data is stored byte by byte. + * For char size between 9 ~ 16 data is stored in 2-byte length. + * Note that the default and recommended char size is 8 bit since it's + * supported by all system. + */ +enum spi_char_size { + /** Character size is 8 bit. */ + SPI_CHAR_SIZE_8 = 0, + /** Character size is 9 bit. */ + SPI_CHAR_SIZE_9 = 1, + /** Character size is 10 bit. */ + SPI_CHAR_SIZE_10 = 2, + /** Character size is 11 bit. */ + SPI_CHAR_SIZE_11 = 3, + /** Character size is 12 bit. */ + SPI_CHAR_SIZE_12 = 4, + /** Character size is 13 bit. */ + SPI_CHAR_SIZE_13 = 5, + /** Character size is 14 bit. */ + SPI_CHAR_SIZE_14 = 6, + /** Character size is 15 bit. */ + SPI_CHAR_SIZE_15 = 7, + /** Character size is 16 bit. */ + SPI_CHAR_SIZE_16 = 8 +}; + +/** + * \brief SPI data order + */ +enum spi_data_order { + /** MSB goes first. */ + SPI_DATA_ORDER_MSB_1ST = 0, + /** LSB goes first. */ + SPI_DATA_ORDER_LSB_1ST = 1 +}; + +/** \brief Transfer descriptor for SPI + * Transfer descriptor holds TX and RX buffers + */ +struct spi_xfer { + /** Pointer to data buffer to TX */ + uint8_t *txbuf; + /** Pointer to data buffer to RX */ + uint8_t *rxbuf; + /** Size of data characters to TX & RX */ + uint32_t size; +}; + +/** SPI generic driver. */ +struct spi_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Reference start of sync/async variables */ + uint32_t sync_async_misc[1]; +}; + +/** + * \brief Calculate the baudrate value for hardware to use to set baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] clk Clock frequency (Hz) for baudrate generation. + * \param[in] baud Target baudrate (bps). + * \return Error or baudrate value. + * \retval >0 Baudrate value. + * \retval ERR_INVALID_ARG Calculation fail. + */ +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_async.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_async.h new file mode 100644 index 0000000..8e5a848 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_async.h @@ -0,0 +1,131 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_ASYNC_H_INCLUDED +#define _HPL_SPI_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Callbacks the SPI driver must offer in async mode + */ +//@{ +/** The callback types */ +enum _spi_async_dev_cb_type { + /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_TX, + /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_RX, + /** Callback type for \ref _spi_async_dev_cb_complete_t. */ + SPI_DEV_CB_COMPLETE, + /** Callback type for error */ + SPI_DEV_CB_ERROR, + /** Number of callbacks. */ + SPI_DEV_CB_N +}; + +struct _spi_async_dev; + +/** \brief The prototype for callback on SPI transfer error. + * If status code is zero, it indicates the normal completion, that is, + * SS deactivation. + * If status code belows zero, it indicates complete. + */ +typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status); + +/** \brief The prototype for callback on SPI transmit/receive event + * For TX, the callback is invoked when transmit is done or ready to start + * transmit. + * For RX, the callback is invoked when receive is done or ready to read data, + * see \ref _spi_async_dev_read_one_t on data reading. + * Without DMA enabled, the callback is invoked on each character event. + * With DMA enabled, the callback is invoked on DMA buffer done. + */ +typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_async_dev_callbacks { + /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t tx; + /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t rx; + /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ + _spi_async_dev_cb_xfer_t complete; + /** Error callback, see \ref */ + _spi_async_dev_cb_error_t err; +}; +//@} + +/** + * \brief SPI async driver + */ +//@{ + +/** SPI driver to support async HAL */ +struct _spi_async_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; + + /** \brief Pointer to callback functions, ignored for polling mode + * Pointer to the callback functions so that initialize the driver to + * handle interrupts. + */ + struct _spi_async_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; +}; +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_m_async.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_m_async.h new file mode 100644 index 0000000..8d3555e --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_m_async.h @@ -0,0 +1,243 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED +#define _HPL_SPI_M_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_m_async_dev _spi_async_dev + +#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on after data transmission complate + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_m_dma.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_m_dma.h new file mode 100644 index 0000000..2b48300 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_m_dma.h @@ -0,0 +1,182 @@ +/** + * \file + * + * \brief SPI Master DMA related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_DMA_H_INCLUDED +#define _HPL_SPI_M_DMA_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI dma device driver. */ +#define _spi_m_dma_dev _spi_dma_dev + +#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); + +/** + * \brief Register the SPI device callback + * \param[in] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); + +/** \brief Do SPI data transfer (TX & RX) with DMA + * Log the TX & RX buffers and transfer them in background. It never blocks. + * + * \param[in] dev Pointer to the SPI device instance. + * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). + * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). + * \param[in] length spi transfer data length. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy. + */ +int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, + const uint16_t length); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_m_sync.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_m_sync.h new file mode 100644 index 0000000..38df15b --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_m_sync.h @@ -0,0 +1,166 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_SYNC_H_INCLUDED +#define _HPL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_m_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); + +/** + * \brief Deinitialize SPI + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI char size + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Transfer the whole message without interrupt + * Transfer the message, it will keep waiting until the message finish or + * error. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] msg Pointer to the message instance to process. + * \return Error or number of characters transferred. + * \retval ERR_BUSY SPI hardware is not ready to start transfer (not + * enabled, busy applying settings, ...). + * \retval SPI_ERR_OVERFLOW Overflow error. + * \retval >=0 Number of characters transferred. + */ +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_s_async.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_s_async.h new file mode 100644 index 0000000..5647243 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_s_async.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED +#define _HPL_SPI_S_ASYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_s_async_dev _spi_async_dev + +#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on Slave Select (SS) rising + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_s_sync.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_s_sync.h new file mode 100644 index 0000000..ff4c811 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_s_sync.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_SYNC_H_INCLUDED +#define _HPL_SPI_S_SYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_s_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retval 0 OK Status + */ +int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); + +/** + * \brief Check if TX ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return TX ready state + * \retval true TX ready + * \retval false TX not ready + */ +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if RX character ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return RX character ready state + * \retval true RX character ready + * \retval false RX character not ready + */ +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if SS deactiviation detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return SS deactiviation state + * \retval true SS deactiviation detected + * \retval false SS deactiviation not detected + */ +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if error is detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return Error detection state + * \retval true Error detected + * \retval false Error not detected + */ +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_sync.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_sync.h new file mode 100644 index 0000000..dc88648 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_spi_sync.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_SYNC_H_INCLUDED +#define _HPL_SPI_SYNC_H_INCLUDED + +#include +#include + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * \section hpl_spi_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI driver to support sync HAL */ +struct _spi_sync_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; +}; + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_usart.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_usart.h new file mode 100644 index 0000000..0e09501 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_usart.h @@ -0,0 +1,113 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_H_INCLUDED +#define _HPL_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART flow control state + */ +union usart_flow_control_state { + struct { + uint8_t cts : 1; + uint8_t rts : 1; + uint8_t unavailable : 1; + uint8_t reserved : 5; + } bit; + uint8_t value; +}; + +/** + * \brief USART baud rate mode + */ +enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; + +/** + * \brief USART data order + */ +enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; + +/** + * \brief USART mode + */ +enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; + +/** + * \brief USART parity + */ +enum usart_parity { + USART_PARITY_EVEN = 0, + USART_PARITY_ODD = 1, + USART_PARITY_NONE = 2, + USART_PARITY_SPACE = 3, + USART_PARITY_MARK = 4 +}; + +/** + * \brief USART stop bits mode + */ +enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; + +/** + * \brief USART character size + */ +enum usart_character_size { + USART_CHARACTER_SIZE_8BITS = 0, + USART_CHARACTER_SIZE_9BITS = 1, + USART_CHARACTER_SIZE_5BITS = 5, + USART_CHARACTER_SIZE_6BITS = 6, + USART_CHARACTER_SIZE_7BITS = 7 +}; + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_usart_async.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_usart_async.h new file mode 100644 index 0000000..3f833d1 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_usart_async.h @@ -0,0 +1,270 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_ASYNC_H_INCLUDED +#define _HPL_USART_ASYNC_H_INCLUDED + +/** + * \addtogroup HPL USART + * + * \section hpl_usart_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_usart.h" +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART callback types + */ +enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; + +/** + * \brief USART device structure + * + * The USART device structure forward declaration. + */ +struct _usart_async_device; + +/** + * \brief USART interrupt callbacks + */ +struct _usart_async_callbacks { + void (*tx_byte_sent)(struct _usart_async_device *device); + void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); + void (*tx_done_cb)(struct _usart_async_device *device); + void (*error_cb)(struct _usart_async_device *device); +}; + +/** + * \brief USART descriptor device structure + */ +struct _usart_async_device { + struct _usart_async_callbacks usart_cb; + struct _irq_descriptor irq; + void * hw; +}; +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize asynchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_deinit(struct _usart_async_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable(struct _usart_async_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_disable(struct _usart_async_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); + +/** + * \brief Enable data register empty interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); + +/** + * \brief Enable transmission complete interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); + +/** + * \brief Enable/disable USART interrupt + * + * param[in] device The pointer to USART device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_usart_sync.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_usart_sync.h new file mode 100644 index 0000000..abc7264 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/include/hpl_usart_sync.h @@ -0,0 +1,254 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SYNC_USART_H_INCLUDED +#define _HPL_SYNC_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor device structure + */ +struct _usart_sync_device { + void *hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_deinit(struct _usart_sync_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_enable(struct _usart_sync_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_disable(struct _usart_sync_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); + +/** + * \brief Read a byte from the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + * + * \return Data received via USART interface. + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART transmitter has sent the byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART transmitter has sent the byte + * \retval false if the USART transmitter has not send the byte + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device); + +/** + * \brief Check if there is data received by USART + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the data received check. + * \retval true if the USART has received a byte + * \retval false if the USART has not received a byte + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_atomic.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_atomic.c new file mode 100644 index 0000000..f56418e --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_atomic.c @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief Critical sections related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_atomic.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Disable interrupts, enter critical section + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic) +{ + *atomic = __get_PRIMASK(); + __disable_irq(); + __DMB(); +} + +/** + * \brief Exit atomic section + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic) +{ + __DMB(); + __set_PRIMASK(*atomic); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t atomic_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_delay.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_delay.c new file mode 100644 index 0000000..6f77cc7 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_delay.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief HAL delay related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include "hal_delay.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief The pointer to a hardware instance used by the driver. + */ +static void *hardware; + +/** + * \brief Initialize Delay driver + */ +void delay_init(void *const hw) +{ + _delay_init(hardware = hw); +} + +/** + * \brief Perform delay in us + */ +void delay_us(const uint16_t us) +{ + _delay_cycles(hardware, _get_cycles_for_us(us)); +} + +/** + * \brief Perform delay in ms + */ +void delay_ms(const uint16_t ms) +{ + _delay_cycles(hardware, _get_cycles_for_ms(ms)); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t delay_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_gpio.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_gpio.c new file mode 100644 index 0000000..00dfea6 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_gpio.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_gpio.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t gpio_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_init.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_init.c new file mode 100644 index 0000000..fb65341 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_init.c @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief HAL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_init.h" + +/** + * \brief Driver version + */ +#define HAL_INIT_VERSION 0x00000001u + +/** + * \brief Retrieve the current driver version + */ +uint32_t init_get_version(void) +{ + return HAL_INIT_VERSION; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_io.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_io.c new file mode 100644 index 0000000..7e8feb0 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_io.c @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief I/O functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t io_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \brief I/O write interface + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->write(io_descr, buf, length); +} + +/** + * \brief I/O read interface + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->read(io_descr, buf, length); +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_sleep.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_sleep.c new file mode 100644 index 0000000..89472f1 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_sleep.c @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Sleep related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_sleep.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode) +{ + if (ERR_NONE != _set_sleep_mode(mode)) + return ERR_INVALID_ARG; + + _go_to_sleep(); + + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version + */ +uint32_t sleep_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_spi_s_sync.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_spi_s_sync.c new file mode 100644 index 0000000..0498769 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_spi_s_sync.c @@ -0,0 +1,262 @@ +/** + * \file + * + * \brief I/O SPI related functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_atomic.h" +#include "hal_spi_s_sync.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Driver version + */ +#define SPI_S_SYNC_DRIVER_VERSION 0x00000001u + +/** Enable TX in transfer. */ +#define SPI_XFER_TX_EN (1u << 0) +/** Enable RX in transfer. */ +#define SPI_XFER_RX_EN (1u << 1) + +/** + * \brief Transfer data + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] xfer Pointer to the transfer struct instance. + * \param[in] flags control options. + * \return Error or number of characters transferred. + * \retval <0 Error. + * \retval >=0 Number of characters transferred. + */ +static int32_t _spi_s_sync_xfer(struct spi_s_sync_descriptor *spi, const struct spi_xfer *xfer, const uint8_t flags) +{ + uint32_t txcnt, rxcnt; + union { + uint16_t u16; + uint8_t u8[4]; + } tmp; + uint32_t n_bytes; + + ASSERT(spi && xfer); + + if (xfer->size == 0) { + return 0; + } + + n_bytes = xfer->size; + if (spi->dev.char_size > 1) { + n_bytes <<= 1; + } + + tmp.u16 = 0; + for (txcnt = 0, rxcnt = 0; txcnt < n_bytes && rxcnt < n_bytes;) { + if (_spi_s_sync_is_error(&spi->dev)) { + return ERR_IO; + } + if ((flags & SPI_XFER_TX_EN) && _spi_s_sync_is_tx_ready(&spi->dev)) { + tmp.u8[0] = xfer->txbuf[txcnt++]; + if (spi->dev.char_size > 1) { + tmp.u8[1] = xfer->txbuf[txcnt++]; + } + _spi_s_sync_write_one(&spi->dev, tmp.u16); + } + if ((flags & SPI_XFER_RX_EN) && _spi_s_sync_is_rx_ready(&spi->dev)) { + tmp.u16 = _spi_s_sync_read_one(&spi->dev); + + if (xfer->rxbuf) { + xfer->rxbuf[rxcnt++] = tmp.u8[0]; + if (spi->dev.char_size > 1) { + xfer->rxbuf[rxcnt++] = tmp.u8[1]; + } + } + } + if (spi->break_on_ss_det && _spi_s_sync_is_ss_deactivated(&spi->dev)) { + break; + } + } + + if (spi->dev.char_size <= 1) { + return (flags & SPI_XFER_RX_EN) ? rxcnt : txcnt; + } + return ((flags & SPI_XFER_RX_EN) ? rxcnt : txcnt) >> 1; +} + +/** \brief Do SPI data write + * + * Register background buffer to transmit data. + * + * It never blocks and return quickly, user check status or set callback to + * know when data is sent. + * + * \param[in] io Pointer to the I/O descriptor. + * \param[in] buf Pointer to the buffer to store data to write. + * \param[in] size Size of the data in number of characters. + * \return Operation status. + * \retval 0 Success. + * \retval -1 Busy, transfer in progress. + * \retval -3 Parameter error. + */ +static int32_t _spi_s_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t size) +{ + struct spi_s_sync_descriptor *spi; + struct spi_xfer xfer; + + ASSERT(io); + + spi = CONTAINER_OF(io, struct spi_s_sync_descriptor, io); + + xfer.txbuf = (uint8_t *)buf; + xfer.size = size; + return _spi_s_sync_xfer(spi, &xfer, SPI_XFER_TX_EN); +} + +/** \brief Do SPI read from ring-buffer (asynchronously) + * + * Read available characters from ring-buffer and return number of characters + * read. + * + * It never blocks and return quickly, user check status or set callback to + * know when data is ready. + * + * \param[in] io Pointer to the I/O descriptor. + * \param[out] buf Pointer to the buffer to store read data, + NULL to discard data. + * \param[in] size Size of the data in number of characters. + * \return Read result. + * \retval n Number of characters read. + * \retval <0 Error. + */ +static int32_t _spi_s_sync_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t size) +{ + struct spi_s_sync_descriptor *spi; + struct spi_xfer xfer; + + ASSERT(io); + + spi = CONTAINER_OF(io, struct spi_s_sync_descriptor, io); + + xfer.rxbuf = (uint8_t *)buf; + xfer.size = size; + return _spi_s_sync_xfer(spi, &xfer, SPI_XFER_RX_EN); +} + +/** + * \brief Initialize the SPI HAL instance function pointer for HPL APIs. + */ +void spi_s_sync_set_func_ptr(struct spi_s_sync_descriptor *spi, void *const func) +{ + ASSERT(spi); + spi->func = (struct _spi_s_sync_hpl_interface *)func; +} + +int32_t spi_s_sync_init(struct spi_s_sync_descriptor *spi, void *const hw) +{ + int32_t rc; + ASSERT(spi && hw); + rc = _spi_s_sync_init(&spi->dev, hw); + + if (rc < 0) { + return rc; + } + + spi->io.read = _spi_s_sync_io_read; + spi->io.write = _spi_s_sync_io_write; + + return ERR_NONE; +} + +void spi_s_sync_deinit(struct spi_s_sync_descriptor *spi) +{ + ASSERT(spi); + _spi_s_sync_deinit(&spi->dev); +} + +void spi_s_sync_enable(struct spi_s_sync_descriptor *spi) +{ + ASSERT(spi); + _spi_s_sync_enable(&spi->dev); +} + +void spi_s_sync_disable(struct spi_s_sync_descriptor *spi) +{ + ASSERT(spi); + _spi_s_sync_disable(&spi->dev); +} + +int32_t spi_s_sync_set_mode(struct spi_s_sync_descriptor *spi, const enum spi_transfer_mode mode) +{ + ASSERT(spi); + return _spi_s_sync_set_mode(&spi->dev, mode); +} + +int32_t spi_s_sync_set_char_size(struct spi_s_sync_descriptor *spi, const enum spi_char_size char_size) +{ + ASSERT(spi); + return _spi_s_sync_set_char_size(&spi->dev, char_size); +} + +int32_t spi_s_sync_set_data_order(struct spi_s_sync_descriptor *spi, const enum spi_data_order dord) +{ + ASSERT(spi); + return _spi_s_sync_set_data_order(&spi->dev, dord); +} + +void spi_s_sync_break_on_ss_detect(struct spi_s_sync_descriptor *spi, const bool enable) +{ + ASSERT(spi); + + spi->break_on_ss_det = enable; +} + +int32_t spi_s_sync_transfer(struct spi_s_sync_descriptor *spi, const struct spi_xfer *xfer) +{ + return _spi_s_sync_xfer(spi, xfer, SPI_XFER_RX_EN | SPI_XFER_TX_EN); +} + +int32_t spi_s_sync_get_io_descriptor(struct spi_s_sync_descriptor *spi, struct io_descriptor **io) +{ + ASSERT(spi && io); + *io = &spi->io; + return ERR_NONE; +} + +uint32_t spi_s_sync_get_version(void) +{ + return SPI_S_SYNC_DRIVER_VERSION; +} + +#ifdef __cplusplus +} +#endif diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_usart_sync.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_usart_sync.c new file mode 100644 index 0000000..ab99c1d --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/src/hal_usart_sync.c @@ -0,0 +1,276 @@ +/** + * \file + * + * \brief I/O USART related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_usart_sync.h" +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief Initialize usart interface + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) +{ + int32_t init_status; + ASSERT(descr && hw); + init_status = _usart_sync_init(&descr->device, hw); + if (init_status) { + return init_status; + } + + descr->io.read = usart_sync_read; + descr->io.write = usart_sync_write; + + return ERR_NONE; +} + +/** + * \brief Uninitialize usart interface + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_deinit(&descr->device); + + descr->io.read = NULL; + descr->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable usart interface + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Disable usart interface + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) +{ + ASSERT(descr && io); + + *io = &descr->io; + return ERR_NONE; +} + +/** + * \brief Specify action for flow control pins + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state) +{ + ASSERT(descr); + _usart_sync_set_flow_control_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Set usart baud rate + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) +{ + ASSERT(descr); + _usart_sync_set_baud_rate(&descr->device, baud_rate); + + return ERR_NONE; +} + +/** + * \brief Set usart data order + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) +{ + ASSERT(descr); + _usart_sync_set_data_order(&descr->device, data_order); + + return ERR_NONE; +} + +/** + * \brief Set usart mode + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) +{ + ASSERT(descr); + _usart_sync_set_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set usart parity + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) +{ + ASSERT(descr); + _usart_sync_set_parity(&descr->device, parity); + + return ERR_NONE; +} + +/** + * \brief Set usart stop bits + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) +{ + ASSERT(descr); + _usart_sync_set_stop_bits(&descr->device, stop_bits); + + return ERR_NONE; +} + +/** + * \brief Set usart character size + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) +{ + ASSERT(descr); + _usart_sync_set_character_size(&descr->device, size); + + return ERR_NONE; +} + +/** + * \brief Retrieve the state of flow control pins + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state) +{ + ASSERT(descr && state); + *state = _usart_sync_get_flow_control_state(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Check if the usart transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_ready_to_send(&descr->device); +} + +/** + * \brief Check if the usart receiver is not empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_byte_received(&descr->device); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t usart_sync_get_version(void) +{ + return DRIVER_VERSION; +} + +/* + * \internal Write the given data to usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf Data to write to usart + * \param[in] length The number of bytes to write + * + * \return The number of bytes written. + */ +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + do { + _usart_sync_write_byte(&descr->device, buf[offset]); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + } while (++offset < length); + while (!_usart_sync_is_transmit_done(&descr->device)) + ; + return (int32_t)offset; +} + +/* + * \internal Read data from usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + do { + while (!_usart_sync_is_byte_received(&descr->device)) + ; + buf[offset] = _usart_sync_read_byte(&descr->device); + } while (++offset < length); + + return (int32_t)offset; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/compiler.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/compiler.h new file mode 100644 index 0000000..f35db3d --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/compiler.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Header + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +/****************************************************************************** + * compiler.h + * + * Created: 05.05.2014 + * Author: N. Fomin + ******************************************************************************/ + +#ifndef _COMPILER_H +#define _COMPILER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef _UNIT_TEST_ +#include "parts.h" +#endif +#include "err_codes.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _COMPILER_H */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/err_codes.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/err_codes.h new file mode 100644 index 0000000..a7aff01 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/err_codes.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Error code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ERROR_CODES_H_INCLUDED +#define ERROR_CODES_H_INCLUDED + +#define ERR_NONE 0 +#define ERR_INVALID_DATA -1 +#define ERR_NO_CHANGE -2 +#define ERR_ABORTED -3 +#define ERR_BUSY -4 +#define ERR_SUSPEND -5 +#define ERR_IO -6 +#define ERR_REQ_FLUSHED -7 +#define ERR_TIMEOUT -8 +#define ERR_BAD_DATA -9 +#define ERR_NOT_FOUND -10 +#define ERR_UNSUPPORTED_DEV -11 +#define ERR_NO_MEMORY -12 +#define ERR_INVALID_ARG -13 +#define ERR_BAD_ADDRESS -14 +#define ERR_BAD_FORMAT -15 +#define ERR_BAD_FRQ -16 +#define ERR_DENIED -17 +#define ERR_ALREADY_INITIALIZED -18 +#define ERR_OVERFLOW -19 +#define ERR_NOT_INITIALIZED -20 +#define ERR_SAMPLERATE_UNAVAILABLE -21 +#define ERR_RESOLUTION_UNAVAILABLE -22 +#define ERR_BAUDRATE_UNAVAILABLE -23 +#define ERR_PACKET_COLLISION -24 +#define ERR_PROTOCOL -25 +#define ERR_PIN_MUX_INVALID -26 +#define ERR_UNSUPPORTED_OP -27 +#define ERR_NO_RESOURCE -28 +#define ERR_NOT_READY -29 +#define ERR_FAILURE -30 +#define ERR_WRONG_LENGTH -31 + +#endif diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/events.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/events.h new file mode 100644 index 0000000..3ee891a --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/events.h @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _EVENTS_H_INCLUDED +#define _EVENTS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \brief List of events. Must start with 0, be unique and follow numerical order. + */ +#define EVENT_IS_READY_TO_SLEEP_ID 0 +#define EVENT_PREPARE_TO_SLEEP_ID 1 +#define EVENT_WOKEN_UP_ID 2 + +#ifdef __cplusplus +} +#endif + +#endif /* _EVENTS_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/parts.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/parts.h new file mode 100644 index 0000000..a953586 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/parts.h @@ -0,0 +1,41 @@ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +#include "samc21.h" + +#include "hri_c21.h" + +#endif /* ATMEL_PARTS_H */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils.h new file mode 100644 index 0000000..1cf2699 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils.h @@ -0,0 +1,368 @@ +/** + * \file + * + * \brief Different macros. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef UTILS_H_INCLUDED +#define UTILS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_macro + * + * @{ + */ + +/** + * \brief Retrieve pointer to parent structure + */ +#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) + +/** + * \brief Retrieve array size + */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param[in] arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set aligned boundary. + */ +#if defined __GNUC__ +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined __ICCARM__ +#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined __CC_ARM +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Flash located data macros + */ +#if defined __GNUC__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __ICCARM__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __CC_ARM +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#endif + +/** + * \brief Optimization + */ +#if defined __GNUC__ +#define OPTIMIZE_HIGH __attribute__((optimize(s))) +#elif defined __CC_ARM +#define OPTIMIZE_HIGH _Pragma("O3") +#elif defined __ICCARM__ +#define OPTIMIZE_HIGH _Pragma("optimize=high") +#endif + +/** + * \brief RAM located function attribute + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define RAMFUNC __ramfunc +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#endif + +/** + * \brief No-init section. + * Place a data object or a function in a no-init section. + */ +#if defined(__CC_ARM) +#define NO_INIT(a) __attribute__((zero_init)) +#elif defined(__ICCARM__) +#define NO_INIT(a) __no_init +#elif defined(__GNUC__) +#define NO_INIT(a) __attribute__((section(".no_init"))) +#endif + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined(__CC_ARM) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined(__ICCARM__) +#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined(__GNUC__) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Define WEAK attribute. + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define WEAK __attribute__((weak)) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define WEAK __weak +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define WEAK __attribute__((weak)) +#endif + +/** + * \brief Pointer to function + */ +typedef void (*FUNC_PTR)(void); + +#define LE_BYTE0(a) ((uint8_t)(a)) +#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) +#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) +#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) + +#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) +#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) + +/** \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + * + * @{ */ + +/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define clz(u) __builtin_clz(u) +#else +#define clz(u) \ + ( \ + ((u) == 0) \ + ? 32 \ + : ((u) & (1ul << 31)) \ + ? 0 \ + : ((u) & (1ul << 30)) \ + ? 1 \ + : ((u) & (1ul << 29)) \ + ? 2 \ + : ((u) & (1ul << 28)) \ + ? 3 \ + : ((u) & (1ul << 27)) \ + ? 4 \ + : ((u) & (1ul << 26)) \ + ? 5 \ + : ((u) & (1ul << 25)) \ + ? 6 \ + : ((u) & (1ul << 24)) \ + ? 7 \ + : ((u) & (1ul << 23)) \ + ? 8 \ + : ((u) & (1ul << 22)) \ + ? 9 \ + : ((u) & (1ul << 21)) \ + ? 10 \ + : ((u) & (1ul << 20)) \ + ? 11 \ + : ((u) & (1ul << 19)) \ + ? 12 \ + : ((u) & (1ul << 18)) \ + ? 13 \ + : ((u) & (1ul << 17)) ? 14 \ + : ((u) & (1ul << 16)) ? 15 \ + : ((u) & (1ul << 15)) ? 16 \ + : ((u) & (1ul << 14)) ? 17 \ + : ((u) & (1ul << 13)) ? 18 \ + : ((u) & (1ul << 12)) ? 19 \ + : ((u) \ + & (1ul \ + << 11)) \ + ? 20 \ + : ((u) \ + & (1ul \ + << 10)) \ + ? 21 \ + : ((u) \ + & (1ul \ + << 9)) \ + ? 22 \ + : ((u) \ + & (1ul \ + << 8)) \ + ? 23 \ + : ((u) & (1ul << 7)) ? 24 \ + : ((u) & (1ul << 6)) ? 25 \ + : ((u) \ + & (1ul \ + << 5)) \ + ? 26 \ + : ((u) & (1ul << 4)) ? 27 \ + : ((u) & (1ul << 3)) ? 28 \ + : ((u) & (1ul << 2)) ? 29 \ + : ( \ + (u) & (1ul << 1)) \ + ? 30 \ + : 31) +#endif + +/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define ctz(u) __builtin_ctz(u) +#else +#define ctz(u) \ + ( \ + (u) & (1ul << 0) \ + ? 0 \ + : (u) & (1ul << 1) \ + ? 1 \ + : (u) & (1ul << 2) \ + ? 2 \ + : (u) & (1ul << 3) \ + ? 3 \ + : (u) & (1ul << 4) \ + ? 4 \ + : (u) & (1ul << 5) \ + ? 5 \ + : (u) & (1ul << 6) \ + ? 6 \ + : (u) & (1ul << 7) \ + ? 7 \ + : (u) & (1ul << 8) \ + ? 8 \ + : (u) & (1ul << 9) \ + ? 9 \ + : (u) & (1ul << 10) \ + ? 10 \ + : (u) & (1ul << 11) \ + ? 11 \ + : (u) & (1ul << 12) \ + ? 12 \ + : (u) & (1ul << 13) \ + ? 13 \ + : (u) & (1ul << 14) \ + ? 14 \ + : (u) & (1ul << 15) \ + ? 15 \ + : (u) & (1ul << 16) \ + ? 16 \ + : (u) & (1ul << 17) \ + ? 17 \ + : (u) & (1ul << 18) \ + ? 18 \ + : (u) & (1ul << 19) ? 19 \ + : (u) & (1ul << 20) ? 20 \ + : (u) & (1ul << 21) ? 21 \ + : (u) & (1ul << 22) ? 22 \ + : (u) & (1ul << 23) ? 23 \ + : (u) & (1ul << 24) ? 24 \ + : (u) & (1ul << 25) ? 25 \ + : (u) & (1ul << 26) ? 26 \ + : (u) & (1ul << 27) ? 27 \ + : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32) +#endif +/** @} */ + +/** + * \brief Counts the number of bits in a mask (no more than 32 bits) + * \param[in] mask Mask of which to count the bits. + */ +#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) + +/** + * \brief Retrieve the start position of bits mask (no more than 32 bits) + * \param[in] mask Mask of which to retrieve the start position. + */ +#define pos_of_mask(mask) ctz(mask) + +/** + * \brief Return division result of a/b and round up the result to the closest + * number divisible by "b" + */ +#define round_up(a, b) (((a)-1) / (b) + 1) + +/** + * \brief Get the minimum of x and y + */ +#define min(x, y) ((x) > (y) ? (y) : (x)) + +/** + * \brief Get the maximum of x and y + */ +#define max(x, y) ((x) > (y) ? (x) : (y)) + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* UTILS_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_assert.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_assert.h new file mode 100644 index 0000000..c2328d6 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_assert.h @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _ASSERT_H_INCLUDED +#define _ASSERT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifndef USE_SIMPLE_ASSERT +//# define USE_SIMPLE_ASSERT +#endif + +/** + * \brief Assert macro + * + * This macro is used to throw asserts. It can be mapped to different function + * based on debug level. + * + * \param[in] condition A condition to be checked; + * assert is thrown if the given condition is false + */ +#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) + +#ifdef DEBUG + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) \ + if (!(condition)) \ + __asm("BKPT #0"); +#else +#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) +#endif + +#else /* DEBUG */ + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) ((void)0) +#else +#define ASSERT_IMPL(condition, file, line) ((void)0) +#endif + +#endif /* DEBUG */ + +/** + * \brief Assert function + * + * This function is used to throw asserts. + * + * \param[in] condition A condition to be checked; assert is thrown if the given + * condition is false + * \param[in] file File name + * \param[in] line Line number + */ +void assert(const bool condition, const char *const file, const int line); + +#ifdef __cplusplus +} +#endif +#endif /* _ASSERT_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_event.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_event.h new file mode 100644 index 0000000..13067c4 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_event.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_EVENT_H_INCLUDED +#define _UTILS_EVENT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * \brief The maximum amount of events + */ +#define EVENT_MAX_AMOUNT 8 + +/** + * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the + * closest number divisible by 8. + */ +#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) + +/** + * \brief The type of event ID. IDs should start with 0 and be in numerical order. + */ +typedef uint8_t event_id_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef uintptr_t event_data_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef void (*event_cb_t)(event_id_t id, event_data_t data); + +/** + * \brief Event structure + */ +struct event { + struct list_element elem; /*! The pointer to next event */ + uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ + event_cb_t cb; /*! Callback to be called when an event occurs */ +}; + +/** + * \brief Subscribe to event + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to subscribe to + * \param[in] cb The callback function to call when the given event occurs + * + * \return The status of subscription + */ +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); + +/** + * \brief Remove event from subscription + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to remove subscription from + * + * \return The status of subscription removing + */ +int32_t event_unsubscribe(struct event *const event, const event_id_t id); + +/** + * \brief Post event + * + * \param[in] id The event ID to post + * \param[in] data The event data to be passed to event subscribers + */ +void event_post(const event_id_t id, const event_data_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_increment_macro.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_increment_macro.h new file mode 100644 index 0000000..464c6cb --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_increment_macro.h @@ -0,0 +1,308 @@ +/** + * \file + * + * \brief Increment macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_INCREMENT_MACRO_H +#define _UTILS_INCREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time increment, result value is entire integer literal + * + * \param[in] val - value to be incremented (254 max) + */ +#define INC_VALUE(val) SP_INC_##val + +// Preprocessor increment implementation +#define SP_INC_0 1 +#define SP_INC_1 2 +#define SP_INC_2 3 +#define SP_INC_3 4 +#define SP_INC_4 5 +#define SP_INC_5 6 +#define SP_INC_6 7 +#define SP_INC_7 8 +#define SP_INC_8 9 +#define SP_INC_9 10 +#define SP_INC_10 11 +#define SP_INC_11 12 +#define SP_INC_12 13 +#define SP_INC_13 14 +#define SP_INC_14 15 +#define SP_INC_15 16 +#define SP_INC_16 17 +#define SP_INC_17 18 +#define SP_INC_18 19 +#define SP_INC_19 20 +#define SP_INC_20 21 +#define SP_INC_21 22 +#define SP_INC_22 23 +#define SP_INC_23 24 +#define SP_INC_24 25 +#define SP_INC_25 26 +#define SP_INC_26 27 +#define SP_INC_27 28 +#define SP_INC_28 29 +#define SP_INC_29 30 +#define SP_INC_30 31 +#define SP_INC_31 32 +#define SP_INC_32 33 +#define SP_INC_33 34 +#define SP_INC_34 35 +#define SP_INC_35 36 +#define SP_INC_36 37 +#define SP_INC_37 38 +#define SP_INC_38 39 +#define SP_INC_39 40 +#define SP_INC_40 41 +#define SP_INC_41 42 +#define SP_INC_42 43 +#define SP_INC_43 44 +#define SP_INC_44 45 +#define SP_INC_45 46 +#define SP_INC_46 47 +#define SP_INC_47 48 +#define SP_INC_48 49 +#define SP_INC_49 50 +#define SP_INC_50 51 +#define SP_INC_51 52 +#define SP_INC_52 53 +#define SP_INC_53 54 +#define SP_INC_54 55 +#define SP_INC_55 56 +#define SP_INC_56 57 +#define SP_INC_57 58 +#define SP_INC_58 59 +#define SP_INC_59 60 +#define SP_INC_60 61 +#define SP_INC_61 62 +#define SP_INC_62 63 +#define SP_INC_63 64 +#define SP_INC_64 65 +#define SP_INC_65 66 +#define SP_INC_66 67 +#define SP_INC_67 68 +#define SP_INC_68 69 +#define SP_INC_69 70 +#define SP_INC_70 71 +#define SP_INC_71 72 +#define SP_INC_72 73 +#define SP_INC_73 74 +#define SP_INC_74 75 +#define SP_INC_75 76 +#define SP_INC_76 77 +#define SP_INC_77 78 +#define SP_INC_78 79 +#define SP_INC_79 80 +#define SP_INC_80 81 +#define SP_INC_81 82 +#define SP_INC_82 83 +#define SP_INC_83 84 +#define SP_INC_84 85 +#define SP_INC_85 86 +#define SP_INC_86 87 +#define SP_INC_87 88 +#define SP_INC_88 89 +#define SP_INC_89 90 +#define SP_INC_90 91 +#define SP_INC_91 92 +#define SP_INC_92 93 +#define SP_INC_93 94 +#define SP_INC_94 95 +#define SP_INC_95 96 +#define SP_INC_96 97 +#define SP_INC_97 98 +#define SP_INC_98 99 +#define SP_INC_99 100 +#define SP_INC_100 101 +#define SP_INC_101 102 +#define SP_INC_102 103 +#define SP_INC_103 104 +#define SP_INC_104 105 +#define SP_INC_105 106 +#define SP_INC_106 107 +#define SP_INC_107 108 +#define SP_INC_108 109 +#define SP_INC_109 110 +#define SP_INC_110 111 +#define SP_INC_111 112 +#define SP_INC_112 113 +#define SP_INC_113 114 +#define SP_INC_114 115 +#define SP_INC_115 116 +#define SP_INC_116 117 +#define SP_INC_117 118 +#define SP_INC_118 119 +#define SP_INC_119 120 +#define SP_INC_120 121 +#define SP_INC_121 122 +#define SP_INC_122 123 +#define SP_INC_123 124 +#define SP_INC_124 125 +#define SP_INC_125 126 +#define SP_INC_126 127 +#define SP_INC_127 128 +#define SP_INC_128 129 +#define SP_INC_129 130 +#define SP_INC_130 131 +#define SP_INC_131 132 +#define SP_INC_132 133 +#define SP_INC_133 134 +#define SP_INC_134 135 +#define SP_INC_135 136 +#define SP_INC_136 137 +#define SP_INC_137 138 +#define SP_INC_138 139 +#define SP_INC_139 140 +#define SP_INC_140 141 +#define SP_INC_141 142 +#define SP_INC_142 143 +#define SP_INC_143 144 +#define SP_INC_144 145 +#define SP_INC_145 146 +#define SP_INC_146 147 +#define SP_INC_147 148 +#define SP_INC_148 149 +#define SP_INC_149 150 +#define SP_INC_150 151 +#define SP_INC_151 152 +#define SP_INC_152 153 +#define SP_INC_153 154 +#define SP_INC_154 155 +#define SP_INC_155 156 +#define SP_INC_156 157 +#define SP_INC_157 158 +#define SP_INC_158 159 +#define SP_INC_159 160 +#define SP_INC_160 161 +#define SP_INC_161 162 +#define SP_INC_162 163 +#define SP_INC_163 164 +#define SP_INC_164 165 +#define SP_INC_165 166 +#define SP_INC_166 167 +#define SP_INC_167 168 +#define SP_INC_168 169 +#define SP_INC_169 170 +#define SP_INC_170 171 +#define SP_INC_171 172 +#define SP_INC_172 173 +#define SP_INC_173 174 +#define SP_INC_174 175 +#define SP_INC_175 176 +#define SP_INC_176 177 +#define SP_INC_177 178 +#define SP_INC_178 179 +#define SP_INC_179 180 +#define SP_INC_180 181 +#define SP_INC_181 182 +#define SP_INC_182 183 +#define SP_INC_183 184 +#define SP_INC_184 185 +#define SP_INC_185 186 +#define SP_INC_186 187 +#define SP_INC_187 188 +#define SP_INC_188 189 +#define SP_INC_189 190 +#define SP_INC_190 191 +#define SP_INC_191 192 +#define SP_INC_192 193 +#define SP_INC_193 194 +#define SP_INC_194 195 +#define SP_INC_195 196 +#define SP_INC_196 197 +#define SP_INC_197 198 +#define SP_INC_198 199 +#define SP_INC_199 200 +#define SP_INC_200 201 +#define SP_INC_201 202 +#define SP_INC_202 203 +#define SP_INC_203 204 +#define SP_INC_204 205 +#define SP_INC_205 206 +#define SP_INC_206 207 +#define SP_INC_207 208 +#define SP_INC_208 209 +#define SP_INC_209 210 +#define SP_INC_210 211 +#define SP_INC_211 212 +#define SP_INC_212 213 +#define SP_INC_213 214 +#define SP_INC_214 215 +#define SP_INC_215 216 +#define SP_INC_216 217 +#define SP_INC_217 218 +#define SP_INC_218 219 +#define SP_INC_219 220 +#define SP_INC_220 221 +#define SP_INC_221 222 +#define SP_INC_222 223 +#define SP_INC_223 224 +#define SP_INC_224 225 +#define SP_INC_225 226 +#define SP_INC_226 227 +#define SP_INC_227 228 +#define SP_INC_228 229 +#define SP_INC_229 230 +#define SP_INC_230 231 +#define SP_INC_231 232 +#define SP_INC_232 233 +#define SP_INC_233 234 +#define SP_INC_234 235 +#define SP_INC_235 236 +#define SP_INC_236 237 +#define SP_INC_237 238 +#define SP_INC_238 239 +#define SP_INC_239 240 +#define SP_INC_240 241 +#define SP_INC_241 242 +#define SP_INC_242 243 +#define SP_INC_243 244 +#define SP_INC_244 245 +#define SP_INC_245 246 +#define SP_INC_246 247 +#define SP_INC_247 248 +#define SP_INC_248 249 +#define SP_INC_249 250 +#define SP_INC_250 251 +#define SP_INC_251 252 +#define SP_INC_252 253 +#define SP_INC_253 254 +#define SP_INC_254 255 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_list.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_list.h new file mode 100644 index 0000000..977e8cc --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_list.h @@ -0,0 +1,164 @@ +/** + * \file + * + * \brief List declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_LIST_H_INCLUDED +#define _UTILS_LIST_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_list + * + * @{ + */ + +#include + +/** + * \brief List element type + */ +struct list_element { + struct list_element *next; +}; + +/** + * \brief List head type + */ +struct list_descriptor { + struct list_element *head; +}; + +/** + * \brief Reset list + * + * \param[in] list The pointer to a list descriptor + */ +static inline void list_reset(struct list_descriptor *const list) +{ + list->head = NULL; +} + +/** + * \brief Retrieve list head + * + * \param[in] list The pointer to a list descriptor + * + * \return A pointer to the head of the given list or NULL if the list is + * empty + */ +static inline void *list_get_head(const struct list_descriptor *const list) +{ + return (void *)list->head; +} + +/** + * \brief Retrieve next list head + * + * \param[in] list The pointer to a list element + * + * \return A pointer to the next list element or NULL if there is not next + * element + */ +static inline void *list_get_next_element(const void *const element) +{ + return element ? ((struct list_element *)element)->next : NULL; +} + +/** + * \brief Insert an element as list head + * + * \param[in] list The pointer to a list element + * \param[in] element An element to insert to the given list + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element); + +/** + * \brief Insert an element after the given list element + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_after(void *const after, void *const element); + +/** + * \brief Insert an element at list end + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element); + +/** + * \brief Check whether an element belongs to a list + * + * \param[in] list The pointer to a list + * \param[in] element An element to check + * + * \return The result of checking + * \retval true If the given element is an element of the given list + * \retval false Otherwise + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element); + +/** + * \brief Removes list head + * + * This function removes the list head and sets the next element after the list + * head as a new list head. + * + * \param[in] list The pointer to a list + * + * \return The pointer to the new list head of NULL if the list head is NULL + */ +void *list_remove_head(struct list_descriptor *const list); + +/** + * \brief Removes the list element + * + * \param[in] list The pointer to a list + * \param[in] element An element to remove + * + * \return The result of element removing + * \retval true The given element is removed from the given list + * \retval false The given element is not an element of the given list + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_repeat_macro.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_repeat_macro.h new file mode 100644 index 0000000..89e6f52 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/include/utils_repeat_macro.h @@ -0,0 +1,322 @@ +/** + * \file + * + * \brief Repeat macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_REPEAT_MACRO_H +#define _UTILS_REPEAT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Sequently repeates specified macro for n times (255 max). + * + * Specified macro shall have two arguments: macro(arg, i) + * arg - user defined argument, which have the same value for all iterations. + * i - iteration number; numbering begins from zero and increments on each + * iteration. + * + * \param[in] macro - macro to be repeated + * \param[in] arg - user defined argument for repeated macro + * \param[in] n - total number of iterations (255 max) + */ +#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) + +#define REPEAT1(macro, arg, n) macro(arg, n) +#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) +#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) +#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) +#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) +#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) +#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) +#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) +#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) +#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) +#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) +#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) +#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) +#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) +#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) +#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) +#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) +#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) +#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) +#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) +#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) +#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) +#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) +#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) +#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) +#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) +#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) +#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) +#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) +#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) +#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) +#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) +#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) +#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) +#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) +#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) +#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) +#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) +#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) +#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) +#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) +#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) +#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) +#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) +#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) +#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) +#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) +#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) +#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) +#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) +#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) +#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) +#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) +#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) +#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) +#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) +#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) +#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) +#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) +#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) +#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) +#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) +#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) +#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) +#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) +#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) +#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) +#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) +#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) +#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) +#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) +#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) +#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) +#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) +#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) +#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) +#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) +#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) +#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) +#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) +#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) +#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) +#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) +#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) +#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) +#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) +#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) +#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) +#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) +#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) +#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) +#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) +#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) +#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) +#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) +#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) +#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) +#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) +#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) +#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) +#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) +#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) +#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) +#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) +#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) +#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) +#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) +#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) +#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) +#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) +#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) +#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) +#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) +#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) +#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) +#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) +#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) +#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) +#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) +#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) +#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) +#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) +#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) +#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) +#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) +#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) +#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) +#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) +#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) +#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) +#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) +#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) +#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) +#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) +#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) +#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) +#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) +#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) +#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) +#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) +#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) +#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) +#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) +#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) +#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) +#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) +#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) +#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) +#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) +#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) +#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) +#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) +#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) +#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) +#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) +#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) +#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) +#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) +#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) +#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) +#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) +#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) +#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) +#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) +#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) +#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) +#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) +#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) +#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) +#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) +#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) +#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) +#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) +#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) +#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) +#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) +#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) +#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) +#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) +#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) +#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) +#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) +#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) +#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) +#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) +#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) +#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) +#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) +#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) +#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) +#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) +#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) +#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) +#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) +#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) +#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) +#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) +#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) +#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) +#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) +#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) +#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) +#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) +#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) +#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) +#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) +#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) +#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) +#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) +#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) +#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) +#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) +#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) +#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) +#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) +#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) +#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) +#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) +#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) +#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) +#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) +#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) +#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) +#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) +#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) +#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) +#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) +#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) +#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) +#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) +#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) +#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) +#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) +#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) +#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) +#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) +#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) +#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) +#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) +#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) +#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) +#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) +#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) +#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) +#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) +#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) +#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) +#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) +#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) +#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) +#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) +#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) +#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) +#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) +#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/src/utils_assert.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/src/utils_assert.c new file mode 100644 index 0000000..b376c97 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/src/utils_assert.c @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include + +/** + * \brief Assert function + */ +void assert(const bool condition, const char *const file, const int line) +{ + if (!(condition)) { + __asm("BKPT #0"); + } + (void)file; + (void)line; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/src/utils_event.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/src/utils_event.c new file mode 100644 index 0000000..d1af9d0 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/src/utils_event.c @@ -0,0 +1,125 @@ +/** + * \file + * + * \brief Events implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) + +static struct list_descriptor events; +static uint8_t subscribed[EVENT_MASK_SIZE]; + +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + + ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); + + if (event->mask[position] & mask) { + return ERR_NO_CHANGE; /* Already subscribed */ + } + + if (!is_list_element(&events, event)) { + memset(event->mask, 0, EVENT_MASK_SIZE); + list_insert_as_head(&events, event); + } + event->cb = cb; + event->mask[position] |= mask; + + subscribed[position] |= mask; + + return ERR_NONE; +} + +int32_t event_unsubscribe(struct event *const event, const event_id_t id) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + uint8_t i; + + ASSERT(event && (id < EVENT_MAX_AMOUNT)); + + if (!(event->mask[position] & mask)) { + return ERR_NO_CHANGE; /* Already unsubscribed */ + } + + event->mask[position] &= ~mask; + + /* Check if there are more subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + break; + } + } + if (!current) { + subscribed[position] &= ~mask; + } + + /* Remove event from the list. Can be unsave, document it! */ + for (i = 0; i < ARRAY_SIZE(event->mask); i++) { + if (event->mask[i]) { + return ERR_NONE; + } + } + list_delete_element(&events, event); + + return ERR_NONE; +} + +void event_post(const event_id_t id, const event_data_t data) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + + ASSERT((id < EVENT_MAX_AMOUNT)); + + if (!(subscribed[position] & mask)) { + return; /* No subscribers */ + } + + /* Find all subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + current->cb(id, data); + } + } +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/src/utils_list.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/src/utils_list.c new file mode 100644 index 0000000..4006a01 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/src/utils_list.c @@ -0,0 +1,136 @@ +/** + * \file + * + * \brief List functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Check whether element belongs to list + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element) +{ + struct list_element *it; + for (it = list->head; it; it = it->next) { + if (it == element) { + return true; + } + } + + return false; +} + +/** + * \brief Insert an element as list head + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element) +{ + ASSERT(!is_list_element(list, element)); + + ((struct list_element *)element)->next = list->head; + list->head = (struct list_element *)element; +} + +/** + * \brief Insert an element after the given list element + */ +void list_insert_after(void *const after, void *const element) +{ + ((struct list_element *)element)->next = ((struct list_element *)after)->next; + ((struct list_element *)after)->next = (struct list_element *)element; +} + +/** + * \brief Insert an element at list end + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element) +{ + struct list_element *it = list->head; + + ASSERT(!is_list_element(list, element)); + + if (!list->head) { + list->head = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; + return; + } + + while (it->next) { + it = it->next; + } + it->next = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; +} + +/** + * \brief Removes list head + */ +void *list_remove_head(struct list_descriptor *const list) +{ + if (list->head) { + struct list_element *tmp = list->head; + + list->head = list->head->next; + return (void *)tmp; + } + + return NULL; +} + +/** + * \brief Removes list element + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element) +{ + if (!element) { + return false; + } + + if (list->head == element) { + list->head = list->head->next; + return true; + } else { + struct list_element *it = list->head; + + while (it && it->next != element) { + it = it->next; + } + if (it) { + it->next = ((struct list_element *)element)->next; + return true; + } + } + + return false; +} + +//@} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/src/utils_syscalls.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/src/utils_syscalls.c new file mode 100644 index 0000000..79e2f1f --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hal/utils/src/utils_syscalls.c @@ -0,0 +1,152 @@ +/** + * \file + * + * \brief Syscalls for SAM0 (GCC). + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#undef errno +extern int errno; +extern int _end; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *_new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +/** + * \brief Replacement of C library of _sbrk + */ +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char * prev_heap; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t)prev_heap; +} + +/** + * \brief Replacement of C library of link + */ +extern int link(char *old, char *_new) +{ + (void)old, (void)_new; + return -1; +} + +/** + * \brief Replacement of C library of _close + */ +extern int _close(int file) +{ + (void)file; + return -1; +} + +/** + * \brief Replacement of C library of _fstat + */ +extern int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + + return 0; +} + +/** + * \brief Replacement of C library of _isatty + */ +extern int _isatty(int file) +{ + (void)file; + return 1; +} + +/** + * \brief Replacement of C library of _lseek + */ +extern int _lseek(int file, int ptr, int dir) +{ + (void)file, (void)ptr, (void)dir; + return 0; +} + +/** + * \brief Replacement of C library of _exit + */ +extern void _exit(int status) +{ + printf("Exiting with status %d.\n", status); + + for (;;) + ; +} + +/** + * \brief Replacement of C library of _kill + */ +extern void _kill(int pid, int sig) +{ + (void)pid, (void)sig; + return; +} + +/** + * \brief Replacement of C library of _getpid + */ +extern int _getpid(void) +{ + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/core/hpl_core_m0plus_base.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/core/hpl_core_m0plus_base.c new file mode 100644 index 0000000..28d799e --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/core/hpl_core_m0plus_base.c @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#ifndef _UNIT_TEST_ +#include +#endif +#include +#include + +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 1000000 +#endif + +#if CONF_CPU_FREQUENCY < 1000 +#define CPU_FREQ_POWER 3 +#elif CONF_CPU_FREQUENCY < 10000 +#define CPU_FREQ_POWER 4 +#elif CONF_CPU_FREQUENCY < 100000 +#define CPU_FREQ_POWER 5 +#elif CONF_CPU_FREQUENCY < 1000000 +#define CPU_FREQ_POWER 6 +#elif CONF_CPU_FREQUENCY < 10000000 +#define CPU_FREQ_POWER 7 +#elif CONF_CPU_FREQUENCY < 100000000 +#define CPU_FREQ_POWER 8 +#endif + +/** + * \brief The array of interrupt handlers + */ +struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; + +/** + * \brief Reset MCU + */ +void _reset_mcu(void) +{ + NVIC_SystemReset(); +} + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void) +{ + __DSB(); + __WFI(); +} + +/** + * \brief Retrieve current IRQ number + */ +uint8_t _irq_get_current(void) +{ + return (uint8_t)__get_IPSR() - 16; +} + +/** + * \brief Disable the given IRQ + */ +void _irq_disable(uint8_t n) +{ + NVIC_DisableIRQ((IRQn_Type)n); +} + +/** + * \brief Set the given IRQ + */ +void _irq_set(uint8_t n) +{ + NVIC_SetPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Clear the given IRQ + */ +void _irq_clear(uint8_t n) +{ + NVIC_ClearPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Enable the given IRQ + */ +void _irq_enable(uint8_t n) +{ + NVIC_EnableIRQ((IRQn_Type)n); +} + +/** + * \brief Register IRQ handler + */ +void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) +{ + ASSERT(n < PERIPH_COUNT_IRQn); + + _irq_table[n] = irq; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Default_Handler(void) +{ + while (1) { + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 8: + return (us * (freq / 100000) + 29) / 30; + case 7: + return (us * (freq / 10000) + 299) / 300; + case 6: + return (us * (freq / 1000) + 2999) / 3000; + case 5: + return (us * (freq / 100) + 29999) / 30000; + case 4: + return (us * (freq / 10) + 299999) / 300000; + default: + return (us * freq + 2999999) / 3000000; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +uint32_t _get_cycles_for_us(const uint16_t us) +{ + return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 8: + return (ms * (freq / 100000) + 2) / 3 * 100; + case 7: + return (ms * (freq / 10000) + 2) / 3 * 10; + case 6: + return (ms * (freq / 1000) + 2) / 3; + case 5: + return (ms * (freq / 100) + 29) / 30; + case 4: + return (ms * (freq / 10) + 299) / 300; + default: + return (ms * (freq / 1) + 2999) / 3000; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +uint32_t _get_cycles_for_ms(const uint16_t ms) +{ + return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} +/** + * \brief Initialize delay functionality + */ +void _delay_init(void *const hw) +{ + (void)hw; +} +/** + * \brief Delay loop to delay n number of cycles + */ +void _delay_cycles(void *const hw, uint32_t cycles) +{ +#ifndef _UNIT_TEST_ + (void)hw; + (void)cycles; +#if defined __GNUC__ + __asm(".syntax unified\n" + "__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n" + ".syntax divided"); +#elif defined __CC_ARM + __asm("__delay:\n" + "subs cycles, cycles, #1\n" + "bhi __delay\n"); +#elif defined __ICCARM__ + __asm("__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n"); +#endif +#endif +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/core/hpl_core_port.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/core/hpl_core_port.h new file mode 100644 index 0000000..3f3e8f2 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/core/hpl_core_port.h @@ -0,0 +1,61 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_PORT_H_INCLUDED +#define _HPL_CORE_PORT_H_INCLUDED + +#include + +/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR + * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), + * there will be assembling errors. + * So the following things are not included for assembling. + */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + +#ifndef _UNIT_TEST_ +#include +#endif + +/** + * \brief Check if it's in ISR handling + * \return \c true if it's in ISR + */ +static inline bool _is_in_isr(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); +} + +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/core/hpl_init.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/core/hpl_init.c new file mode 100644 index 0000000..367e142 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/core/hpl_init.c @@ -0,0 +1,75 @@ +/** + * \file + * + * \brief HPL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include + +#include +#include + +/* Referenced GCLKs (out of 0~7), should be initialized firstly + */ +#define _GCLK_INIT_1ST 0x00000000 +/* Not referenced GCLKs, initialized last */ +#define _GCLK_INIT_LAST 0x000000FF + +/** + * \brief Initialize the hardware abstraction layer + */ +void _init_chip(void) +{ + hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); + + _osc32kctrl_init_sources(); + _oscctrl_init_sources(); + _mclk_init(); +#if _GCLK_INIT_1ST + _gclk_init_generators_by_fref(_GCLK_INIT_1ST); +#endif + _oscctrl_init_referenced_generators(); + _gclk_init_generators_by_fref(_GCLK_INIT_LAST); + + _div_init(); + +#if CONF_DMAC_ENABLE + hri_mclk_set_AHBMASK_DMAC_bit(MCLK); + _dma_init(); +#endif + +#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) + _port_event_init(); +#endif +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/divas/hpl_divas.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/divas/hpl_divas.c new file mode 100644 index 0000000..2a39ac3 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/divas/hpl_divas.c @@ -0,0 +1,128 @@ +/** + * \file + * + * \brief Division operation related functionality. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#include +#define _DIVAS_CRITICAL_ENTER() \ + do { \ + volatile hal_atomic_t _divas_atomic; \ + _divas_atomic = __get_PRIMASK(); \ + __disable_irq(); +#define _DIVAS_CRITICAL_LEAVE() \ + __set_PRIMASK(_divas_atomic); \ + } \ + while (0) + +/** Return 32 bit result, the result only. */ +#define _divas_result32() (DIVAS->RESULT.reg) + +/** Return 64 bit result, the result and remainder. */ +#define _divas_result64() (*((uint64_t *)(&DIVAS->RESULT.reg))) + +/** \brief Execute hardware for division + * \param[in] s Indicate operation mode: signed/unsigned + * \param[in] n The dividend + * \param[in] d The divisor + */ +static inline void _divas_div(const uint8_t s, const uint32_t n, const uint32_t d) +{ + DIVAS->CTRLA.bit.SIGNED = s; + DIVAS->DIVIDEND.reg = n; + DIVAS->DIVISOR.reg = d; + while (DIVAS->STATUS.bit.BUSY) { + /* Wait the division is complete. */ + } +} + +/** + * \brief Initialize hardware for division operation + */ +void _div_init(void) +{ + hri_divas_write_CTRLA_DLZ_bit(DIVAS, CONF_DIVAS_DLZ); +} + +/** + * \brief Do signed division + */ +int32_t __aeabi_idiv(int32_t numerator, int32_t denominator) +{ + int32_t res; + _DIVAS_CRITICAL_ENTER(); + _divas_div(1, numerator, denominator); + res = _divas_result32(); + _DIVAS_CRITICAL_LEAVE(); + return res; +} + +/** + * \brief Do unsigned division + */ +uint32_t __aeabi_uidiv(uint32_t numerator, uint32_t denominator) +{ + uint32_t res; + _DIVAS_CRITICAL_ENTER(); + _divas_div(0, numerator, denominator); + res = _divas_result32(); + _DIVAS_CRITICAL_LEAVE(); + return res; +} + +/** + * \brief Do signed division, return result and remainder + */ +uint64_t __aeabi_idivmod(int numerator, int denominator) +{ + uint64_t res; + _DIVAS_CRITICAL_ENTER(); + _divas_div(1, numerator, denominator); + res = _divas_result64(); + _DIVAS_CRITICAL_LEAVE(); + return res; +} + +/** + * \brief Do unsigned division, return result and remainder + */ +uint64_t __aeabi_uidivmod(unsigned numerator, unsigned denominator) +{ + uint64_t res; + _DIVAS_CRITICAL_ENTER(); + _divas_div(0, numerator, denominator); + res = _divas_result64(); + _DIVAS_CRITICAL_LEAVE(); + return res; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/dmac/hpl_dmac.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/dmac/hpl_dmac.c new file mode 100644 index 0000000..153c0f3 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/dmac/hpl_dmac.c @@ -0,0 +1,244 @@ + +/** + * \file + * + * \brief Generic DMAC related functionality. + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include + +#if CONF_DMAC_ENABLE + +/* Section containing first descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _descriptor_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; + +/* Section containing current descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _write_back_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; + +/* Array containing callbacks for DMAC channels */ +static struct _dma_resource _resources[DMAC_CH_NUM]; + +/* This macro DMAC configuration */ +#define DMAC_CHANNEL_CFG(i, n) \ + {(CONF_DMAC_ENABLE_##n << DMAC_CHCTRLA_ENABLE_Pos), \ + DMAC_CHCTRLB_TRIGACT(CONF_DMAC_TRIGACT_##n) | DMAC_CHCTRLB_TRIGSRC(CONF_DMAC_TRIGSRC_##n) \ + | DMAC_CHCTRLB_LVL(CONF_DMAC_LVL_##n) | (CONF_DMAC_EVOE_##n << DMAC_CHCTRLB_EVOE_Pos) \ + | (CONF_DMAC_EVIE_##n << DMAC_CHCTRLB_EVIE_Pos) | DMAC_CHCTRLB_EVACT(CONF_DMAC_EVACT_##n), \ + DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ + | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ + | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ + | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, + +/* DMAC channel configuration */ +struct dmac_channel_cfg { + uint8_t ctrla; + uint32_t ctrlb; + uint16_t btctrl; +}; + +/* DMAC channel configurations */ +const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; + +/** + * \brief Initialize DMAC + */ +int32_t _dma_init(void) +{ + uint8_t i = 0; + + hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); + hri_dmac_clear_CTRL_CRCENABLE_bit(DMAC); + hri_dmac_set_CHCTRLA_SWRST_bit(DMAC); + + hri_dmac_write_CTRL_reg(DMAC, + (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) + | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) + | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); + hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); + + hri_dmac_write_QOSCTRL_reg(DMAC, + DMAC_QOSCTRL_WRBQOS(CONF_DMAC_WRBQOS) | DMAC_QOSCTRL_FQOS(CONF_DMAC_FQOS) + | DMAC_QOSCTRL_DQOS(CONF_DMAC_DQOS)); + + hri_dmac_write_PRICTRL0_reg( + DMAC, + DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) + | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) + | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) + | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); + hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); + hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); + + for (; i < DMAC_CH_NUM; i++) { + hri_dmac_write_CHID_reg(DMAC, i); + + hri_dmac_write_CHCTRLA_RUNSTDBY_bit(DMAC, _cfgs[i].ctrla & DMAC_CHCTRLA_RUNSTDBY); + + hri_dmac_write_CHCTRLB_reg(DMAC, _cfgs[i].ctrlb); + hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0); + } + + NVIC_DisableIRQ(DMAC_IRQn); + NVIC_ClearPendingIRQ(DMAC_IRQn); + NVIC_EnableIRQ(DMAC_IRQn); + + hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); + + return ERR_NONE; +} + +/** + * \brief Enable/disable DMA interrupt + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) +{ + hri_dmac_write_CHID_reg(DMAC, channel); + + if (DMA_TRANSFER_COMPLETE_CB == type) { + hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, state); + } else if (DMA_TRANSFER_ERROR_CB == type) { + hri_dmac_write_CHINTEN_TERR_bit(DMAC, state); + } +} + +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) +{ + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); + + return ERR_NONE; +} + +int32_t _dma_set_source_address(const uint8_t channel, const void *const src) +{ + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); + + return ERR_NONE; +} + +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel) +{ + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel], + (uint32_t)&_descriptor_section[next_channel]); + + return ERR_NONE; +} + +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) +{ + uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); + uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); + + return ERR_NONE; +} + +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) +{ + hri_dmac_write_CHID_reg(DMAC, channel); + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); + hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC); + if (software_trigger) { + hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); + } + + return ERR_NONE; +} + +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) +{ + *resource = &_resources[channel]; + + return ERR_NONE; +} + +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +/** + * \internal DMAC interrupt handler + */ +static inline void _dmac_handler(void) +{ + uint8_t channel = hri_dmac_read_INTPEND_ID_bf(DMAC); + uint8_t current_channel = hri_dmac_read_CHID_reg(DMAC); + uint8_t flag_status; + struct _dma_resource *tmp_resource = &_resources[channel]; + + hri_dmac_write_CHID_reg(DMAC, channel); + flag_status = hri_dmac_get_CHINTFLAG_reg(DMAC, DMAC_CHINTFLAG_MASK); + + if (flag_status & DMAC_CHINTFLAG_TERR) { + hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC); + tmp_resource->dma_cb.error(tmp_resource); + } else if (flag_status & DMAC_CHINTFLAG_TCMPL) { + hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC); + tmp_resource->dma_cb.transfer_done(tmp_resource); + } + hri_dmac_write_CHID_reg(DMAC, current_channel); +} + +/** + * \brief DMAC interrupt handler + */ +void DMAC_Handler(void) +{ + _dmac_handler(); +} + +#endif /* CONF_DMAC_ENABLE */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/gclk/hpl_gclk.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/gclk/hpl_gclk.c new file mode 100644 index 0000000..f93ec0c --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/gclk/hpl_gclk.c @@ -0,0 +1,246 @@ + +/** + * \file + * + * \brief Generic Clock Controller related functionality. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initializes generators + */ +void _gclk_init_generators(void) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); +#endif +} + +void _gclk_init_generators_by_fref(uint32_t bm) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + if (bm & (1ul << 0)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + if (bm & (1ul << 1)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + if (bm & (1ul << 2)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + if (bm & (1ul << 3)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + if (bm & (1ul << 4)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + if (bm & (1ul << 5)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + if (bm & (1ul << 6)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + if (bm & (1ul << 7)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + if (bm & (1ul << 8)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); + } +#endif +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/gclk/hpl_gclk_base.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/gclk/hpl_gclk_base.h new file mode 100644 index 0000000..3e7d282 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/gclk/hpl_gclk_base.h @@ -0,0 +1,87 @@ +/** + * \file + * + * \brief Generic Clock Controller. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GCLK_H_INCLUDED +#define _HPL_GCLK_H_INCLUDED + +#include +#ifdef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup gclk_group GCLK Hardware Proxy Layer + * + * \section gclk_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Enable clock on the given channel with the given clock source + * + * This function maps the given clock source to the given clock channel + * and enables channel. + * + * \param[in] channel The channel to enable clock for + * \param[in] source The clock source for the given channel + */ +static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) +{ + + hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); +} + +/** + * \brief Initialize GCLK generators by function references + * \param[in] bm Bit mapping for referenced generators, + * a bit 1 in position triggers generator initialization. + */ +void _gclk_init_generators_by_fref(uint32_t bm); + +//@} +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/mclk/hpl_mclk.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/mclk/hpl_mclk.c new file mode 100644 index 0000000..bb079d8 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/mclk/hpl_mclk.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief SAM Main Clock. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void) +{ + void *hw = (void *)MCLK; + hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_CPUDIV(CONF_MCLK_CPUDIV)); +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/osc32kctrl/hpl_osc32kctrl.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/osc32kctrl/hpl_osc32kctrl.c new file mode 100644 index 0000000..09fcc4b --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/osc32kctrl/hpl_osc32kctrl.c @@ -0,0 +1,107 @@ +/** + * \file + * + * \brief SAM 32k Oscillators Controller. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void) +{ + void * hw = (void *)OSC32KCTRL; + uint16_t calib = 0; + +#if CONF_XOSC32K_CONFIG == 1 + hri_osc32kctrl_write_XOSC32K_reg( + hw, + OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) + | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) + | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos) + | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) + | (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos)); + + hri_osc32kctrl_write_CFDCTRL_reg(hw, + (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos) + | (CONF_XOSC32K_SWBEN << OSC32KCTRL_CFDCTRL_SWBACK_Pos)); + + hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos)); +#endif + +#if CONF_OSC32K_CONFIG == 1 + /* OSC32K calibration value at bit 18:12 of memory 0x00806020 */ + calib = (*((uint32_t *)0x00806020) & 0x007F000) >> 12; + hri_osc32kctrl_write_OSC32K_reg( + hw, +#if CONF_OSC32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSC32K_CALIB(CONF_OSC32K_CALIB) | +#else + OSC32KCTRL_OSC32K_CALIB(calib) | +#endif + OSC32KCTRL_OSC32K_STARTUP(CONF_OSC32K_STARTUP) | (CONF_OSC32K_ONDEMAND << OSC32KCTRL_OSC32K_ONDEMAND_Pos) + | (CONF_OSC32K_RUNSTDBY << OSC32KCTRL_OSC32K_RUNSTDBY_Pos) + | (CONF_OSC32K_EN1K << OSC32KCTRL_OSC32K_EN1K_Pos) | (CONF_OSC32K_EN32K << OSC32KCTRL_OSC32K_EN32K_Pos) + | (CONF_OSC32K_ENABLE << OSC32KCTRL_OSC32K_ENABLE_Pos)); +#endif +#if CONF_OSCULP32K_CONFIG == 1 + calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); + hri_osc32kctrl_write_OSCULP32K_reg(hw, +#if CONF_OSC32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSCULP32K_CALIB(CONF_OSC32K_CALIB) +#else + OSC32KCTRL_OSCULP32K_CALIB(calib) +#endif + ); +#endif + +#if CONF_XOSC32K_CONFIG +#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0 + while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw)) + ; +#endif +#if CONF_OSCULP32K_ULP32KSW == 1 + hri_osc32kctrl_set_OSCULP32K_reg(hw, OSC32KCTRL_OSCULP32K_ULP32KSW); + while (!hri_osc32kctrl_get_STATUS_ULP32KSW_bit(hw)) + ; +#endif +#endif + +#if CONF_OSC32K_CONFIG == 1 +#if CONF_OSC32K_ENABLE == 1 && CONF_OSC32K_ONDEMAND == 0 + while (!hri_osc32kctrl_get_STATUS_OSC32KRDY_bit(hw)) + ; +#endif +#endif + hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); + (void)calib; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/oscctrl/hpl_oscctrl.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/oscctrl/hpl_oscctrl.c new file mode 100644 index 0000000..e4e0986 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/oscctrl/hpl_oscctrl.c @@ -0,0 +1,121 @@ +/** + * \file + * + * \brief SAM Oscillators Controller. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_XOSC_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg( + hw, + OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC_STARTUP) | (0 << OSCCTRL_XOSCCTRL_AMPGC_Pos) + | OSCCTRL_XOSCCTRL_GAIN(CONF_XOSC_GAIN) | (CONF_XOSC_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) + | (CONF_XOSC_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) + | (CONF_XOSC_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); + + hri_oscctrl_write_EVCTRL_reg(hw, (CONF_XOSC_CFDEO << OSCCTRL_EVCTRL_CFDEO_Pos)); +#endif +#if CONF_OSC48M_CONFIG == 1 + hri_oscctrl_write_OSC48MCTRL_reg(hw, + (CONF_OSC48M_RUNSTDBY << OSCCTRL_OSC48MCTRL_RUNSTDBY_Pos) + | (CONF_OSC48M_ENABLE << OSCCTRL_OSC48MCTRL_ENABLE_Pos)); + hri_oscctrl_write_OSC48MDIV_reg(hw, OSCCTRL_OSC48MDIV_DIV(CONF_OSC48M_DIV)); + while (hri_oscctrl_get_OSC48MSYNCBUSY_OSC48MDIV_bit(hw)) + ; + hri_oscctrl_write_OSC48MSTUP_reg(hw, OSCCTRL_OSC48MSTUP_STARTUP(CONF_OSC48M_STARTUP)); +#endif + +#if CONF_XOSC_CONFIG == 1 +#if CONF_XOSC_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY_bit(hw)) + ; +#endif +#if CONF_XOSC_AMPGC == 1 + hri_oscctrl_set_XOSCCTRL_AMPGC_bit(hw); +#endif +#if CONF_XOSC_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_OSC48M_CONFIG == 1 +#if CONF_OSC48M_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_OSC48MRDY_bit(hw)) + ; +#endif +#if CONF_OSC48M_ONDEMAND == 1 + hri_oscctrl_set_OSC48MCTRL_ONDEMAND_bit(hw); +#endif +#endif + (void)hw; +} + +void _oscctrl_init_referenced_generators(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_DPLL_CONFIG == 1 +#if CONF_DPLL_REFCLK == 2 + hri_gclk_write_PCHCTRL_reg(GCLK, 0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DPLL_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_DPLL_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_DPLL_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg( + hw, + OSCCTRL_DPLLCTRLB_DIV(CONF_DPLL_DIV) | (CONF_DPLL_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) + | OSCCTRL_DPLLCTRLB_LTIME(CONF_DPLL_LTIME) | OSCCTRL_DPLLCTRLB_REFCLK(CONF_DPLL_REFCLK) + | (CONF_DPLL_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) | (CONF_DPLL_LPEN << OSCCTRL_DPLLCTRLB_LPEN_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_DPLL_FILTER)); + hri_oscctrl_write_DPLLPRESC_reg(hw, OSCCTRL_DPLLPRESC_PRESC(CONF_DPLL_PRESC)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + (CONF_DPLL_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_DPLL_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_DPLL_CONFIG == 1 +#if CONF_DPLL_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw))) + ; +#endif +#if CONF_DPLL_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw); +#endif +#endif + (void)hw; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/pm/hpl_pm.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/pm/hpl_pm.c new file mode 100644 index 0000000..03bbc4f --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/pm/hpl_pm.c @@ -0,0 +1,64 @@ + +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Retrieve the reset reason + */ +enum reset_reason _get_reset_reason(void) +{ + return (enum reset_reason)hri_rstc_read_RCAUSE_reg(RSTC); +} + +/** + * \brief Set the sleep mode for the device + */ +int32_t _set_sleep_mode(const uint8_t mode) +{ + switch (mode) { + case 2: /* IDLE */ + case 4: /* STANDBY */ + case 5: /* BACKUP */ + case 6: /* OFF */ + hri_pm_write_SLEEPCFG_SLEEPMODE_bf(PM, mode); + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/pm/hpl_pm_base.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/pm/hpl_pm_base.h new file mode 100644 index 0000000..5a50a91 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/pm/hpl_pm_base.h @@ -0,0 +1,45 @@ +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HPL_PM_BASE_H_INCLUDED +#define _HPL_PM_BASE_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/port/hpl_gpio_base.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/port/hpl_gpio_base.h new file mode 100644 index 0000000..3cc1981 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/port/hpl_gpio_base.h @@ -0,0 +1,170 @@ + +/** + * \file + * + * \brief SAM PORT. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include + +/** + * \brief Set direction on port with mask + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + switch (direction) { + case GPIO_DIRECTION_OFF: + hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_IN: + hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg(PORT, + port, + PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN + | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_OUT: + hri_port_set_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + default: + ASSERT(false); + } +} + +/** + * \brief Set output level on port with mask + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + if (level) { + hri_port_set_OUT_reg(PORT_IOBUS, port, mask); + } else { + hri_port_clear_OUT_reg(PORT_IOBUS, port, mask); + } +} + +/** + * \brief Change output level to the opposite with mask + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) +{ + hri_port_toggle_OUT_reg(PORT_IOBUS, port, mask); +} + +/** + * \brief Get input levels on all port pins + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port) +{ + uint32_t tmp; + + CRITICAL_SECTION_ENTER(); + + uint32_t dir_tmp = hri_port_read_DIR_reg(PORT_IOBUS, port); + + tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; + tmp |= hri_port_read_OUT_reg(PORT_IOBUS, port) & dir_tmp; + + CRITICAL_SECTION_LEAVE(); + + return tmp; +} + +/** + * \brief Set pin pull mode + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode) +{ + switch (pull_mode) { + case GPIO_PULL_OFF: + hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); + break; + + case GPIO_PULL_UP: + hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_set_OUT_reg(PORT_IOBUS, port, 1U << pin); + break; + + case GPIO_PULL_DOWN: + hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_clear_OUT_reg(PORT_IOBUS, port, 1U << pin); + break; + + default: + ASSERT(false); + break; + } +} + +/** + * \brief Set gpio pin function + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) +{ + uint8_t port = GPIO_PORT(gpio); + uint8_t pin = GPIO_PIN(gpio); + + if (function == GPIO_PIN_FUNCTION_OFF) { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); + + } else { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); + + if (pin & 1) { + // Odd numbered pin + hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); + } else { + // Even numbered pin + hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); + } + } +} + +static inline void _port_event_init() +{ + hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/sercom/hpl_sercom.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/sercom/hpl_sercom.c new file mode 100644 index 0000000..a241e97 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hpl/sercom/hpl_sercom.c @@ -0,0 +1,2929 @@ + +/** + * \file + * + * \brief SAM Serial Communication Interface + * + * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONF_SERCOM_0_USART_ENABLE +#define CONF_SERCOM_0_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_USART_ENABLE +#define CONF_SERCOM_1_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_USART_ENABLE +#define CONF_SERCOM_3_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_USART_ENABLE +#define CONF_SERCOM_4_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_USART_ENABLE +#define CONF_SERCOM_5_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_USART_ENABLE +#define CONF_SERCOM_6_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_USART_ENABLE +#define CONF_SERCOM_7_USART_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as USART. */ +#define SERCOM_USART_AMOUNT \ + (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ + + CONF_SERCOM_4_USART_ENABLE + CONF_SERCOM_5_USART_ENABLE + CONF_SERCOM_6_USART_ENABLE \ + + CONF_SERCOM_7_USART_ENABLE) + +/** + * \brief Macro is used to fill usart configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define SERCOM_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ + | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ + | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ + | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ + | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ + | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ + | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ + | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ + SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ + | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ + | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ + | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ + | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ + | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ + (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ + CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ + } + +/** + * \brief SERCOM USART configuration type + */ +struct usart_configuration { + uint8_t number; + hri_sercomusart_ctrla_reg_t ctrl_a; + hri_sercomusart_ctrlb_reg_t ctrl_b; + hri_sercomusart_baud_reg_t baud; + uint8_t fractional; + hri_sercomusart_rxpl_reg_t rxpl; + hri_sercomusart_dbgctrl_reg_t debug_ctrl; +}; + +#if SERCOM_USART_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct usart_configuration _usarts[1] = {{0}}; +#else +/** + * \brief Array of SERCOM USART configurations + */ +static struct usart_configuration _usarts[] = { +#if CONF_SERCOM_0_USART_ENABLE == 1 + SERCOM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_USART_ENABLE == 1 + SERCOM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_USART_ENABLE == 1 + SERCOM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_USART_ENABLE == 1 + SERCOM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_USART_ENABLE == 1 + SERCOM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_USART_ENABLE == 1 + SERCOM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_USART_ENABLE == 1 + SERCOM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_USART_ENABLE == 1 + SERCOM_CONFIGURATION(7), +#endif +}; +#endif + +static uint8_t _get_sercom_index(const void *const hw); +static uint8_t _sercom_get_irq_num(const void *const hw); +static void _sercom_init_irq_param(const void *const hw, void *dev); +static uint8_t _sercom_get_hardware_index(const void *const hw); + +static int32_t _usart_init(void *const hw); +static inline void _usart_deinit(void *const hw); +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); +static void _usart_set_data_order(void *const hw, const enum usart_data_order order); +static void _usart_set_mode(void *const hw, const enum usart_mode mode); +static void _usart_set_parity(void *const hw, const enum usart_parity parity); +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); +static void _usart_set_character_size(void *const hw, const enum usart_character_size size); + +/** + * \brief Initialize synchronous SERCOM USART + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _usart_init(hw); +} + +/** + * \brief Initialize asynchronous SERCOM USART + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _usart_init(hw); + if (init_status) { + return init_status; + } + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_sync_deinit(struct _usart_sync_device *const device) +{ + _usart_deinit(device->hw); +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_async_deinit(struct _usart_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _usart_deinit(device->hw); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_sync_enable(struct _usart_sync_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_async_enable(struct _usart_async_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_sync_disable(struct _usart_sync_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_async_disable(struct _usart_async_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Set baud rate + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set baud rate + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set data order + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set data order + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set mode + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set mode + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set parity + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set parity + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set stop bits mode + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set stop bits mode + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set character size + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Set character size + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given SERCOM USART instance + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_DATA_reg(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if USART transmission complete + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_TXC_bit(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if there is data received by USART + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_RXC_bit(device->hw); +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Enable data register empty interrupt + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_DRE_bit(device->hw); +} + +/** + * \brief Enable transmission complete interrupt + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_TXC_bit(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given sercom hardware instance + */ +static uint8_t _sercom_get_hardware_index(const void *const hw) +{ +#ifdef _UNIT_TEST_ + return ((uint32_t)hw - (uint32_t)SERCOM0) / sizeof(Sercom); +#endif + + return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10; +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Enable/disable USART interrupt + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { + hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); + hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); + } else if (USART_ASYNC_RX_DONE == type) { + hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); + } else if (USART_ASYNC_ERROR == type) { + hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static uint8_t _get_sercom_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_usarts); i++) { + if (_usarts[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return 0; +} + +/** + * \brief Init irq param with the given sercom hardware instance + */ +static void _sercom_init_irq_param(const void *const hw, void *dev) +{ +} + +/** + * \internal Initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + * + * \return The status of initialization + */ +static int32_t _usart_init(void *const hw) +{ + uint8_t i = _get_sercom_index(hw); + + if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { + uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk; + if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + } + hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); + } + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + + hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); + hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); + if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { + ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; + ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; + } else { + hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); + } + + hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); + hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); + + return ERR_NONE; +} + +/** + * \internal De-initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _usart_deinit(void *const hw) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate SERCOM clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { + return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; + } + + if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { + return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); + } + + if (USART_BAUDRATE_SYNCH == mode) { + return clock_rate / baud / 2 - 1; + } + + return 0; +} + +/** + * \internal Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_BAUD_reg(hw, baud_rate); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +static void _usart_set_data_order(void *const hw, const enum usart_data_order order) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_DORD_bit(hw, order); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +static void _usart_set_mode(void *const hw, const enum usart_mode mode) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +static void _usart_set_parity(void *const hw, const enum usart_parity parity) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + + if (USART_PARITY_NONE != parity) { + hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); + } else { + hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); + } + + hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +static void _usart_set_character_size(void *const hw, const enum usart_character_size size) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomusart_set_CTRLA_ENABLE_bit(hw); + } +} + + /* Sercom I2C implementation */ + +#ifndef CONF_SERCOM_0_I2CM_ENABLE +#define CONF_SERCOM_0_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CM_ENABLE +#define CONF_SERCOM_2_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CM_ENABLE +#define CONF_SERCOM_3_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CM_ENABLE +#define CONF_SERCOM_4_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CM_ENABLE +#define CONF_SERCOM_5_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CM_ENABLE +#define CONF_SERCOM_6_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CM_ENABLE +#define CONF_SERCOM_7_I2CM_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Master. */ +#define SERCOM_I2CM_AMOUNT \ + (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ + + CONF_SERCOM_4_I2CM_ENABLE + CONF_SERCOM_5_I2CM_ENABLE + CONF_SERCOM_6_I2CM_ENABLE + CONF_SERCOM_7_I2CM_ENABLE) + +/** + * \brief Macro is used to fill i2cm configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CM_CONFIGURATION(n) \ + { \ + (n), \ + (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ + | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ + SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ + CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ + } + +#define ERROR_FLAG (1 << 7) +#define SB_FLAG (1 << 1) +#define MB_FLAG (1 << 0) + +#define CMD_STOP 0x3 +#define I2C_IDLE 0x1 +#define I2C_SM 0x0 +#define I2C_FM 0x1 +#define I2C_HS 0x2 +#define TEN_ADDR_FRAME 0x78 +#define TEN_ADDR_MASK 0x3ff +#define SEVEN_ADDR_MASK 0x7f + +/** + * \brief SERCOM I2CM configuration type + */ +struct i2cm_configuration { + uint8_t number; + hri_sercomi2cm_ctrla_reg_t ctrl_a; + hri_sercomi2cm_ctrlb_reg_t ctrl_b; + hri_sercomi2cm_baud_reg_t baud; + hri_sercomi2cm_dbgctrl_reg_t dbgctrl; + uint16_t trise; + uint32_t clk; /* SERCOM peripheral clock frequency */ +}; + +static inline int32_t _i2c_m_enable_implementation(void *hw); +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); + +#if SERCOM_I2CM_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct i2cm_configuration _i2cms[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2CM configurations + */ +static struct i2cm_configuration _i2cms[] = { +#if CONF_SERCOM_0_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2cm_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { + if (_i2cms[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +static inline void _sercom_i2c_send_stop(void *const hw) +{ + hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); +} + +/** + * \brief SERCOM I2CM analyze hardware status and transfer next byte + */ +static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) +{ + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); + + if (flags & MB_FLAG) { + /* tx error */ + if (status & SERCOM_I2CM_STATUS_ARBLOST) { + hri_sercomi2cm_clear_interrupt_MB_bit(hw); + msg->flags |= I2C_M_FAIL; + msg->flags &= ~I2C_M_BUSY; + + if (status & SERCOM_I2CM_STATUS_BUSERR) { + return I2C_ERR_BUS; + } + + return I2C_ERR_BAD_ADDRESS; + } else { + if (status & SERCOM_I2CM_STATUS_RXNACK) { + + /* Slave rejects to receive more data */ + if (msg->len > 0) { + msg->flags |= I2C_M_FAIL; + } + + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + + return I2C_NACK; + } + + if (msg->flags & I2C_M_TEN) { + hri_sercomi2cm_write_ADDR_reg(hw, + ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + msg->flags &= ~I2C_M_TEN; + + return I2C_OK; + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } else { + hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); + msg->buffer++; + msg->len--; + } + + return I2C_OK; + } + } else if (flags & SB_FLAG) { + if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { + msg->len--; + + /* last byte, send nack */ + if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + hri_sercomi2cm_clear_CTRLB_SMEN_bit(hw); + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } + + /* Accessing DATA.DATA auto-triggers I2C bus operations. + * The operation performed depends on the state of + * CTRLB.ACKACT, CTRLB.SMEN + **/ + *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); + } else { + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + return I2C_NACK; + } + + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + } + + return I2C_OK; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + return _i2c_m_enable_implementation(i2c_dev->hw); +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Retrieve IRQ number for the given hardware instance + */ +static uint8_t _sercom_get_irq_num(const void *const hw) +{ + return SERCOM0_IRQn + _sercom_get_hardware_index(hw); +} + +/** + * \brief Initialize sercom i2c module to use in async mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) +{ + int32_t init_status; + + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); + if (init_status) { + return init_status; + } + + _sercom_init_irq_param(hw, (void *)i2c_dev); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Transfer the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + return ERR_NONE; +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail, return the error code + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) +{ + int ret; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (msg->len == 0) { + return ERR_NONE; + } + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(i2c_dev->hw); + + ret = _sercom_i2c_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Set callback to be called in interrupt handler + * + * \param[in] i2c_dev The pointer to master i2c device + * \param[in] type The callback type + * \param[in] func The callback function pointer + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, + FUNC_PTR func) +{ + switch (type) { + case I2C_M_ASYNC_DEVICE_ERROR: + i2c_dev->cb.error = (_i2c_error_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_TX_COMPLETE: + i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_RX_COMPLETE: + i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; + break; + default: + /* error */ + break; + } + + return ERR_NONE; +} + +/** + * \brief Set stop condition on I2C + * + * \param i2c_dev Pointer to master i2c device + * + * \return Operation status + * \retval I2C_OK Operation was successfull + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +/** + * \brief Get number of bytes left in transfer buffer + * + * \param i2c_dev Pointer to i2c master device + * + * \return Bytes left in buffer + * \retval =>0 Bytes left in buffer + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) +{ + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return i2c_dev->service.msg.len; + } + + return 0; +} + +/** + * \brief Initialize sercom i2c module to use in sync mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) +{ + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + return _i2c_m_sync_init_impl(&i2c_dev->service, hw); +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + return _i2c_m_enable_implementation(i2c_dev->hw); +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C master interrupt + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state) +{ + if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); + hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); + } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { + hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \brief Wait for bus response + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] flags Store the hardware response + * + * \return Bus response status. + * \retval 0 Bus response status OK + * \retval <0 Bus response fail + */ +inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) +{ + uint32_t timeout = 65535; + void * hw = i2c_dev->hw; + + do { + *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); + + if (timeout-- == 0) { + return I2C_ERR_BUS; + } + } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); + + return I2C_OK; +} + +/** + * \brief Send the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint32_t flags; + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + return _sercom_i2c_sync_analyse_flags(hw, flags, msg); +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail or partial fail, return the error code + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) +{ + uint32_t flags; + int ret; + void * hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return I2C_ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(hw); + + ret = _sercom_i2c_sync_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + while (i2c_dev->service.msg.flags & I2C_M_BUSY) { + ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + + if (ret) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); + } + + return ret; +} + +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +static inline int32_t _i2c_m_enable_implementation(void *const hw) +{ + int timeout = 65535; + int timeout_attempt = 4; + + ASSERT(hw); + + /* Enable interrupts */ + hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); + + while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { + timeout--; + + if (timeout <= 0) { + if (--timeout_attempt) + timeout = 65535; + else + return I2C_ERR_BUSY; + hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); + } + } + return ERR_NONE; +} + +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) +{ + uint8_t i = _get_i2cm_index(hw); + + if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { + uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; + if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE); + } + hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode); + } + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + + hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); + hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); + hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); + + service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); + + service->trise = _i2cms[i].trise; + + return ERR_NONE; +} + + /* SERCOM I2C slave */ + +#ifndef CONF_SERCOM_0_I2CS_ENABLE +#define CONF_SERCOM_0_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CS_ENABLE +#define CONF_SERCOM_1_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CS_ENABLE +#define CONF_SERCOM_2_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CS_ENABLE +#define CONF_SERCOM_3_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CS_ENABLE +#define CONF_SERCOM_4_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CS_ENABLE +#define CONF_SERCOM_5_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CS_ENABLE +#define CONF_SERCOM_6_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CS_ENABLE +#define CONF_SERCOM_7_I2CS_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Slave. */ +#define SERCOM_I2CS_AMOUNT \ + (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ + + CONF_SERCOM_4_I2CS_ENABLE + CONF_SERCOM_5_I2CS_ENABLE + CONF_SERCOM_6_I2CS_ENABLE + CONF_SERCOM_7_I2CS_ENABLE) + +/** + * \brief Macro is used to fill I2C slave configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CS_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ + | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ + | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ + SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ + (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ + | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ + } + +/** + * \brief Macro to check 10-bit addressing + */ +#define I2CS_7BIT_ADDRESSING_MASK 0x7F + +static int32_t _i2c_s_init(void *const hw); +static int8_t _get_i2c_s_index(const void *const hw); +static inline void _i2c_s_deinit(void *const hw); +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); + +/** + * \brief SERCOM I2C slave configuration type + */ +struct i2cs_configuration { + uint8_t number; + hri_sercomi2cs_ctrla_reg_t ctrl_a; + hri_sercomi2cs_ctrlb_reg_t ctrl_b; + hri_sercomi2cs_addr_reg_t address; +}; + +#if SERCOM_I2CS_AMOUNT < 1 +/** Dummy array for compiling. */ +static struct i2cs_configuration _i2css[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2C slave configurations + */ +static struct i2cs_configuration _i2css[] = { +#if CONF_SERCOM_0_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \brief Initialize synchronous I2C slave + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) +{ + int32_t status; + + ASSERT(device); + + status = _i2c_s_init(hw); + if (status) { + return status; + } + device->hw = hw; + + return ERR_NONE; +} + +/** + * \brief Initialize asynchronous I2C slave + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _i2c_s_init(hw); + if (init_status) { + return init_status; + } + + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + // Enable Address Match and PREC interrupt by default. + hri_sercomi2cs_set_INTEN_AMATCH_bit(hw); + hri_sercomi2cs_set_INTEN_PREC_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize synchronous I2C + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) +{ + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize asynchronous I2C + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given I2C instance + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_DATA_reg(device->hw); +} + +/** + * \brief Check if I2C is ready to send next byt + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Check if there is data received by I2C + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Clear the Data Ready interrupt flag + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_INTFLAG_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Abort data transmission + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C slave interrupt + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); + } else if (I2C_S_DEVICE_ERROR == type) { + hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); + } + + return ERR_NONE; +} + +/** + * \internal Initalize i2c slave hardware + * + * \param[in] p The pointer to hardware instance + * + *\ return status of initialization + */ +static int32_t _i2c_s_init(void *const hw) +{ + int8_t i = _get_i2c_s_index(hw); + if (i == -1) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomi2cs_is_syncing(hw, SERCOM_I2CS_CTRLA_SWRST)) { + uint32_t mode = _i2css[i].ctrl_a & SERCOM_I2CS_CTRLA_MODE_Msk; + if (hri_sercomi2cs_get_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_ENABLE)) { + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_ENABLE); + } + hri_sercomi2cs_write_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_SWRST | mode); + } + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + + hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); + hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); + hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); + + return ERR_NONE; +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + * + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2c_s_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2css); i++) { + if (_i2css[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _i2c_s_deinit(void *const hw) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + * \param[in] address Address to set + */ +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) +{ + bool enabled; + + enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); + } + + return ERR_NONE; +} + + /* Sercom SPI implementation */ + +#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE +#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) +#endif + +#define SPI_DEV_IRQ_MODE 0x8000 + +#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) +#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) + +COMPILER_PACK_SET(1) +/** Initialization configuration of registers. */ +struct sercomspi_regs_cfg { + uint32_t ctrla; + uint32_t ctrlb; + uint32_t addr; + uint8_t baud; + uint8_t dbgctrl; + uint16_t dummy_byte; + uint8_t n; +}; +COMPILER_PACK_RESET() + +/** Build configuration from header macros. */ +#define SERCOMSPI_REGS(n) \ + { \ + (((CONF_SERCOM_##n##_SPI_DORD) << SERCOM_SPI_CTRLA_DORD_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ + | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ + | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ + | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ + ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ + | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ + | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ + | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ + (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ + | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ + ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ + (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ + CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ + n /* sercom number */ \ + } + +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_SPI_ENABLE +#define CONF_SERCOM_1_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_SPI_ENABLE +#define CONF_SERCOM_2_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_SPI_ENABLE +#define CONF_SERCOM_4_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_SPI_ENABLE +#define CONF_SERCOM_5_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_SPI_ENABLE +#define CONF_SERCOM_6_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_SPI_ENABLE +#define CONF_SERCOM_7_SPI_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as SPI */ +#define SERCOM_SPI_AMOUNT \ + (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ + + CONF_SERCOM_4_SPI_ENABLE + CONF_SERCOM_5_SPI_ENABLE + CONF_SERCOM_6_SPI_ENABLE + CONF_SERCOM_7_SPI_ENABLE) + +#if SERCOM_SPI_AMOUNT < 1 +/** Dummy array for compiling. */ +static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; +#else +/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ +static const struct sercomspi_regs_cfg sercomspi_regs[] = { +#if CONF_SERCOM_0_SPI_ENABLE + SERCOMSPI_REGS(0), +#endif +#if CONF_SERCOM_1_SPI_ENABLE + SERCOMSPI_REGS(1), +#endif +#if CONF_SERCOM_2_SPI_ENABLE + SERCOMSPI_REGS(2), +#endif +#if CONF_SERCOM_3_SPI_ENABLE + SERCOMSPI_REGS(3), +#endif +#if CONF_SERCOM_4_SPI_ENABLE + SERCOMSPI_REGS(4), +#endif +#if CONF_SERCOM_5_SPI_ENABLE + SERCOMSPI_REGS(5), +#endif +#if CONF_SERCOM_6_SPI_ENABLE + SERCOMSPI_REGS(6), +#endif +#if CONF_SERCOM_7_SPI_ENABLE + SERCOMSPI_REGS(7), +#endif +}; +#endif + +/** \internal De-initialize SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return De-initialization status + */ +static int32_t _spi_deinit(void *const hw) +{ + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_set_CTRLA_SWRST_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_sync_enable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_set_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_async_enable(void *const hw) +{ + _spi_sync_enable(hw); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_sync_disable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_async_disable(void *const hw) +{ + _spi_sync_disable(hw); + hri_sercomspi_clear_INTEN_reg( + hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI mode + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] mode The mode to set + * + * \return Setting mode status + */ +static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); + ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI baudrate + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting baudrate status + */ +static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_write_BAUD_reg(hw, baud_val); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI char size + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * \param[out] size Stored char size + * + * \return Setting char size status + */ +static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) +{ + /* Only 8-bit or 9-bit accepted */ + if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { + return ERR_INVALID_ARG; + } + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { + return ERR_BUSY; + } + + hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); + *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI data order + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting data order status + */ +static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + + if (dord == SPI_DATA_ORDER_LSB_1ST) { + ctrla |= SERCOM_SPI_CTRLA_DORD; + } else { + ctrla &= ~SERCOM_SPI_CTRLA_DORD; + } + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \brief Load SERCOM registers to init for SPI master mode + * The settings will be applied with default master mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg( + hw, + (regs->ctrlb + & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) + | (SERCOM_SPI_CTRLB_RXEN)); + hri_sercomspi_write_BAUD_reg(hw, regs->baud); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); +} + +/** \brief Load SERCOM registers to init for SPI slave mode + * The settings will be applied with default slave mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg(hw, + (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) + | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); + hri_sercomspi_write_ADDR_reg(hw, regs->addr); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); + while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) + ; +} + +/** \brief Return the pointer to register settings of specific SERCOM + * \param[in] hw_addr The hardware register base address. + * \return Pointer to register settings of specific SERCOM. + */ +static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) +{ + uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); + uint8_t i; + + for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { + if (sercomspi_regs[i].n == n) { + return &sercomspi_regs[i]; + } + } + + return NULL; +} + +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) +{ + const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); + + ASSERT(dev && hw); + + if (regs == NULL) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; + if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE); + } + hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode); + } + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + + dev->prvt = hw; + + if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { + _spi_load_regs_slave(hw, regs); + } else { + _spi_load_regs_master(hw, regs); + } + + /* Load character size from default hardware configuration */ + dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; + + dev->dummy_byte = regs->dummy_byte; + + return ERR_NONE; +} + +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) +{ + return _spi_m_sync_init(dev, hw); +} + +int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) +{ + struct _spi_async_dev *spid = dev; + /* Do hardware initialize. */ + int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); + + if (rc < 0) { + return rc; + } + + _sercom_init_irq_param(hw, (void *)dev); + /* Initialize callbacks: must use them */ + spid->callbacks.complete = NULL; + spid->callbacks.rx = NULL; + spid->callbacks.tx = NULL; + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) +{ + return _spi_m_async_init(dev, hw); +} + +int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_m_async_enable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_m_async_disable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) +{ + int32_t rc; + ASSERT(dev); + + /* Not accept 0es */ + if (clk == 0 || baud == 0) { + return ERR_INVALID_ARG; + } + + /* Check baudrate range of current assigned clock */ + if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { + return ERR_INVALID_ARG; + } + + rc = ((clk >> 1) / baud) - 1; + return rc; +} + +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +/** Wait until SPI bus idle. */ +static inline void _spi_wait_bus_idle(void *const hw) +{ + while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { + ; + } + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); +} + +/** Holds run time information for message sync transaction. */ +struct _spi_trans_ctrl { + /** Pointer to transmitting data buffer. */ + uint8_t *txbuf; + /** Pointer to receiving data buffer. */ + uint8_t *rxbuf; + /** Count number of data transmitted. */ + uint32_t txcnt; + /** Count number of data received. */ + uint32_t rxcnt; + /** Data character size. */ + uint8_t char_size; +}; + +/** Check interrupt flag of RXC and update transaction runtime information. */ +static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) +{ + uint32_t data; + + if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { + return false; + } + + data = hri_sercomspi_read_DATA_reg(hw); + + if (ctrl->rxbuf) { + *ctrl->rxbuf++ = (uint8_t)data; + + if (ctrl->char_size > 1) { + *ctrl->rxbuf++ = (uint8_t)(data >> 8); + } + } + + ctrl->rxcnt++; + + return true; +} + +/** Check interrupt flag of DRE and update transaction runtime information. */ +static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, + uint16_t dummy) +{ + uint32_t data; + + if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { + return; + } + + if (ctrl->txbuf) { + data = *ctrl->txbuf++; + + if (ctrl->char_size > 1) { + data |= (*ctrl->txbuf) << 8; + ctrl->txbuf++; + } + } else { + data = dummy; + } + + ctrl->txcnt++; + hri_sercomspi_write_DATA_reg(hw, data); +} + +/** Check interrupt flag of ERROR and update transaction runtime information. */ +static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) +{ + if (SERCOM_SPI_INTFLAG_ERROR & iflag) { + hri_sercomspi_clear_STATUS_reg(hw, ~0); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return ERR_OVERFLOW; + } + + return ERR_NONE; +} + +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) +{ + void * hw = dev->prvt; + int32_t rc = 0; + struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; + + ASSERT(dev && hw); + + /* If settings are not applied (pending), we can not go on */ + if (hri_sercomspi_is_syncing( + hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { + return ERR_BUSY; + } + + /* SPI must be enabled to start synchronous transfer */ + if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { + return ERR_NOT_INITIALIZED; + } + + for (;;) { + uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); + + if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { + /* In master mode, do not start next byte before previous byte received + * to make better output waveform */ + if (ctrl.rxcnt >= ctrl.txcnt) { + _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); + } + } + + rc = _spi_err_check(iflag, hw); + + if (rc < 0) { + break; + } + if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { + rc = ctrl.txcnt; + break; + } + } + /* Wait until SPI bus idle */ + _spi_wait_bus_idle(hw); + + return rc; +} + +int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (state) { + hri_sercomspi_set_INTEN_DRE_bit(hw); + } else { + hri_sercomspi_clear_INTEN_DRE_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx(dev, state); +} + +int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev); + ASSERT(hw); + + if (state) { + hri_sercomspi_set_INTEN_RXC_bit(hw); + } else { + hri_sercomspi_clear_INTEN_RXC_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_rx(dev, state); +} + +int32_t _spi_m_async_enable_tx_complete(struct _spi_async_dev *dev, bool state) +{ + ASSERT(dev && dev->prvt); + + if (state) { + hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); + } else { + hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx_complete(dev, state); +} + +int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + typedef void (*func_t)(void); + struct _spi_async_dev *spid = dev; + + ASSERT(dev && (cb_type < SPI_DEV_CB_N)); + + func_t *p_ls = (func_t *)&spid->callbacks; + p_ls[cb_type] = (func_t)func; + + return ERR_NONE; +} + +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + return _spi_m_async_register_callback(dev, cb_type, func); +} + +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); +} + +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); +} + +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); + return true; + } + return false; +} + +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { + hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return true; + } + return false; +} + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + ASSERT(device); + + if (SPI_DEV_CB_ERROR == type) { + hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); + } +} + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + _spi_m_async_set_irq_state(device, type, state); +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_ac_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_ac_c21.h new file mode 100644 index 0000000..5a88b97 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_ac_c21.h @@ -0,0 +1,2241 @@ +/** + * \file + * + * \brief SAM AC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_AC_COMPONENT_ +#ifndef _HRI_AC_C21_H_INCLUDED_ +#define _HRI_AC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AC_CRITICAL_SECTIONS) +#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AC_CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_ac_evctrl_reg_t; +typedef uint32_t hri_ac_compctrl_reg_t; +typedef uint32_t hri_ac_syncbusy_reg_t; +typedef uint8_t hri_ac_ctrla_reg_t; +typedef uint8_t hri_ac_ctrlb_reg_t; +typedef uint8_t hri_ac_dbgctrl_reg_t; +typedef uint8_t hri_ac_intenset_reg_t; +typedef uint8_t hri_ac_intflag_reg_t; +typedef uint8_t hri_ac_scaler_reg_t; +typedef uint8_t hri_ac_statusa_reg_t; +typedef uint8_t hri_ac_statusb_reg_t; +typedef uint8_t hri_ac_winctrl_reg_t; + +static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + while (((Ac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + return ((Ac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_INTFLAG_COMP2_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP2) >> AC_INTFLAG_COMP2_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP2_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP2; +} + +static inline bool hri_ac_get_INTFLAG_COMP3_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP3) >> AC_INTFLAG_COMP3_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP3_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP3; +} + +static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline bool hri_ac_get_INTFLAG_WIN1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN1) >> AC_INTFLAG_WIN1_Pos; +} + +static inline void hri_ac_clear_INTFLAG_WIN1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN1; +} + +static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_interrupt_COMP2_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP2) >> AC_INTFLAG_COMP2_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP2_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP2; +} + +static inline bool hri_ac_get_interrupt_COMP3_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP3) >> AC_INTFLAG_COMP3_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP3_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP3; +} + +static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline bool hri_ac_get_interrupt_WIN1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN1) >> AC_INTFLAG_WIN1_Pos; +} + +static inline void hri_ac_clear_interrupt_WIN1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN1; +} + +static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) +{ + return ((Ac *)hw)->INTFLAG.reg; +} + +static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + ((Ac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; +} + +static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; +} + +static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; + } +} + +static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; +} + +static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; +} + +static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; +} + +static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; + } +} + +static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; +} + +static inline void hri_ac_set_INTEN_COMP2_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP2; +} + +static inline bool hri_ac_get_INTEN_COMP2_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP2) >> AC_INTENSET_COMP2_Pos; +} + +static inline void hri_ac_write_INTEN_COMP2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP2; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP2; + } +} + +static inline void hri_ac_clear_INTEN_COMP2_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP2; +} + +static inline void hri_ac_set_INTEN_COMP3_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP3; +} + +static inline bool hri_ac_get_INTEN_COMP3_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP3) >> AC_INTENSET_COMP3_Pos; +} + +static inline void hri_ac_write_INTEN_COMP3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP3; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP3; + } +} + +static inline void hri_ac_clear_INTEN_COMP3_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP3; +} + +static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; +} + +static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; +} + +static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; + } +} + +static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; +} + +static inline void hri_ac_set_INTEN_WIN1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN1; +} + +static inline bool hri_ac_get_INTEN_WIN1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN1) >> AC_INTENSET_WIN1_Pos; +} + +static inline void hri_ac_write_INTEN_WIN1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN1; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN1; + } +} + +static inline void hri_ac_clear_INTEN_WIN1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN1; +} + +static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENSET.reg = mask; +} + +static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) +{ + return ((Ac *)hw)->INTENSET.reg; +} + +static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) +{ + ((Ac *)hw)->INTENSET.reg = data; + ((Ac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE2_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE2) >> AC_STATUSA_STATE2_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE3_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE3) >> AC_STATUSA_STATE3_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE1_bf(const void *const hw, hri_ac_statusa_reg_t mask) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE1(mask)) >> AC_STATUSA_WSTATE1_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE1_bf(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE1_Msk) >> AC_STATUSA_WSTATE1_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSA.reg; +} + +static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY2_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY2) >> AC_STATUSB_READY2_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY3_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY3) >> AC_STATUSB_READY3_Pos; +} + +static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSB.reg; +} + +static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL2_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL2) >> AC_SYNCBUSY_COMPCTRL2_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL3_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL3) >> AC_SYNCBUSY_COMPCTRL3_Pos; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Ac *)hw)->SYNCBUSY.reg; +} + +static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= ~AC_CTRLA_ENABLE; + tmp |= value << AC_CTRLA_ENABLE_Pos; + ((Ac *)hw)->CTRLA.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->CTRLA.reg; +} + +static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO0; + tmp |= value << AC_EVCTRL_COMPEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO1; + tmp |= value << AC_EVCTRL_COMPEO1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO2) >> AC_EVCTRL_COMPEO2_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO2; + tmp |= value << AC_EVCTRL_COMPEO2_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO3) >> AC_EVCTRL_COMPEO3_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO3; + tmp |= value << AC_EVCTRL_COMPEO3_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_WINEO0; + tmp |= value << AC_EVCTRL_WINEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_WINEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_WINEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_WINEO1) >> AC_EVCTRL_WINEO1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_WINEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_WINEO1; + tmp |= value << AC_EVCTRL_WINEO1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_WINEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_WINEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI0; + tmp |= value << AC_EVCTRL_COMPEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI1; + tmp |= value << AC_EVCTRL_COMPEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI2) >> AC_EVCTRL_COMPEI2_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI2; + tmp |= value << AC_EVCTRL_COMPEI2_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI3) >> AC_EVCTRL_COMPEI3_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI3; + tmp |= value << AC_EVCTRL_COMPEI3_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI0; + tmp |= value << AC_EVCTRL_INVEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI1; + tmp |= value << AC_EVCTRL_INVEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI2) >> AC_EVCTRL_INVEI2_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI2; + tmp |= value << AC_EVCTRL_INVEI2_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI3) >> AC_EVCTRL_INVEI3_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI3; + tmp |= value << AC_EVCTRL_INVEI3_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->EVCTRL.reg; +} + +static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= ~AC_DBGCTRL_DBGRUN; + tmp |= value << AC_DBGCTRL_DBGRUN_Pos; + ((Ac *)hw)->DBGCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->DBGCTRL.reg; +} + +static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WEN0; + tmp |= value << AC_WINCTRL_WEN0_Pos; + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_WINCTRL_WEN1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN1; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_WINCTRL_WEN1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WEN1) >> AC_WINCTRL_WEN1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_WINCTRL_WEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WEN1; + tmp |= value << AC_WINCTRL_WEN1_Pos; + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WEN1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN1; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WEN1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN1; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WINTSEL0_Msk; + tmp |= AC_WINCTRL_WINTSEL0(data); + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_set_WINCTRL_WINTSEL1_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL1(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL1_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL1(mask)) >> AC_WINCTRL_WINTSEL1_Pos; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_WINTSEL1_bf(const void *const hw, hri_ac_winctrl_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WINTSEL1_Msk; + tmp |= AC_WINCTRL_WINTSEL1(data); + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WINTSEL1_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL1(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WINTSEL1_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL1(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL1_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL1_Msk) >> AC_WINCTRL_WINTSEL1_Pos; + return tmp; +} + +static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + return ((Ac *)hw)->WINCTRL.reg; +} + +static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, + hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= ~AC_SCALER_VALUE_Msk; + tmp |= AC_SCALER_VALUE(data); + ((Ac *)hw)->SCALER[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) +{ + return ((Ac *)hw)->SCALER[index].reg; +} + +static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_ENABLE; + tmp |= value << AC_COMPCTRL_ENABLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SINGLE; + tmp |= value << AC_COMPCTRL_SINGLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_RUNSTDBY; + tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SWAP; + tmp |= value << AC_COMPCTRL_SWAP_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYSTEN; + tmp |= value << AC_COMPCTRL_HYSTEN_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_INTSEL_Msk; + tmp |= AC_COMPCTRL_INTSEL(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXNEG_Msk; + tmp |= AC_COMPCTRL_MUXNEG(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXPOS_Msk; + tmp |= AC_COMPCTRL_MUXPOS(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SPEED_Msk; + tmp |= AC_COMPCTRL_SPEED(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_FLEN_Msk; + tmp |= AC_COMPCTRL_FLEN(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_OUT_Msk; + tmp |= AC_COMPCTRL_OUT(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->COMPCTRL[index].reg; +} + +static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AC_C21_H_INCLUDED */ +#endif /* _SAMC21_AC_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_adc_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_adc_c21.h new file mode 100644 index 0000000..21d74db --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_adc_c21.h @@ -0,0 +1,2847 @@ +/** + * \file + * + * \brief SAM ADC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_ADC_COMPONENT_ +#ifndef _HRI_ADC_C21_H_INCLUDED_ +#define _HRI_ADC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ADC_CRITICAL_SECTIONS) +#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ADC_CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_adc_calib_reg_t; +typedef uint16_t hri_adc_ctrlc_reg_t; +typedef uint16_t hri_adc_gaincorr_reg_t; +typedef uint16_t hri_adc_inputctrl_reg_t; +typedef uint16_t hri_adc_offsetcorr_reg_t; +typedef uint16_t hri_adc_result_reg_t; +typedef uint16_t hri_adc_syncbusy_reg_t; +typedef uint16_t hri_adc_winlt_reg_t; +typedef uint16_t hri_adc_winut_reg_t; +typedef uint32_t hri_adc_seqctrl_reg_t; +typedef uint8_t hri_adc_avgctrl_reg_t; +typedef uint8_t hri_adc_ctrla_reg_t; +typedef uint8_t hri_adc_ctrlb_reg_t; +typedef uint8_t hri_adc_dbgctrl_reg_t; +typedef uint8_t hri_adc_evctrl_reg_t; +typedef uint8_t hri_adc_intenset_reg_t; +typedef uint8_t hri_adc_intflag_reg_t; +typedef uint8_t hri_adc_refctrl_reg_t; +typedef uint8_t hri_adc_sampctrl_reg_t; +typedef uint8_t hri_adc_seqstatus_reg_t; +typedef uint8_t hri_adc_swtrig_reg_t; + +static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + while (((Adc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + return ((Adc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) +{ + return ((Adc *)hw)->INTFLAG.reg; +} + +static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + ((Adc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; +} + +static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; +} + +static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; + } +} + +static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; +} + +static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; +} + +static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; +} + +static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; + } +} + +static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; +} + +static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; +} + +static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; +} + +static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; + } +} + +static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; +} + +static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENSET.reg = mask; +} + +static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) +{ + return ((Adc *)hw)->INTENSET.reg; +} + +static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) +{ + ((Adc *)hw)->INTENSET.reg = data; + ((Adc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_adc_get_SEQSTATUS_SEQBUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQBUSY) >> ADC_SEQSTATUS_SEQBUSY_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_SEQSTATE_bf(const void *const hw, + hri_adc_seqstatus_reg_t mask) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE(mask)) >> ADC_SEQSTATUS_SEQSTATE_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_SEQSTATE_bf(const void *const hw) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE_Msk) >> ADC_SEQSTATUS_SEQSTATE_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_reg(const void *const hw, hri_adc_seqstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SEQSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_reg(const void *const hw) +{ + return ((Adc *)hw)->SEQSTATUS.reg; +} + +static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_CTRLC_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLC) >> ADC_SYNCBUSY_CTRLC_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Adc *)hw)->SYNCBUSY.reg; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) +{ + return ((Adc *)hw)->RESULT.reg; +} + +static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ENABLE; + tmp |= value << ADC_CTRLA_ENABLE_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SLAVEEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SLAVEEN) >> ADC_CTRLA_SLAVEEN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_SLAVEEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_SLAVEEN; + tmp |= value << ADC_CTRLA_SLAVEEN_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_RUNSTDBY; + tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ONDEMAND; + tmp |= value << ADC_CTRLA_ONDEMAND_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + return ((Adc *)hw)->CTRLA.reg; +} + +static inline void hri_adc_set_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_PRESCALER(mask)) >> ADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_PRESCALER_Msk; + tmp |= ADC_CTRLB_PRESCALER(data); + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_PRESCALER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_PRESCALER_Msk) >> ADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) +{ + return ((Adc *)hw)->CTRLB.reg; +} + +static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFCOMP; + tmp |= value << ADC_REFCTRL_REFCOMP_Pos; + ((Adc *)hw)->REFCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFSEL_Msk; + tmp |= ADC_REFCTRL_REFSEL(data); + ((Adc *)hw)->REFCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->REFCTRL.reg; +} + +static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHEI; + tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTEI; + tmp |= value << ADC_EVCTRL_STARTEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHINV; + tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTINV; + tmp |= value << ADC_EVCTRL_STARTINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_RESRDYEO; + tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_WINMONEO; + tmp |= value << ADC_EVCTRL_WINMONEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->EVCTRL.reg; +} + +static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; + tmp |= ADC_INPUTCTRL_MUXPOS(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; + tmp |= ADC_INPUTCTRL_MUXNEG(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->INPUTCTRL.reg; +} + +static inline void hri_adc_set_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_DIFFMODE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_DIFFMODE) >> ADC_CTRLC_DIFFMODE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_DIFFMODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_DIFFMODE; + tmp |= value << ADC_CTRLC_DIFFMODE_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_LEFTADJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_LEFTADJ) >> ADC_CTRLC_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_LEFTADJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_LEFTADJ; + tmp |= value << ADC_CTRLC_LEFTADJ_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_FREERUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_FREERUN) >> ADC_CTRLC_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_FREERUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_FREERUN; + tmp |= value << ADC_CTRLC_FREERUN_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_CORREN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_CORREN) >> ADC_CTRLC_CORREN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_CORREN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_CORREN; + tmp |= value << ADC_CTRLC_CORREN_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_R2R_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_R2R) >> ADC_CTRLC_R2R_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_R2R_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_R2R; + tmp |= value << ADC_CTRLC_R2R_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_RESSEL(mask)) >> ADC_CTRLC_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_RESSEL_Msk; + tmp |= ADC_CTRLC_RESSEL(data); + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_RESSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_RESSEL_Msk) >> ADC_CTRLC_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_WINMODE(mask)) >> ADC_CTRLC_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_WINMODE_Msk; + tmp |= ADC_CTRLC_WINMODE(data); + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_WINMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_WINMODE_Msk) >> ADC_CTRLC_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_DUALSEL(mask)) >> ADC_CTRLC_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_DUALSEL_Msk; + tmp |= ADC_CTRLC_DUALSEL(data); + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_DUALSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_DUALSEL_Msk) >> ADC_CTRLC_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->CTRLC.reg; +} + +static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; + tmp |= ADC_AVGCTRL_SAMPLENUM(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_ADJRES_Msk; + tmp |= ADC_AVGCTRL_ADJRES(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->AVGCTRL.reg; +} + +static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_OFFCOMP; + tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; + tmp |= ADC_SAMPCTRL_SAMPLEN(data); + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SAMPCTRL.reg; +} + +static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= ~ADC_WINLT_WINLT_Msk; + tmp |= ADC_WINLT_WINLT(data); + ((Adc *)hw)->WINLT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + return ((Adc *)hw)->WINLT.reg; +} + +static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= ~ADC_WINUT_WINUT_Msk; + tmp |= ADC_WINUT_WINUT(data); + ((Adc *)hw)->WINUT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + return ((Adc *)hw)->WINUT.reg; +} + +static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= ~ADC_GAINCORR_GAINCORR_Msk; + tmp |= ADC_GAINCORR_GAINCORR(data); + ((Adc *)hw)->GAINCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + return ((Adc *)hw)->GAINCORR.reg; +} + +static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, + hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; + tmp |= ADC_OFFSETCORR_OFFSETCORR(data); + ((Adc *)hw)->OFFSETCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->OFFSETCORR.reg; +} + +static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_FLUSH; + tmp |= value << ADC_SWTRIG_FLUSH_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_START; + tmp |= value << ADC_SWTRIG_START_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SWTRIG.reg; +} + +static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= ~ADC_DBGCTRL_DBGRUN; + tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; + ((Adc *)hw)->DBGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->DBGCTRL.reg; +} + +static inline void hri_adc_set_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg |= ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp = (tmp & ADC_SEQCTRL_SEQEN(mask)) >> ADC_SEQCTRL_SEQEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t data) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp &= ~ADC_SEQCTRL_SEQEN_Msk; + tmp |= ADC_SEQCTRL_SEQEN(data); + ((Adc *)hw)->SEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg &= ~ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg ^= ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_SEQEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp = (tmp & ADC_SEQCTRL_SEQEN_Msk) >> ADC_SEQCTRL_SEQEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->SEQCTRL.reg; +} + +static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASCOMP_Msk; + tmp |= ADC_CALIB_BIASCOMP(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASREFBUF_Msk; + tmp |= ADC_CALIB_BIASREFBUF(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) +{ + return ((Adc *)hw)->CALIB.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ADC_C21_H_INCLUDED */ +#endif /* _SAMC21_ADC_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_c21.h new file mode 100644 index 0000000..8dd7d9b --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_c21.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief SAM C21 HRI top-level header file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HRI_C21_H_INCLUDED_ +#define _HRI_C21_H_INCLUDED_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* _HRI_C21_H_INCLUDED_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_can_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_can_c21.h new file mode 100644 index 0000000..42bf5eb --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_can_c21.h @@ -0,0 +1,16997 @@ +/** + * \file + * + * \brief SAM CAN + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_CAN_COMPONENT_ +#ifndef _HRI_CAN_C21_H_INCLUDED_ +#define _HRI_CAN_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CAN_CRITICAL_SECTIONS) +#define CAN_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CAN_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CAN_CRITICAL_SECTION_ENTER() +#define CAN_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_can_cccr_reg_t; +typedef uint32_t hri_can_crel_reg_t; +typedef uint32_t hri_can_dbtp_reg_t; +typedef uint32_t hri_can_ecr_reg_t; +typedef uint32_t hri_can_endn_reg_t; +typedef uint32_t hri_can_gfc_reg_t; +typedef uint32_t hri_can_hpms_reg_t; +typedef uint32_t hri_can_ie_reg_t; +typedef uint32_t hri_can_ile_reg_t; +typedef uint32_t hri_can_ils_reg_t; +typedef uint32_t hri_can_ir_reg_t; +typedef uint32_t hri_can_mrcfg_reg_t; +typedef uint32_t hri_can_nbtp_reg_t; +typedef uint32_t hri_can_ndat1_reg_t; +typedef uint32_t hri_can_ndat2_reg_t; +typedef uint32_t hri_can_psr_reg_t; +typedef uint32_t hri_can_rwd_reg_t; +typedef uint32_t hri_can_rxbc_reg_t; +typedef uint32_t hri_can_rxesc_reg_t; +typedef uint32_t hri_can_rxf0a_reg_t; +typedef uint32_t hri_can_rxf0c_reg_t; +typedef uint32_t hri_can_rxf0s_reg_t; +typedef uint32_t hri_can_rxf1a_reg_t; +typedef uint32_t hri_can_rxf1c_reg_t; +typedef uint32_t hri_can_rxf1s_reg_t; +typedef uint32_t hri_can_sidfc_reg_t; +typedef uint32_t hri_can_tdcr_reg_t; +typedef uint32_t hri_can_test_reg_t; +typedef uint32_t hri_can_tocc_reg_t; +typedef uint32_t hri_can_tocv_reg_t; +typedef uint32_t hri_can_tscc_reg_t; +typedef uint32_t hri_can_tscv_reg_t; +typedef uint32_t hri_can_txbar_reg_t; +typedef uint32_t hri_can_txbc_reg_t; +typedef uint32_t hri_can_txbcf_reg_t; +typedef uint32_t hri_can_txbcie_reg_t; +typedef uint32_t hri_can_txbcr_reg_t; +typedef uint32_t hri_can_txbrp_reg_t; +typedef uint32_t hri_can_txbtie_reg_t; +typedef uint32_t hri_can_txbto_reg_t; +typedef uint32_t hri_can_txefa_reg_t; +typedef uint32_t hri_can_txefc_reg_t; +typedef uint32_t hri_can_txefs_reg_t; +typedef uint32_t hri_can_txesc_reg_t; +typedef uint32_t hri_can_txfqs_reg_t; +typedef uint32_t hri_can_xidam_reg_t; +typedef uint32_t hri_can_xidfc_reg_t; + +static inline hri_can_crel_reg_t hri_can_get_CREL_SUBSTEP_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP(mask)) >> CAN_CREL_SUBSTEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_SUBSTEP_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP_Msk) >> CAN_CREL_SUBSTEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_STEP_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_STEP(mask)) >> CAN_CREL_STEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_STEP_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_STEP_Msk) >> CAN_CREL_STEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_REL_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_REL(mask)) >> CAN_CREL_REL_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_REL_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_REL_Msk) >> CAN_CREL_REL_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_reg(const void *const hw, hri_can_crel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CREL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_reg(const void *const hw) +{ + return ((Can *)hw)->CREL.reg; +} + +static inline hri_can_endn_reg_t hri_can_get_ENDN_ETV_bf(const void *const hw, hri_can_endn_reg_t mask) +{ + return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV(mask)) >> CAN_ENDN_ETV_Pos; +} + +static inline hri_can_endn_reg_t hri_can_read_ENDN_ETV_bf(const void *const hw) +{ + return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV_Msk) >> CAN_ENDN_ETV_Pos; +} + +static inline hri_can_endn_reg_t hri_can_get_ENDN_reg(const void *const hw, hri_can_endn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ENDN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_endn_reg_t hri_can_read_ENDN_reg(const void *const hw) +{ + return ((Can *)hw)->ENDN.reg; +} + +static inline hri_can_tscv_reg_t hri_can_get_TSCV_TSC_bf(const void *const hw, hri_can_tscv_reg_t mask) +{ + return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC(mask)) >> CAN_TSCV_TSC_Pos; +} + +static inline hri_can_tscv_reg_t hri_can_read_TSCV_TSC_bf(const void *const hw) +{ + return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC_Msk) >> CAN_TSCV_TSC_Pos; +} + +static inline hri_can_tscv_reg_t hri_can_get_TSCV_reg(const void *const hw, hri_can_tscv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCV.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_tscv_reg_t hri_can_read_TSCV_reg(const void *const hw) +{ + return ((Can *)hw)->TSCV.reg; +} + +static inline bool hri_can_get_ECR_RP_bit(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_RP) >> CAN_ECR_RP_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_TEC_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_TEC(mask)) >> CAN_ECR_TEC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_TEC_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_REC_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_REC(mask)) >> CAN_ECR_REC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_REC_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_CEL_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_CEL(mask)) >> CAN_ECR_CEL_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_CEL_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_CEL_Msk) >> CAN_ECR_CEL_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_reg(const void *const hw, hri_can_ecr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ECR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_reg(const void *const hw) +{ + return ((Can *)hw)->ECR.reg; +} + +static inline bool hri_can_get_PSR_EP_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_EP) >> CAN_PSR_EP_Pos; +} + +static inline bool hri_can_get_PSR_EW_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_EW) >> CAN_PSR_EW_Pos; +} + +static inline bool hri_can_get_PSR_BO_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_BO) >> CAN_PSR_BO_Pos; +} + +static inline bool hri_can_get_PSR_RESI_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RESI) >> CAN_PSR_RESI_Pos; +} + +static inline bool hri_can_get_PSR_RBRS_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RBRS) >> CAN_PSR_RBRS_Pos; +} + +static inline bool hri_can_get_PSR_RFDF_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RFDF) >> CAN_PSR_RFDF_Pos; +} + +static inline bool hri_can_get_PSR_PXE_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_PXE) >> CAN_PSR_PXE_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_LEC_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_LEC(mask)) >> CAN_PSR_LEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_LEC_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_LEC_Msk) >> CAN_PSR_LEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_ACT_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_ACT(mask)) >> CAN_PSR_ACT_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_ACT_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_ACT_Msk) >> CAN_PSR_ACT_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_DLEC_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC(mask)) >> CAN_PSR_DLEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_DLEC_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC_Msk) >> CAN_PSR_DLEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_TDCV_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV(mask)) >> CAN_PSR_TDCV_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_TDCV_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV_Msk) >> CAN_PSR_TDCV_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_reg(const void *const hw, hri_can_psr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->PSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_reg(const void *const hw) +{ + return ((Can *)hw)->PSR.reg; +} + +static inline bool hri_can_get_HPMS_FLST_bit(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FLST) >> CAN_HPMS_FLST_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_BIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX(mask)) >> CAN_HPMS_BIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_BIDX_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX_Msk) >> CAN_HPMS_BIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_MSI_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI(mask)) >> CAN_HPMS_MSI_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_MSI_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI_Msk) >> CAN_HPMS_MSI_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_FIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX(mask)) >> CAN_HPMS_FIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_FIDX_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX_Msk) >> CAN_HPMS_FIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_reg(const void *const hw, hri_can_hpms_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->HPMS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_reg(const void *const hw) +{ + return ((Can *)hw)->HPMS.reg; +} + +static inline bool hri_can_get_RXF0S_F0F_bit(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0F) >> CAN_RXF0S_F0F_Pos; +} + +static inline bool hri_can_get_RXF0S_RF0L_bit(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_RF0L) >> CAN_RXF0S_RF0L_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0FL_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL(mask)) >> CAN_RXF0S_F0FL_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0FL_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL_Msk) >> CAN_RXF0S_F0FL_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0GI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI(mask)) >> CAN_RXF0S_F0GI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0GI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0PI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI(mask)) >> CAN_RXF0S_F0PI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0PI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI_Msk) >> CAN_RXF0S_F0PI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_reg(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0S.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0S.reg; +} + +static inline bool hri_can_get_RXF1S_F1F_bit(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1F) >> CAN_RXF1S_F1F_Pos; +} + +static inline bool hri_can_get_RXF1S_RF1L_bit(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_RF1L) >> CAN_RXF1S_RF1L_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1FL_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL(mask)) >> CAN_RXF1S_F1FL_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1FL_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL_Msk) >> CAN_RXF1S_F1FL_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1GI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI(mask)) >> CAN_RXF1S_F1GI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1GI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1PI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI(mask)) >> CAN_RXF1S_F1PI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1PI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI_Msk) >> CAN_RXF1S_F1PI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_DMS_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS(mask)) >> CAN_RXF1S_DMS_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_DMS_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS_Msk) >> CAN_RXF1S_DMS_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_reg(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1S.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1S.reg; +} + +static inline bool hri_can_get_TXFQS_TFQF_bit(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQF) >> CAN_TXFQS_TFQF_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFFL_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL(mask)) >> CAN_TXFQS_TFFL_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFFL_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL_Msk) >> CAN_TXFQS_TFFL_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFGI_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI(mask)) >> CAN_TXFQS_TFGI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFGI_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI_Msk) >> CAN_TXFQS_TFGI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFQPI_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI(mask)) >> CAN_TXFQS_TFQPI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFQPI_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_reg(const void *const hw, hri_can_txfqs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXFQS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_reg(const void *const hw) +{ + return ((Can *)hw)->TXFQS.reg; +} + +static inline bool hri_can_get_TXBRP_TRP0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP0) >> CAN_TXBRP_TRP0_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP1) >> CAN_TXBRP_TRP1_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP2) >> CAN_TXBRP_TRP2_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP3) >> CAN_TXBRP_TRP3_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP4) >> CAN_TXBRP_TRP4_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP5) >> CAN_TXBRP_TRP5_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP6) >> CAN_TXBRP_TRP6_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP7) >> CAN_TXBRP_TRP7_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP8) >> CAN_TXBRP_TRP8_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP9) >> CAN_TXBRP_TRP9_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP10) >> CAN_TXBRP_TRP10_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP11) >> CAN_TXBRP_TRP11_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP12) >> CAN_TXBRP_TRP12_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP13) >> CAN_TXBRP_TRP13_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP14) >> CAN_TXBRP_TRP14_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP15) >> CAN_TXBRP_TRP15_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP16) >> CAN_TXBRP_TRP16_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP17) >> CAN_TXBRP_TRP17_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP18) >> CAN_TXBRP_TRP18_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP19) >> CAN_TXBRP_TRP19_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP20) >> CAN_TXBRP_TRP20_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP21) >> CAN_TXBRP_TRP21_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP22) >> CAN_TXBRP_TRP22_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP23) >> CAN_TXBRP_TRP23_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP24) >> CAN_TXBRP_TRP24_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP25) >> CAN_TXBRP_TRP25_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP26) >> CAN_TXBRP_TRP26_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP27) >> CAN_TXBRP_TRP27_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP28) >> CAN_TXBRP_TRP28_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP29) >> CAN_TXBRP_TRP29_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP30) >> CAN_TXBRP_TRP30_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP31) >> CAN_TXBRP_TRP31_Pos; +} + +static inline hri_can_txbrp_reg_t hri_can_get_TXBRP_reg(const void *const hw, hri_can_txbrp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBRP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbrp_reg_t hri_can_read_TXBRP_reg(const void *const hw) +{ + return ((Can *)hw)->TXBRP.reg; +} + +static inline bool hri_can_get_TXBTO_TO0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO0) >> CAN_TXBTO_TO0_Pos; +} + +static inline bool hri_can_get_TXBTO_TO1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO1) >> CAN_TXBTO_TO1_Pos; +} + +static inline bool hri_can_get_TXBTO_TO2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO2) >> CAN_TXBTO_TO2_Pos; +} + +static inline bool hri_can_get_TXBTO_TO3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO3) >> CAN_TXBTO_TO3_Pos; +} + +static inline bool hri_can_get_TXBTO_TO4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO4) >> CAN_TXBTO_TO4_Pos; +} + +static inline bool hri_can_get_TXBTO_TO5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO5) >> CAN_TXBTO_TO5_Pos; +} + +static inline bool hri_can_get_TXBTO_TO6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO6) >> CAN_TXBTO_TO6_Pos; +} + +static inline bool hri_can_get_TXBTO_TO7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO7) >> CAN_TXBTO_TO7_Pos; +} + +static inline bool hri_can_get_TXBTO_TO8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO8) >> CAN_TXBTO_TO8_Pos; +} + +static inline bool hri_can_get_TXBTO_TO9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO9) >> CAN_TXBTO_TO9_Pos; +} + +static inline bool hri_can_get_TXBTO_TO10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO10) >> CAN_TXBTO_TO10_Pos; +} + +static inline bool hri_can_get_TXBTO_TO11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO11) >> CAN_TXBTO_TO11_Pos; +} + +static inline bool hri_can_get_TXBTO_TO12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO12) >> CAN_TXBTO_TO12_Pos; +} + +static inline bool hri_can_get_TXBTO_TO13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO13) >> CAN_TXBTO_TO13_Pos; +} + +static inline bool hri_can_get_TXBTO_TO14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO14) >> CAN_TXBTO_TO14_Pos; +} + +static inline bool hri_can_get_TXBTO_TO15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO15) >> CAN_TXBTO_TO15_Pos; +} + +static inline bool hri_can_get_TXBTO_TO16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO16) >> CAN_TXBTO_TO16_Pos; +} + +static inline bool hri_can_get_TXBTO_TO17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO17) >> CAN_TXBTO_TO17_Pos; +} + +static inline bool hri_can_get_TXBTO_TO18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO18) >> CAN_TXBTO_TO18_Pos; +} + +static inline bool hri_can_get_TXBTO_TO19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO19) >> CAN_TXBTO_TO19_Pos; +} + +static inline bool hri_can_get_TXBTO_TO20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO20) >> CAN_TXBTO_TO20_Pos; +} + +static inline bool hri_can_get_TXBTO_TO21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO21) >> CAN_TXBTO_TO21_Pos; +} + +static inline bool hri_can_get_TXBTO_TO22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO22) >> CAN_TXBTO_TO22_Pos; +} + +static inline bool hri_can_get_TXBTO_TO23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO23) >> CAN_TXBTO_TO23_Pos; +} + +static inline bool hri_can_get_TXBTO_TO24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO24) >> CAN_TXBTO_TO24_Pos; +} + +static inline bool hri_can_get_TXBTO_TO25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO25) >> CAN_TXBTO_TO25_Pos; +} + +static inline bool hri_can_get_TXBTO_TO26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO26) >> CAN_TXBTO_TO26_Pos; +} + +static inline bool hri_can_get_TXBTO_TO27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO27) >> CAN_TXBTO_TO27_Pos; +} + +static inline bool hri_can_get_TXBTO_TO28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO28) >> CAN_TXBTO_TO28_Pos; +} + +static inline bool hri_can_get_TXBTO_TO29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO29) >> CAN_TXBTO_TO29_Pos; +} + +static inline bool hri_can_get_TXBTO_TO30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO30) >> CAN_TXBTO_TO30_Pos; +} + +static inline bool hri_can_get_TXBTO_TO31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO31) >> CAN_TXBTO_TO31_Pos; +} + +static inline hri_can_txbto_reg_t hri_can_get_TXBTO_reg(const void *const hw, hri_can_txbto_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTO.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbto_reg_t hri_can_read_TXBTO_reg(const void *const hw) +{ + return ((Can *)hw)->TXBTO.reg; +} + +static inline bool hri_can_get_TXBCF_CF0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF0) >> CAN_TXBCF_CF0_Pos; +} + +static inline bool hri_can_get_TXBCF_CF1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF1) >> CAN_TXBCF_CF1_Pos; +} + +static inline bool hri_can_get_TXBCF_CF2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF2) >> CAN_TXBCF_CF2_Pos; +} + +static inline bool hri_can_get_TXBCF_CF3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF3) >> CAN_TXBCF_CF3_Pos; +} + +static inline bool hri_can_get_TXBCF_CF4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF4) >> CAN_TXBCF_CF4_Pos; +} + +static inline bool hri_can_get_TXBCF_CF5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF5) >> CAN_TXBCF_CF5_Pos; +} + +static inline bool hri_can_get_TXBCF_CF6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF6) >> CAN_TXBCF_CF6_Pos; +} + +static inline bool hri_can_get_TXBCF_CF7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF7) >> CAN_TXBCF_CF7_Pos; +} + +static inline bool hri_can_get_TXBCF_CF8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF8) >> CAN_TXBCF_CF8_Pos; +} + +static inline bool hri_can_get_TXBCF_CF9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF9) >> CAN_TXBCF_CF9_Pos; +} + +static inline bool hri_can_get_TXBCF_CF10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF10) >> CAN_TXBCF_CF10_Pos; +} + +static inline bool hri_can_get_TXBCF_CF11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF11) >> CAN_TXBCF_CF11_Pos; +} + +static inline bool hri_can_get_TXBCF_CF12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF12) >> CAN_TXBCF_CF12_Pos; +} + +static inline bool hri_can_get_TXBCF_CF13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF13) >> CAN_TXBCF_CF13_Pos; +} + +static inline bool hri_can_get_TXBCF_CF14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF14) >> CAN_TXBCF_CF14_Pos; +} + +static inline bool hri_can_get_TXBCF_CF15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF15) >> CAN_TXBCF_CF15_Pos; +} + +static inline bool hri_can_get_TXBCF_CF16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF16) >> CAN_TXBCF_CF16_Pos; +} + +static inline bool hri_can_get_TXBCF_CF17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF17) >> CAN_TXBCF_CF17_Pos; +} + +static inline bool hri_can_get_TXBCF_CF18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF18) >> CAN_TXBCF_CF18_Pos; +} + +static inline bool hri_can_get_TXBCF_CF19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF19) >> CAN_TXBCF_CF19_Pos; +} + +static inline bool hri_can_get_TXBCF_CF20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF20) >> CAN_TXBCF_CF20_Pos; +} + +static inline bool hri_can_get_TXBCF_CF21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF21) >> CAN_TXBCF_CF21_Pos; +} + +static inline bool hri_can_get_TXBCF_CF22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF22) >> CAN_TXBCF_CF22_Pos; +} + +static inline bool hri_can_get_TXBCF_CF23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF23) >> CAN_TXBCF_CF23_Pos; +} + +static inline bool hri_can_get_TXBCF_CF24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF24) >> CAN_TXBCF_CF24_Pos; +} + +static inline bool hri_can_get_TXBCF_CF25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF25) >> CAN_TXBCF_CF25_Pos; +} + +static inline bool hri_can_get_TXBCF_CF26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF26) >> CAN_TXBCF_CF26_Pos; +} + +static inline bool hri_can_get_TXBCF_CF27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF27) >> CAN_TXBCF_CF27_Pos; +} + +static inline bool hri_can_get_TXBCF_CF28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF28) >> CAN_TXBCF_CF28_Pos; +} + +static inline bool hri_can_get_TXBCF_CF29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF29) >> CAN_TXBCF_CF29_Pos; +} + +static inline bool hri_can_get_TXBCF_CF30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF30) >> CAN_TXBCF_CF30_Pos; +} + +static inline bool hri_can_get_TXBCF_CF31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF31) >> CAN_TXBCF_CF31_Pos; +} + +static inline hri_can_txbcf_reg_t hri_can_get_TXBCF_reg(const void *const hw, hri_can_txbcf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbcf_reg_t hri_can_read_TXBCF_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCF.reg; +} + +static inline bool hri_can_get_TXEFS_EFF_bit(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFF) >> CAN_TXEFS_EFF_Pos; +} + +static inline bool hri_can_get_TXEFS_TEFL_bit(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_TEFL) >> CAN_TXEFS_TEFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFFL_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL(mask)) >> CAN_TXEFS_EFFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFFL_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL_Msk) >> CAN_TXEFS_EFFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFGI_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI(mask)) >> CAN_TXEFS_EFGI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFGI_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFPI_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI(mask)) >> CAN_TXEFS_EFPI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFPI_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI_Msk) >> CAN_TXEFS_EFPI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_reg(const void *const hw, hri_can_txefs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFS.reg; +} + +static inline void hri_can_set_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg |= CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp = (tmp & CAN_MRCFG_QOS(mask)) >> CAN_MRCFG_QOS_Pos; + return tmp; +} + +static inline void hri_can_write_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->MRCFG.reg; + tmp &= ~CAN_MRCFG_QOS_Msk; + tmp |= CAN_MRCFG_QOS(data); + ((Can *)hw)->MRCFG.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg &= ~CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg ^= CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_QOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp = (tmp & CAN_MRCFG_QOS_Msk) >> CAN_MRCFG_QOS_Pos; + return tmp; +} + +static inline void hri_can_set_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_reg(const void *const hw) +{ + return ((Can *)hw)->MRCFG.reg; +} + +static inline void hri_can_set_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_DBTP_TDC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_TDC) >> CAN_DBTP_TDC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_DBTP_TDC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_TDC; + tmp |= value << CAN_DBTP_TDC_Pos; + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DSJW(mask)) >> CAN_DBTP_DSJW_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DSJW_Msk; + tmp |= CAN_DBTP_DSJW(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DSJW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DSJW_Msk) >> CAN_DBTP_DSJW_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG2(mask)) >> CAN_DBTP_DTSEG2_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DTSEG2_Msk; + tmp |= CAN_DBTP_DTSEG2(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG2_Msk) >> CAN_DBTP_DTSEG2_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG1(mask)) >> CAN_DBTP_DTSEG1_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DTSEG1_Msk; + tmp |= CAN_DBTP_DTSEG1(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG1_Msk) >> CAN_DBTP_DTSEG1_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DBRP(mask)) >> CAN_DBTP_DBRP_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DBRP_Msk; + tmp |= CAN_DBTP_DBRP(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DBRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DBRP_Msk) >> CAN_DBTP_DBRP_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_reg(const void *const hw) +{ + return ((Can *)hw)->DBTP.reg; +} + +static inline void hri_can_set_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TEST_LBCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_LBCK) >> CAN_TEST_LBCK_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TEST_LBCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_LBCK; + tmp |= value << CAN_TEST_LBCK_Pos; + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TEST_RX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_RX) >> CAN_TEST_RX_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TEST_RX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_RX; + tmp |= value << CAN_TEST_RX_Pos; + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_get_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_TX(mask)) >> CAN_TEST_TX_Pos; + return tmp; +} + +static inline void hri_can_write_TEST_TX_bf(const void *const hw, hri_can_test_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_TX_Msk; + tmp |= CAN_TEST_TX(data); + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_read_TEST_TX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_TX_Msk) >> CAN_TEST_TX_Pos; + return tmp; +} + +static inline void hri_can_set_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_get_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TEST_reg(const void *const hw, hri_can_test_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_read_TEST_reg(const void *const hw) +{ + return ((Can *)hw)->TEST.reg; +} + +static inline void hri_can_set_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDC(mask)) >> CAN_RWD_WDC_Pos; + return tmp; +} + +static inline void hri_can_write_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RWD.reg; + tmp &= ~CAN_RWD_WDC_Msk; + tmp |= CAN_RWD_WDC(data); + ((Can *)hw)->RWD.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_WDC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDC_Msk) >> CAN_RWD_WDC_Pos; + return tmp; +} + +static inline void hri_can_set_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDV(mask)) >> CAN_RWD_WDV_Pos; + return tmp; +} + +static inline void hri_can_write_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RWD.reg; + tmp &= ~CAN_RWD_WDV_Msk; + tmp |= CAN_RWD_WDV(data); + ((Can *)hw)->RWD.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_WDV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDV_Msk) >> CAN_RWD_WDV_Pos; + return tmp; +} + +static inline void hri_can_set_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RWD_reg(const void *const hw, hri_can_rwd_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_reg(const void *const hw) +{ + return ((Can *)hw)->RWD.reg; +} + +static inline void hri_can_set_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_INIT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_INIT) >> CAN_CCCR_INIT_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_INIT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_INIT; + tmp |= value << CAN_CCCR_INIT_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CCE) >> CAN_CCCR_CCE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CCE; + tmp |= value << CAN_CCCR_CCE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_ASM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_ASM) >> CAN_CCCR_ASM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_ASM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_ASM; + tmp |= value << CAN_CCCR_ASM_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CSA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CSA) >> CAN_CCCR_CSA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CSA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CSA; + tmp |= value << CAN_CCCR_CSA_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CSR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CSR) >> CAN_CCCR_CSR_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CSR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CSR; + tmp |= value << CAN_CCCR_CSR_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_MON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_MON) >> CAN_CCCR_MON_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_MON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_MON; + tmp |= value << CAN_CCCR_MON_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_DAR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_DAR) >> CAN_CCCR_DAR_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_DAR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_DAR; + tmp |= value << CAN_CCCR_DAR_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_TEST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_TEST) >> CAN_CCCR_TEST_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_TEST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_TEST; + tmp |= value << CAN_CCCR_TEST_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_FDOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_FDOE) >> CAN_CCCR_FDOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_FDOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_FDOE; + tmp |= value << CAN_CCCR_FDOE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_BRSE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_BRSE) >> CAN_CCCR_BRSE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_BRSE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_BRSE; + tmp |= value << CAN_CCCR_BRSE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_PXHD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_PXHD) >> CAN_CCCR_PXHD_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_PXHD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_PXHD; + tmp |= value << CAN_CCCR_PXHD_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_EFBI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_EFBI) >> CAN_CCCR_EFBI_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_EFBI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_EFBI; + tmp |= value << CAN_CCCR_EFBI_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_TXP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_TXP) >> CAN_CCCR_TXP_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_TXP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_TXP; + tmp |= value << CAN_CCCR_TXP_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_NISO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_NISO) >> CAN_CCCR_NISO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_NISO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_NISO; + tmp |= value << CAN_CCCR_NISO_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_cccr_reg_t hri_can_get_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_CCCR_reg(const void *const hw, hri_can_cccr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_cccr_reg_t hri_can_read_CCCR_reg(const void *const hw) +{ + return ((Can *)hw)->CCCR.reg; +} + +static inline void hri_can_set_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG2(mask)) >> CAN_NBTP_NTSEG2_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NTSEG2_Msk; + tmp |= CAN_NBTP_NTSEG2(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG2_Msk) >> CAN_NBTP_NTSEG2_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG1(mask)) >> CAN_NBTP_NTSEG1_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NTSEG1_Msk; + tmp |= CAN_NBTP_NTSEG1(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG1_Msk) >> CAN_NBTP_NTSEG1_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NBRP(mask)) >> CAN_NBTP_NBRP_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NBRP_Msk; + tmp |= CAN_NBTP_NBRP(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NBRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NBRP_Msk) >> CAN_NBTP_NBRP_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NSJW(mask)) >> CAN_NBTP_NSJW_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NSJW_Msk; + tmp |= CAN_NBTP_NSJW(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NSJW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NSJW_Msk) >> CAN_NBTP_NSJW_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_reg(const void *const hw) +{ + return ((Can *)hw)->NBTP.reg; +} + +static inline void hri_can_set_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TSS(mask)) >> CAN_TSCC_TSS_Pos; + return tmp; +} + +static inline void hri_can_write_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TSCC.reg; + tmp &= ~CAN_TSCC_TSS_Msk; + tmp |= CAN_TSCC_TSS(data); + ((Can *)hw)->TSCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_TSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TSS_Msk) >> CAN_TSCC_TSS_Pos; + return tmp; +} + +static inline void hri_can_set_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TCP(mask)) >> CAN_TSCC_TCP_Pos; + return tmp; +} + +static inline void hri_can_write_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TSCC.reg; + tmp &= ~CAN_TSCC_TCP_Msk; + tmp |= CAN_TSCC_TCP(data); + ((Can *)hw)->TSCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_TCP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TCP_Msk) >> CAN_TSCC_TCP_Pos; + return tmp; +} + +static inline void hri_can_set_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TSCC_reg(const void *const hw, hri_can_tscc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_reg(const void *const hw) +{ + return ((Can *)hw)->TSCC.reg; +} + +static inline void hri_can_set_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TOCC_ETOC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_ETOC) >> CAN_TOCC_ETOC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TOCC_ETOC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_ETOC; + tmp |= value << CAN_TOCC_ETOC_Pos; + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOS(mask)) >> CAN_TOCC_TOS_Pos; + return tmp; +} + +static inline void hri_can_write_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_TOS_Msk; + tmp |= CAN_TOCC_TOS(data); + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOS_Msk) >> CAN_TOCC_TOS_Pos; + return tmp; +} + +static inline void hri_can_set_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOP(mask)) >> CAN_TOCC_TOP_Pos; + return tmp; +} + +static inline void hri_can_write_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_TOP_Msk; + tmp |= CAN_TOCC_TOP(data); + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOP_Msk) >> CAN_TOCC_TOP_Pos; + return tmp; +} + +static inline void hri_can_set_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TOCC_reg(const void *const hw, hri_can_tocc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_reg(const void *const hw) +{ + return ((Can *)hw)->TOCC.reg; +} + +static inline void hri_can_set_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg |= CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_get_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp = (tmp & CAN_TOCV_TOC(mask)) >> CAN_TOCV_TOC_Pos; + return tmp; +} + +static inline void hri_can_write_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCV.reg; + tmp &= ~CAN_TOCV_TOC_Msk; + tmp |= CAN_TOCV_TOC(data); + ((Can *)hw)->TOCV.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg &= ~CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg ^= CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_read_TOCV_TOC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp = (tmp & CAN_TOCV_TOC_Msk) >> CAN_TOCV_TOC_Pos; + return tmp; +} + +static inline void hri_can_set_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_get_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TOCV_reg(const void *const hw, hri_can_tocv_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_read_TOCV_reg(const void *const hw) +{ + return ((Can *)hw)->TOCV.reg; +} + +static inline void hri_can_set_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCF(mask)) >> CAN_TDCR_TDCF_Pos; + return tmp; +} + +static inline void hri_can_write_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TDCR.reg; + tmp &= ~CAN_TDCR_TDCF_Msk; + tmp |= CAN_TDCR_TDCF(data); + ((Can *)hw)->TDCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCF_Msk) >> CAN_TDCR_TDCF_Pos; + return tmp; +} + +static inline void hri_can_set_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCO(mask)) >> CAN_TDCR_TDCO_Pos; + return tmp; +} + +static inline void hri_can_write_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TDCR.reg; + tmp &= ~CAN_TDCR_TDCO_Msk; + tmp |= CAN_TDCR_TDCO(data); + ((Can *)hw)->TDCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCO_Msk) >> CAN_TDCR_TDCO_Pos; + return tmp; +} + +static inline void hri_can_set_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_reg(const void *const hw) +{ + return ((Can *)hw)->TDCR.reg; +} + +static inline void hri_can_set_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0N_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0N) >> CAN_IR_RF0N_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0N_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0N; + tmp |= value << CAN_IR_RF0N_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0W_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0W) >> CAN_IR_RF0W_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0W_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0W; + tmp |= value << CAN_IR_RF0W_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0F_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0F) >> CAN_IR_RF0F_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0F_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0F; + tmp |= value << CAN_IR_RF0F_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0L_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0L) >> CAN_IR_RF0L_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0L_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0L; + tmp |= value << CAN_IR_RF0L_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1N_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1N) >> CAN_IR_RF1N_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1N_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1N; + tmp |= value << CAN_IR_RF1N_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1W_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1W) >> CAN_IR_RF1W_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1W_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1W; + tmp |= value << CAN_IR_RF1W_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1F_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1F) >> CAN_IR_RF1F_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1F_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1F; + tmp |= value << CAN_IR_RF1F_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1L_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1L) >> CAN_IR_RF1L_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1L_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1L; + tmp |= value << CAN_IR_RF1L_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_HPM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_HPM) >> CAN_IR_HPM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_HPM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_HPM; + tmp |= value << CAN_IR_HPM_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TC) >> CAN_IR_TC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TC; + tmp |= value << CAN_IR_TC_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TCF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TCF) >> CAN_IR_TCF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TCF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TCF; + tmp |= value << CAN_IR_TCF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TFE) >> CAN_IR_TFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TFE; + tmp |= value << CAN_IR_TFE_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFN) >> CAN_IR_TEFN_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFN; + tmp |= value << CAN_IR_TEFN_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFW) >> CAN_IR_TEFW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFW; + tmp |= value << CAN_IR_TEFW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFF) >> CAN_IR_TEFF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFF; + tmp |= value << CAN_IR_TEFF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFL) >> CAN_IR_TEFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFL; + tmp |= value << CAN_IR_TEFL_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TSW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TSW) >> CAN_IR_TSW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TSW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TSW; + tmp |= value << CAN_IR_TSW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_MRAF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_MRAF) >> CAN_IR_MRAF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_MRAF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_MRAF; + tmp |= value << CAN_IR_MRAF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TOO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TOO) >> CAN_IR_TOO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TOO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TOO; + tmp |= value << CAN_IR_TOO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_DRX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_DRX) >> CAN_IR_DRX_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_DRX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_DRX; + tmp |= value << CAN_IR_DRX_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BEC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BEC) >> CAN_IR_BEC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BEC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BEC; + tmp |= value << CAN_IR_BEC_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BEU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BEU) >> CAN_IR_BEU_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BEU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BEU; + tmp |= value << CAN_IR_BEU_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_ELO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_ELO) >> CAN_IR_ELO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_ELO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_ELO; + tmp |= value << CAN_IR_ELO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_EP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_EP) >> CAN_IR_EP_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_EP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_EP; + tmp |= value << CAN_IR_EP_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_EW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_EW) >> CAN_IR_EW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_EW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_EW; + tmp |= value << CAN_IR_EW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BO) >> CAN_IR_BO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BO; + tmp |= value << CAN_IR_BO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_WDI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_WDI) >> CAN_IR_WDI_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_WDI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_WDI; + tmp |= value << CAN_IR_WDI_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_PEA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_PEA) >> CAN_IR_PEA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_PEA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_PEA; + tmp |= value << CAN_IR_PEA_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_PED_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_PED) >> CAN_IR_PED_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_PED_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_PED; + tmp |= value << CAN_IR_PED_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_ARA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_ARA) >> CAN_IR_ARA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_ARA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_ARA; + tmp |= value << CAN_IR_ARA_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ir_reg_t hri_can_get_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_IR_reg(const void *const hw, hri_can_ir_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ir_reg_t hri_can_read_IR_reg(const void *const hw) +{ + return ((Can *)hw)->IR.reg; +} + +static inline void hri_can_set_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0NE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0NE) >> CAN_IE_RF0NE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0NE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0NE; + tmp |= value << CAN_IE_RF0NE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0WE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0WE) >> CAN_IE_RF0WE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0WE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0WE; + tmp |= value << CAN_IE_RF0WE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0FE) >> CAN_IE_RF0FE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0FE; + tmp |= value << CAN_IE_RF0FE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0LE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0LE) >> CAN_IE_RF0LE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0LE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0LE; + tmp |= value << CAN_IE_RF0LE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1NE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1NE) >> CAN_IE_RF1NE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1NE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1NE; + tmp |= value << CAN_IE_RF1NE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1WE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1WE) >> CAN_IE_RF1WE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1WE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1WE; + tmp |= value << CAN_IE_RF1WE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1FE) >> CAN_IE_RF1FE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1FE; + tmp |= value << CAN_IE_RF1FE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1LE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1LE) >> CAN_IE_RF1LE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1LE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1LE; + tmp |= value << CAN_IE_RF1LE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_HPME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_HPME) >> CAN_IE_HPME_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_HPME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_HPME; + tmp |= value << CAN_IE_HPME_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TCE) >> CAN_IE_TCE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TCE; + tmp |= value << CAN_IE_TCE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TCFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TCFE) >> CAN_IE_TCFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TCFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TCFE; + tmp |= value << CAN_IE_TCFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TFEE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TFEE) >> CAN_IE_TFEE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TFEE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TFEE; + tmp |= value << CAN_IE_TFEE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFNE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFNE) >> CAN_IE_TEFNE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFNE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFNE; + tmp |= value << CAN_IE_TEFNE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFWE) >> CAN_IE_TEFWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFWE; + tmp |= value << CAN_IE_TEFWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFFE) >> CAN_IE_TEFFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFFE; + tmp |= value << CAN_IE_TEFFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFLE) >> CAN_IE_TEFLE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFLE; + tmp |= value << CAN_IE_TEFLE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TSWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TSWE) >> CAN_IE_TSWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TSWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TSWE; + tmp |= value << CAN_IE_TSWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_MRAFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_MRAFE) >> CAN_IE_MRAFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_MRAFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_MRAFE; + tmp |= value << CAN_IE_MRAFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TOOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TOOE) >> CAN_IE_TOOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TOOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TOOE; + tmp |= value << CAN_IE_TOOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_DRXE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_DRXE) >> CAN_IE_DRXE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_DRXE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_DRXE; + tmp |= value << CAN_IE_DRXE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BECE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BECE) >> CAN_IE_BECE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BECE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BECE; + tmp |= value << CAN_IE_BECE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BEUE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BEUE) >> CAN_IE_BEUE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BEUE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BEUE; + tmp |= value << CAN_IE_BEUE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_ELOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_ELOE) >> CAN_IE_ELOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_ELOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_ELOE; + tmp |= value << CAN_IE_ELOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_EPE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_EPE) >> CAN_IE_EPE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_EPE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_EPE; + tmp |= value << CAN_IE_EPE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_EWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_EWE) >> CAN_IE_EWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_EWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_EWE; + tmp |= value << CAN_IE_EWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BOE) >> CAN_IE_BOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BOE; + tmp |= value << CAN_IE_BOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_WDIE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_WDIE) >> CAN_IE_WDIE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_WDIE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_WDIE; + tmp |= value << CAN_IE_WDIE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_PEAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_PEAE) >> CAN_IE_PEAE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_PEAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_PEAE; + tmp |= value << CAN_IE_PEAE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_PEDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_PEDE) >> CAN_IE_PEDE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_PEDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_PEDE; + tmp |= value << CAN_IE_PEDE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_ARAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_ARAE) >> CAN_IE_ARAE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_ARAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_ARAE; + tmp |= value << CAN_IE_ARAE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ie_reg_t hri_can_get_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_IE_reg(const void *const hw, hri_can_ie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ie_reg_t hri_can_read_IE_reg(const void *const hw) +{ + return ((Can *)hw)->IE.reg; +} + +static inline void hri_can_set_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0NL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0NL) >> CAN_ILS_RF0NL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0NL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0NL; + tmp |= value << CAN_ILS_RF0NL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0WL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0WL) >> CAN_ILS_RF0WL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0WL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0WL; + tmp |= value << CAN_ILS_RF0WL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0FL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0FL) >> CAN_ILS_RF0FL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0FL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0FL; + tmp |= value << CAN_ILS_RF0FL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0LL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0LL) >> CAN_ILS_RF0LL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0LL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0LL; + tmp |= value << CAN_ILS_RF0LL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1NL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1NL) >> CAN_ILS_RF1NL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1NL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1NL; + tmp |= value << CAN_ILS_RF1NL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1WL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1WL) >> CAN_ILS_RF1WL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1WL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1WL; + tmp |= value << CAN_ILS_RF1WL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1FL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1FL) >> CAN_ILS_RF1FL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1FL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1FL; + tmp |= value << CAN_ILS_RF1FL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1LL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1LL) >> CAN_ILS_RF1LL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1LL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1LL; + tmp |= value << CAN_ILS_RF1LL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_HPML_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_HPML) >> CAN_ILS_HPML_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_HPML_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_HPML; + tmp |= value << CAN_ILS_HPML_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TCL) >> CAN_ILS_TCL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TCL; + tmp |= value << CAN_ILS_TCL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TCFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TCFL) >> CAN_ILS_TCFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TCFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TCFL; + tmp |= value << CAN_ILS_TCFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TFEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TFEL) >> CAN_ILS_TFEL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TFEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TFEL; + tmp |= value << CAN_ILS_TFEL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFNL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFNL) >> CAN_ILS_TEFNL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFNL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFNL; + tmp |= value << CAN_ILS_TEFNL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFWL) >> CAN_ILS_TEFWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFWL; + tmp |= value << CAN_ILS_TEFWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFFL) >> CAN_ILS_TEFFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFFL; + tmp |= value << CAN_ILS_TEFFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFLL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFLL) >> CAN_ILS_TEFLL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFLL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFLL; + tmp |= value << CAN_ILS_TEFLL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TSWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TSWL) >> CAN_ILS_TSWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TSWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TSWL; + tmp |= value << CAN_ILS_TSWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_MRAFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_MRAFL) >> CAN_ILS_MRAFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_MRAFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_MRAFL; + tmp |= value << CAN_ILS_MRAFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TOOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TOOL) >> CAN_ILS_TOOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TOOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TOOL; + tmp |= value << CAN_ILS_TOOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_DRXL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_DRXL) >> CAN_ILS_DRXL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_DRXL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_DRXL; + tmp |= value << CAN_ILS_DRXL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BECL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BECL) >> CAN_ILS_BECL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BECL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BECL; + tmp |= value << CAN_ILS_BECL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BEUL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BEUL) >> CAN_ILS_BEUL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BEUL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BEUL; + tmp |= value << CAN_ILS_BEUL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_ELOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_ELOL) >> CAN_ILS_ELOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_ELOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_ELOL; + tmp |= value << CAN_ILS_ELOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_EPL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_EPL) >> CAN_ILS_EPL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_EPL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_EPL; + tmp |= value << CAN_ILS_EPL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_EWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_EWL) >> CAN_ILS_EWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_EWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_EWL; + tmp |= value << CAN_ILS_EWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BOL) >> CAN_ILS_BOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BOL; + tmp |= value << CAN_ILS_BOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_WDIL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_WDIL) >> CAN_ILS_WDIL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_WDIL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_WDIL; + tmp |= value << CAN_ILS_WDIL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_PEAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_PEAL) >> CAN_ILS_PEAL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_PEAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_PEAL; + tmp |= value << CAN_ILS_PEAL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_PEDL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_PEDL) >> CAN_ILS_PEDL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_PEDL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_PEDL; + tmp |= value << CAN_ILS_PEDL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_ARAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_ARAL) >> CAN_ILS_ARAL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_ARAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_ARAL; + tmp |= value << CAN_ILS_ARAL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ils_reg_t hri_can_get_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_ILS_reg(const void *const hw, hri_can_ils_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ils_reg_t hri_can_read_ILS_reg(const void *const hw) +{ + return ((Can *)hw)->ILS.reg; +} + +static inline void hri_can_set_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILE_EINT0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp = (tmp & CAN_ILE_EINT0) >> CAN_ILE_EINT0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILE_EINT0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILE.reg; + tmp &= ~CAN_ILE_EINT0; + tmp |= value << CAN_ILE_EINT0_Pos; + ((Can *)hw)->ILE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILE_EINT1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp = (tmp & CAN_ILE_EINT1) >> CAN_ILE_EINT1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILE_EINT1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILE.reg; + tmp &= ~CAN_ILE_EINT1; + tmp |= value << CAN_ILE_EINT1_Pos; + ((Can *)hw)->ILE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ile_reg_t hri_can_get_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_ILE_reg(const void *const hw, hri_can_ile_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ile_reg_t hri_can_read_ILE_reg(const void *const hw) +{ + return ((Can *)hw)->ILE.reg; +} + +static inline void hri_can_set_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_GFC_RRFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_RRFE) >> CAN_GFC_RRFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_GFC_RRFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_RRFE; + tmp |= value << CAN_GFC_RRFE_Pos; + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_GFC_RRFS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_RRFS) >> CAN_GFC_RRFS_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_GFC_RRFS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_RRFS; + tmp |= value << CAN_GFC_RRFS_Pos; + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFE(mask)) >> CAN_GFC_ANFE_Pos; + return tmp; +} + +static inline void hri_can_write_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_ANFE_Msk; + tmp |= CAN_GFC_ANFE(data); + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFE_Msk) >> CAN_GFC_ANFE_Pos; + return tmp; +} + +static inline void hri_can_set_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFS(mask)) >> CAN_GFC_ANFS_Pos; + return tmp; +} + +static inline void hri_can_write_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_ANFS_Msk; + tmp |= CAN_GFC_ANFS(data); + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFS_Msk) >> CAN_GFC_ANFS_Pos; + return tmp; +} + +static inline void hri_can_set_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_GFC_reg(const void *const hw, hri_can_gfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_reg(const void *const hw) +{ + return ((Can *)hw)->GFC.reg; +} + +static inline void hri_can_set_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_FLSSA(mask)) >> CAN_SIDFC_FLSSA_Pos; + return tmp; +} + +static inline void hri_can_write_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= ~CAN_SIDFC_FLSSA_Msk; + tmp |= CAN_SIDFC_FLSSA(data); + ((Can *)hw)->SIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_FLSSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_FLSSA_Msk) >> CAN_SIDFC_FLSSA_Pos; + return tmp; +} + +static inline void hri_can_set_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_LSS(mask)) >> CAN_SIDFC_LSS_Pos; + return tmp; +} + +static inline void hri_can_write_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= ~CAN_SIDFC_LSS_Msk; + tmp |= CAN_SIDFC_LSS(data); + ((Can *)hw)->SIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_LSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_LSS_Msk) >> CAN_SIDFC_LSS_Pos; + return tmp; +} + +static inline void hri_can_set_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_reg(const void *const hw) +{ + return ((Can *)hw)->SIDFC.reg; +} + +static inline void hri_can_set_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_FLESA(mask)) >> CAN_XIDFC_FLESA_Pos; + return tmp; +} + +static inline void hri_can_write_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= ~CAN_XIDFC_FLESA_Msk; + tmp |= CAN_XIDFC_FLESA(data); + ((Can *)hw)->XIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_FLESA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_FLESA_Msk) >> CAN_XIDFC_FLESA_Pos; + return tmp; +} + +static inline void hri_can_set_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_LSE(mask)) >> CAN_XIDFC_LSE_Pos; + return tmp; +} + +static inline void hri_can_write_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= ~CAN_XIDFC_LSE_Msk; + tmp |= CAN_XIDFC_LSE(data); + ((Can *)hw)->XIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_LSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_LSE_Msk) >> CAN_XIDFC_LSE_Pos; + return tmp; +} + +static inline void hri_can_set_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_reg(const void *const hw) +{ + return ((Can *)hw)->XIDFC.reg; +} + +static inline void hri_can_set_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg |= CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_get_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp = (tmp & CAN_XIDAM_EIDM(mask)) >> CAN_XIDAM_EIDM_Pos; + return tmp; +} + +static inline void hri_can_write_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDAM.reg; + tmp &= ~CAN_XIDAM_EIDM_Msk; + tmp |= CAN_XIDAM_EIDM(data); + ((Can *)hw)->XIDAM.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg &= ~CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg ^= CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_read_XIDAM_EIDM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp = (tmp & CAN_XIDAM_EIDM_Msk) >> CAN_XIDAM_EIDM_Pos; + return tmp; +} + +static inline void hri_can_set_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_get_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_read_XIDAM_reg(const void *const hw) +{ + return ((Can *)hw)->XIDAM.reg; +} + +static inline void hri_can_set_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND0) >> CAN_NDAT1_ND0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND0; + tmp |= value << CAN_NDAT1_ND0_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND1) >> CAN_NDAT1_ND1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND1; + tmp |= value << CAN_NDAT1_ND1_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND2) >> CAN_NDAT1_ND2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND2; + tmp |= value << CAN_NDAT1_ND2_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND3) >> CAN_NDAT1_ND3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND3; + tmp |= value << CAN_NDAT1_ND3_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND4) >> CAN_NDAT1_ND4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND4; + tmp |= value << CAN_NDAT1_ND4_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND5) >> CAN_NDAT1_ND5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND5; + tmp |= value << CAN_NDAT1_ND5_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND6) >> CAN_NDAT1_ND6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND6; + tmp |= value << CAN_NDAT1_ND6_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND7) >> CAN_NDAT1_ND7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND7; + tmp |= value << CAN_NDAT1_ND7_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND8) >> CAN_NDAT1_ND8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND8; + tmp |= value << CAN_NDAT1_ND8_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND9) >> CAN_NDAT1_ND9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND9; + tmp |= value << CAN_NDAT1_ND9_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND10) >> CAN_NDAT1_ND10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND10; + tmp |= value << CAN_NDAT1_ND10_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND11) >> CAN_NDAT1_ND11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND11; + tmp |= value << CAN_NDAT1_ND11_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND12) >> CAN_NDAT1_ND12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND12; + tmp |= value << CAN_NDAT1_ND12_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND13) >> CAN_NDAT1_ND13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND13; + tmp |= value << CAN_NDAT1_ND13_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND14) >> CAN_NDAT1_ND14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND14; + tmp |= value << CAN_NDAT1_ND14_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND15) >> CAN_NDAT1_ND15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND15; + tmp |= value << CAN_NDAT1_ND15_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND16) >> CAN_NDAT1_ND16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND16; + tmp |= value << CAN_NDAT1_ND16_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND17) >> CAN_NDAT1_ND17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND17; + tmp |= value << CAN_NDAT1_ND17_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND18) >> CAN_NDAT1_ND18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND18; + tmp |= value << CAN_NDAT1_ND18_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND19) >> CAN_NDAT1_ND19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND19; + tmp |= value << CAN_NDAT1_ND19_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND20) >> CAN_NDAT1_ND20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND20; + tmp |= value << CAN_NDAT1_ND20_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND21) >> CAN_NDAT1_ND21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND21; + tmp |= value << CAN_NDAT1_ND21_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND22) >> CAN_NDAT1_ND22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND22; + tmp |= value << CAN_NDAT1_ND22_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND23) >> CAN_NDAT1_ND23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND23; + tmp |= value << CAN_NDAT1_ND23_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND24) >> CAN_NDAT1_ND24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND24; + tmp |= value << CAN_NDAT1_ND24_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND25) >> CAN_NDAT1_ND25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND25; + tmp |= value << CAN_NDAT1_ND25_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND26) >> CAN_NDAT1_ND26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND26; + tmp |= value << CAN_NDAT1_ND26_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND27) >> CAN_NDAT1_ND27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND27; + tmp |= value << CAN_NDAT1_ND27_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND28) >> CAN_NDAT1_ND28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND28; + tmp |= value << CAN_NDAT1_ND28_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND29) >> CAN_NDAT1_ND29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND29; + tmp |= value << CAN_NDAT1_ND29_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND30) >> CAN_NDAT1_ND30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND30; + tmp |= value << CAN_NDAT1_ND30_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND31) >> CAN_NDAT1_ND31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND31; + tmp |= value << CAN_NDAT1_ND31_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat1_reg_t hri_can_get_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat1_reg_t hri_can_read_NDAT1_reg(const void *const hw) +{ + return ((Can *)hw)->NDAT1.reg; +} + +static inline void hri_can_set_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND32_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND32) >> CAN_NDAT2_ND32_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND32_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND32; + tmp |= value << CAN_NDAT2_ND32_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND33_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND33) >> CAN_NDAT2_ND33_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND33_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND33; + tmp |= value << CAN_NDAT2_ND33_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND34_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND34) >> CAN_NDAT2_ND34_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND34_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND34; + tmp |= value << CAN_NDAT2_ND34_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND35_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND35) >> CAN_NDAT2_ND35_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND35_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND35; + tmp |= value << CAN_NDAT2_ND35_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND36_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND36) >> CAN_NDAT2_ND36_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND36_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND36; + tmp |= value << CAN_NDAT2_ND36_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND37_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND37) >> CAN_NDAT2_ND37_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND37_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND37; + tmp |= value << CAN_NDAT2_ND37_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND38_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND38) >> CAN_NDAT2_ND38_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND38_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND38; + tmp |= value << CAN_NDAT2_ND38_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND39_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND39) >> CAN_NDAT2_ND39_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND39_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND39; + tmp |= value << CAN_NDAT2_ND39_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND40_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND40) >> CAN_NDAT2_ND40_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND40_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND40; + tmp |= value << CAN_NDAT2_ND40_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND41_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND41) >> CAN_NDAT2_ND41_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND41_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND41; + tmp |= value << CAN_NDAT2_ND41_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND42_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND42) >> CAN_NDAT2_ND42_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND42_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND42; + tmp |= value << CAN_NDAT2_ND42_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND43_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND43) >> CAN_NDAT2_ND43_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND43_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND43; + tmp |= value << CAN_NDAT2_ND43_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND44_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND44) >> CAN_NDAT2_ND44_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND44_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND44; + tmp |= value << CAN_NDAT2_ND44_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND45_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND45) >> CAN_NDAT2_ND45_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND45_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND45; + tmp |= value << CAN_NDAT2_ND45_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND46_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND46) >> CAN_NDAT2_ND46_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND46_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND46; + tmp |= value << CAN_NDAT2_ND46_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND47_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND47) >> CAN_NDAT2_ND47_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND47_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND47; + tmp |= value << CAN_NDAT2_ND47_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND48_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND48) >> CAN_NDAT2_ND48_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND48_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND48; + tmp |= value << CAN_NDAT2_ND48_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND49_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND49) >> CAN_NDAT2_ND49_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND49_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND49; + tmp |= value << CAN_NDAT2_ND49_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND50_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND50) >> CAN_NDAT2_ND50_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND50_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND50; + tmp |= value << CAN_NDAT2_ND50_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND51_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND51) >> CAN_NDAT2_ND51_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND51_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND51; + tmp |= value << CAN_NDAT2_ND51_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND52_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND52) >> CAN_NDAT2_ND52_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND52_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND52; + tmp |= value << CAN_NDAT2_ND52_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND53_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND53) >> CAN_NDAT2_ND53_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND53_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND53; + tmp |= value << CAN_NDAT2_ND53_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND54_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND54) >> CAN_NDAT2_ND54_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND54_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND54; + tmp |= value << CAN_NDAT2_ND54_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND55_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND55) >> CAN_NDAT2_ND55_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND55_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND55; + tmp |= value << CAN_NDAT2_ND55_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND56_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND56) >> CAN_NDAT2_ND56_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND56_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND56; + tmp |= value << CAN_NDAT2_ND56_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND57_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND57) >> CAN_NDAT2_ND57_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND57_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND57; + tmp |= value << CAN_NDAT2_ND57_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND58_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND58) >> CAN_NDAT2_ND58_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND58_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND58; + tmp |= value << CAN_NDAT2_ND58_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND59_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND59) >> CAN_NDAT2_ND59_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND59_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND59; + tmp |= value << CAN_NDAT2_ND59_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND60_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND60) >> CAN_NDAT2_ND60_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND60_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND60; + tmp |= value << CAN_NDAT2_ND60_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND61_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND61) >> CAN_NDAT2_ND61_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND61_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND61; + tmp |= value << CAN_NDAT2_ND61_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND62_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND62) >> CAN_NDAT2_ND62_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND62_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND62; + tmp |= value << CAN_NDAT2_ND62_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND63_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND63) >> CAN_NDAT2_ND63_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND63_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND63; + tmp |= value << CAN_NDAT2_ND63_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat2_reg_t hri_can_get_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat2_reg_t hri_can_read_NDAT2_reg(const void *const hw) +{ + return ((Can *)hw)->NDAT2.reg; +} + +static inline void hri_can_set_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_RXF0C_F0OM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0OM) >> CAN_RXF0C_F0OM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_RXF0C_F0OM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0OM; + tmp |= value << CAN_RXF0C_F0OM_Pos; + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0SA(mask)) >> CAN_RXF0C_F0SA_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0SA_Msk; + tmp |= CAN_RXF0C_F0SA(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0SA_Msk) >> CAN_RXF0C_F0SA_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0S(mask)) >> CAN_RXF0C_F0S_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0S_Msk; + tmp |= CAN_RXF0C_F0S(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0S_Msk) >> CAN_RXF0C_F0S_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0WM(mask)) >> CAN_RXF0C_F0WM_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0WM_Msk; + tmp |= CAN_RXF0C_F0WM(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0WM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0WM_Msk) >> CAN_RXF0C_F0WM_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0C.reg; +} + +static inline void hri_can_set_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg |= CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp = (tmp & CAN_RXF0A_F0AI(mask)) >> CAN_RXF0A_F0AI_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0A.reg; + tmp &= ~CAN_RXF0A_F0AI_Msk; + tmp |= CAN_RXF0A_F0AI(data); + ((Can *)hw)->RXF0A.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg &= ~CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg ^= CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_F0AI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp = (tmp & CAN_RXF0A_F0AI_Msk) >> CAN_RXF0A_F0AI_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0A.reg; +} + +static inline void hri_can_set_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg |= CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_get_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp = (tmp & CAN_RXBC_RBSA(mask)) >> CAN_RXBC_RBSA_Pos; + return tmp; +} + +static inline void hri_can_write_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXBC.reg; + tmp &= ~CAN_RXBC_RBSA_Msk; + tmp |= CAN_RXBC_RBSA(data); + ((Can *)hw)->RXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg &= ~CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg ^= CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_read_RXBC_RBSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp = (tmp & CAN_RXBC_RBSA_Msk) >> CAN_RXBC_RBSA_Pos; + return tmp; +} + +static inline void hri_can_set_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_get_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_read_RXBC_reg(const void *const hw) +{ + return ((Can *)hw)->RXBC.reg; +} + +static inline void hri_can_set_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_RXF1C_F1OM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1OM) >> CAN_RXF1C_F1OM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_RXF1C_F1OM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1OM; + tmp |= value << CAN_RXF1C_F1OM_Pos; + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1SA(mask)) >> CAN_RXF1C_F1SA_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1SA_Msk; + tmp |= CAN_RXF1C_F1SA(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1SA_Msk) >> CAN_RXF1C_F1SA_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1S(mask)) >> CAN_RXF1C_F1S_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1S_Msk; + tmp |= CAN_RXF1C_F1S(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1S_Msk) >> CAN_RXF1C_F1S_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1WM(mask)) >> CAN_RXF1C_F1WM_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1WM_Msk; + tmp |= CAN_RXF1C_F1WM(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1WM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1WM_Msk) >> CAN_RXF1C_F1WM_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1C.reg; +} + +static inline void hri_can_set_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg |= CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp = (tmp & CAN_RXF1A_F1AI(mask)) >> CAN_RXF1A_F1AI_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1A.reg; + tmp &= ~CAN_RXF1A_F1AI_Msk; + tmp |= CAN_RXF1A_F1AI(data); + ((Can *)hw)->RXF1A.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg &= ~CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg ^= CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_F1AI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp = (tmp & CAN_RXF1A_F1AI_Msk) >> CAN_RXF1A_F1AI_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1A.reg; +} + +static inline void hri_can_set_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F0DS(mask)) >> CAN_RXESC_F0DS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_F0DS_Msk; + tmp |= CAN_RXESC_F0DS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F0DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F0DS_Msk) >> CAN_RXESC_F0DS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F1DS(mask)) >> CAN_RXESC_F1DS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_F1DS_Msk; + tmp |= CAN_RXESC_F1DS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F1DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F1DS_Msk) >> CAN_RXESC_F1DS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_RBDS(mask)) >> CAN_RXESC_RBDS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_RBDS_Msk; + tmp |= CAN_RXESC_RBDS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_RBDS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_RBDS_Msk) >> CAN_RXESC_RBDS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_reg(const void *const hw) +{ + return ((Can *)hw)->RXESC.reg; +} + +static inline void hri_can_set_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBC_TFQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQM) >> CAN_TXBC_TFQM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBC_TFQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TFQM; + tmp |= value << CAN_TXBC_TFQM_Pos; + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TBSA(mask)) >> CAN_TXBC_TBSA_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TBSA_Msk; + tmp |= CAN_TXBC_TBSA(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_TBSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TBSA_Msk) >> CAN_TXBC_TBSA_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_NDTB(mask)) >> CAN_TXBC_NDTB_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_NDTB_Msk; + tmp |= CAN_TXBC_NDTB(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_NDTB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_NDTB_Msk) >> CAN_TXBC_NDTB_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQS(mask)) >> CAN_TXBC_TFQS_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TFQS_Msk; + tmp |= CAN_TXBC_TFQS(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_TFQS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQS_Msk) >> CAN_TXBC_TFQS_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBC_reg(const void *const hw, hri_can_txbc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_reg(const void *const hw) +{ + return ((Can *)hw)->TXBC.reg; +} + +static inline void hri_can_set_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg |= CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_get_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp = (tmp & CAN_TXESC_TBDS(mask)) >> CAN_TXESC_TBDS_Pos; + return tmp; +} + +static inline void hri_can_write_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXESC.reg; + tmp &= ~CAN_TXESC_TBDS_Msk; + tmp |= CAN_TXESC_TBDS(data); + ((Can *)hw)->TXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg &= ~CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg ^= CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_read_TXESC_TBDS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp = (tmp & CAN_TXESC_TBDS_Msk) >> CAN_TXESC_TBDS_Pos; + return tmp; +} + +static inline void hri_can_set_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_get_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXESC_reg(const void *const hw, hri_can_txesc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_read_TXESC_reg(const void *const hw) +{ + return ((Can *)hw)->TXESC.reg; +} + +static inline void hri_can_set_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR0) >> CAN_TXBAR_AR0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR0; + tmp |= value << CAN_TXBAR_AR0_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR1) >> CAN_TXBAR_AR1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR1; + tmp |= value << CAN_TXBAR_AR1_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR2) >> CAN_TXBAR_AR2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR2; + tmp |= value << CAN_TXBAR_AR2_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR3) >> CAN_TXBAR_AR3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR3; + tmp |= value << CAN_TXBAR_AR3_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR4) >> CAN_TXBAR_AR4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR4; + tmp |= value << CAN_TXBAR_AR4_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR5) >> CAN_TXBAR_AR5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR5; + tmp |= value << CAN_TXBAR_AR5_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR6) >> CAN_TXBAR_AR6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR6; + tmp |= value << CAN_TXBAR_AR6_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR7) >> CAN_TXBAR_AR7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR7; + tmp |= value << CAN_TXBAR_AR7_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR8) >> CAN_TXBAR_AR8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR8; + tmp |= value << CAN_TXBAR_AR8_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR9) >> CAN_TXBAR_AR9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR9; + tmp |= value << CAN_TXBAR_AR9_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR10) >> CAN_TXBAR_AR10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR10; + tmp |= value << CAN_TXBAR_AR10_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR11) >> CAN_TXBAR_AR11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR11; + tmp |= value << CAN_TXBAR_AR11_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR12) >> CAN_TXBAR_AR12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR12; + tmp |= value << CAN_TXBAR_AR12_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR13) >> CAN_TXBAR_AR13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR13; + tmp |= value << CAN_TXBAR_AR13_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR14) >> CAN_TXBAR_AR14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR14; + tmp |= value << CAN_TXBAR_AR14_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR15) >> CAN_TXBAR_AR15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR15; + tmp |= value << CAN_TXBAR_AR15_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR16) >> CAN_TXBAR_AR16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR16; + tmp |= value << CAN_TXBAR_AR16_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR17) >> CAN_TXBAR_AR17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR17; + tmp |= value << CAN_TXBAR_AR17_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR18) >> CAN_TXBAR_AR18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR18; + tmp |= value << CAN_TXBAR_AR18_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR19) >> CAN_TXBAR_AR19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR19; + tmp |= value << CAN_TXBAR_AR19_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR20) >> CAN_TXBAR_AR20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR20; + tmp |= value << CAN_TXBAR_AR20_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR21) >> CAN_TXBAR_AR21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR21; + tmp |= value << CAN_TXBAR_AR21_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR22) >> CAN_TXBAR_AR22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR22; + tmp |= value << CAN_TXBAR_AR22_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR23) >> CAN_TXBAR_AR23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR23; + tmp |= value << CAN_TXBAR_AR23_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR24) >> CAN_TXBAR_AR24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR24; + tmp |= value << CAN_TXBAR_AR24_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR25) >> CAN_TXBAR_AR25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR25; + tmp |= value << CAN_TXBAR_AR25_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR26) >> CAN_TXBAR_AR26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR26; + tmp |= value << CAN_TXBAR_AR26_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR27) >> CAN_TXBAR_AR27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR27; + tmp |= value << CAN_TXBAR_AR27_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR28) >> CAN_TXBAR_AR28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR28; + tmp |= value << CAN_TXBAR_AR28_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR29) >> CAN_TXBAR_AR29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR29; + tmp |= value << CAN_TXBAR_AR29_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR30) >> CAN_TXBAR_AR30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR30; + tmp |= value << CAN_TXBAR_AR30_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR31) >> CAN_TXBAR_AR31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR31; + tmp |= value << CAN_TXBAR_AR31_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbar_reg_t hri_can_get_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbar_reg_t hri_can_read_TXBAR_reg(const void *const hw) +{ + return ((Can *)hw)->TXBAR.reg; +} + +static inline void hri_can_set_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR0) >> CAN_TXBCR_CR0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR0; + tmp |= value << CAN_TXBCR_CR0_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR1) >> CAN_TXBCR_CR1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR1; + tmp |= value << CAN_TXBCR_CR1_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR2) >> CAN_TXBCR_CR2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR2; + tmp |= value << CAN_TXBCR_CR2_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR3) >> CAN_TXBCR_CR3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR3; + tmp |= value << CAN_TXBCR_CR3_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR4) >> CAN_TXBCR_CR4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR4; + tmp |= value << CAN_TXBCR_CR4_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR5) >> CAN_TXBCR_CR5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR5; + tmp |= value << CAN_TXBCR_CR5_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR6) >> CAN_TXBCR_CR6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR6; + tmp |= value << CAN_TXBCR_CR6_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR7) >> CAN_TXBCR_CR7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR7; + tmp |= value << CAN_TXBCR_CR7_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR8) >> CAN_TXBCR_CR8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR8; + tmp |= value << CAN_TXBCR_CR8_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR9) >> CAN_TXBCR_CR9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR9; + tmp |= value << CAN_TXBCR_CR9_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR10) >> CAN_TXBCR_CR10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR10; + tmp |= value << CAN_TXBCR_CR10_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR11) >> CAN_TXBCR_CR11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR11; + tmp |= value << CAN_TXBCR_CR11_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR12) >> CAN_TXBCR_CR12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR12; + tmp |= value << CAN_TXBCR_CR12_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR13) >> CAN_TXBCR_CR13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR13; + tmp |= value << CAN_TXBCR_CR13_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR14) >> CAN_TXBCR_CR14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR14; + tmp |= value << CAN_TXBCR_CR14_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR15) >> CAN_TXBCR_CR15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR15; + tmp |= value << CAN_TXBCR_CR15_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR16) >> CAN_TXBCR_CR16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR16; + tmp |= value << CAN_TXBCR_CR16_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR17) >> CAN_TXBCR_CR17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR17; + tmp |= value << CAN_TXBCR_CR17_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR18) >> CAN_TXBCR_CR18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR18; + tmp |= value << CAN_TXBCR_CR18_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR19) >> CAN_TXBCR_CR19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR19; + tmp |= value << CAN_TXBCR_CR19_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR20) >> CAN_TXBCR_CR20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR20; + tmp |= value << CAN_TXBCR_CR20_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR21) >> CAN_TXBCR_CR21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR21; + tmp |= value << CAN_TXBCR_CR21_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR22) >> CAN_TXBCR_CR22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR22; + tmp |= value << CAN_TXBCR_CR22_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR23) >> CAN_TXBCR_CR23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR23; + tmp |= value << CAN_TXBCR_CR23_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR24) >> CAN_TXBCR_CR24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR24; + tmp |= value << CAN_TXBCR_CR24_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR25) >> CAN_TXBCR_CR25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR25; + tmp |= value << CAN_TXBCR_CR25_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR26) >> CAN_TXBCR_CR26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR26; + tmp |= value << CAN_TXBCR_CR26_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR27) >> CAN_TXBCR_CR27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR27; + tmp |= value << CAN_TXBCR_CR27_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR28) >> CAN_TXBCR_CR28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR28; + tmp |= value << CAN_TXBCR_CR28_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR29) >> CAN_TXBCR_CR29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR29; + tmp |= value << CAN_TXBCR_CR29_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR30) >> CAN_TXBCR_CR30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR30; + tmp |= value << CAN_TXBCR_CR30_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR31) >> CAN_TXBCR_CR31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR31; + tmp |= value << CAN_TXBCR_CR31_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcr_reg_t hri_can_get_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcr_reg_t hri_can_read_TXBCR_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCR.reg; +} + +static inline void hri_can_set_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE0) >> CAN_TXBTIE_TIE0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE0; + tmp |= value << CAN_TXBTIE_TIE0_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE1) >> CAN_TXBTIE_TIE1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE1; + tmp |= value << CAN_TXBTIE_TIE1_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE2) >> CAN_TXBTIE_TIE2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE2; + tmp |= value << CAN_TXBTIE_TIE2_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE3) >> CAN_TXBTIE_TIE3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE3; + tmp |= value << CAN_TXBTIE_TIE3_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE4) >> CAN_TXBTIE_TIE4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE4; + tmp |= value << CAN_TXBTIE_TIE4_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE5) >> CAN_TXBTIE_TIE5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE5; + tmp |= value << CAN_TXBTIE_TIE5_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE6) >> CAN_TXBTIE_TIE6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE6; + tmp |= value << CAN_TXBTIE_TIE6_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE7) >> CAN_TXBTIE_TIE7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE7; + tmp |= value << CAN_TXBTIE_TIE7_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE8) >> CAN_TXBTIE_TIE8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE8; + tmp |= value << CAN_TXBTIE_TIE8_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE9) >> CAN_TXBTIE_TIE9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE9; + tmp |= value << CAN_TXBTIE_TIE9_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE10) >> CAN_TXBTIE_TIE10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE10; + tmp |= value << CAN_TXBTIE_TIE10_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE11) >> CAN_TXBTIE_TIE11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE11; + tmp |= value << CAN_TXBTIE_TIE11_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE12) >> CAN_TXBTIE_TIE12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE12; + tmp |= value << CAN_TXBTIE_TIE12_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE13) >> CAN_TXBTIE_TIE13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE13; + tmp |= value << CAN_TXBTIE_TIE13_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE14) >> CAN_TXBTIE_TIE14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE14; + tmp |= value << CAN_TXBTIE_TIE14_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE15) >> CAN_TXBTIE_TIE15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE15; + tmp |= value << CAN_TXBTIE_TIE15_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE16) >> CAN_TXBTIE_TIE16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE16; + tmp |= value << CAN_TXBTIE_TIE16_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE17) >> CAN_TXBTIE_TIE17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE17; + tmp |= value << CAN_TXBTIE_TIE17_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE18) >> CAN_TXBTIE_TIE18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE18; + tmp |= value << CAN_TXBTIE_TIE18_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE19) >> CAN_TXBTIE_TIE19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE19; + tmp |= value << CAN_TXBTIE_TIE19_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE20) >> CAN_TXBTIE_TIE20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE20; + tmp |= value << CAN_TXBTIE_TIE20_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE21) >> CAN_TXBTIE_TIE21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE21; + tmp |= value << CAN_TXBTIE_TIE21_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE22) >> CAN_TXBTIE_TIE22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE22; + tmp |= value << CAN_TXBTIE_TIE22_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE23) >> CAN_TXBTIE_TIE23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE23; + tmp |= value << CAN_TXBTIE_TIE23_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE24) >> CAN_TXBTIE_TIE24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE24; + tmp |= value << CAN_TXBTIE_TIE24_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE25) >> CAN_TXBTIE_TIE25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE25; + tmp |= value << CAN_TXBTIE_TIE25_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE26) >> CAN_TXBTIE_TIE26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE26; + tmp |= value << CAN_TXBTIE_TIE26_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE27) >> CAN_TXBTIE_TIE27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE27; + tmp |= value << CAN_TXBTIE_TIE27_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE28) >> CAN_TXBTIE_TIE28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE28; + tmp |= value << CAN_TXBTIE_TIE28_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE29) >> CAN_TXBTIE_TIE29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE29; + tmp |= value << CAN_TXBTIE_TIE29_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE30) >> CAN_TXBTIE_TIE30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE30; + tmp |= value << CAN_TXBTIE_TIE30_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE31) >> CAN_TXBTIE_TIE31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE31; + tmp |= value << CAN_TXBTIE_TIE31_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbtie_reg_t hri_can_get_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbtie_reg_t hri_can_read_TXBTIE_reg(const void *const hw) +{ + return ((Can *)hw)->TXBTIE.reg; +} + +static inline void hri_can_set_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE0) >> CAN_TXBCIE_CFIE0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE0; + tmp |= value << CAN_TXBCIE_CFIE0_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE1) >> CAN_TXBCIE_CFIE1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE1; + tmp |= value << CAN_TXBCIE_CFIE1_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE2) >> CAN_TXBCIE_CFIE2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE2; + tmp |= value << CAN_TXBCIE_CFIE2_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE3) >> CAN_TXBCIE_CFIE3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE3; + tmp |= value << CAN_TXBCIE_CFIE3_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE4) >> CAN_TXBCIE_CFIE4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE4; + tmp |= value << CAN_TXBCIE_CFIE4_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE5) >> CAN_TXBCIE_CFIE5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE5; + tmp |= value << CAN_TXBCIE_CFIE5_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE6) >> CAN_TXBCIE_CFIE6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE6; + tmp |= value << CAN_TXBCIE_CFIE6_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE7) >> CAN_TXBCIE_CFIE7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE7; + tmp |= value << CAN_TXBCIE_CFIE7_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE8) >> CAN_TXBCIE_CFIE8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE8; + tmp |= value << CAN_TXBCIE_CFIE8_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE9) >> CAN_TXBCIE_CFIE9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE9; + tmp |= value << CAN_TXBCIE_CFIE9_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE10) >> CAN_TXBCIE_CFIE10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE10; + tmp |= value << CAN_TXBCIE_CFIE10_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE11) >> CAN_TXBCIE_CFIE11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE11; + tmp |= value << CAN_TXBCIE_CFIE11_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE12) >> CAN_TXBCIE_CFIE12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE12; + tmp |= value << CAN_TXBCIE_CFIE12_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE13) >> CAN_TXBCIE_CFIE13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE13; + tmp |= value << CAN_TXBCIE_CFIE13_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE14) >> CAN_TXBCIE_CFIE14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE14; + tmp |= value << CAN_TXBCIE_CFIE14_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE15) >> CAN_TXBCIE_CFIE15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE15; + tmp |= value << CAN_TXBCIE_CFIE15_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE16) >> CAN_TXBCIE_CFIE16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE16; + tmp |= value << CAN_TXBCIE_CFIE16_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE17) >> CAN_TXBCIE_CFIE17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE17; + tmp |= value << CAN_TXBCIE_CFIE17_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE18) >> CAN_TXBCIE_CFIE18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE18; + tmp |= value << CAN_TXBCIE_CFIE18_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE19) >> CAN_TXBCIE_CFIE19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE19; + tmp |= value << CAN_TXBCIE_CFIE19_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE20) >> CAN_TXBCIE_CFIE20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE20; + tmp |= value << CAN_TXBCIE_CFIE20_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE21) >> CAN_TXBCIE_CFIE21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE21; + tmp |= value << CAN_TXBCIE_CFIE21_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE22) >> CAN_TXBCIE_CFIE22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE22; + tmp |= value << CAN_TXBCIE_CFIE22_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE23) >> CAN_TXBCIE_CFIE23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE23; + tmp |= value << CAN_TXBCIE_CFIE23_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE24) >> CAN_TXBCIE_CFIE24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE24; + tmp |= value << CAN_TXBCIE_CFIE24_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE25) >> CAN_TXBCIE_CFIE25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE25; + tmp |= value << CAN_TXBCIE_CFIE25_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE26) >> CAN_TXBCIE_CFIE26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE26; + tmp |= value << CAN_TXBCIE_CFIE26_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE27) >> CAN_TXBCIE_CFIE27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE27; + tmp |= value << CAN_TXBCIE_CFIE27_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE28) >> CAN_TXBCIE_CFIE28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE28; + tmp |= value << CAN_TXBCIE_CFIE28_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE29) >> CAN_TXBCIE_CFIE29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE29; + tmp |= value << CAN_TXBCIE_CFIE29_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE30) >> CAN_TXBCIE_CFIE30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE30; + tmp |= value << CAN_TXBCIE_CFIE30_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE31) >> CAN_TXBCIE_CFIE31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE31; + tmp |= value << CAN_TXBCIE_CFIE31_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcie_reg_t hri_can_get_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcie_reg_t hri_can_read_TXBCIE_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCIE.reg; +} + +static inline void hri_can_set_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFSA(mask)) >> CAN_TXEFC_EFSA_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFSA_Msk; + tmp |= CAN_TXEFC_EFSA(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFSA_Msk) >> CAN_TXEFC_EFSA_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFS(mask)) >> CAN_TXEFC_EFS_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFS_Msk; + tmp |= CAN_TXEFC_EFS(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFS_Msk) >> CAN_TXEFC_EFS_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFWM(mask)) >> CAN_TXEFC_EFWM_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFWM_Msk; + tmp |= CAN_TXEFC_EFWM(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFWM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFWM_Msk) >> CAN_TXEFC_EFWM_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFC.reg; +} + +static inline void hri_can_set_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg |= CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_get_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp = (tmp & CAN_TXEFA_EFAI(mask)) >> CAN_TXEFA_EFAI_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFA.reg; + tmp &= ~CAN_TXEFA_EFAI_Msk; + tmp |= CAN_TXEFA_EFAI(data); + ((Can *)hw)->TXEFA.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg &= ~CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg ^= CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_read_TXEFA_EFAI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp = (tmp & CAN_TXEFA_EFAI_Msk) >> CAN_TXEFA_EFAI_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_get_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_read_TXEFA_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFA.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CAN_C21_H_INCLUDED */ +#endif /* _SAMC21_CAN_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_ccl_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_ccl_c21.h new file mode 100644 index 0000000..e59ce0e --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_ccl_c21.h @@ -0,0 +1,776 @@ +/** + * \file + * + * \brief SAM CCL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_CCL_COMPONENT_ +#ifndef _HRI_CCL_C21_H_INCLUDED_ +#define _HRI_CCL_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CCL_CRITICAL_SECTIONS) +#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CCL_CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ccl_lutctrl_reg_t; +typedef uint8_t hri_ccl_ctrl_reg_t; +typedef uint8_t hri_ccl_seqctrl_reg_t; + +static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_ENABLE; + tmp |= value << CCL_CTRL_ENABLE_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_RUNSTDBY; + tmp |= value << CCL_CTRL_RUNSTDBY_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw) +{ + return ((Ccl *)hw)->CTRL.reg; +} + +static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= ~CCL_SEQCTRL_SEQSEL_Msk; + tmp |= CCL_SEQCTRL_SEQSEL(data); + ((Ccl *)hw)->SEQCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->SEQCTRL[index].reg; +} + +static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_ENABLE; + tmp |= value << CCL_LUTCTRL_ENABLE_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_EDGESEL; + tmp |= value << CCL_LUTCTRL_EDGESEL_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INVEI; + tmp |= value << CCL_LUTCTRL_INVEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEI; + tmp |= value << CCL_LUTCTRL_LUTEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEO; + tmp |= value << CCL_LUTCTRL_LUTEO_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_FILTSEL_Msk; + tmp |= CCL_LUTCTRL_FILTSEL(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL0_Msk; + tmp |= CCL_LUTCTRL_INSEL0(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL1_Msk; + tmp |= CCL_LUTCTRL_INSEL1(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL2_Msk; + tmp |= CCL_LUTCTRL_INSEL2(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_TRUTH_Msk; + tmp |= CCL_LUTCTRL_TRUTH(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->LUTCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CCL_C21_H_INCLUDED */ +#endif /* _SAMC21_CCL_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_dac_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_dac_c21.h new file mode 100644 index 0000000..05736c3 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_dac_c21.h @@ -0,0 +1,966 @@ +/** + * \file + * + * \brief SAM DAC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_DAC_COMPONENT_ +#ifndef _HRI_DAC_C21_H_INCLUDED_ +#define _HRI_DAC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DAC_CRITICAL_SECTIONS) +#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DAC_CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dac_data_reg_t; +typedef uint16_t hri_dac_databuf_reg_t; +typedef uint32_t hri_dac_syncbusy_reg_t; +typedef uint8_t hri_dac_ctrla_reg_t; +typedef uint8_t hri_dac_ctrlb_reg_t; +typedef uint8_t hri_dac_dbgctrl_reg_t; +typedef uint8_t hri_dac_evctrl_reg_t; +typedef uint8_t hri_dac_intenset_reg_t; +typedef uint8_t hri_dac_intflag_reg_t; +typedef uint8_t hri_dac_status_reg_t; + +static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + while (((Dac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + return ((Dac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN) >> DAC_INTFLAG_UNDERRUN_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY) >> DAC_INTFLAG_EMPTY_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN) >> DAC_INTFLAG_UNDERRUN_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN; +} + +static inline bool hri_dac_get_interrupt_EMPTY_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY) >> DAC_INTFLAG_EMPTY_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY; +} + +static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) +{ + return ((Dac *)hw)->INTFLAG.reg; +} + +static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + ((Dac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_dac_set_INTEN_UNDERRUN_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN) >> DAC_INTENSET_UNDERRUN_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN; +} + +static inline void hri_dac_set_INTEN_EMPTY_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY; +} + +static inline bool hri_dac_get_INTEN_EMPTY_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY) >> DAC_INTENSET_EMPTY_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY; +} + +static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENSET.reg = mask; +} + +static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) +{ + return ((Dac *)hw)->INTENSET.reg; +} + +static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) +{ + ((Dac *)hw)->INTENSET.reg = data; + ((Dac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_dac_get_STATUS_READY_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY) >> DAC_STATUS_READY_Pos; +} + +static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) +{ + return ((Dac *)hw)->STATUS.reg; +} + +static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA) >> DAC_SYNCBUSY_DATA_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF) >> DAC_SYNCBUSY_DATABUF_Pos; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Dac *)hw)->SYNCBUSY.reg; +} + +static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= ~DAC_CTRLA_ENABLE; + tmp |= value << DAC_CTRLA_ENABLE_Pos; + ((Dac *)hw)->CTRLA.reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_RUNSTDBY) >> DAC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= ~DAC_CTRLA_RUNSTDBY; + tmp |= value << DAC_CTRLA_RUNSTDBY_Pos; + ((Dac *)hw)->CTRLA.reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) +{ + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + return ((Dac *)hw)->CTRLA.reg; +} + +static inline void hri_dac_set_CTRLB_EOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_EOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_EOEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_EOEN) >> DAC_CTRLB_EOEN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_EOEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_EOEN; + tmp |= value << DAC_CTRLB_EOEN_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_EOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_EOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_EOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_EOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_IOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_IOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_IOEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_IOEN) >> DAC_CTRLB_IOEN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_IOEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_IOEN; + tmp |= value << DAC_CTRLB_IOEN_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_IOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_IOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_IOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_IOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_LEFTADJ_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_LEFTADJ; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_LEFTADJ_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_LEFTADJ) >> DAC_CTRLB_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_LEFTADJ; + tmp |= value << DAC_CTRLB_LEFTADJ_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_LEFTADJ_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_LEFTADJ; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_LEFTADJ_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_LEFTADJ; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_VPD_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_VPD; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_VPD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_VPD) >> DAC_CTRLB_VPD_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_VPD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_VPD; + tmp |= value << DAC_CTRLB_VPD_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_VPD_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_VPD; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_VPD_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_VPD; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_DITHER_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DITHER; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_DITHER_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_DITHER) >> DAC_CTRLB_DITHER_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_DITHER_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_DITHER; + tmp |= value << DAC_CTRLB_DITHER_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_DITHER_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DITHER; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_DITHER_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DITHER; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_REFSEL_Msk; + tmp |= DAC_CTRLB_REFSEL(data); + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) +{ + return ((Dac *)hw)->CTRLB.reg; +} + +static inline void hri_dac_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI) >> DAC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI; + tmp |= value << DAC_EVCTRL_STARTEI_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO) >> DAC_EVCTRL_EMPTYEO_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO; + tmp |= value << DAC_EVCTRL_EMPTYEO_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI) >> DAC_EVCTRL_INVEI_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI; + tmp |= value << DAC_EVCTRL_INVEI_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->EVCTRL.reg; +} + +static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= ~DAC_DBGCTRL_DBGRUN; + tmp |= value << DAC_DBGCTRL_DBGRUN_Pos; + ((Dac *)hw)->DBGCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dac_write_DATA_reg(const void *const hw, hri_dac_data_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATA.reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATA); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_write_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATABUF.reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATABUF); + DAC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DAC_C21_H_INCLUDED */ +#endif /* _SAMC21_DAC_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_divas_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_divas_c21.h new file mode 100644 index 0000000..934fe12 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_divas_c21.h @@ -0,0 +1,546 @@ +/** + * \file + * + * \brief SAM DIVAS + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_DIVAS_COMPONENT_ +#ifndef _HRI_DIVAS_C21_H_INCLUDED_ +#define _HRI_DIVAS_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DIVAS_CRITICAL_SECTIONS) +#define DIVAS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DIVAS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DIVAS_CRITICAL_SECTION_ENTER() +#define DIVAS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_divas_dividend_reg_t; +typedef uint32_t hri_divas_divisor_reg_t; +typedef uint32_t hri_divas_rem_reg_t; +typedef uint32_t hri_divas_result_reg_t; +typedef uint32_t hri_divas_sqrnum_reg_t; +typedef uint8_t hri_divas_ctrla_reg_t; +typedef uint8_t hri_divas_status_reg_t; + +static inline hri_divas_result_reg_t hri_divas_get_RESULT_RESULT_bf(const void *const hw, hri_divas_result_reg_t mask) +{ + return (((Divas *)hw)->RESULT.reg & DIVAS_RESULT_RESULT(mask)) >> DIVAS_RESULT_RESULT_Pos; +} + +static inline hri_divas_result_reg_t hri_divas_read_RESULT_RESULT_bf(const void *const hw) +{ + return (((Divas *)hw)->RESULT.reg & DIVAS_RESULT_RESULT_Msk) >> DIVAS_RESULT_RESULT_Pos; +} + +static inline hri_divas_result_reg_t hri_divas_get_RESULT_reg(const void *const hw, hri_divas_result_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_divas_result_reg_t hri_divas_read_RESULT_reg(const void *const hw) +{ + return ((Divas *)hw)->RESULT.reg; +} + +static inline hri_divas_rem_reg_t hri_divas_get_REM_REM_bf(const void *const hw, hri_divas_rem_reg_t mask) +{ + return (((Divas *)hw)->REM.reg & DIVAS_REM_REM(mask)) >> DIVAS_REM_REM_Pos; +} + +static inline hri_divas_rem_reg_t hri_divas_read_REM_REM_bf(const void *const hw) +{ + return (((Divas *)hw)->REM.reg & DIVAS_REM_REM_Msk) >> DIVAS_REM_REM_Pos; +} + +static inline hri_divas_rem_reg_t hri_divas_get_REM_reg(const void *const hw, hri_divas_rem_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->REM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_divas_rem_reg_t hri_divas_read_REM_reg(const void *const hw) +{ + return ((Divas *)hw)->REM.reg; +} + +static inline void hri_divas_set_CTRLA_SIGNED_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg |= DIVAS_CTRLA_SIGNED; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_divas_get_CTRLA_SIGNED_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Divas *)hw)->CTRLA.reg; + tmp = (tmp & DIVAS_CTRLA_SIGNED) >> DIVAS_CTRLA_SIGNED_Pos; + return (bool)tmp; +} + +static inline void hri_divas_write_CTRLA_SIGNED_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DIVAS_CRITICAL_SECTION_ENTER(); + tmp = ((Divas *)hw)->CTRLA.reg; + tmp &= ~DIVAS_CTRLA_SIGNED; + tmp |= value << DIVAS_CTRLA_SIGNED_Pos; + ((Divas *)hw)->CTRLA.reg = tmp; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_CTRLA_SIGNED_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg &= ~DIVAS_CTRLA_SIGNED; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_CTRLA_SIGNED_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg ^= DIVAS_CTRLA_SIGNED; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_set_CTRLA_DLZ_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg |= DIVAS_CTRLA_DLZ; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_divas_get_CTRLA_DLZ_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Divas *)hw)->CTRLA.reg; + tmp = (tmp & DIVAS_CTRLA_DLZ) >> DIVAS_CTRLA_DLZ_Pos; + return (bool)tmp; +} + +static inline void hri_divas_write_CTRLA_DLZ_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DIVAS_CRITICAL_SECTION_ENTER(); + tmp = ((Divas *)hw)->CTRLA.reg; + tmp &= ~DIVAS_CTRLA_DLZ; + tmp |= value << DIVAS_CTRLA_DLZ_Pos; + ((Divas *)hw)->CTRLA.reg = tmp; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_CTRLA_DLZ_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg &= ~DIVAS_CTRLA_DLZ; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_CTRLA_DLZ_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg ^= DIVAS_CTRLA_DLZ; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_set_CTRLA_reg(const void *const hw, hri_divas_ctrla_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg |= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_ctrla_reg_t hri_divas_get_CTRLA_reg(const void *const hw, hri_divas_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Divas *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_divas_write_CTRLA_reg(const void *const hw, hri_divas_ctrla_reg_t data) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg = data; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_CTRLA_reg(const void *const hw, hri_divas_ctrla_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg &= ~mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_CTRLA_reg(const void *const hw, hri_divas_ctrla_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg ^= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_ctrla_reg_t hri_divas_read_CTRLA_reg(const void *const hw) +{ + return ((Divas *)hw)->CTRLA.reg; +} + +static inline void hri_divas_set_DIVIDEND_DIVIDEND_bf(const void *const hw, hri_divas_dividend_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVIDEND.reg |= DIVAS_DIVIDEND_DIVIDEND(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_dividend_reg_t hri_divas_get_DIVIDEND_DIVIDEND_bf(const void *const hw, + hri_divas_dividend_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->DIVIDEND.reg; + tmp = (tmp & DIVAS_DIVIDEND_DIVIDEND(mask)) >> DIVAS_DIVIDEND_DIVIDEND_Pos; + return tmp; +} + +static inline void hri_divas_write_DIVIDEND_DIVIDEND_bf(const void *const hw, hri_divas_dividend_reg_t data) +{ + uint32_t tmp; + DIVAS_CRITICAL_SECTION_ENTER(); + tmp = ((Divas *)hw)->DIVIDEND.reg; + tmp &= ~DIVAS_DIVIDEND_DIVIDEND_Msk; + tmp |= DIVAS_DIVIDEND_DIVIDEND(data); + ((Divas *)hw)->DIVIDEND.reg = tmp; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_DIVIDEND_DIVIDEND_bf(const void *const hw, hri_divas_dividend_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVIDEND.reg &= ~DIVAS_DIVIDEND_DIVIDEND(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_DIVIDEND_DIVIDEND_bf(const void *const hw, hri_divas_dividend_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVIDEND.reg ^= DIVAS_DIVIDEND_DIVIDEND(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_dividend_reg_t hri_divas_read_DIVIDEND_DIVIDEND_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->DIVIDEND.reg; + tmp = (tmp & DIVAS_DIVIDEND_DIVIDEND_Msk) >> DIVAS_DIVIDEND_DIVIDEND_Pos; + return tmp; +} + +static inline void hri_divas_set_DIVIDEND_reg(const void *const hw, hri_divas_dividend_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVIDEND.reg |= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_dividend_reg_t hri_divas_get_DIVIDEND_reg(const void *const hw, hri_divas_dividend_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->DIVIDEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_divas_write_DIVIDEND_reg(const void *const hw, hri_divas_dividend_reg_t data) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVIDEND.reg = data; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_DIVIDEND_reg(const void *const hw, hri_divas_dividend_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVIDEND.reg &= ~mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_DIVIDEND_reg(const void *const hw, hri_divas_dividend_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVIDEND.reg ^= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_dividend_reg_t hri_divas_read_DIVIDEND_reg(const void *const hw) +{ + return ((Divas *)hw)->DIVIDEND.reg; +} + +static inline void hri_divas_set_DIVISOR_DIVISOR_bf(const void *const hw, hri_divas_divisor_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVISOR.reg |= DIVAS_DIVISOR_DIVISOR(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_divisor_reg_t hri_divas_get_DIVISOR_DIVISOR_bf(const void *const hw, + hri_divas_divisor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->DIVISOR.reg; + tmp = (tmp & DIVAS_DIVISOR_DIVISOR(mask)) >> DIVAS_DIVISOR_DIVISOR_Pos; + return tmp; +} + +static inline void hri_divas_write_DIVISOR_DIVISOR_bf(const void *const hw, hri_divas_divisor_reg_t data) +{ + uint32_t tmp; + DIVAS_CRITICAL_SECTION_ENTER(); + tmp = ((Divas *)hw)->DIVISOR.reg; + tmp &= ~DIVAS_DIVISOR_DIVISOR_Msk; + tmp |= DIVAS_DIVISOR_DIVISOR(data); + ((Divas *)hw)->DIVISOR.reg = tmp; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_DIVISOR_DIVISOR_bf(const void *const hw, hri_divas_divisor_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVISOR.reg &= ~DIVAS_DIVISOR_DIVISOR(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_DIVISOR_DIVISOR_bf(const void *const hw, hri_divas_divisor_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVISOR.reg ^= DIVAS_DIVISOR_DIVISOR(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_divisor_reg_t hri_divas_read_DIVISOR_DIVISOR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->DIVISOR.reg; + tmp = (tmp & DIVAS_DIVISOR_DIVISOR_Msk) >> DIVAS_DIVISOR_DIVISOR_Pos; + return tmp; +} + +static inline void hri_divas_set_DIVISOR_reg(const void *const hw, hri_divas_divisor_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVISOR.reg |= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_divisor_reg_t hri_divas_get_DIVISOR_reg(const void *const hw, hri_divas_divisor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->DIVISOR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_divas_write_DIVISOR_reg(const void *const hw, hri_divas_divisor_reg_t data) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVISOR.reg = data; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_DIVISOR_reg(const void *const hw, hri_divas_divisor_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVISOR.reg &= ~mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_DIVISOR_reg(const void *const hw, hri_divas_divisor_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVISOR.reg ^= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_divisor_reg_t hri_divas_read_DIVISOR_reg(const void *const hw) +{ + return ((Divas *)hw)->DIVISOR.reg; +} + +static inline void hri_divas_set_SQRNUM_SQRNUM_bf(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->SQRNUM.reg |= DIVAS_SQRNUM_SQRNUM(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_sqrnum_reg_t hri_divas_get_SQRNUM_SQRNUM_bf(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->SQRNUM.reg; + tmp = (tmp & DIVAS_SQRNUM_SQRNUM(mask)) >> DIVAS_SQRNUM_SQRNUM_Pos; + return tmp; +} + +static inline void hri_divas_write_SQRNUM_SQRNUM_bf(const void *const hw, hri_divas_sqrnum_reg_t data) +{ + uint32_t tmp; + DIVAS_CRITICAL_SECTION_ENTER(); + tmp = ((Divas *)hw)->SQRNUM.reg; + tmp &= ~DIVAS_SQRNUM_SQRNUM_Msk; + tmp |= DIVAS_SQRNUM_SQRNUM(data); + ((Divas *)hw)->SQRNUM.reg = tmp; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_SQRNUM_SQRNUM_bf(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->SQRNUM.reg &= ~DIVAS_SQRNUM_SQRNUM(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_SQRNUM_SQRNUM_bf(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->SQRNUM.reg ^= DIVAS_SQRNUM_SQRNUM(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_sqrnum_reg_t hri_divas_read_SQRNUM_SQRNUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->SQRNUM.reg; + tmp = (tmp & DIVAS_SQRNUM_SQRNUM_Msk) >> DIVAS_SQRNUM_SQRNUM_Pos; + return tmp; +} + +static inline void hri_divas_set_SQRNUM_reg(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->SQRNUM.reg |= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_sqrnum_reg_t hri_divas_get_SQRNUM_reg(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->SQRNUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_divas_write_SQRNUM_reg(const void *const hw, hri_divas_sqrnum_reg_t data) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->SQRNUM.reg = data; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_SQRNUM_reg(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->SQRNUM.reg &= ~mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_SQRNUM_reg(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->SQRNUM.reg ^= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_sqrnum_reg_t hri_divas_read_SQRNUM_reg(const void *const hw) +{ + return ((Divas *)hw)->SQRNUM.reg; +} + +static inline bool hri_divas_get_STATUS_BUSY_bit(const void *const hw) +{ + return (((Divas *)hw)->STATUS.reg & DIVAS_STATUS_BUSY) >> DIVAS_STATUS_BUSY_Pos; +} + +static inline void hri_divas_clear_STATUS_BUSY_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->STATUS.reg = DIVAS_STATUS_BUSY; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_divas_get_STATUS_DBZ_bit(const void *const hw) +{ + return (((Divas *)hw)->STATUS.reg & DIVAS_STATUS_DBZ) >> DIVAS_STATUS_DBZ_Pos; +} + +static inline void hri_divas_clear_STATUS_DBZ_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->STATUS.reg = DIVAS_STATUS_DBZ; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_status_reg_t hri_divas_get_STATUS_reg(const void *const hw, hri_divas_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Divas *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_divas_clear_STATUS_reg(const void *const hw, hri_divas_status_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->STATUS.reg = mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_status_reg_t hri_divas_read_STATUS_reg(const void *const hw) +{ + return ((Divas *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DIVAS_C21_H_INCLUDED */ +#endif /* _SAMC21_DIVAS_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_dmac_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_dmac_c21.h new file mode 100644 index 0000000..25eeed3 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_dmac_c21.h @@ -0,0 +1,4339 @@ +/** + * \file + * + * \brief SAM DMAC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_DMAC_COMPONENT_ +#ifndef _HRI_DMAC_C21_H_INCLUDED_ +#define _HRI_DMAC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) +#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DMAC_CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dmac_crcctrl_reg_t; +typedef uint16_t hri_dmac_ctrl_reg_t; +typedef uint16_t hri_dmac_intpend_reg_t; +typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; +typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; +typedef uint32_t hri_dmac_active_reg_t; +typedef uint32_t hri_dmac_baseaddr_reg_t; +typedef uint32_t hri_dmac_busych_reg_t; +typedef uint32_t hri_dmac_chctrlb_reg_t; +typedef uint32_t hri_dmac_crcchksum_reg_t; +typedef uint32_t hri_dmac_crcdatain_reg_t; +typedef uint32_t hri_dmac_intstatus_reg_t; +typedef uint32_t hri_dmac_pendch_reg_t; +typedef uint32_t hri_dmac_prictrl0_reg_t; +typedef uint32_t hri_dmac_swtrigctrl_reg_t; +typedef uint32_t hri_dmac_wrbaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; +typedef uint8_t hri_dmac_chctrla_reg_t; +typedef uint8_t hri_dmac_chid_reg_t; +typedef uint8_t hri_dmac_chintenset_reg_t; +typedef uint8_t hri_dmac_chintflag_reg_t; +typedef uint8_t hri_dmac_chstatus_reg_t; +typedef uint8_t hri_dmac_crcstatus_reg_t; +typedef uint8_t hri_dmac_dbgctrl_reg_t; +typedef uint8_t hri_dmac_qosctrl_reg_t; + +static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHINTFLAG.reg; +} + +static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + ((Dmac *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHINTENSET.reg; +} + +static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) +{ + ((Dmac *)hw)->CHINTENSET.reg = data; + ((Dmac *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->CHINTENCLR.reg = mask; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTSTATUS.reg; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; +} + +static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->BUSYCH.reg; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PENDCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->PENDCH.reg; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->ACTIVE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) +{ + return ((Dmac *)hw)->ACTIVE.reg; +} + +static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHSTATUS.reg; +} + +static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_DMAENABLE; + tmp |= value << DMAC_CTRL_DMAENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_CRCENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_CRCENABLE) >> DMAC_CTRL_CRCENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_CRCENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_CRCENABLE; + tmp |= value << DMAC_CTRL_CRCENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN0; + tmp |= value << DMAC_CTRL_LVLEN0_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN1; + tmp |= value << DMAC_CTRL_LVLEN1_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN2; + tmp |= value << DMAC_CTRL_LVLEN2_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN3; + tmp |= value << DMAC_CTRL_LVLEN3_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CTRL.reg; +} + +static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, + hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; + tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; + tmp |= DMAC_CRCCTRL_CRCPOLY(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; + tmp |= DMAC_CRCCTRL_CRCSRC(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCTRL.reg; +} + +static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, + hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; + tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); + ((Dmac *)hw)->CRCDATAIN.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCDATAIN.reg; +} + +static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, + hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; + tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); + ((Dmac *)hw)->CRCCHKSUM.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCHKSUM.reg; +} + +static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= ~DMAC_DBGCTRL_DBGRUN; + tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; + ((Dmac *)hw)->DBGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dmac_set_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_WRBQOS(mask)) >> DMAC_QOSCTRL_WRBQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_WRBQOS_Msk; + tmp |= DMAC_QOSCTRL_WRBQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_WRBQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_WRBQOS_Msk) >> DMAC_QOSCTRL_WRBQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_FQOS(mask)) >> DMAC_QOSCTRL_FQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_FQOS_Msk; + tmp |= DMAC_QOSCTRL_FQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_FQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_FQOS_Msk) >> DMAC_QOSCTRL_FQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_DQOS(mask)) >> DMAC_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_DQOS_Msk; + tmp |= DMAC_QOSCTRL_DQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_DQOS_Msk) >> DMAC_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->QOSCTRL.reg; +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, + hri_dmac_swtrigctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->SWTRIGCTRL.reg; +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN0; + tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN1; + tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN2; + tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN3; + tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) +{ + return ((Dmac *)hw)->PRICTRL0.reg; +} + +static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TERR; + tmp |= value << DMAC_INTPEND_TERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TCMPL; + tmp |= value << DMAC_INTPEND_TCMPL_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_SUSP; + tmp |= value << DMAC_INTPEND_SUSP_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_FERR; + tmp |= value << DMAC_INTPEND_FERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_BUSY; + tmp |= value << DMAC_INTPEND_BUSY_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_PEND; + tmp |= value << DMAC_INTPEND_PEND_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_ID_Msk; + tmp |= DMAC_INTPEND_ID(data); + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTPEND.reg; +} + +static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, + hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; + tmp |= DMAC_BASEADDR_BASEADDR(data); + ((Dmac *)hw)->BASEADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->BASEADDR.reg; +} + +static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; + tmp |= DMAC_WRBADDR_WRBADDR(data); + ((Dmac *)hw)->WRBADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->WRBADDR.reg; +} + +static inline void hri_dmac_set_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg |= DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp = (tmp & DMAC_CHID_ID(mask)) >> DMAC_CHID_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHID.reg; + tmp &= ~DMAC_CHID_ID_Msk; + tmp |= DMAC_CHID_ID(data); + ((Dmac *)hw)->CHID.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg &= ~DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg ^= DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_ID_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp = (tmp & DMAC_CHID_ID_Msk) >> DMAC_CHID_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHID_reg(const void *const hw, hri_dmac_chid_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHID.reg; +} + +static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((Dmac *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((Dmac *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHCTRLA.reg; +} + +static inline void hri_dmac_set_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLB_EVIE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVIE) >> DMAC_CHCTRLB_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVIE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVIE; + tmp |= value << DMAC_CHCTRLB_EVIE_Pos; + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLB_EVOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVOE) >> DMAC_CHCTRLB_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVOE; + tmp |= value << DMAC_CHCTRLB_EVOE_Pos; + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVACT(mask)) >> DMAC_CHCTRLB_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVACT_Msk; + tmp |= DMAC_CHCTRLB_EVACT(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_EVACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVACT_Msk) >> DMAC_CHCTRLB_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_LVL(mask)) >> DMAC_CHCTRLB_LVL_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_LVL_Msk; + tmp |= DMAC_CHCTRLB_LVL(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_LVL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_LVL_Msk) >> DMAC_CHCTRLB_LVL_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGSRC(mask)) >> DMAC_CHCTRLB_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLB_TRIGSRC(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGSRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGSRC_Msk) >> DMAC_CHCTRLB_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGACT(mask)) >> DMAC_CHCTRLB_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_TRIGACT_Msk; + tmp |= DMAC_CHCTRLB_TRIGACT(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGACT_Msk) >> DMAC_CHCTRLB_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHCTRLB.reg; +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CRCSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCSTATUS.reg; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_VALID; + tmp |= value << DMAC_BTCTRL_VALID_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_SRCINC; + tmp |= value << DMAC_BTCTRL_SRCINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_DSTINC; + tmp |= value << DMAC_BTCTRL_DSTINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSEL; + tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; + tmp |= DMAC_BTCTRL_EVOSEL(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; + tmp |= DMAC_BTCTRL_BLOCKACT(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; + tmp |= DMAC_BTCTRL_BEATSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; + tmp |= DMAC_BTCTRL_STEPSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCTRL.reg; +} + +static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= ~DMAC_BTCNT_BTCNT_Msk; + tmp |= DMAC_BTCNT_BTCNT(data); + ((DmacDescriptor *)hw)->BTCNT.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCNT.reg; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t +hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; + tmp |= DMAC_SRCADDR_SRCADDR(data); + ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->SRCADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; + tmp |= DMAC_DSTADDR_DSTADDR(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DSTADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; + tmp |= DMAC_DESCADDR_DESCADDR(data); + ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DESCADDR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DMAC_C21_H_INCLUDED */ +#endif /* _SAMC21_DMAC_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_dsu_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_dsu_c21.h new file mode 100644 index 0000000..c9cce9c --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_dsu_c21.h @@ -0,0 +1,1187 @@ +/** + * \file + * + * \brief SAM DSU + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_DSU_COMPONENT_ +#ifndef _HRI_DSU_C21_H_INCLUDED_ +#define _HRI_DSU_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DSU_CRITICAL_SECTIONS) +#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DSU_CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_dsu_addr_reg_t; +typedef uint32_t hri_dsu_cid0_reg_t; +typedef uint32_t hri_dsu_cid1_reg_t; +typedef uint32_t hri_dsu_cid2_reg_t; +typedef uint32_t hri_dsu_cid3_reg_t; +typedef uint32_t hri_dsu_data_reg_t; +typedef uint32_t hri_dsu_dcc_reg_t; +typedef uint32_t hri_dsu_dcfg_reg_t; +typedef uint32_t hri_dsu_did_reg_t; +typedef uint32_t hri_dsu_end_reg_t; +typedef uint32_t hri_dsu_entry0_reg_t; +typedef uint32_t hri_dsu_entry1_reg_t; +typedef uint32_t hri_dsu_length_reg_t; +typedef uint32_t hri_dsu_memtype_reg_t; +typedef uint32_t hri_dsu_pid0_reg_t; +typedef uint32_t hri_dsu_pid1_reg_t; +typedef uint32_t hri_dsu_pid2_reg_t; +typedef uint32_t hri_dsu_pid3_reg_t; +typedef uint32_t hri_dsu_pid4_reg_t; +typedef uint32_t hri_dsu_pid5_reg_t; +typedef uint32_t hri_dsu_pid6_reg_t; +typedef uint32_t hri_dsu_pid7_reg_t; +typedef uint8_t hri_dsu_ctrl_reg_t; +typedef uint8_t hri_dsu_statusa_reg_t; +typedef uint8_t hri_dsu_statusb_reg_t; +typedef uint8_t hri_dsu_statusc_reg_t; + +static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; +} + +static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSB.reg; +} + +static inline hri_dsu_statusc_reg_t hri_dsu_get_STATUSC_STATE_bf(const void *const hw, hri_dsu_statusc_reg_t mask) +{ + return (((Dsu *)hw)->STATUSC.reg & DSU_STATUSC_STATE(mask)) >> DSU_STATUSC_STATE_Pos; +} + +static inline hri_dsu_statusc_reg_t hri_dsu_read_STATUSC_STATE_bf(const void *const hw) +{ + return (((Dsu *)hw)->STATUSC.reg & DSU_STATUSC_STATE_Msk) >> DSU_STATUSC_STATE_Pos; +} + +static inline hri_dsu_statusc_reg_t hri_dsu_get_STATUSC_reg(const void *const hw, hri_dsu_statusc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_statusc_reg_t hri_dsu_read_STATUSC_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSC.reg; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) +{ + return ((Dsu *)hw)->DID.reg; +} + +static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; +} + +static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY0.reg; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY1.reg; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->END.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) +{ + return ((Dsu *)hw)->END.reg; +} + +static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) +{ + return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MEMTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) +{ + return ((Dsu *)hw)->MEMTYPE.reg; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID4.reg; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID5.reg; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID6.reg; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID7.reg; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID0.reg; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID1.reg; +} + +static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID2.reg; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID3.reg; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID0.reg; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID1.reg; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID2.reg; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID3.reg; +} + +static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_AMOD_Msk; + tmp |= DSU_ADDR_AMOD(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_ADDR_Msk; + tmp |= DSU_ADDR_ADDR(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) +{ + return ((Dsu *)hw)->ADDR.reg; +} + +static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= ~DSU_LENGTH_LENGTH_Msk; + tmp |= DSU_LENGTH_LENGTH(data); + ((Dsu *)hw)->LENGTH.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) +{ + return ((Dsu *)hw)->LENGTH.reg; +} + +static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= ~DSU_DATA_DATA_Msk; + tmp |= DSU_DATA_DATA(data); + ((Dsu *)hw)->DATA.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) +{ + return ((Dsu *)hw)->DATA.reg; +} + +static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= ~DSU_DCC_DATA_Msk; + tmp |= DSU_DCC_DATA(data); + ((Dsu *)hw)->DCC[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCC[index].reg; +} + +static inline void hri_dsu_set_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg |= DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp = (tmp & DSU_DCFG_DCFG(mask)) >> DSU_DCFG_DCFG_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp &= ~DSU_DCFG_DCFG_Msk; + tmp |= DSU_DCFG_DCFG(data); + ((Dsu *)hw)->DCFG[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg &= ~DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg ^= DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_DCFG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp = (tmp & DSU_DCFG_DCFG_Msk) >> DSU_DCFG_DCFG_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCFG[index].reg; +} + +static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; +} + +static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; +} + +static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; +} + +static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSA.reg; +} + +static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CTRL.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DSU_C21_H_INCLUDED */ +#endif /* _SAMC21_DSU_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_eic_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_eic_c21.h new file mode 100644 index 0000000..d99e811 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_eic_c21.h @@ -0,0 +1,1463 @@ +/** + * \file + * + * \brief SAM EIC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_EIC_COMPONENT_ +#ifndef _HRI_EIC_C21_H_INCLUDED_ +#define _HRI_EIC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EIC_CRITICAL_SECTIONS) +#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EIC_CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_eic_nmiflag_reg_t; +typedef uint32_t hri_eic_asynch_reg_t; +typedef uint32_t hri_eic_config_reg_t; +typedef uint32_t hri_eic_evctrl_reg_t; +typedef uint32_t hri_eic_intenset_reg_t; +typedef uint32_t hri_eic_intflag_reg_t; +typedef uint32_t hri_eic_syncbusy_reg_t; +typedef uint8_t hri_eic_ctrla_reg_t; +typedef uint8_t hri_eic_nmictrl_reg_t; + +static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + while (((Eic *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + return ((Eic *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) +{ + return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; +} + +static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) +{ + ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Eic *)hw)->NMIFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->NMIFLAG.reg; +} + +static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + ((Eic *)hw)->NMIFLAG.reg = mask; +} + +static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->INTFLAG.reg; +} + +static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + ((Eic *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); + ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); +} + +static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = mask; +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) +{ + return ((Eic *)hw)->INTENSET.reg; +} + +static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = data; + ((Eic *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Eic *)hw)->SYNCBUSY.reg; +} + +static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_ENABLE; + tmp |= value << EIC_CTRLA_ENABLE_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_CKSEL; + tmp |= value << EIC_CTRLA_CKSEL_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg = data; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) +{ + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + return ((Eic *)hw)->CTRLA.reg; +} + +static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIFILTEN; + tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIASYNCH; + tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMISENSE_Msk; + tmp |= EIC_NMICTRL_NMISENSE(data); + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->NMICTRL.reg; +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; + tmp |= EIC_EVCTRL_EXTINTEO(data); + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->EVCTRL.reg; +} + +static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= ~EIC_ASYNCH_ASYNCH_Msk; + tmp |= EIC_ASYNCH_ASYNCH(data); + ((Eic *)hw)->ASYNCH.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) +{ + return ((Eic *)hw)->ASYNCH.reg; +} + +static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN0; + tmp |= value << EIC_CONFIG_FILTEN0_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN1; + tmp |= value << EIC_CONFIG_FILTEN1_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN2; + tmp |= value << EIC_CONFIG_FILTEN2_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN3; + tmp |= value << EIC_CONFIG_FILTEN3_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN4; + tmp |= value << EIC_CONFIG_FILTEN4_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN5; + tmp |= value << EIC_CONFIG_FILTEN5_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN6; + tmp |= value << EIC_CONFIG_FILTEN6_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN7; + tmp |= value << EIC_CONFIG_FILTEN7_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE0_Msk; + tmp |= EIC_CONFIG_SENSE0(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE1_Msk; + tmp |= EIC_CONFIG_SENSE1(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE2_Msk; + tmp |= EIC_CONFIG_SENSE2(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE3_Msk; + tmp |= EIC_CONFIG_SENSE3(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE4_Msk; + tmp |= EIC_CONFIG_SENSE4(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE5_Msk; + tmp |= EIC_CONFIG_SENSE5(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE6_Msk; + tmp |= EIC_CONFIG_SENSE6(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE7_Msk; + tmp |= EIC_CONFIG_SENSE7(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) +{ + return ((Eic *)hw)->CONFIG[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EIC_C21_H_INCLUDED */ +#endif /* _SAMC21_EIC_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_evsys_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_evsys_c21.h new file mode 100644 index 0000000..aad1437 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_evsys_c21.h @@ -0,0 +1,1725 @@ +/** + * \file + * + * \brief SAM EVSYS + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_EVSYS_COMPONENT_ +#ifndef _HRI_EVSYS_C21_H_INCLUDED_ +#define _HRI_EVSYS_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) +#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EVSYS_CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_evsys_channel_reg_t; +typedef uint32_t hri_evsys_chstatus_reg_t; +typedef uint32_t hri_evsys_intenset_reg_t; +typedef uint32_t hri_evsys_intflag_reg_t; +typedef uint32_t hri_evsys_swevt_reg_t; +typedef uint32_t hri_evsys_user_reg_t; +typedef uint8_t hri_evsys_ctrla_reg_t; + +static inline bool hri_evsys_get_INTFLAG_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; +} + +static inline bool hri_evsys_get_INTFLAG_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; +} + +static inline bool hri_evsys_get_INTFLAG_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; +} + +static inline bool hri_evsys_get_INTFLAG_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; +} + +static inline bool hri_evsys_get_INTFLAG_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; +} + +static inline bool hri_evsys_get_INTFLAG_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; +} + +static inline bool hri_evsys_get_INTFLAG_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; +} + +static inline bool hri_evsys_get_INTFLAG_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; +} + +static inline bool hri_evsys_get_INTFLAG_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR8) >> EVSYS_INTFLAG_OVR8_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR8; +} + +static inline bool hri_evsys_get_INTFLAG_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR9) >> EVSYS_INTFLAG_OVR9_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR9; +} + +static inline bool hri_evsys_get_INTFLAG_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR10) >> EVSYS_INTFLAG_OVR10_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR10; +} + +static inline bool hri_evsys_get_INTFLAG_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR11) >> EVSYS_INTFLAG_OVR11_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR11; +} + +static inline bool hri_evsys_get_INTFLAG_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; +} + +static inline bool hri_evsys_get_INTFLAG_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; +} + +static inline bool hri_evsys_get_INTFLAG_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; +} + +static inline bool hri_evsys_get_INTFLAG_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; +} + +static inline bool hri_evsys_get_INTFLAG_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; +} + +static inline bool hri_evsys_get_INTFLAG_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; +} + +static inline bool hri_evsys_get_INTFLAG_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; +} + +static inline bool hri_evsys_get_INTFLAG_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; +} + +static inline bool hri_evsys_get_INTFLAG_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD8) >> EVSYS_INTFLAG_EVD8_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD8; +} + +static inline bool hri_evsys_get_INTFLAG_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD9) >> EVSYS_INTFLAG_EVD9_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD9; +} + +static inline bool hri_evsys_get_INTFLAG_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD10) >> EVSYS_INTFLAG_EVD10_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD10; +} + +static inline bool hri_evsys_get_INTFLAG_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD11) >> EVSYS_INTFLAG_EVD11_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD11; +} + +static inline bool hri_evsys_get_interrupt_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; +} + +static inline bool hri_evsys_get_interrupt_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; +} + +static inline bool hri_evsys_get_interrupt_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; +} + +static inline bool hri_evsys_get_interrupt_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; +} + +static inline bool hri_evsys_get_interrupt_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; +} + +static inline bool hri_evsys_get_interrupt_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; +} + +static inline bool hri_evsys_get_interrupt_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; +} + +static inline bool hri_evsys_get_interrupt_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; +} + +static inline bool hri_evsys_get_interrupt_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR8) >> EVSYS_INTFLAG_OVR8_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR8; +} + +static inline bool hri_evsys_get_interrupt_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR9) >> EVSYS_INTFLAG_OVR9_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR9; +} + +static inline bool hri_evsys_get_interrupt_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR10) >> EVSYS_INTFLAG_OVR10_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR10; +} + +static inline bool hri_evsys_get_interrupt_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR11) >> EVSYS_INTFLAG_OVR11_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR11; +} + +static inline bool hri_evsys_get_interrupt_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; +} + +static inline bool hri_evsys_get_interrupt_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; +} + +static inline bool hri_evsys_get_interrupt_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; +} + +static inline bool hri_evsys_get_interrupt_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; +} + +static inline bool hri_evsys_get_interrupt_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; +} + +static inline bool hri_evsys_get_interrupt_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; +} + +static inline bool hri_evsys_get_interrupt_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; +} + +static inline bool hri_evsys_get_interrupt_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; +} + +static inline bool hri_evsys_get_interrupt_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD8) >> EVSYS_INTFLAG_EVD8_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD8; +} + +static inline bool hri_evsys_get_interrupt_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD9) >> EVSYS_INTFLAG_EVD9_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD9; +} + +static inline bool hri_evsys_get_interrupt_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD10) >> EVSYS_INTFLAG_EVD10_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD10; +} + +static inline bool hri_evsys_get_interrupt_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD11) >> EVSYS_INTFLAG_EVD11_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD11; +} + +static inline hri_evsys_intflag_reg_t hri_evsys_get_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intflag_reg_t hri_evsys_read_INTFLAG_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTFLAG.reg; +} + +static inline void hri_evsys_clear_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) +{ + ((Evsys *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_evsys_set_INTEN_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; +} + +static inline bool hri_evsys_get_INTEN_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR0) >> EVSYS_INTENSET_OVR0_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; + } +} + +static inline void hri_evsys_clear_INTEN_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; +} + +static inline void hri_evsys_set_INTEN_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; +} + +static inline bool hri_evsys_get_INTEN_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR1) >> EVSYS_INTENSET_OVR1_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; + } +} + +static inline void hri_evsys_clear_INTEN_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; +} + +static inline void hri_evsys_set_INTEN_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; +} + +static inline bool hri_evsys_get_INTEN_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR2) >> EVSYS_INTENSET_OVR2_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; + } +} + +static inline void hri_evsys_clear_INTEN_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; +} + +static inline void hri_evsys_set_INTEN_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; +} + +static inline bool hri_evsys_get_INTEN_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR3) >> EVSYS_INTENSET_OVR3_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; + } +} + +static inline void hri_evsys_clear_INTEN_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; +} + +static inline void hri_evsys_set_INTEN_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; +} + +static inline bool hri_evsys_get_INTEN_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR4) >> EVSYS_INTENSET_OVR4_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; + } +} + +static inline void hri_evsys_clear_INTEN_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; +} + +static inline void hri_evsys_set_INTEN_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; +} + +static inline bool hri_evsys_get_INTEN_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR5) >> EVSYS_INTENSET_OVR5_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; + } +} + +static inline void hri_evsys_clear_INTEN_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; +} + +static inline void hri_evsys_set_INTEN_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; +} + +static inline bool hri_evsys_get_INTEN_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR6) >> EVSYS_INTENSET_OVR6_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; + } +} + +static inline void hri_evsys_clear_INTEN_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; +} + +static inline void hri_evsys_set_INTEN_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; +} + +static inline bool hri_evsys_get_INTEN_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR7) >> EVSYS_INTENSET_OVR7_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; + } +} + +static inline void hri_evsys_clear_INTEN_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; +} + +static inline void hri_evsys_set_INTEN_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR8; +} + +static inline bool hri_evsys_get_INTEN_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR8) >> EVSYS_INTENSET_OVR8_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR8; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR8; + } +} + +static inline void hri_evsys_clear_INTEN_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR8; +} + +static inline void hri_evsys_set_INTEN_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR9; +} + +static inline bool hri_evsys_get_INTEN_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR9) >> EVSYS_INTENSET_OVR9_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR9; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR9; + } +} + +static inline void hri_evsys_clear_INTEN_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR9; +} + +static inline void hri_evsys_set_INTEN_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR10; +} + +static inline bool hri_evsys_get_INTEN_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR10) >> EVSYS_INTENSET_OVR10_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR10; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR10; + } +} + +static inline void hri_evsys_clear_INTEN_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR10; +} + +static inline void hri_evsys_set_INTEN_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR11; +} + +static inline bool hri_evsys_get_INTEN_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR11) >> EVSYS_INTENSET_OVR11_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR11; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR11; + } +} + +static inline void hri_evsys_clear_INTEN_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR11; +} + +static inline void hri_evsys_set_INTEN_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; +} + +static inline bool hri_evsys_get_INTEN_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD0) >> EVSYS_INTENSET_EVD0_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; + } +} + +static inline void hri_evsys_clear_INTEN_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; +} + +static inline void hri_evsys_set_INTEN_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; +} + +static inline bool hri_evsys_get_INTEN_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD1) >> EVSYS_INTENSET_EVD1_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; + } +} + +static inline void hri_evsys_clear_INTEN_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; +} + +static inline void hri_evsys_set_INTEN_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; +} + +static inline bool hri_evsys_get_INTEN_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD2) >> EVSYS_INTENSET_EVD2_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; + } +} + +static inline void hri_evsys_clear_INTEN_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; +} + +static inline void hri_evsys_set_INTEN_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; +} + +static inline bool hri_evsys_get_INTEN_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD3) >> EVSYS_INTENSET_EVD3_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; + } +} + +static inline void hri_evsys_clear_INTEN_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; +} + +static inline void hri_evsys_set_INTEN_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; +} + +static inline bool hri_evsys_get_INTEN_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD4) >> EVSYS_INTENSET_EVD4_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; + } +} + +static inline void hri_evsys_clear_INTEN_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; +} + +static inline void hri_evsys_set_INTEN_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; +} + +static inline bool hri_evsys_get_INTEN_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD5) >> EVSYS_INTENSET_EVD5_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; + } +} + +static inline void hri_evsys_clear_INTEN_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; +} + +static inline void hri_evsys_set_INTEN_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; +} + +static inline bool hri_evsys_get_INTEN_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD6) >> EVSYS_INTENSET_EVD6_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; + } +} + +static inline void hri_evsys_clear_INTEN_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; +} + +static inline void hri_evsys_set_INTEN_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; +} + +static inline bool hri_evsys_get_INTEN_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD7) >> EVSYS_INTENSET_EVD7_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; + } +} + +static inline void hri_evsys_clear_INTEN_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; +} + +static inline void hri_evsys_set_INTEN_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD8; +} + +static inline bool hri_evsys_get_INTEN_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD8) >> EVSYS_INTENSET_EVD8_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD8; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD8; + } +} + +static inline void hri_evsys_clear_INTEN_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD8; +} + +static inline void hri_evsys_set_INTEN_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD9; +} + +static inline bool hri_evsys_get_INTEN_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD9) >> EVSYS_INTENSET_EVD9_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD9; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD9; + } +} + +static inline void hri_evsys_clear_INTEN_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD9; +} + +static inline void hri_evsys_set_INTEN_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD10; +} + +static inline bool hri_evsys_get_INTEN_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD10) >> EVSYS_INTENSET_EVD10_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD10; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD10; + } +} + +static inline void hri_evsys_clear_INTEN_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD10; +} + +static inline void hri_evsys_set_INTEN_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD11; +} + +static inline bool hri_evsys_get_INTEN_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD11) >> EVSYS_INTENSET_EVD11_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD11; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD11; + } +} + +static inline void hri_evsys_clear_INTEN_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD11; +} + +static inline void hri_evsys_set_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + ((Evsys *)hw)->INTENSET.reg = mask; +} + +static inline hri_evsys_intenset_reg_t hri_evsys_get_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intenset_reg_t hri_evsys_read_INTEN_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTENSET.reg; +} + +static inline void hri_evsys_write_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t data) +{ + ((Evsys *)hw)->INTENSET.reg = data; + ((Evsys *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_evsys_clear_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + ((Evsys *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY0_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY0) >> EVSYS_CHSTATUS_USRRDY0_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY1_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY1) >> EVSYS_CHSTATUS_USRRDY1_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY2_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY2) >> EVSYS_CHSTATUS_USRRDY2_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY3_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY3) >> EVSYS_CHSTATUS_USRRDY3_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY4_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY4) >> EVSYS_CHSTATUS_USRRDY4_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY5_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY5) >> EVSYS_CHSTATUS_USRRDY5_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY6_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY6) >> EVSYS_CHSTATUS_USRRDY6_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY7_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY7) >> EVSYS_CHSTATUS_USRRDY7_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY8_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY8) >> EVSYS_CHSTATUS_USRRDY8_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY9_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY9) >> EVSYS_CHSTATUS_USRRDY9_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY10_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY10) >> EVSYS_CHSTATUS_USRRDY10_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY11_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY11) >> EVSYS_CHSTATUS_USRRDY11_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY0_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY0) >> EVSYS_CHSTATUS_CHBUSY0_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY1_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY1) >> EVSYS_CHSTATUS_CHBUSY1_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY2_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY2) >> EVSYS_CHSTATUS_CHBUSY2_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY3_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY3) >> EVSYS_CHSTATUS_CHBUSY3_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY4_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY4) >> EVSYS_CHSTATUS_CHBUSY4_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY5_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY5) >> EVSYS_CHSTATUS_CHBUSY5_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY6_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY6) >> EVSYS_CHSTATUS_CHBUSY6_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY7_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY7) >> EVSYS_CHSTATUS_CHBUSY7_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY8_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY8) >> EVSYS_CHSTATUS_CHBUSY8_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY9_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY9) >> EVSYS_CHSTATUS_CHBUSY9_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY10_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY10) >> EVSYS_CHSTATUS_CHBUSY10_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY11_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY11) >> EVSYS_CHSTATUS_CHBUSY11_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, hri_evsys_chstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw) +{ + return ((Evsys *)hw)->CHSTATUS.reg; +} + +static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) +{ + return ((Evsys *)hw)->CTRLA.reg; +} + +static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->CHANNEL[index].reg; +} + +static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= ~EVSYS_USER_CHANNEL_Msk; + tmp |= EVSYS_USER_CHANNEL(data); + ((Evsys *)hw)->USER[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->USER[index].reg; +} + +static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->SWEVT.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EVSYS_C21_H_INCLUDED */ +#endif /* _SAMC21_EVSYS_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_freqm_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_freqm_c21.h new file mode 100644 index 0000000..616cec2 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_freqm_c21.h @@ -0,0 +1,464 @@ +/** + * \file + * + * \brief SAM FREQM + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_FREQM_COMPONENT_ +#ifndef _HRI_FREQM_C21_H_INCLUDED_ +#define _HRI_FREQM_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_FREQM_CRITICAL_SECTIONS) +#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define FREQM_CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_freqm_cfga_reg_t; +typedef uint32_t hri_freqm_syncbusy_reg_t; +typedef uint32_t hri_freqm_value_reg_t; +typedef uint8_t hri_freqm_ctrla_reg_t; +typedef uint8_t hri_freqm_ctrlb_reg_t; +typedef uint8_t hri_freqm_intenset_reg_t; +typedef uint8_t hri_freqm_intflag_reg_t; +typedef uint8_t hri_freqm_status_reg_t; + +static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + while (((Freqm *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + return ((Freqm *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTFLAG.reg; +} + +static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + ((Freqm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; +} + +static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos; +} + +static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; + } else { + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; + } +} + +static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; +} + +static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENSET.reg = mask; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTENSET.reg; +} + +static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data) +{ + ((Freqm *)hw)->INTENSET.reg = data; + ((Freqm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Freqm *)hw)->SYNCBUSY.reg; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->VALUE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw) +{ + return ((Freqm *)hw)->VALUE.reg; +} + +static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= ~FREQM_CTRLA_ENABLE; + tmp |= value << FREQM_CTRLA_ENABLE_Pos; + ((Freqm *)hw)->CTRLA.reg = tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg = data; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw) +{ + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + return ((Freqm *)hw)->CTRLA.reg; +} + +static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data) +{ + uint16_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= ~FREQM_CFGA_REFNUM_Msk; + tmp |= FREQM_CFGA_REFNUM(data); + ((Freqm *)hw)->CFGA.reg = tmp; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw) +{ + return ((Freqm *)hw)->CFGA.reg; +} + +static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos; +} + +static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos; +} + +static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw) +{ + return ((Freqm *)hw)->STATUS.reg; +} + +static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLB.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_FREQM_C21_H_INCLUDED */ +#endif /* _SAMC21_FREQM_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_gclk_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_gclk_c21.h new file mode 100644 index 0000000..0234e1e --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_gclk_c21.h @@ -0,0 +1,790 @@ +/** + * \file + * + * \brief SAM GCLK + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_GCLK_COMPONENT_ +#ifndef _HRI_GCLK_C21_H_INCLUDED_ +#define _HRI_GCLK_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) +#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GCLK_CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gclk_genctrl_reg_t; +typedef uint32_t hri_gclk_pchctrl_reg_t; +typedef uint32_t hri_gclk_syncbusy_reg_t; +typedef uint8_t hri_gclk_ctrla_reg_t; + +static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + while (((Gclk *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + return ((Gclk *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Gclk *)hw)->SYNCBUSY.reg; +} + +static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + return ((Gclk *)hw)->CTRLA.reg; +} + +static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_GENEN; + tmp |= value << GCLK_GENCTRL_GENEN_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_IDC; + tmp |= value << GCLK_GENCTRL_IDC_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OOV; + tmp |= value << GCLK_GENCTRL_OOV_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OE; + tmp |= value << GCLK_GENCTRL_OE_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIVSEL; + tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_RUNSTDBY; + tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_SRC_Msk; + tmp |= GCLK_GENCTRL_SRC(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIV_Msk; + tmp |= GCLK_GENCTRL_DIV(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + return ((Gclk *)hw)->GENCTRL[index].reg; +} + +static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_CHEN; + tmp |= value << GCLK_PCHCTRL_CHEN_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_WRTLOCK; + tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_GEN_Msk; + tmp |= GCLK_PCHCTRL_GEN(data); + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Gclk *)hw)->PCHCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GCLK_C21_H_INCLUDED */ +#endif /* _SAMC21_GCLK_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_hmatrixb_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_hmatrixb_c21.h new file mode 100644 index 0000000..95e0f8c --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_hmatrixb_c21.h @@ -0,0 +1,408 @@ +/** + * \file + * + * \brief SAM HMATRIXB + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_HMATRIXB_COMPONENT_ +#ifndef _HRI_HMATRIXB_C21_H_INCLUDED_ +#define _HRI_HMATRIXB_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS) +#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define HMATRIXB_CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_hmatrixb_mcfg_reg_t; +typedef uint32_t hri_hmatrixb_mrcr_reg_t; +typedef uint32_t hri_hmatrixb_pras_reg_t; +typedef uint32_t hri_hmatrixb_prbs_reg_t; +typedef uint32_t hri_hmatrixb_scfg_reg_t; +typedef uint32_t hri_hmatrixb_sfr_reg_t; +typedef uint32_t hri_hmatrixbprs_pras_reg_t; +typedef uint32_t hri_hmatrixbprs_prbs_reg_t; + +static inline void hri_hmatrixb_set_MCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_mcfg_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MCFG[index].reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_mcfg_reg_t hri_hmatrixb_get_MCFG_reg(const void *const hw, uint8_t index, + hri_hmatrixb_mcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->MCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_MCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_mcfg_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MCFG[index].reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_MCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_mcfg_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MCFG[index].reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_MCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_mcfg_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MCFG[index].reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_mcfg_reg_t hri_hmatrixb_read_MCFG_reg(const void *const hw, uint8_t index) +{ + return ((Hmatrixb *)hw)->MCFG[index].reg; +} + +static inline void hri_hmatrixb_set_SCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_scfg_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SCFG[index].reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_scfg_reg_t hri_hmatrixb_get_SCFG_reg(const void *const hw, uint8_t index, + hri_hmatrixb_scfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->SCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_SCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_scfg_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SCFG[index].reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_SCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_scfg_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SCFG[index].reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_SCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_scfg_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SCFG[index].reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_scfg_reg_t hri_hmatrixb_read_SCFG_reg(const void *const hw, uint8_t index) +{ + return ((Hmatrixb *)hw)->SCFG[index].reg; +} + +static inline void hri_hmatrixb_set_MRCR_reg(const void *const hw, hri_hmatrixb_mrcr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MRCR.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_mrcr_reg_t hri_hmatrixb_get_MRCR_reg(const void *const hw, hri_hmatrixb_mrcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->MRCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_MRCR_reg(const void *const hw, hri_hmatrixb_mrcr_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MRCR.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_MRCR_reg(const void *const hw, hri_hmatrixb_mrcr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MRCR.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_MRCR_reg(const void *const hw, hri_hmatrixb_mrcr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MRCR.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_mrcr_reg_t hri_hmatrixb_read_MRCR_reg(const void *const hw) +{ + return ((Hmatrixb *)hw)->MRCR.reg; +} + +static inline void hri_hmatrixb_set_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SFR[index].reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_sfr_reg_t hri_hmatrixb_get_SFR_reg(const void *const hw, uint8_t index, + hri_hmatrixb_sfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->SFR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SFR[index].reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SFR[index].reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SFR[index].reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_sfr_reg_t hri_hmatrixb_read_SFR_reg(const void *const hw, uint8_t index) +{ + return ((Hmatrixb *)hw)->SFR[index].reg; +} + +static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRAS.reg; +} + +static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRBS.reg; +} + +static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; +} + +static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_HMATRIXB_C21_H_INCLUDED */ +#endif /* _SAMC21_HMATRIXB_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_mclk_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_mclk_c21.h new file mode 100644 index 0000000..50253df --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_mclk_c21.h @@ -0,0 +1,2490 @@ +/** + * \file + * + * \brief SAM MCLK + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_MCLK_COMPONENT_ +#ifndef _HRI_MCLK_C21_H_INCLUDED_ +#define _HRI_MCLK_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MCLK_CRITICAL_SECTIONS) +#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MCLK_CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mclk_ahbmask_reg_t; +typedef uint32_t hri_mclk_apbamask_reg_t; +typedef uint32_t hri_mclk_apbbmask_reg_t; +typedef uint32_t hri_mclk_apbcmask_reg_t; +typedef uint8_t hri_mclk_cpudiv_reg_t; +typedef uint8_t hri_mclk_intenset_reg_t; +typedef uint8_t hri_mclk_intflag_reg_t; + +static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTFLAG.reg; +} + +static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + ((Mclk *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; +} + +static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; +} + +static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; + } else { + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; + } +} + +static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; +} + +static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENSET.reg = mask; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTENSET.reg; +} + +static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data) +{ + ((Mclk *)hw)->INTENSET.reg = data; + ((Mclk *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_mclk_set_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_CPUDIV(mask)) >> MCLK_CPUDIV_CPUDIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= ~MCLK_CPUDIV_CPUDIV_Msk; + tmp |= MCLK_CPUDIV_CPUDIV(data); + ((Mclk *)hw)->CPUDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_CPUDIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_CPUDIV_Msk) >> MCLK_CPUDIV_CPUDIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->CPUDIV.reg; +} + +static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB0; + tmp |= value << MCLK_AHBMASK_HPB0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB1; + tmp |= value << MCLK_AHBMASK_HPB1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB2; + tmp |= value << MCLK_AHBMASK_HPB2_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DSU; + tmp |= value << MCLK_AHBMASK_DSU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HMATRIXHS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMATRIXHS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HMATRIXHS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HMATRIXHS) >> MCLK_AHBMASK_HMATRIXHS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HMATRIXHS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HMATRIXHS; + tmp |= value << MCLK_AHBMASK_HMATRIXHS_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HMATRIXHS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMATRIXHS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HMATRIXHS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMATRIXHS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL; + tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HSRAM; + tmp |= value << MCLK_AHBMASK_HSRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DMAC; + tmp |= value << MCLK_AHBMASK_DMAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CAN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CAN0) >> MCLK_AHBMASK_CAN0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CAN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CAN0; + tmp |= value << MCLK_AHBMASK_CAN0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CAN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CAN1) >> MCLK_AHBMASK_CAN1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CAN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CAN1; + tmp |= value << MCLK_AHBMASK_CAN1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PAC; + tmp |= value << MCLK_AHBMASK_PAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_PICACHU) >> MCLK_AHBMASK_NVMCTRL_PICACHU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_PICACHU; + tmp |= value << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DIVAS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DIVAS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DIVAS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DIVAS) >> MCLK_AHBMASK_DIVAS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DIVAS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DIVAS; + tmp |= value << MCLK_AHBMASK_DIVAS_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DIVAS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DIVAS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DIVAS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DIVAS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->AHBMASK.reg; +} + +static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PAC; + tmp |= value << MCLK_APBAMASK_PAC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PM; + tmp |= value << MCLK_APBAMASK_PM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_MCLK; + tmp |= value << MCLK_APBAMASK_MCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RSTC; + tmp |= value << MCLK_APBAMASK_RSTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSCCTRL; + tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSC32KCTRL; + tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SUPC; + tmp |= value << MCLK_APBAMASK_SUPC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_GCLK; + tmp |= value << MCLK_APBAMASK_GCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_WDT; + tmp |= value << MCLK_APBAMASK_WDT_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RTC; + tmp |= value << MCLK_APBAMASK_RTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_EIC; + tmp |= value << MCLK_APBAMASK_EIC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_FREQM; + tmp |= value << MCLK_APBAMASK_FREQM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_TSENS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TSENS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_TSENS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_TSENS) >> MCLK_APBAMASK_TSENS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_TSENS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_TSENS; + tmp |= value << MCLK_APBAMASK_TSENS_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_TSENS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TSENS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_TSENS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TSENS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBAMASK.reg; +} + +static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_PORT; + tmp |= value << MCLK_APBBMASK_PORT_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_DSU; + tmp |= value << MCLK_APBBMASK_DSU_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_NVMCTRL; + tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_HMATRIXHS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_HMATRIXHS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_HMATRIXHS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_HMATRIXHS) >> MCLK_APBBMASK_HMATRIXHS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_HMATRIXHS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_HMATRIXHS; + tmp |= value << MCLK_APBBMASK_HMATRIXHS_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_HMATRIXHS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_HMATRIXHS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_HMATRIXHS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_HMATRIXHS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBBMASK.reg; +} + +static inline void hri_mclk_set_APBCMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_EVSYS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_EVSYS) >> MCLK_APBCMASK_EVSYS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_EVSYS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_EVSYS; + tmp |= value << MCLK_APBCMASK_EVSYS_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM0) >> MCLK_APBCMASK_SERCOM0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM0; + tmp |= value << MCLK_APBCMASK_SERCOM0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM1) >> MCLK_APBCMASK_SERCOM1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM1; + tmp |= value << MCLK_APBCMASK_SERCOM1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM2) >> MCLK_APBCMASK_SERCOM2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM2; + tmp |= value << MCLK_APBCMASK_SERCOM2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM3) >> MCLK_APBCMASK_SERCOM3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM3; + tmp |= value << MCLK_APBCMASK_SERCOM3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM4) >> MCLK_APBCMASK_SERCOM4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM4; + tmp |= value << MCLK_APBCMASK_SERCOM4_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM5) >> MCLK_APBCMASK_SERCOM5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM5; + tmp |= value << MCLK_APBCMASK_SERCOM5_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC0) >> MCLK_APBCMASK_TCC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC0; + tmp |= value << MCLK_APBCMASK_TCC0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC1) >> MCLK_APBCMASK_TCC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC1; + tmp |= value << MCLK_APBCMASK_TCC1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC2; + tmp |= value << MCLK_APBCMASK_TCC2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC0) >> MCLK_APBCMASK_TC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC0; + tmp |= value << MCLK_APBCMASK_TC0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC1) >> MCLK_APBCMASK_TC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC1; + tmp |= value << MCLK_APBCMASK_TC1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC2) >> MCLK_APBCMASK_TC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC2; + tmp |= value << MCLK_APBCMASK_TC2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC3) >> MCLK_APBCMASK_TC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC3; + tmp |= value << MCLK_APBCMASK_TC3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC4; + tmp |= value << MCLK_APBCMASK_TC4_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_ADC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_ADC0) >> MCLK_APBCMASK_ADC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_ADC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_ADC0; + tmp |= value << MCLK_APBCMASK_ADC0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_ADC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_ADC1) >> MCLK_APBCMASK_ADC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_ADC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_ADC1; + tmp |= value << MCLK_APBCMASK_ADC1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SDADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SDADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SDADC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SDADC) >> MCLK_APBCMASK_SDADC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SDADC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SDADC; + tmp |= value << MCLK_APBCMASK_SDADC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SDADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SDADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SDADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SDADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AC; + tmp |= value << MCLK_APBCMASK_AC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_DAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_DAC) >> MCLK_APBCMASK_DAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_DAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_DAC; + tmp |= value << MCLK_APBCMASK_DAC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_PTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_PTC) >> MCLK_APBCMASK_PTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_PTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_PTC; + tmp |= value << MCLK_APBCMASK_PTC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_CCL; + tmp |= value << MCLK_APBCMASK_CCL_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBCMASK.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MCLK_C21_H_INCLUDED */ +#endif /* _SAMC21_MCLK_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_mpu_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_mpu_c21.h new file mode 100644 index 0000000..ef2b76c --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_mpu_c21.h @@ -0,0 +1,266 @@ +/** + * \file + * + * \brief SAM MPU + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_MPU_COMPONENT_ +#ifndef _HRI_MPU_C21_H_INCLUDED_ +#define _HRI_MPU_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MPU_CRITICAL_SECTIONS) +#define MPU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MPU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MPU_CRITICAL_SECTION_ENTER() +#define MPU_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mpu_ctrl_reg_t; +typedef uint32_t hri_mpu_rasr_reg_t; +typedef uint32_t hri_mpu_rbar_reg_t; +typedef uint32_t hri_mpu_rnr_reg_t; +typedef uint32_t hri_mpu_type_reg_t; + +static inline bool hri_mpu_get_TYPE_SEPARATE_bit(const void *const hw) +{ + return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_SEPARATE) >> 0; +} + +static inline hri_mpu_type_reg_t hri_mpu_get_TYPE_DREGION_bf(const void *const hw, hri_mpu_type_reg_t mask) +{ + return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_DREGION(mask)) >> 8; +} + +static inline hri_mpu_type_reg_t hri_mpu_read_TYPE_DREGION_bf(const void *const hw) +{ + return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_DREGION_Msk) >> 8; +} + +static inline hri_mpu_type_reg_t hri_mpu_get_TYPE_IREGION_bf(const void *const hw, hri_mpu_type_reg_t mask) +{ + return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_IREGION(mask)) >> 16; +} + +static inline hri_mpu_type_reg_t hri_mpu_read_TYPE_IREGION_bf(const void *const hw) +{ + return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_IREGION_Msk) >> 16; +} + +static inline hri_mpu_type_reg_t hri_mpu_get_TYPE_reg(const void *const hw, hri_mpu_type_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mpu *)hw)->TYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mpu_type_reg_t hri_mpu_read_TYPE_reg(const void *const hw) +{ + return ((Mpu *)hw)->TYPE.reg; +} + +static inline void hri_mpu_set_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->CTRL.reg |= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_ctrl_reg_t hri_mpu_get_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mpu *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mpu_write_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t data) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->CTRL.reg = data; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_clear_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->CTRL.reg &= ~mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_toggle_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->CTRL.reg ^= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_ctrl_reg_t hri_mpu_read_CTRL_reg(const void *const hw) +{ + return ((Mpu *)hw)->CTRL.reg; +} + +static inline void hri_mpu_set_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RNR.reg |= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_rnr_reg_t hri_mpu_get_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mpu *)hw)->RNR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mpu_write_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t data) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RNR.reg = data; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_clear_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RNR.reg &= ~mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_toggle_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RNR.reg ^= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_rnr_reg_t hri_mpu_read_RNR_reg(const void *const hw) +{ + return ((Mpu *)hw)->RNR.reg; +} + +static inline void hri_mpu_set_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RBAR.reg |= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_rbar_reg_t hri_mpu_get_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mpu *)hw)->RBAR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mpu_write_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t data) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RBAR.reg = data; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_clear_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RBAR.reg &= ~mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_toggle_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RBAR.reg ^= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_rbar_reg_t hri_mpu_read_RBAR_reg(const void *const hw) +{ + return ((Mpu *)hw)->RBAR.reg; +} + +static inline void hri_mpu_set_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RASR.reg |= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_rasr_reg_t hri_mpu_get_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mpu *)hw)->RASR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mpu_write_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t data) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RASR.reg = data; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_clear_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RASR.reg &= ~mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_toggle_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RASR.reg ^= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_rasr_reg_t hri_mpu_read_RASR_reg(const void *const hw) +{ + return ((Mpu *)hw)->RASR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MPU_C21_H_INCLUDED */ +#endif /* _SAMC21_MPU_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_mtb_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_mtb_c21.h new file mode 100644 index 0000000..fb60372 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_mtb_c21.h @@ -0,0 +1,551 @@ +/** + * \file + * + * \brief SAM MTB + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_MTB_COMPONENT_ +#ifndef _HRI_MTB_C21_H_INCLUDED_ +#define _HRI_MTB_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MTB_CRITICAL_SECTIONS) +#define MTB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MTB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MTB_CRITICAL_SECTION_ENTER() +#define MTB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mtb_authstatus_reg_t; +typedef uint32_t hri_mtb_base_reg_t; +typedef uint32_t hri_mtb_cid0_reg_t; +typedef uint32_t hri_mtb_cid1_reg_t; +typedef uint32_t hri_mtb_cid2_reg_t; +typedef uint32_t hri_mtb_cid3_reg_t; +typedef uint32_t hri_mtb_claimset_reg_t; +typedef uint32_t hri_mtb_devarch_reg_t; +typedef uint32_t hri_mtb_devid_reg_t; +typedef uint32_t hri_mtb_devtype_reg_t; +typedef uint32_t hri_mtb_flow_reg_t; +typedef uint32_t hri_mtb_itctrl_reg_t; +typedef uint32_t hri_mtb_lockaccess_reg_t; +typedef uint32_t hri_mtb_lockstatus_reg_t; +typedef uint32_t hri_mtb_master_reg_t; +typedef uint32_t hri_mtb_pid0_reg_t; +typedef uint32_t hri_mtb_pid1_reg_t; +typedef uint32_t hri_mtb_pid2_reg_t; +typedef uint32_t hri_mtb_pid3_reg_t; +typedef uint32_t hri_mtb_pid4_reg_t; +typedef uint32_t hri_mtb_pid5_reg_t; +typedef uint32_t hri_mtb_pid6_reg_t; +typedef uint32_t hri_mtb_pid7_reg_t; +typedef uint32_t hri_mtb_position_reg_t; + +static inline void hri_mtb_set_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + ((Mtb *)hw)->CLAIMSET.reg = mask; +} + +static inline hri_mtb_claimset_reg_t hri_mtb_get_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CLAIMSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_claimset_reg_t hri_mtb_read_CLAIM_reg(const void *const hw) +{ + return ((Mtb *)hw)->CLAIMSET.reg; +} + +static inline void hri_mtb_write_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t data) +{ + ((Mtb *)hw)->CLAIMSET.reg = data; + ((Mtb *)hw)->CLAIMCLR.reg = ~data; +} + +static inline void hri_mtb_clear_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + ((Mtb *)hw)->CLAIMCLR.reg = mask; +} + +static inline hri_mtb_base_reg_t hri_mtb_get_BASE_reg(const void *const hw, hri_mtb_base_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->BASE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_base_reg_t hri_mtb_read_BASE_reg(const void *const hw) +{ + return ((Mtb *)hw)->BASE.reg; +} + +static inline hri_mtb_lockstatus_reg_t hri_mtb_get_LOCKSTATUS_reg(const void *const hw, hri_mtb_lockstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->LOCKSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_lockstatus_reg_t hri_mtb_read_LOCKSTATUS_reg(const void *const hw) +{ + return ((Mtb *)hw)->LOCKSTATUS.reg; +} + +static inline hri_mtb_authstatus_reg_t hri_mtb_get_AUTHSTATUS_reg(const void *const hw, hri_mtb_authstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->AUTHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_authstatus_reg_t hri_mtb_read_AUTHSTATUS_reg(const void *const hw) +{ + return ((Mtb *)hw)->AUTHSTATUS.reg; +} + +static inline hri_mtb_devarch_reg_t hri_mtb_get_DEVARCH_reg(const void *const hw, hri_mtb_devarch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVARCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devarch_reg_t hri_mtb_read_DEVARCH_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVARCH.reg; +} + +static inline hri_mtb_devid_reg_t hri_mtb_get_DEVID_reg(const void *const hw, hri_mtb_devid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devid_reg_t hri_mtb_read_DEVID_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVID.reg; +} + +static inline hri_mtb_devtype_reg_t hri_mtb_get_DEVTYPE_reg(const void *const hw, hri_mtb_devtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devtype_reg_t hri_mtb_read_DEVTYPE_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVTYPE.reg; +} + +static inline hri_mtb_pid4_reg_t hri_mtb_get_PID4_reg(const void *const hw, hri_mtb_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid4_reg_t hri_mtb_read_PID4_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID4.reg; +} + +static inline hri_mtb_pid5_reg_t hri_mtb_get_PID5_reg(const void *const hw, hri_mtb_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid5_reg_t hri_mtb_read_PID5_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID5.reg; +} + +static inline hri_mtb_pid6_reg_t hri_mtb_get_PID6_reg(const void *const hw, hri_mtb_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid6_reg_t hri_mtb_read_PID6_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID6.reg; +} + +static inline hri_mtb_pid7_reg_t hri_mtb_get_PID7_reg(const void *const hw, hri_mtb_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid7_reg_t hri_mtb_read_PID7_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID7.reg; +} + +static inline hri_mtb_pid0_reg_t hri_mtb_get_PID0_reg(const void *const hw, hri_mtb_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid0_reg_t hri_mtb_read_PID0_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID0.reg; +} + +static inline hri_mtb_pid1_reg_t hri_mtb_get_PID1_reg(const void *const hw, hri_mtb_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid1_reg_t hri_mtb_read_PID1_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID1.reg; +} + +static inline hri_mtb_pid2_reg_t hri_mtb_get_PID2_reg(const void *const hw, hri_mtb_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid2_reg_t hri_mtb_read_PID2_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID2.reg; +} + +static inline hri_mtb_pid3_reg_t hri_mtb_get_PID3_reg(const void *const hw, hri_mtb_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid3_reg_t hri_mtb_read_PID3_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID3.reg; +} + +static inline hri_mtb_cid0_reg_t hri_mtb_get_CID0_reg(const void *const hw, hri_mtb_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid0_reg_t hri_mtb_read_CID0_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID0.reg; +} + +static inline hri_mtb_cid1_reg_t hri_mtb_get_CID1_reg(const void *const hw, hri_mtb_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid1_reg_t hri_mtb_read_CID1_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID1.reg; +} + +static inline hri_mtb_cid2_reg_t hri_mtb_get_CID2_reg(const void *const hw, hri_mtb_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid2_reg_t hri_mtb_read_CID2_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID2.reg; +} + +static inline hri_mtb_cid3_reg_t hri_mtb_get_CID3_reg(const void *const hw, hri_mtb_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid3_reg_t hri_mtb_read_CID3_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID3.reg; +} + +static inline void hri_mtb_set_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_position_reg_t hri_mtb_get_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->POSITION.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_POSITION_reg(const void *const hw, hri_mtb_position_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_position_reg_t hri_mtb_read_POSITION_reg(const void *const hw) +{ + return ((Mtb *)hw)->POSITION.reg; +} + +static inline void hri_mtb_set_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_master_reg_t hri_mtb_get_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->MASTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_MASTER_reg(const void *const hw, hri_mtb_master_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_master_reg_t hri_mtb_read_MASTER_reg(const void *const hw) +{ + return ((Mtb *)hw)->MASTER.reg; +} + +static inline void hri_mtb_set_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_flow_reg_t hri_mtb_get_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->FLOW.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_flow_reg_t hri_mtb_read_FLOW_reg(const void *const hw) +{ + return ((Mtb *)hw)->FLOW.reg; +} + +static inline void hri_mtb_set_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_itctrl_reg_t hri_mtb_get_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->ITCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_itctrl_reg_t hri_mtb_read_ITCTRL_reg(const void *const hw) +{ + return ((Mtb *)hw)->ITCTRL.reg; +} + +static inline void hri_mtb_set_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_lockaccess_reg_t hri_mtb_get_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->LOCKACCESS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_lockaccess_reg_t hri_mtb_read_LOCKACCESS_reg(const void *const hw) +{ + return ((Mtb *)hw)->LOCKACCESS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MTB_C21_H_INCLUDED */ +#endif /* _SAMC21_MTB_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_nvic_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_nvic_c21.h new file mode 100644 index 0000000..aea356b --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_nvic_c21.h @@ -0,0 +1,269 @@ +/** + * \file + * + * \brief SAM NVIC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_NVIC_COMPONENT_ +#ifndef _HRI_NVIC_C21_H_INCLUDED_ +#define _HRI_NVIC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVIC_CRITICAL_SECTIONS) +#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVIC_CRITICAL_SECTION_ENTER() +#define NVIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_nvic_icer_reg_t; +typedef uint32_t hri_nvic_icpr_reg_t; +typedef uint32_t hri_nvic_ipr_reg_t; +typedef uint32_t hri_nvic_iser_reg_t; +typedef uint32_t hri_nvic_ispr_reg_t; + +static inline void hri_nvic_set_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_iser_reg_t hri_nvic_get_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ISER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ISER_reg(const void *const hw, hri_nvic_iser_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_iser_reg_t hri_nvic_read_ISER_reg(const void *const hw) +{ + return ((Nvic *)hw)->ISER.reg; +} + +static inline void hri_nvic_set_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icer_reg_t hri_nvic_get_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ICER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ICER_reg(const void *const hw, hri_nvic_icer_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icer_reg_t hri_nvic_read_ICER_reg(const void *const hw) +{ + return ((Nvic *)hw)->ICER.reg; +} + +static inline void hri_nvic_set_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ispr_reg_t hri_nvic_get_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ISPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ispr_reg_t hri_nvic_read_ISPR_reg(const void *const hw) +{ + return ((Nvic *)hw)->ISPR.reg; +} + +static inline void hri_nvic_set_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icpr_reg_t hri_nvic_get_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ICPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icpr_reg_t hri_nvic_read_ICPR_reg(const void *const hw) +{ + return ((Nvic *)hw)->ICPR.reg; +} + +static inline void hri_nvic_set_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ipr_reg_t hri_nvic_get_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->IPR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ipr_reg_t hri_nvic_read_IPR_reg(const void *const hw, uint8_t index) +{ + return ((Nvic *)hw)->IPR[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVIC_C21_H_INCLUDED */ +#endif /* _SAMC21_NVIC_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_nvmctrl_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_nvmctrl_c21.h new file mode 100644 index 0000000..76ebdb3 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_nvmctrl_c21.h @@ -0,0 +1,1103 @@ +/** + * \file + * + * \brief SAM NVMCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_NVMCTRL_COMPONENT_ +#ifndef _HRI_NVMCTRL_C21_H_INCLUDED_ +#define _HRI_NVMCTRL_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) +#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVMCTRL_CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_nvmctrl_ctrla_reg_t; +typedef uint16_t hri_nvmctrl_lock_reg_t; +typedef uint16_t hri_nvmctrl_status_reg_t; +typedef uint32_t hri_nvmctrl_addr_reg_t; +typedef uint32_t hri_nvmctrl_ctrlb_reg_t; +typedef uint32_t hri_nvmctrl_param_reg_t; +typedef uint32_t hri_nvmctrl_pbldata0_reg_t; +typedef uint32_t hri_nvmctrl_pbldata1_reg_t; +typedef uint8_t hri_nvmctrl_intenset_reg_t; +typedef uint8_t hri_nvmctrl_intflag_reg_t; + +static inline bool hri_nvmctrl_get_INTFLAG_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; +} + +static inline bool hri_nvmctrl_get_interrupt_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; +} + +static inline bool hri_nvmctrl_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, + hri_nvmctrl_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_nvmctrl_set_INTEN_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; +} + +static inline bool hri_nvmctrl_get_INTEN_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_READY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; + } +} + +static inline void hri_nvmctrl_clear_INTEN_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; +} + +static inline void hri_nvmctrl_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; +} + +static inline bool hri_nvmctrl_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; +} + +static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, + hri_nvmctrl_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTENSET.reg; +} + +static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) +{ + ((Nvmctrl *)hw)->INTENSET.reg = data; + ((Nvmctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = mask; +} + +static inline hri_nvmctrl_pbldata0_reg_t hri_nvmctrl_get_PBLDATA0_reg(const void *const hw, + hri_nvmctrl_pbldata0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PBLDATA0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_pbldata0_reg_t hri_nvmctrl_read_PBLDATA0_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PBLDATA0.reg; +} + +static inline hri_nvmctrl_pbldata1_reg_t hri_nvmctrl_get_PBLDATA1_reg(const void *const hw, + hri_nvmctrl_pbldata1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PBLDATA1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_pbldata1_reg_t hri_nvmctrl_read_PBLDATA1_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PBLDATA1.reg; +} + +static inline void hri_nvmctrl_set_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMD(mask)) >> NVMCTRL_CTRLA_CMD_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CMD_Msk; + tmp |= NVMCTRL_CTRLA_CMD(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMD_Msk) >> NVMCTRL_CTRLA_CMD_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMDEX(mask)) >> NVMCTRL_CTRLA_CMDEX_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CMDEX_Msk; + tmp |= NVMCTRL_CTRLA_CMDEX(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMDEX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMDEX_Msk) >> NVMCTRL_CTRLA_CMDEX_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLA.reg; +} + +static inline void hri_nvmctrl_set_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLB_MANW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_MANW) >> NVMCTRL_CTRLB_MANW_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_MANW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_MANW; + tmp |= value << NVMCTRL_CTRLB_MANW_Pos; + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_RWS(mask)) >> NVMCTRL_CTRLB_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_RWS_Msk; + tmp |= NVMCTRL_CTRLB_RWS(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_RWS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_RWS_Msk) >> NVMCTRL_CTRLB_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_SLEEPPRM_bf(const void *const hw, + hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM(mask)) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_SLEEPPRM_Msk; + tmp |= NVMCTRL_CTRLB_SLEEPPRM(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_SLEEPPRM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM_Msk) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_READMODE_bf(const void *const hw, + hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_READMODE(mask)) >> NVMCTRL_CTRLB_READMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_READMODE_Msk; + tmp |= NVMCTRL_CTRLB_READMODE(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_READMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_READMODE_Msk) >> NVMCTRL_CTRLB_READMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_CACHEDIS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_CACHEDIS_bf(const void *const hw, + hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_CACHEDIS(mask)) >> NVMCTRL_CTRLB_CACHEDIS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_CACHEDIS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_CACHEDIS_Msk; + tmp |= NVMCTRL_CTRLB_CACHEDIS(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_CACHEDIS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_CACHEDIS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_CACHEDIS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_CACHEDIS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_CACHEDIS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_CACHEDIS_Msk) >> NVMCTRL_CTRLB_CACHEDIS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLB.reg; +} + +static inline void hri_nvmctrl_set_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_NVMP_Msk; + tmp |= NVMCTRL_PARAM_NVMP(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_PSZ_Msk; + tmp |= NVMCTRL_PARAM_PSZ(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_RWWEEP_bf(const void *const hw, + hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_RWWEEP(mask)) >> NVMCTRL_PARAM_RWWEEP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_RWWEEP_Msk; + tmp |= NVMCTRL_PARAM_RWWEEP(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_RWWEEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_RWWEEP_Msk) >> NVMCTRL_PARAM_RWWEEP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PARAM.reg; +} + +static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= ~NVMCTRL_ADDR_ADDR_Msk; + tmp |= NVMCTRL_ADDR_ADDR(data); + ((Nvmctrl *)hw)->ADDR.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ADDR.reg; +} + +static inline void hri_nvmctrl_set_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg |= NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp = (tmp & NVMCTRL_LOCK_LOCK(mask)) >> NVMCTRL_LOCK_LOCK_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp &= ~NVMCTRL_LOCK_LOCK_Msk; + tmp |= NVMCTRL_LOCK_LOCK(data); + ((Nvmctrl *)hw)->LOCK.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg &= ~NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg ^= NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_LOCK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp = (tmp & NVMCTRL_LOCK_LOCK_Msk) >> NVMCTRL_LOCK_LOCK_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->LOCK.reg; +} + +static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_PRM_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PRM; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_LOAD_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOAD; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PROGE) >> NVMCTRL_STATUS_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_PROGE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PROGE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOCKE) >> NVMCTRL_STATUS_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_LOCKE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOCKE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_NVME) >> NVMCTRL_STATUS_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_NVME_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_NVME; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_SB_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SB) >> NVMCTRL_STATUS_SB_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_SB_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_SB; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_clear_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVMCTRL_C21_H_INCLUDED */ +#endif /* _SAMC21_NVMCTRL_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_osc32kctrl_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_osc32kctrl_c21.h new file mode 100644 index 0000000..32b14b9 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_osc32kctrl_c21.h @@ -0,0 +1,1500 @@ +/** + * \file + * + * \brief SAM OSC32KCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_OSC32KCTRL_COMPONENT_ +#ifndef _HRI_OSC32KCTRL_C21_H_INCLUDED_ +#define _HRI_OSC32KCTRL_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_osc32kctrl_xosc32k_reg_t; +typedef uint32_t hri_osc32kctrl_intenset_reg_t; +typedef uint32_t hri_osc32kctrl_intflag_reg_t; +typedef uint32_t hri_osc32kctrl_osc32k_reg_t; +typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; +typedef uint32_t hri_osc32kctrl_rtcctrl_reg_t; +typedef uint32_t hri_osc32kctrl_status_reg_t; +typedef uint8_t hri_osc32kctrl_cfdctrl_reg_t; +typedef uint8_t hri_osc32kctrl_evctrl_reg_t; + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTFLAG_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_OSC32KRDY) >> OSC32KCTRL_INTFLAG_OSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_OSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTFLAG_CLKFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_CLKFAIL) >> OSC32KCTRL_INTFLAG_CLKFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_CLKFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_CLKFAIL; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_interrupt_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_OSC32KRDY) >> OSC32KCTRL_INTFLAG_OSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_OSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_interrupt_CLKFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_CLKFAIL) >> OSC32KCTRL_INTFLAG_CLKFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_CLKFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_CLKFAIL; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, + hri_osc32kctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline void hri_osc32kctrl_set_INTEN_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_OSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTEN_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_OSC32KRDY) >> OSC32KCTRL_INTENSET_OSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_OSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_OSC32KRDY; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_OSC32KRDY; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_OSC32KRDY; +} + +static inline void hri_osc32kctrl_set_INTEN_CLKFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_CLKFAIL; +} + +static inline bool hri_osc32kctrl_get_INTEN_CLKFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_CLKFAIL) >> OSC32KCTRL_INTENSET_CLKFAIL_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_CLKFAIL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_CLKFAIL; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_CLKFAIL; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_CLKFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_CLKFAIL; +} + +static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, + hri_osc32kctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTENSET.reg; +} + +static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = data; + ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_OSC32KRDY) >> OSC32KCTRL_STATUS_OSC32KRDY_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_CLKFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_CLKFAIL) >> OSC32KCTRL_STATUS_CLKFAIL_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_CLKSW_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_CLKSW) >> OSC32KCTRL_STATUS_CLKSW_Pos; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, + hri_osc32kctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->STATUS.reg; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; + tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); + ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->RTCCTRL.reg; +} + +static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; + tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; + tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN32K; + tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN1K; + tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; + tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->XOSC32K.reg; +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK; + tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const hw, + hri_osc32kctrl_cfdctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->CFDCTRL.reg; +} + +static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= ~OSC32KCTRL_EVCTRL_CFDEO; + tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos; + ((Osc32kctrl *)hw)->EVCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const hw, + hri_osc32kctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_osc32kctrl_set_OSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_ENABLE) >> OSC32KCTRL_OSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_ENABLE; + tmp |= value << OSC32KCTRL_OSC32K_ENABLE_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_EN32K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_EN32K) >> OSC32KCTRL_OSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_EN32K; + tmp |= value << OSC32KCTRL_OSC32K_EN32K_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_EN1K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_EN1K) >> OSC32KCTRL_OSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_EN1K; + tmp |= value << OSC32KCTRL_OSC32K_EN1K_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_RUNSTDBY) >> OSC32KCTRL_OSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_RUNSTDBY; + tmp |= value << OSC32KCTRL_OSC32K_RUNSTDBY_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_ONDEMAND) >> OSC32KCTRL_OSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_ONDEMAND; + tmp |= value << OSC32KCTRL_OSC32K_ONDEMAND_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_WRTLOCK) >> OSC32KCTRL_OSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_WRTLOCK; + tmp |= value << OSC32KCTRL_OSC32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_get_OSC32K_STARTUP_bf(const void *const hw, + hri_osc32kctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_STARTUP(mask)) >> OSC32KCTRL_OSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_STARTUP_Msk; + tmp |= OSC32KCTRL_OSC32K_STARTUP(data); + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_read_OSC32K_STARTUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_STARTUP_Msk) >> OSC32KCTRL_OSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_get_OSC32K_CALIB_bf(const void *const hw, + hri_osc32kctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_CALIB(mask)) >> OSC32KCTRL_OSC32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_CALIB_Msk; + tmp |= OSC32KCTRL_OSC32K_CALIB(data); + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_read_OSC32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_CALIB_Msk) >> OSC32KCTRL_OSC32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_get_OSC32K_reg(const void *const hw, + hri_osc32kctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_read_OSC32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->OSC32K.reg; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; + tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->OSCULP32K.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSC32KCTRL_C21_H_INCLUDED */ +#endif /* _SAMC21_OSC32KCTRL_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_oscctrl_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_oscctrl_c21.h new file mode 100644 index 0000000..a2fba3f --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_oscctrl_c21.h @@ -0,0 +1,2509 @@ +/** + * \file + * + * \brief SAM OSCCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_OSCCTRL_COMPONENT_ +#ifndef _HRI_OSCCTRL_C21_H_INCLUDED_ +#define _HRI_OSCCTRL_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) +#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSCCTRL_CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_oscctrl_xoscctrl_reg_t; +typedef uint32_t hri_oscctrl_cal48m_reg_t; +typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrl_dpllratio_reg_t; +typedef uint32_t hri_oscctrl_intenset_reg_t; +typedef uint32_t hri_oscctrl_intflag_reg_t; +typedef uint32_t hri_oscctrl_osc48msyncbusy_reg_t; +typedef uint32_t hri_oscctrl_status_reg_t; +typedef uint8_t hri_oscctrl_cfdpresc_reg_t; +typedef uint8_t hri_oscctrl_dpllctrla_reg_t; +typedef uint8_t hri_oscctrl_dpllpresc_reg_t; +typedef uint8_t hri_oscctrl_dpllstatus_reg_t; +typedef uint8_t hri_oscctrl_dpllsyncbusy_reg_t; +typedef uint8_t hri_oscctrl_evctrl_reg_t; +typedef uint8_t hri_oscctrl_osc48mctrl_reg_t; +typedef uint8_t hri_oscctrl_osc48mdiv_reg_t; +typedef uint8_t hri_oscctrl_osc48mstup_reg_t; + +static inline void hri_oscctrl_osc48msyncbusy_wait_for_sync(const void *const hw, hri_oscctrl_osc48msyncbusy_reg_t reg) +{ + while (((Oscctrl *)hw)->OSC48MSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrl_osc48msyncbusy_is_syncing(const void *const hw, hri_oscctrl_osc48msyncbusy_reg_t reg) +{ + return ((Oscctrl *)hw)->OSC48MSYNCBUSY.reg & reg; +} + +static inline void hri_oscctrl_dpllsyncbusy_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + while (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrl_dpllsyncbusy_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL) >> OSCCTRL_INTFLAG_XOSCFAIL_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL; +} + +static inline bool hri_oscctrl_get_INTFLAG_OSC48MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC48MRDY) >> OSCCTRL_INTFLAG_OSC48MRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_OSC48MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC48MRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCFAIL_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL) >> OSCCTRL_INTFLAG_XOSCFAIL_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCFAIL_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL; +} + +static inline bool hri_oscctrl_get_interrupt_OSC48MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC48MRDY) >> OSCCTRL_INTFLAG_OSC48MRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_OSC48MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC48MRDY; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, + hri_oscctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) +{ + ((Oscctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY) >> OSCCTRL_INTENSET_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; +} + +static inline void hri_oscctrl_set_INTEN_XOSCFAIL_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCFAIL_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL) >> OSCCTRL_INTENSET_XOSCFAIL_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCFAIL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCFAIL_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL; +} + +static inline void hri_oscctrl_set_INTEN_OSC48MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC48MRDY; +} + +static inline bool hri_oscctrl_get_INTEN_OSC48MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_OSC48MRDY) >> OSCCTRL_INTENSET_OSC48MRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_OSC48MRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC48MRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC48MRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_OSC48MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC48MRDY; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKR) >> OSCCTRL_INTENSET_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKF) >> OSCCTRL_INTENSET_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLTO) >> OSCCTRL_INTENSET_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLDRTO) >> OSCCTRL_INTENSET_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO; +} + +static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, + hri_oscctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTENSET.reg; +} + +static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) +{ + ((Oscctrl *)hw)->INTENSET.reg = data; + ((Oscctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY) >> OSCCTRL_STATUS_XOSCRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCFAIL_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL) >> OSCCTRL_STATUS_XOSCFAIL_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCCKSW_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW) >> OSCCTRL_STATUS_XOSCCKSW_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_OSC48MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_OSC48MRDY) >> OSCCTRL_STATUS_OSC48MRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKR) >> OSCCTRL_STATUS_DPLLLCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKF) >> OSCCTRL_STATUS_DPLLLCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLTO) >> OSCCTRL_STATUS_DPLLTO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLDRTO) >> OSCCTRL_STATUS_DPLLLDRTO_Pos; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->STATUS.reg; +} + +static inline bool hri_oscctrl_get_OSC48MSYNCBUSY_OSC48MDIV_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->OSC48MSYNCBUSY.reg & OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV) + >> OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV_Pos; +} + +static inline hri_oscctrl_osc48msyncbusy_reg_t hri_oscctrl_get_OSC48MSYNCBUSY_reg(const void *const hw, + hri_oscctrl_osc48msyncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_osc48msyncbusy_reg_t hri_oscctrl_read_OSC48MSYNCBUSY_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->OSC48MSYNCBUSY.reg; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLPRESC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLPRESC) >> OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, + hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLSTATUS.reg; +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; + tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; + tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_CFDEN; + tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_SWBEN; + tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_AMPGC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_AMPGC) >> OSCCTRL_XOSCCTRL_AMPGC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_AMPGC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_AMPGC; + tmp |= value << OSCCTRL_XOSCCTRL_AMPGC_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_AMPGC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_AMPGC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_GAIN(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_GAIN_bf(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN(mask)) >> OSCCTRL_XOSCCTRL_GAIN_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_GAIN_Msk; + tmp |= OSCCTRL_XOSCCTRL_GAIN(data); + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_GAIN(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_GAIN(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_GAIN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN_Msk) >> OSCCTRL_XOSCCTRL_GAIN_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; + tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->XOSCCTRL.reg; +} + +static inline void hri_oscctrl_set_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg |= OSCCTRL_CFDPRESC_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_get_CFDPRESC_CFDPRESC_bf(const void *const hw, + hri_oscctrl_cfdpresc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->CFDPRESC.reg; + tmp = (tmp & OSCCTRL_CFDPRESC_CFDPRESC(mask)) >> OSCCTRL_CFDPRESC_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->CFDPRESC.reg; + tmp &= ~OSCCTRL_CFDPRESC_CFDPRESC_Msk; + tmp |= OSCCTRL_CFDPRESC_CFDPRESC(data); + ((Oscctrl *)hw)->CFDPRESC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg &= ~OSCCTRL_CFDPRESC_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg ^= OSCCTRL_CFDPRESC_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_read_CFDPRESC_CFDPRESC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->CFDPRESC.reg; + tmp = (tmp & OSCCTRL_CFDPRESC_CFDPRESC_Msk) >> OSCCTRL_CFDPRESC_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_get_CFDPRESC_reg(const void *const hw, + hri_oscctrl_cfdpresc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->CFDPRESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_read_CFDPRESC_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->CFDPRESC.reg; +} + +static inline void hri_oscctrl_set_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_EVCTRL_CFDEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSCCTRL_EVCTRL_CFDEO) >> OSCCTRL_EVCTRL_CFDEO_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= ~OSCCTRL_EVCTRL_CFDEO; + tmp |= value << OSCCTRL_EVCTRL_CFDEO_Pos; + ((Oscctrl *)hw)->EVCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_oscctrl_set_OSC48MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg |= OSCCTRL_OSC48MCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC48MCTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC48MCTRL_ENABLE) >> OSCCTRL_OSC48MCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC48MCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC48MCTRL.reg; + tmp &= ~OSCCTRL_OSC48MCTRL_ENABLE; + tmp |= value << OSCCTRL_OSC48MCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->OSC48MCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg &= ~OSCCTRL_OSC48MCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg ^= OSCCTRL_OSC48MCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC48MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg |= OSCCTRL_OSC48MCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC48MCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC48MCTRL_RUNSTDBY) >> OSCCTRL_OSC48MCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC48MCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC48MCTRL.reg; + tmp &= ~OSCCTRL_OSC48MCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_OSC48MCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->OSC48MCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg &= ~OSCCTRL_OSC48MCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg ^= OSCCTRL_OSC48MCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC48MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg |= OSCCTRL_OSC48MCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC48MCTRL_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC48MCTRL_ONDEMAND) >> OSCCTRL_OSC48MCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC48MCTRL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC48MCTRL.reg; + tmp &= ~OSCCTRL_OSC48MCTRL_ONDEMAND; + tmp |= value << OSCCTRL_OSC48MCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->OSC48MCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg &= ~OSCCTRL_OSC48MCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg ^= OSCCTRL_OSC48MCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC48MCTRL_reg(const void *const hw, hri_oscctrl_osc48mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mctrl_reg_t hri_oscctrl_get_OSC48MCTRL_reg(const void *const hw, + hri_oscctrl_osc48mctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_OSC48MCTRL_reg(const void *const hw, hri_oscctrl_osc48mctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MCTRL_reg(const void *const hw, hri_oscctrl_osc48mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MCTRL_reg(const void *const hw, hri_oscctrl_osc48mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mctrl_reg_t hri_oscctrl_read_OSC48MCTRL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->OSC48MCTRL.reg; +} + +static inline void hri_oscctrl_set_OSC48MDIV_DIV_bf(const void *const hw, hri_oscctrl_osc48mdiv_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MDIV.reg |= OSCCTRL_OSC48MDIV_DIV(mask); + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mdiv_reg_t hri_oscctrl_get_OSC48MDIV_DIV_bf(const void *const hw, + hri_oscctrl_osc48mdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MDIV.reg; + tmp = (tmp & OSCCTRL_OSC48MDIV_DIV(mask)) >> OSCCTRL_OSC48MDIV_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_OSC48MDIV_DIV_bf(const void *const hw, hri_oscctrl_osc48mdiv_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC48MDIV.reg; + tmp &= ~OSCCTRL_OSC48MDIV_DIV_Msk; + tmp |= OSCCTRL_OSC48MDIV_DIV(data); + ((Oscctrl *)hw)->OSC48MDIV.reg = tmp; + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MDIV_DIV_bf(const void *const hw, hri_oscctrl_osc48mdiv_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MDIV.reg &= ~OSCCTRL_OSC48MDIV_DIV(mask); + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MDIV_DIV_bf(const void *const hw, hri_oscctrl_osc48mdiv_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MDIV.reg ^= OSCCTRL_OSC48MDIV_DIV(mask); + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mdiv_reg_t hri_oscctrl_read_OSC48MDIV_DIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MDIV.reg; + tmp = (tmp & OSCCTRL_OSC48MDIV_DIV_Msk) >> OSCCTRL_OSC48MDIV_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_OSC48MDIV_reg(const void *const hw, hri_oscctrl_osc48mdiv_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MDIV.reg |= mask; + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mdiv_reg_t hri_oscctrl_get_OSC48MDIV_reg(const void *const hw, + hri_oscctrl_osc48mdiv_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->OSC48MDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_OSC48MDIV_reg(const void *const hw, hri_oscctrl_osc48mdiv_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MDIV.reg = data; + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MDIV_reg(const void *const hw, hri_oscctrl_osc48mdiv_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MDIV.reg &= ~mask; + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MDIV_reg(const void *const hw, hri_oscctrl_osc48mdiv_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MDIV.reg ^= mask; + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mdiv_reg_t hri_oscctrl_read_OSC48MDIV_reg(const void *const hw) +{ + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + return ((Oscctrl *)hw)->OSC48MDIV.reg; +} + +static inline void hri_oscctrl_set_OSC48MSTUP_STARTUP_bf(const void *const hw, hri_oscctrl_osc48mstup_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MSTUP.reg |= OSCCTRL_OSC48MSTUP_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mstup_reg_t hri_oscctrl_get_OSC48MSTUP_STARTUP_bf(const void *const hw, + hri_oscctrl_osc48mstup_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MSTUP.reg; + tmp = (tmp & OSCCTRL_OSC48MSTUP_STARTUP(mask)) >> OSCCTRL_OSC48MSTUP_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_OSC48MSTUP_STARTUP_bf(const void *const hw, hri_oscctrl_osc48mstup_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC48MSTUP.reg; + tmp &= ~OSCCTRL_OSC48MSTUP_STARTUP_Msk; + tmp |= OSCCTRL_OSC48MSTUP_STARTUP(data); + ((Oscctrl *)hw)->OSC48MSTUP.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MSTUP_STARTUP_bf(const void *const hw, hri_oscctrl_osc48mstup_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MSTUP.reg &= ~OSCCTRL_OSC48MSTUP_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MSTUP_STARTUP_bf(const void *const hw, hri_oscctrl_osc48mstup_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MSTUP.reg ^= OSCCTRL_OSC48MSTUP_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mstup_reg_t hri_oscctrl_read_OSC48MSTUP_STARTUP_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MSTUP.reg; + tmp = (tmp & OSCCTRL_OSC48MSTUP_STARTUP_Msk) >> OSCCTRL_OSC48MSTUP_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_OSC48MSTUP_reg(const void *const hw, hri_oscctrl_osc48mstup_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MSTUP.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mstup_reg_t hri_oscctrl_get_OSC48MSTUP_reg(const void *const hw, + hri_oscctrl_osc48mstup_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MSTUP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_OSC48MSTUP_reg(const void *const hw, hri_oscctrl_osc48mstup_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MSTUP.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MSTUP_reg(const void *const hw, hri_oscctrl_osc48mstup_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MSTUP.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MSTUP_reg(const void *const hw, hri_oscctrl_osc48mstup_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MSTUP.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mstup_reg_t hri_oscctrl_read_OSC48MSTUP_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->OSC48MSTUP.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg = data; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw) +{ + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->DPLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((Oscctrl *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((Oscctrl *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg = data; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw) +{ + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((Oscctrl *)hw)->DPLLRATIO.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LPEN) >> OSCCTRL_DPLLCTRLB_LPEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LPEN; + tmp |= value << OSCCTRL_DPLLCTRLB_LPEN_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLCTRLB.reg; +} + +static inline void hri_oscctrl_set_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg |= OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_PRESC_bf(const void *const hw, + hri_oscctrl_dpllpresc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC(mask)) >> OSCCTRL_DPLLPRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp &= ~OSCCTRL_DPLLPRESC_PRESC_Msk; + tmp |= OSCCTRL_DPLLPRESC_PRESC(data); + ((Oscctrl *)hw)->DPLLPRESC.reg = tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg &= ~OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg ^= OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_PRESC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC_Msk) >> OSCCTRL_DPLLPRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg |= mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_reg(const void *const hw, + hri_oscctrl_dpllpresc_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg = data; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg &= ~mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg ^= mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_reg(const void *const hw) +{ + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((Oscctrl *)hw)->DPLLPRESC.reg; +} + +static inline void hri_oscctrl_set_CAL48M_FCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg |= OSCCTRL_CAL48M_FCAL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_get_CAL48M_FCAL_bf(const void *const hw, + hri_oscctrl_cal48m_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp = (tmp & OSCCTRL_CAL48M_FCAL(mask)) >> OSCCTRL_CAL48M_FCAL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_CAL48M_FCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp &= ~OSCCTRL_CAL48M_FCAL_Msk; + tmp |= OSCCTRL_CAL48M_FCAL(data); + ((Oscctrl *)hw)->CAL48M.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_CAL48M_FCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg &= ~OSCCTRL_CAL48M_FCAL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_CAL48M_FCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg ^= OSCCTRL_CAL48M_FCAL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_read_CAL48M_FCAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp = (tmp & OSCCTRL_CAL48M_FCAL_Msk) >> OSCCTRL_CAL48M_FCAL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_CAL48M_FRANGE_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg |= OSCCTRL_CAL48M_FRANGE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_get_CAL48M_FRANGE_bf(const void *const hw, + hri_oscctrl_cal48m_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp = (tmp & OSCCTRL_CAL48M_FRANGE(mask)) >> OSCCTRL_CAL48M_FRANGE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_CAL48M_FRANGE_bf(const void *const hw, hri_oscctrl_cal48m_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp &= ~OSCCTRL_CAL48M_FRANGE_Msk; + tmp |= OSCCTRL_CAL48M_FRANGE(data); + ((Oscctrl *)hw)->CAL48M.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_CAL48M_FRANGE_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg &= ~OSCCTRL_CAL48M_FRANGE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_CAL48M_FRANGE_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg ^= OSCCTRL_CAL48M_FRANGE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_read_CAL48M_FRANGE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp = (tmp & OSCCTRL_CAL48M_FRANGE_Msk) >> OSCCTRL_CAL48M_FRANGE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_CAL48M_TCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg |= OSCCTRL_CAL48M_TCAL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_get_CAL48M_TCAL_bf(const void *const hw, + hri_oscctrl_cal48m_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp = (tmp & OSCCTRL_CAL48M_TCAL(mask)) >> OSCCTRL_CAL48M_TCAL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_CAL48M_TCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp &= ~OSCCTRL_CAL48M_TCAL_Msk; + tmp |= OSCCTRL_CAL48M_TCAL(data); + ((Oscctrl *)hw)->CAL48M.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_CAL48M_TCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg &= ~OSCCTRL_CAL48M_TCAL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_CAL48M_TCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg ^= OSCCTRL_CAL48M_TCAL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_read_CAL48M_TCAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp = (tmp & OSCCTRL_CAL48M_TCAL_Msk) >> OSCCTRL_CAL48M_TCAL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_CAL48M_reg(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_get_CAL48M_reg(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_CAL48M_reg(const void *const hw, hri_oscctrl_cal48m_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_CAL48M_reg(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_CAL48M_reg(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_read_CAL48M_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->CAL48M.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSCCTRL_C21_H_INCLUDED */ +#endif /* _SAMC21_OSCCTRL_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_pac_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_pac_c21.h new file mode 100644 index 0000000..8072936 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_pac_c21.h @@ -0,0 +1,1176 @@ +/** + * \file + * + * \brief SAM PAC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_PAC_COMPONENT_ +#ifndef _HRI_PAC_C21_H_INCLUDED_ +#define _HRI_PAC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PAC_CRITICAL_SECTIONS) +#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PAC_CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pac_intflaga_reg_t; +typedef uint32_t hri_pac_intflagahb_reg_t; +typedef uint32_t hri_pac_intflagb_reg_t; +typedef uint32_t hri_pac_intflagc_reg_t; +typedef uint32_t hri_pac_statusa_reg_t; +typedef uint32_t hri_pac_statusb_reg_t; +typedef uint32_t hri_pac_statusc_reg_t; +typedef uint32_t hri_pac_wrctrl_reg_t; +typedef uint8_t hri_pac_evctrl_reg_t; +typedef uint8_t hri_pac_intenset_reg_t; + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; +} + +static inline bool hri_pac_get_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMCM0P) >> PAC_INTFLAGAHB_HSRAMCM0P_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMCM0P; +} + +static inline bool hri_pac_get_INTFLAGAHB_HSRAMDSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMDSU) >> PAC_INTFLAGAHB_HSRAMDSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HSRAMDSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMDSU; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; +} + +static inline bool hri_pac_get_INTFLAGAHB_LPRAMDMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_LPRAMDMAC) >> PAC_INTFLAGAHB_LPRAMDMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_LPRAMDMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_LPRAMDMAC; +} + +static inline bool hri_pac_get_INTFLAGAHB_DIVAS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_DIVAS) >> PAC_INTFLAGAHB_DIVAS_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_DIVAS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_DIVAS; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGAHB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGAHB.reg; +} + +static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGAHB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC; +} + +static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; +} + +static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; +} + +static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; +} + +static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; +} + +static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; +} + +static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; +} + +static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; +} + +static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; +} + +static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM; +} + +static inline bool hri_pac_get_INTFLAGA_TSENS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TSENS) >> PAC_INTFLAGA_TSENS_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_TSENS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TSENS; +} + +static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGA.reg; +} + +static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + ((Pac *)hw)->INTFLAGA.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT; +} + +static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; +} + +static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; +} + +static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC; +} + +static inline bool hri_pac_get_INTFLAGB_MTB_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_MTB) >> PAC_INTFLAGB_MTB_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_MTB_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_MTB; +} + +static inline bool hri_pac_get_INTFLAGB_HMATRIXHS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_HMATRIXHS) >> PAC_INTFLAGB_HMATRIXHS_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_HMATRIXHS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_HMATRIXHS; +} + +static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGB.reg; +} + +static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGC_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_EVSYS) >> PAC_INTFLAGC_EVSYS_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_EVSYS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_EVSYS; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM0) >> PAC_INTFLAGC_SERCOM0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM0; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM1) >> PAC_INTFLAGC_SERCOM1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM1; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM2) >> PAC_INTFLAGC_SERCOM2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM2; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM3) >> PAC_INTFLAGC_SERCOM3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM3; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM4) >> PAC_INTFLAGC_SERCOM4_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM4; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM5) >> PAC_INTFLAGC_SERCOM5_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM5; +} + +static inline bool hri_pac_get_INTFLAGC_CAN0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN0) >> PAC_INTFLAGC_CAN0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CAN0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN0; +} + +static inline bool hri_pac_get_INTFLAGC_CAN1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN1) >> PAC_INTFLAGC_CAN1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CAN1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN1; +} + +static inline bool hri_pac_get_INTFLAGC_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC0) >> PAC_INTFLAGC_TCC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC0; +} + +static inline bool hri_pac_get_INTFLAGC_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC1) >> PAC_INTFLAGC_TCC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC1; +} + +static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2; +} + +static inline bool hri_pac_get_INTFLAGC_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC0) >> PAC_INTFLAGC_TC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC0; +} + +static inline bool hri_pac_get_INTFLAGC_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC1) >> PAC_INTFLAGC_TC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC1; +} + +static inline bool hri_pac_get_INTFLAGC_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC2) >> PAC_INTFLAGC_TC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC2; +} + +static inline bool hri_pac_get_INTFLAGC_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC3) >> PAC_INTFLAGC_TC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC3; +} + +static inline bool hri_pac_get_INTFLAGC_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC4) >> PAC_INTFLAGC_TC4_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC4; +} + +static inline bool hri_pac_get_INTFLAGC_ADC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ADC0) >> PAC_INTFLAGC_ADC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_ADC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ADC0; +} + +static inline bool hri_pac_get_INTFLAGC_ADC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ADC1) >> PAC_INTFLAGC_ADC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_ADC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ADC1; +} + +static inline bool hri_pac_get_INTFLAGC_SDADC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SDADC) >> PAC_INTFLAGC_SDADC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SDADC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SDADC; +} + +static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC; +} + +static inline bool hri_pac_get_INTFLAGC_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_DAC) >> PAC_INTFLAGC_DAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_DAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_DAC; +} + +static inline bool hri_pac_get_INTFLAGC_PTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PTC) >> PAC_INTFLAGC_PTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_PTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PTC; +} + +static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL; +} + +static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGC.reg; +} + +static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + ((Pac *)hw)->INTFLAGC.reg = mask; +} + +static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; +} + +static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; +} + +static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; + } else { + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; + } +} + +static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; +} + +static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENSET.reg = mask; +} + +static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) +{ + return ((Pac *)hw)->INTENSET.reg; +} + +static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) +{ + ((Pac *)hw)->INTENSET.reg = data; + ((Pac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos; +} + +static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; +} + +static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; +} + +static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; +} + +static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; +} + +static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos; +} + +static inline bool hri_pac_get_STATUSA_TSENS_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TSENS) >> PAC_STATUSA_TSENS_Pos; +} + +static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSA.reg; +} + +static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos; +} + +static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; +} + +static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos; +} + +static inline bool hri_pac_get_STATUSB_MTB_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_MTB) >> PAC_STATUSB_MTB_Pos; +} + +static inline bool hri_pac_get_STATUSB_HMATRIXHS_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_HMATRIXHS) >> PAC_STATUSB_HMATRIXHS_Pos; +} + +static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSB.reg; +} + +static inline bool hri_pac_get_STATUSC_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_EVSYS) >> PAC_STATUSC_EVSYS_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM0) >> PAC_STATUSC_SERCOM0_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM1) >> PAC_STATUSC_SERCOM1_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM2) >> PAC_STATUSC_SERCOM2_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM3) >> PAC_STATUSC_SERCOM3_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM4) >> PAC_STATUSC_SERCOM4_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM5) >> PAC_STATUSC_SERCOM5_Pos; +} + +static inline bool hri_pac_get_STATUSC_CAN0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN0) >> PAC_STATUSC_CAN0_Pos; +} + +static inline bool hri_pac_get_STATUSC_CAN1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN1) >> PAC_STATUSC_CAN1_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC0) >> PAC_STATUSC_TCC0_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC1) >> PAC_STATUSC_TCC1_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC0) >> PAC_STATUSC_TC0_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC1) >> PAC_STATUSC_TC1_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC2) >> PAC_STATUSC_TC2_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC3) >> PAC_STATUSC_TC3_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC4) >> PAC_STATUSC_TC4_Pos; +} + +static inline bool hri_pac_get_STATUSC_ADC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ADC0) >> PAC_STATUSC_ADC0_Pos; +} + +static inline bool hri_pac_get_STATUSC_ADC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ADC1) >> PAC_STATUSC_ADC1_Pos; +} + +static inline bool hri_pac_get_STATUSC_SDADC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SDADC) >> PAC_STATUSC_SDADC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos; +} + +static inline bool hri_pac_get_STATUSC_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_DAC) >> PAC_STATUSC_DAC_Pos; +} + +static inline bool hri_pac_get_STATUSC_PTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PTC) >> PAC_STATUSC_PTC_Pos; +} + +static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos; +} + +static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSC.reg; +} + +static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_PERID_Msk; + tmp |= PAC_WRCTRL_PERID(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_KEY_Msk; + tmp |= PAC_WRCTRL_KEY(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->WRCTRL.reg; +} + +static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= ~PAC_EVCTRL_ERREO; + tmp |= value << PAC_EVCTRL_ERREO_Pos; + ((Pac *)hw)->EVCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PAC_C21_H_INCLUDED */ +#endif /* _SAMC21_PAC_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_pm_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_pm_c21.h new file mode 100644 index 0000000..f4a2675 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_pm_c21.h @@ -0,0 +1,279 @@ +/** + * \file + * + * \brief SAM PM + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_PM_COMPONENT_ +#ifndef _HRI_PM_C21_H_INCLUDED_ +#define _HRI_PM_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PM_CRITICAL_SECTIONS) +#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PM_CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_pm_stdbycfg_reg_t; +typedef uint8_t hri_pm_sleepcfg_reg_t; + +static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; + tmp |= PM_SLEEPCFG_SLEEPMODE(data); + ((Pm *)hw)->SLEEPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->SLEEPCFG.reg; +} + +static inline void hri_pm_set_STDBYCFG_BBIASHS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASHS_Msk; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_STDBYCFG_BBIASHS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASHS_Msk) >> PM_STDBYCFG_BBIASHS_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_STDBYCFG_BBIASHS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_BBIASHS_Msk; + tmp |= value << PM_STDBYCFG_BBIASHS_Pos; + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_BBIASHS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASHS_Msk; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_BBIASHS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASHS_Msk; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_VREGSMOD(mask)) >> PM_STDBYCFG_VREGSMOD_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_VREGSMOD_Msk; + tmp |= PM_STDBYCFG_VREGSMOD(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_VREGSMOD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_VREGSMOD_Msk) >> PM_STDBYCFG_VREGSMOD_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->STDBYCFG.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PM_C21_H_INCLUDED */ +#endif /* _SAMC21_PM_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_port_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_port_c21.h new file mode 100644 index 0000000..76845a2 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_port_c21.h @@ -0,0 +1,2357 @@ +/** + * \file + * + * \brief SAM PORT + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_PORT_COMPONENT_ +#ifndef _HRI_PORT_C21_H_INCLUDED_ +#define _HRI_PORT_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PORT_CRITICAL_SECTIONS) +#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PORT_CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_port_ctrl_reg_t; +typedef uint32_t hri_port_dir_reg_t; +typedef uint32_t hri_port_evctrl_reg_t; +typedef uint32_t hri_port_in_reg_t; +typedef uint32_t hri_port_out_reg_t; +typedef uint32_t hri_port_wrconfig_reg_t; +typedef uint32_t hri_portgroup_ctrl_reg_t; +typedef uint32_t hri_portgroup_dir_reg_t; +typedef uint32_t hri_portgroup_evctrl_reg_t; +typedef uint32_t hri_portgroup_in_reg_t; +typedef uint32_t hri_portgroup_out_reg_t; +typedef uint32_t hri_portgroup_wrconfig_reg_t; +typedef uint8_t hri_port_pincfg_reg_t; +typedef uint8_t hri_port_pmux_reg_t; +typedef uint8_t hri_portgroup_pincfg_reg_t; +typedef uint8_t hri_portgroup_pmux_reg_t; + +static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) +{ + return ((PortGroup *)hw)->DIR.reg; +} + +static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = data; + ((PortGroup *)hw)->DIRCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = mask; +} + +static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) +{ + return ((PortGroup *)hw)->OUT.reg; +} + +static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = data; + ((PortGroup *)hw)->OUTCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) +{ + return ((PortGroup *)hw)->IN.reg; +} + +static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((PortGroup *)hw)->CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->CTRL.reg; +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->EVCTRL.reg; +} + +static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PMUX[index].reg; +} + +static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PINCFG[index].reg; +} + +static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].DIR.reg; +} + +static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; +} + +static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; +} + +static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; +} + +static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].OUT.reg; +} + +static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; +} + +static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; +} + +static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].IN.reg; +} + +static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].CTRL.reg; +} + +static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].EVCTRL.reg; +} + +static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; +} + +static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; +} + +static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, + hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PORT_C21_H_INCLUDED */ +#endif /* _SAMC21_PORT_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_rstc_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_rstc_c21.h new file mode 100644 index 0000000..e72770b --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_rstc_c21.h @@ -0,0 +1,103 @@ +/** + * \file + * + * \brief SAM RSTC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_RSTC_COMPONENT_ +#ifndef _HRI_RSTC_C21_H_INCLUDED_ +#define _HRI_RSTC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) +#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RSTC_CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint8_t hri_rstc_rcause_reg_t; + +static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->RCAUSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw) +{ + return ((Rstc *)hw)->RCAUSE.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RSTC_C21_H_INCLUDED */ +#endif /* _SAMC21_RSTC_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_rtc_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_rtc_c21.h new file mode 100644 index 0000000..950968c --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_rtc_c21.h @@ -0,0 +1,6175 @@ +/** + * \file + * + * \brief SAM RTC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_RTC_COMPONENT_ +#ifndef _HRI_RTC_C21_H_INCLUDED_ +#define _HRI_RTC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RTC_CRITICAL_SECTIONS) +#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RTC_CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_rtcmode0_ctrla_reg_t; +typedef uint16_t hri_rtcmode0_intenset_reg_t; +typedef uint16_t hri_rtcmode0_intflag_reg_t; +typedef uint16_t hri_rtcmode1_comp_reg_t; +typedef uint16_t hri_rtcmode1_count_reg_t; +typedef uint16_t hri_rtcmode1_ctrla_reg_t; +typedef uint16_t hri_rtcmode1_intenset_reg_t; +typedef uint16_t hri_rtcmode1_intflag_reg_t; +typedef uint16_t hri_rtcmode1_per_reg_t; +typedef uint16_t hri_rtcmode2_ctrla_reg_t; +typedef uint16_t hri_rtcmode2_intenset_reg_t; +typedef uint16_t hri_rtcmode2_intflag_reg_t; +typedef uint32_t hri_rtcalarm_alarm_reg_t; +typedef uint32_t hri_rtcmode0_comp_reg_t; +typedef uint32_t hri_rtcmode0_count_reg_t; +typedef uint32_t hri_rtcmode0_evctrl_reg_t; +typedef uint32_t hri_rtcmode0_syncbusy_reg_t; +typedef uint32_t hri_rtcmode1_evctrl_reg_t; +typedef uint32_t hri_rtcmode1_syncbusy_reg_t; +typedef uint32_t hri_rtcmode2_alarm_reg_t; +typedef uint32_t hri_rtcmode2_clock_reg_t; +typedef uint32_t hri_rtcmode2_evctrl_reg_t; +typedef uint32_t hri_rtcmode2_syncbusy_reg_t; +typedef uint8_t hri_rtc_dbgctrl_reg_t; +typedef uint8_t hri_rtc_freqcorr_reg_t; +typedef uint8_t hri_rtcalarm_mask_reg_t; +typedef uint8_t hri_rtcmode2_mask_reg_t; + +static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; +} + +static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, + hri_rtcmode0_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTFLAG.reg; +} + +static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, + hri_rtcmode1_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTFLAG.reg; +} + +static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, + hri_rtcmode2_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTFLAG.reg; +} + +static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; + } +} + +static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = mask; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, + hri_rtcmode0_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTENSET.reg; +} + +static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = data; + ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; + } +} + +static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = mask; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, + hri_rtcmode1_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTENSET.reg; +} + +static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = data; + ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; + } +} + +static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = mask; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, + hri_rtcmode2_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTENSET.reg; +} + +static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = data; + ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode0_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode1_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode2_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; +} + +static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_ENABLE; + tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; + tmp |= RTC_MODE0_CTRLA_MODE(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE0_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE0.CTRLA.reg; +} + +static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_ENABLE; + tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; + tmp |= RTC_MODE1_CTRLA_MODE(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE1_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE1.CTRLA.reg; +} + +static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_ENABLE; + tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLKREP; + tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; + tmp |= RTC_MODE2_CTRLA_MODE(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE2_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + return ((Rtc *)hw)->MODE2.CTRLA.reg; +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO0; + tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO1; + tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO2; + tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO3; + tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO4; + tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO5; + tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO6; + tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO7; + tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_OVFEO; + tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, + hri_rtcmode0_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.EVCTRL.reg; +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO0; + tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO1; + tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO2; + tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO3; + tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO4; + tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO5; + tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO6; + tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO7; + tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_OVFEO; + tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, + hri_rtcmode1_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.EVCTRL.reg; +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO0; + tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO1; + tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO2; + tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO3; + tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO4; + tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO5; + tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO6; + tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO7; + tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_OVFEO; + tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, + hri_rtcmode2_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.EVCTRL.reg; +} + +static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.DBGCTRL.reg; +} + +static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + return ((Rtc *)hw)->MODE0.FREQCORR.reg; +} + +static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; + tmp |= RTC_MODE0_COUNT_COUNT(data); + ((Rtc *)hw)->MODE0.COUNT.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE0.COUNT.reg; +} + +static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; + tmp |= RTC_MODE1_COUNT_COUNT(data); + ((Rtc *)hw)->MODE1.COUNT.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE1.COUNT.reg; +} + +static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; + tmp |= RTC_MODE2_CLOCK_SECOND(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; + tmp |= RTC_MODE2_CLOCK_MINUTE(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; + tmp |= RTC_MODE2_CLOCK_HOUR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; + tmp |= RTC_MODE2_CLOCK_DAY(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; + tmp |= RTC_MODE2_CLOCK_MONTH(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; + tmp |= RTC_MODE2_CLOCK_YEAR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return ((Rtc *)hw)->MODE2.CLOCK.reg; +} + +static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= ~RTC_MODE1_PER_PER_Msk; + tmp |= RTC_MODE1_PER_PER(data); + ((Rtc *)hw)->MODE1.PER.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + return ((Rtc *)hw)->MODE1.PER.reg; +} + +static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= ~RTC_MODE0_COMP_COMP_Msk; + tmp |= RTC_MODE0_COMP_COMP(data); + ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + return ((Rtc *)hw)->MODE0.COMP[index].reg; +} + +static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= ~RTC_MODE1_COMP_COMP_Msk; + tmp |= RTC_MODE1_COMP_COMP(data); + ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + return ((Rtc *)hw)->MODE1.COMP[index].reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode2_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode2_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode2_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode2_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode2_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode2_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode2_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode2_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode2_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode2_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode2_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode2_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode2_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode0_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode0_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode0_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode0_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode0_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode0_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode0_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode0_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode0_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode0_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode0_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode0_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode0_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode1_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode1_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode1_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode1_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode1_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode1_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode1_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode1_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode1_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode1_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode1_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode1_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode1_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RTC_C21_H_INCLUDED */ +#endif /* _SAMC21_RTC_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_sdadc_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_sdadc_c21.h new file mode 100644 index 0000000..286e911 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_sdadc_c21.h @@ -0,0 +1,2543 @@ +/** + * \file + * + * \brief SAM SDADC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_SDADC_COMPONENT_ +#ifndef _HRI_SDADC_C21_H_INCLUDED_ +#define _HRI_SDADC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SDADC_CRITICAL_SECTIONS) +#define SDADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SDADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SDADC_CRITICAL_SECTION_ENTER() +#define SDADC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sdadc_ctrlb_reg_t; +typedef uint16_t hri_sdadc_gaincorr_reg_t; +typedef uint32_t hri_sdadc_offsetcorr_reg_t; +typedef uint32_t hri_sdadc_result_reg_t; +typedef uint32_t hri_sdadc_syncbusy_reg_t; +typedef uint32_t hri_sdadc_winlt_reg_t; +typedef uint32_t hri_sdadc_winut_reg_t; +typedef uint8_t hri_sdadc_anactrl_reg_t; +typedef uint8_t hri_sdadc_ctrla_reg_t; +typedef uint8_t hri_sdadc_ctrlc_reg_t; +typedef uint8_t hri_sdadc_dbgctrl_reg_t; +typedef uint8_t hri_sdadc_evctrl_reg_t; +typedef uint8_t hri_sdadc_inputctrl_reg_t; +typedef uint8_t hri_sdadc_intenset_reg_t; +typedef uint8_t hri_sdadc_intflag_reg_t; +typedef uint8_t hri_sdadc_refctrl_reg_t; +typedef uint8_t hri_sdadc_seqctrl_reg_t; +typedef uint8_t hri_sdadc_seqstatus_reg_t; +typedef uint8_t hri_sdadc_shiftcorr_reg_t; +typedef uint8_t hri_sdadc_swtrig_reg_t; +typedef uint8_t hri_sdadc_winctrl_reg_t; + +static inline void hri_sdadc_wait_for_sync(const void *const hw, hri_sdadc_syncbusy_reg_t reg) +{ + while (((Sdadc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sdadc_is_syncing(const void *const hw, hri_sdadc_syncbusy_reg_t reg) +{ + return ((Sdadc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_sdadc_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTFLAG.reg & SDADC_INTFLAG_RESRDY) >> SDADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_sdadc_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTFLAG.reg = SDADC_INTFLAG_RESRDY; +} + +static inline bool hri_sdadc_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTFLAG.reg & SDADC_INTFLAG_OVERRUN) >> SDADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_sdadc_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTFLAG.reg = SDADC_INTFLAG_OVERRUN; +} + +static inline bool hri_sdadc_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTFLAG.reg & SDADC_INTFLAG_WINMON) >> SDADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_sdadc_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTFLAG.reg = SDADC_INTFLAG_WINMON; +} + +static inline bool hri_sdadc_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTFLAG.reg & SDADC_INTFLAG_RESRDY) >> SDADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_sdadc_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTFLAG.reg = SDADC_INTFLAG_RESRDY; +} + +static inline bool hri_sdadc_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTFLAG.reg & SDADC_INTFLAG_OVERRUN) >> SDADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_sdadc_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTFLAG.reg = SDADC_INTFLAG_OVERRUN; +} + +static inline bool hri_sdadc_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTFLAG.reg & SDADC_INTFLAG_WINMON) >> SDADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_sdadc_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTFLAG.reg = SDADC_INTFLAG_WINMON; +} + +static inline hri_sdadc_intflag_reg_t hri_sdadc_get_INTFLAG_reg(const void *const hw, hri_sdadc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdadc_intflag_reg_t hri_sdadc_read_INTFLAG_reg(const void *const hw) +{ + return ((Sdadc *)hw)->INTFLAG.reg; +} + +static inline void hri_sdadc_clear_INTFLAG_reg(const void *const hw, hri_sdadc_intflag_reg_t mask) +{ + ((Sdadc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_sdadc_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTENSET.reg = SDADC_INTENSET_RESRDY; +} + +static inline bool hri_sdadc_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTENSET.reg & SDADC_INTENSET_RESRDY) >> SDADC_INTENSET_RESRDY_Pos; +} + +static inline void hri_sdadc_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sdadc *)hw)->INTENCLR.reg = SDADC_INTENSET_RESRDY; + } else { + ((Sdadc *)hw)->INTENSET.reg = SDADC_INTENSET_RESRDY; + } +} + +static inline void hri_sdadc_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTENCLR.reg = SDADC_INTENSET_RESRDY; +} + +static inline void hri_sdadc_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTENSET.reg = SDADC_INTENSET_OVERRUN; +} + +static inline bool hri_sdadc_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTENSET.reg & SDADC_INTENSET_OVERRUN) >> SDADC_INTENSET_OVERRUN_Pos; +} + +static inline void hri_sdadc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sdadc *)hw)->INTENCLR.reg = SDADC_INTENSET_OVERRUN; + } else { + ((Sdadc *)hw)->INTENSET.reg = SDADC_INTENSET_OVERRUN; + } +} + +static inline void hri_sdadc_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTENCLR.reg = SDADC_INTENSET_OVERRUN; +} + +static inline void hri_sdadc_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTENSET.reg = SDADC_INTENSET_WINMON; +} + +static inline bool hri_sdadc_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTENSET.reg & SDADC_INTENSET_WINMON) >> SDADC_INTENSET_WINMON_Pos; +} + +static inline void hri_sdadc_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sdadc *)hw)->INTENCLR.reg = SDADC_INTENSET_WINMON; + } else { + ((Sdadc *)hw)->INTENSET.reg = SDADC_INTENSET_WINMON; + } +} + +static inline void hri_sdadc_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTENCLR.reg = SDADC_INTENSET_WINMON; +} + +static inline void hri_sdadc_set_INTEN_reg(const void *const hw, hri_sdadc_intenset_reg_t mask) +{ + ((Sdadc *)hw)->INTENSET.reg = mask; +} + +static inline hri_sdadc_intenset_reg_t hri_sdadc_get_INTEN_reg(const void *const hw, hri_sdadc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdadc_intenset_reg_t hri_sdadc_read_INTEN_reg(const void *const hw) +{ + return ((Sdadc *)hw)->INTENSET.reg; +} + +static inline void hri_sdadc_write_INTEN_reg(const void *const hw, hri_sdadc_intenset_reg_t data) +{ + ((Sdadc *)hw)->INTENSET.reg = data; + ((Sdadc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_sdadc_clear_INTEN_reg(const void *const hw, hri_sdadc_intenset_reg_t mask) +{ + ((Sdadc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_sdadc_get_SEQSTATUS_SEQBUSY_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SEQSTATUS.reg & SDADC_SEQSTATUS_SEQBUSY) >> SDADC_SEQSTATUS_SEQBUSY_Pos; +} + +static inline hri_sdadc_seqstatus_reg_t hri_sdadc_get_SEQSTATUS_SEQSTATE_bf(const void *const hw, + hri_sdadc_seqstatus_reg_t mask) +{ + return (((Sdadc *)hw)->SEQSTATUS.reg & SDADC_SEQSTATUS_SEQSTATE(mask)) >> SDADC_SEQSTATUS_SEQSTATE_Pos; +} + +static inline hri_sdadc_seqstatus_reg_t hri_sdadc_read_SEQSTATUS_SEQSTATE_bf(const void *const hw) +{ + return (((Sdadc *)hw)->SEQSTATUS.reg & SDADC_SEQSTATUS_SEQSTATE_Msk) >> SDADC_SEQSTATUS_SEQSTATE_Pos; +} + +static inline hri_sdadc_seqstatus_reg_t hri_sdadc_get_SEQSTATUS_reg(const void *const hw, + hri_sdadc_seqstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->SEQSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdadc_seqstatus_reg_t hri_sdadc_read_SEQSTATUS_reg(const void *const hw) +{ + return ((Sdadc *)hw)->SEQSTATUS.reg; +} + +static inline bool hri_sdadc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_SWRST) >> SDADC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_ENABLE) >> SDADC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_CTRLC_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_CTRLC) >> SDADC_SYNCBUSY_CTRLC_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_INPUTCTRL) >> SDADC_SYNCBUSY_INPUTCTRL_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_WINCTRL_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_WINCTRL) >> SDADC_SYNCBUSY_WINCTRL_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_WINLT_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_WINLT) >> SDADC_SYNCBUSY_WINLT_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_WINUT_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_WINUT) >> SDADC_SYNCBUSY_WINUT_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_OFFSETCORR) >> SDADC_SYNCBUSY_OFFSETCORR_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_GAINCORR) >> SDADC_SYNCBUSY_GAINCORR_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_SHIFTCORR_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_SHIFTCORR) >> SDADC_SYNCBUSY_SHIFTCORR_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_SWTRIG) >> SDADC_SYNCBUSY_SWTRIG_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_ANACTRL_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_ANACTRL) >> SDADC_SYNCBUSY_ANACTRL_Pos; +} + +static inline hri_sdadc_syncbusy_reg_t hri_sdadc_get_SYNCBUSY_reg(const void *const hw, hri_sdadc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdadc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdadc_syncbusy_reg_t hri_sdadc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sdadc *)hw)->SYNCBUSY.reg; +} + +static inline hri_sdadc_result_reg_t hri_sdadc_get_RESULT_RESULT_bf(const void *const hw, hri_sdadc_result_reg_t mask) +{ + return (((Sdadc *)hw)->RESULT.reg & SDADC_RESULT_RESULT(mask)) >> SDADC_RESULT_RESULT_Pos; +} + +static inline hri_sdadc_result_reg_t hri_sdadc_read_RESULT_RESULT_bf(const void *const hw) +{ + return (((Sdadc *)hw)->RESULT.reg & SDADC_RESULT_RESULT_Msk) >> SDADC_RESULT_RESULT_Pos; +} + +static inline hri_sdadc_result_reg_t hri_sdadc_get_RESULT_RESERVED_bf(const void *const hw, hri_sdadc_result_reg_t mask) +{ + return (((Sdadc *)hw)->RESULT.reg & SDADC_RESULT_RESERVED(mask)) >> SDADC_RESULT_RESERVED_Pos; +} + +static inline hri_sdadc_result_reg_t hri_sdadc_read_RESULT_RESERVED_bf(const void *const hw) +{ + return (((Sdadc *)hw)->RESULT.reg & SDADC_RESULT_RESERVED_Msk) >> SDADC_RESULT_RESERVED_Pos; +} + +static inline hri_sdadc_result_reg_t hri_sdadc_get_RESULT_reg(const void *const hw, hri_sdadc_result_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdadc *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdadc_result_reg_t hri_sdadc_read_RESULT_reg(const void *const hw) +{ + return ((Sdadc *)hw)->RESULT.reg; +} + +static inline void hri_sdadc_set_CTRLA_SWRST_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg |= SDADC_CTRLA_SWRST; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST); + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp = (tmp & SDADC_CTRLA_SWRST) >> SDADC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg |= SDADC_CTRLA_ENABLE; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp = (tmp & SDADC_CTRLA_ENABLE) >> SDADC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp &= ~SDADC_CTRLA_ENABLE; + tmp |= value << SDADC_CTRLA_ENABLE_Pos; + ((Sdadc *)hw)->CTRLA.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg &= ~SDADC_CTRLA_ENABLE; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg ^= SDADC_CTRLA_ENABLE; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg |= SDADC_CTRLA_RUNSTDBY; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp = (tmp & SDADC_CTRLA_RUNSTDBY) >> SDADC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp &= ~SDADC_CTRLA_RUNSTDBY; + tmp |= value << SDADC_CTRLA_RUNSTDBY_Pos; + ((Sdadc *)hw)->CTRLA.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg &= ~SDADC_CTRLA_RUNSTDBY; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg ^= SDADC_CTRLA_RUNSTDBY; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg |= SDADC_CTRLA_ONDEMAND; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp = (tmp & SDADC_CTRLA_ONDEMAND) >> SDADC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp &= ~SDADC_CTRLA_ONDEMAND; + tmp |= value << SDADC_CTRLA_ONDEMAND_Pos; + ((Sdadc *)hw)->CTRLA.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg &= ~SDADC_CTRLA_ONDEMAND; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg ^= SDADC_CTRLA_ONDEMAND; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_CTRLA_reg(const void *const hw, hri_sdadc_ctrla_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrla_reg_t hri_sdadc_get_CTRLA_reg(const void *const hw, hri_sdadc_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_CTRLA_reg(const void *const hw, hri_sdadc_ctrla_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLA_reg(const void *const hw, hri_sdadc_ctrla_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLA_reg(const void *const hw, hri_sdadc_ctrla_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrla_reg_t hri_sdadc_read_CTRLA_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + return ((Sdadc *)hw)->CTRLA.reg; +} + +static inline void hri_sdadc_set_REFCTRL_ONREFBUF_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg |= SDADC_REFCTRL_ONREFBUF; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_REFCTRL_ONREFBUF_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp = (tmp & SDADC_REFCTRL_ONREFBUF) >> SDADC_REFCTRL_ONREFBUF_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_REFCTRL_ONREFBUF_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp &= ~SDADC_REFCTRL_ONREFBUF; + tmp |= value << SDADC_REFCTRL_ONREFBUF_Pos; + ((Sdadc *)hw)->REFCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_REFCTRL_ONREFBUF_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg &= ~SDADC_REFCTRL_ONREFBUF; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_REFCTRL_ONREFBUF_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg ^= SDADC_REFCTRL_ONREFBUF; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg |= SDADC_REFCTRL_REFSEL(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_refctrl_reg_t hri_sdadc_get_REFCTRL_REFSEL_bf(const void *const hw, + hri_sdadc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp = (tmp & SDADC_REFCTRL_REFSEL(mask)) >> SDADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_sdadc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_sdadc_refctrl_reg_t data) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp &= ~SDADC_REFCTRL_REFSEL_Msk; + tmp |= SDADC_REFCTRL_REFSEL(data); + ((Sdadc *)hw)->REFCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg &= ~SDADC_REFCTRL_REFSEL(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg ^= SDADC_REFCTRL_REFSEL(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_refctrl_reg_t hri_sdadc_read_REFCTRL_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp = (tmp & SDADC_REFCTRL_REFSEL_Msk) >> SDADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_sdadc_set_REFCTRL_REFRANGE_bf(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg |= SDADC_REFCTRL_REFRANGE(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_refctrl_reg_t hri_sdadc_get_REFCTRL_REFRANGE_bf(const void *const hw, + hri_sdadc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp = (tmp & SDADC_REFCTRL_REFRANGE(mask)) >> SDADC_REFCTRL_REFRANGE_Pos; + return tmp; +} + +static inline void hri_sdadc_write_REFCTRL_REFRANGE_bf(const void *const hw, hri_sdadc_refctrl_reg_t data) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp &= ~SDADC_REFCTRL_REFRANGE_Msk; + tmp |= SDADC_REFCTRL_REFRANGE(data); + ((Sdadc *)hw)->REFCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_REFCTRL_REFRANGE_bf(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg &= ~SDADC_REFCTRL_REFRANGE(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_REFCTRL_REFRANGE_bf(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg ^= SDADC_REFCTRL_REFRANGE(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_refctrl_reg_t hri_sdadc_read_REFCTRL_REFRANGE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp = (tmp & SDADC_REFCTRL_REFRANGE_Msk) >> SDADC_REFCTRL_REFRANGE_Pos; + return tmp; +} + +static inline void hri_sdadc_set_REFCTRL_reg(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg |= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_refctrl_reg_t hri_sdadc_get_REFCTRL_reg(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_REFCTRL_reg(const void *const hw, hri_sdadc_refctrl_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg = data; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_REFCTRL_reg(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg &= ~mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_REFCTRL_reg(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg ^= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_refctrl_reg_t hri_sdadc_read_REFCTRL_reg(const void *const hw) +{ + return ((Sdadc *)hw)->REFCTRL.reg; +} + +static inline void hri_sdadc_set_CTRLB_PRESCALER_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg |= SDADC_CTRLB_PRESCALER(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_get_CTRLB_PRESCALER_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp = (tmp & SDADC_CTRLB_PRESCALER(mask)) >> SDADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_sdadc_write_CTRLB_PRESCALER_bf(const void *const hw, hri_sdadc_ctrlb_reg_t data) +{ + uint16_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp &= ~SDADC_CTRLB_PRESCALER_Msk; + tmp |= SDADC_CTRLB_PRESCALER(data); + ((Sdadc *)hw)->CTRLB.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLB_PRESCALER_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg &= ~SDADC_CTRLB_PRESCALER(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLB_PRESCALER_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg ^= SDADC_CTRLB_PRESCALER(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_read_CTRLB_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp = (tmp & SDADC_CTRLB_PRESCALER_Msk) >> SDADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_sdadc_set_CTRLB_OSR_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg |= SDADC_CTRLB_OSR(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_get_CTRLB_OSR_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp = (tmp & SDADC_CTRLB_OSR(mask)) >> SDADC_CTRLB_OSR_Pos; + return tmp; +} + +static inline void hri_sdadc_write_CTRLB_OSR_bf(const void *const hw, hri_sdadc_ctrlb_reg_t data) +{ + uint16_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp &= ~SDADC_CTRLB_OSR_Msk; + tmp |= SDADC_CTRLB_OSR(data); + ((Sdadc *)hw)->CTRLB.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLB_OSR_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg &= ~SDADC_CTRLB_OSR(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLB_OSR_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg ^= SDADC_CTRLB_OSR(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_read_CTRLB_OSR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp = (tmp & SDADC_CTRLB_OSR_Msk) >> SDADC_CTRLB_OSR_Pos; + return tmp; +} + +static inline void hri_sdadc_set_CTRLB_SKPCNT_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg |= SDADC_CTRLB_SKPCNT(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_get_CTRLB_SKPCNT_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp = (tmp & SDADC_CTRLB_SKPCNT(mask)) >> SDADC_CTRLB_SKPCNT_Pos; + return tmp; +} + +static inline void hri_sdadc_write_CTRLB_SKPCNT_bf(const void *const hw, hri_sdadc_ctrlb_reg_t data) +{ + uint16_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp &= ~SDADC_CTRLB_SKPCNT_Msk; + tmp |= SDADC_CTRLB_SKPCNT(data); + ((Sdadc *)hw)->CTRLB.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLB_SKPCNT_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg &= ~SDADC_CTRLB_SKPCNT(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLB_SKPCNT_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg ^= SDADC_CTRLB_SKPCNT(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_read_CTRLB_SKPCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp = (tmp & SDADC_CTRLB_SKPCNT_Msk) >> SDADC_CTRLB_SKPCNT_Pos; + return tmp; +} + +static inline void hri_sdadc_set_CTRLB_reg(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg |= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_get_CTRLB_reg(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_CTRLB_reg(const void *const hw, hri_sdadc_ctrlb_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg = data; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLB_reg(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg &= ~mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLB_reg(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg ^= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_read_CTRLB_reg(const void *const hw) +{ + return ((Sdadc *)hw)->CTRLB.reg; +} + +static inline void hri_sdadc_set_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg |= SDADC_EVCTRL_FLUSHEI; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp = (tmp & SDADC_EVCTRL_FLUSHEI) >> SDADC_EVCTRL_FLUSHEI_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp &= ~SDADC_EVCTRL_FLUSHEI; + tmp |= value << SDADC_EVCTRL_FLUSHEI_Pos; + ((Sdadc *)hw)->EVCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg &= ~SDADC_EVCTRL_FLUSHEI; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg ^= SDADC_EVCTRL_FLUSHEI; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg |= SDADC_EVCTRL_STARTEI; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp = (tmp & SDADC_EVCTRL_STARTEI) >> SDADC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp &= ~SDADC_EVCTRL_STARTEI; + tmp |= value << SDADC_EVCTRL_STARTEI_Pos; + ((Sdadc *)hw)->EVCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg &= ~SDADC_EVCTRL_STARTEI; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg ^= SDADC_EVCTRL_STARTEI; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg |= SDADC_EVCTRL_FLUSHINV; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp = (tmp & SDADC_EVCTRL_FLUSHINV) >> SDADC_EVCTRL_FLUSHINV_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp &= ~SDADC_EVCTRL_FLUSHINV; + tmp |= value << SDADC_EVCTRL_FLUSHINV_Pos; + ((Sdadc *)hw)->EVCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg &= ~SDADC_EVCTRL_FLUSHINV; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg ^= SDADC_EVCTRL_FLUSHINV; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_EVCTRL_STARTINV_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg |= SDADC_EVCTRL_STARTINV; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_EVCTRL_STARTINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp = (tmp & SDADC_EVCTRL_STARTINV) >> SDADC_EVCTRL_STARTINV_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp &= ~SDADC_EVCTRL_STARTINV; + tmp |= value << SDADC_EVCTRL_STARTINV_Pos; + ((Sdadc *)hw)->EVCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_EVCTRL_STARTINV_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg &= ~SDADC_EVCTRL_STARTINV; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_EVCTRL_STARTINV_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg ^= SDADC_EVCTRL_STARTINV; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg |= SDADC_EVCTRL_RESRDYEO; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp = (tmp & SDADC_EVCTRL_RESRDYEO) >> SDADC_EVCTRL_RESRDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp &= ~SDADC_EVCTRL_RESRDYEO; + tmp |= value << SDADC_EVCTRL_RESRDYEO_Pos; + ((Sdadc *)hw)->EVCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg &= ~SDADC_EVCTRL_RESRDYEO; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg ^= SDADC_EVCTRL_RESRDYEO; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_EVCTRL_WINMONEO_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg |= SDADC_EVCTRL_WINMONEO; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_EVCTRL_WINMONEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp = (tmp & SDADC_EVCTRL_WINMONEO) >> SDADC_EVCTRL_WINMONEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp &= ~SDADC_EVCTRL_WINMONEO; + tmp |= value << SDADC_EVCTRL_WINMONEO_Pos; + ((Sdadc *)hw)->EVCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_EVCTRL_WINMONEO_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg &= ~SDADC_EVCTRL_WINMONEO; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg ^= SDADC_EVCTRL_WINMONEO; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_EVCTRL_reg(const void *const hw, hri_sdadc_evctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg |= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_evctrl_reg_t hri_sdadc_get_EVCTRL_reg(const void *const hw, hri_sdadc_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_EVCTRL_reg(const void *const hw, hri_sdadc_evctrl_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg = data; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_EVCTRL_reg(const void *const hw, hri_sdadc_evctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg &= ~mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_EVCTRL_reg(const void *const hw, hri_sdadc_evctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg ^= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_evctrl_reg_t hri_sdadc_read_EVCTRL_reg(const void *const hw) +{ + return ((Sdadc *)hw)->EVCTRL.reg; +} + +static inline void hri_sdadc_set_INPUTCTRL_MUXSEL_bf(const void *const hw, hri_sdadc_inputctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->INPUTCTRL.reg |= SDADC_INPUTCTRL_MUXSEL(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_inputctrl_reg_t hri_sdadc_get_INPUTCTRL_MUXSEL_bf(const void *const hw, + hri_sdadc_inputctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->INPUTCTRL.reg; + tmp = (tmp & SDADC_INPUTCTRL_MUXSEL(mask)) >> SDADC_INPUTCTRL_MUXSEL_Pos; + return tmp; +} + +static inline void hri_sdadc_write_INPUTCTRL_MUXSEL_bf(const void *const hw, hri_sdadc_inputctrl_reg_t data) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->INPUTCTRL.reg; + tmp &= ~SDADC_INPUTCTRL_MUXSEL_Msk; + tmp |= SDADC_INPUTCTRL_MUXSEL(data); + ((Sdadc *)hw)->INPUTCTRL.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_INPUTCTRL_MUXSEL_bf(const void *const hw, hri_sdadc_inputctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->INPUTCTRL.reg &= ~SDADC_INPUTCTRL_MUXSEL(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_INPUTCTRL_MUXSEL_bf(const void *const hw, hri_sdadc_inputctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->INPUTCTRL.reg ^= SDADC_INPUTCTRL_MUXSEL(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_inputctrl_reg_t hri_sdadc_read_INPUTCTRL_MUXSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->INPUTCTRL.reg; + tmp = (tmp & SDADC_INPUTCTRL_MUXSEL_Msk) >> SDADC_INPUTCTRL_MUXSEL_Pos; + return tmp; +} + +static inline void hri_sdadc_set_INPUTCTRL_reg(const void *const hw, hri_sdadc_inputctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->INPUTCTRL.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_inputctrl_reg_t hri_sdadc_get_INPUTCTRL_reg(const void *const hw, + hri_sdadc_inputctrl_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + tmp = ((Sdadc *)hw)->INPUTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_INPUTCTRL_reg(const void *const hw, hri_sdadc_inputctrl_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->INPUTCTRL.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_INPUTCTRL_reg(const void *const hw, hri_sdadc_inputctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->INPUTCTRL.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_INPUTCTRL_reg(const void *const hw, hri_sdadc_inputctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->INPUTCTRL.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_inputctrl_reg_t hri_sdadc_read_INPUTCTRL_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + return ((Sdadc *)hw)->INPUTCTRL.reg; +} + +static inline void hri_sdadc_set_CTRLC_FREERUN_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLC.reg |= SDADC_CTRLC_FREERUN; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_CTRLC_FREERUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->CTRLC.reg; + tmp = (tmp & SDADC_CTRLC_FREERUN) >> SDADC_CTRLC_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_CTRLC_FREERUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->CTRLC.reg; + tmp &= ~SDADC_CTRLC_FREERUN; + tmp |= value << SDADC_CTRLC_FREERUN_Pos; + ((Sdadc *)hw)->CTRLC.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLC_FREERUN_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLC.reg &= ~SDADC_CTRLC_FREERUN; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLC_FREERUN_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLC.reg ^= SDADC_CTRLC_FREERUN; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_CTRLC_reg(const void *const hw, hri_sdadc_ctrlc_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLC.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlc_reg_t hri_sdadc_get_CTRLC_reg(const void *const hw, hri_sdadc_ctrlc_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + tmp = ((Sdadc *)hw)->CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_CTRLC_reg(const void *const hw, hri_sdadc_ctrlc_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLC.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLC_reg(const void *const hw, hri_sdadc_ctrlc_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLC.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLC_reg(const void *const hw, hri_sdadc_ctrlc_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLC.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlc_reg_t hri_sdadc_read_CTRLC_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + return ((Sdadc *)hw)->CTRLC.reg; +} + +static inline void hri_sdadc_set_WINCTRL_WINMODE_bf(const void *const hw, hri_sdadc_winctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINCTRL.reg |= SDADC_WINCTRL_WINMODE(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winctrl_reg_t hri_sdadc_get_WINCTRL_WINMODE_bf(const void *const hw, + hri_sdadc_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->WINCTRL.reg; + tmp = (tmp & SDADC_WINCTRL_WINMODE(mask)) >> SDADC_WINCTRL_WINMODE_Pos; + return tmp; +} + +static inline void hri_sdadc_write_WINCTRL_WINMODE_bf(const void *const hw, hri_sdadc_winctrl_reg_t data) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->WINCTRL.reg; + tmp &= ~SDADC_WINCTRL_WINMODE_Msk; + tmp |= SDADC_WINCTRL_WINMODE(data); + ((Sdadc *)hw)->WINCTRL.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_WINCTRL_WINMODE_bf(const void *const hw, hri_sdadc_winctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINCTRL.reg &= ~SDADC_WINCTRL_WINMODE(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_WINCTRL_WINMODE_bf(const void *const hw, hri_sdadc_winctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINCTRL.reg ^= SDADC_WINCTRL_WINMODE(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winctrl_reg_t hri_sdadc_read_WINCTRL_WINMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->WINCTRL.reg; + tmp = (tmp & SDADC_WINCTRL_WINMODE_Msk) >> SDADC_WINCTRL_WINMODE_Pos; + return tmp; +} + +static inline void hri_sdadc_set_WINCTRL_reg(const void *const hw, hri_sdadc_winctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINCTRL.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winctrl_reg_t hri_sdadc_get_WINCTRL_reg(const void *const hw, hri_sdadc_winctrl_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + tmp = ((Sdadc *)hw)->WINCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_WINCTRL_reg(const void *const hw, hri_sdadc_winctrl_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINCTRL.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_WINCTRL_reg(const void *const hw, hri_sdadc_winctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINCTRL.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_WINCTRL_reg(const void *const hw, hri_sdadc_winctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINCTRL.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winctrl_reg_t hri_sdadc_read_WINCTRL_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + return ((Sdadc *)hw)->WINCTRL.reg; +} + +static inline void hri_sdadc_set_WINLT_WINLT_bf(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINLT.reg |= SDADC_WINLT_WINLT(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winlt_reg_t hri_sdadc_get_WINLT_WINLT_bf(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + tmp = ((Sdadc *)hw)->WINLT.reg; + tmp = (tmp & SDADC_WINLT_WINLT(mask)) >> SDADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_sdadc_write_WINLT_WINLT_bf(const void *const hw, hri_sdadc_winlt_reg_t data) +{ + uint32_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->WINLT.reg; + tmp &= ~SDADC_WINLT_WINLT_Msk; + tmp |= SDADC_WINLT_WINLT(data); + ((Sdadc *)hw)->WINLT.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_WINLT_WINLT_bf(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINLT.reg &= ~SDADC_WINLT_WINLT(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_WINLT_WINLT_bf(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINLT.reg ^= SDADC_WINLT_WINLT(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winlt_reg_t hri_sdadc_read_WINLT_WINLT_bf(const void *const hw) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + tmp = ((Sdadc *)hw)->WINLT.reg; + tmp = (tmp & SDADC_WINLT_WINLT_Msk) >> SDADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_sdadc_set_WINLT_reg(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINLT.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winlt_reg_t hri_sdadc_get_WINLT_reg(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + tmp = ((Sdadc *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_WINLT_reg(const void *const hw, hri_sdadc_winlt_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINLT.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_WINLT_reg(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINLT.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_WINLT_reg(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINLT.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winlt_reg_t hri_sdadc_read_WINLT_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + return ((Sdadc *)hw)->WINLT.reg; +} + +static inline void hri_sdadc_set_WINUT_WINUT_bf(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINUT.reg |= SDADC_WINUT_WINUT(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winut_reg_t hri_sdadc_get_WINUT_WINUT_bf(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + tmp = ((Sdadc *)hw)->WINUT.reg; + tmp = (tmp & SDADC_WINUT_WINUT(mask)) >> SDADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_sdadc_write_WINUT_WINUT_bf(const void *const hw, hri_sdadc_winut_reg_t data) +{ + uint32_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->WINUT.reg; + tmp &= ~SDADC_WINUT_WINUT_Msk; + tmp |= SDADC_WINUT_WINUT(data); + ((Sdadc *)hw)->WINUT.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_WINUT_WINUT_bf(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINUT.reg &= ~SDADC_WINUT_WINUT(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_WINUT_WINUT_bf(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINUT.reg ^= SDADC_WINUT_WINUT(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winut_reg_t hri_sdadc_read_WINUT_WINUT_bf(const void *const hw) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + tmp = ((Sdadc *)hw)->WINUT.reg; + tmp = (tmp & SDADC_WINUT_WINUT_Msk) >> SDADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_sdadc_set_WINUT_reg(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINUT.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winut_reg_t hri_sdadc_get_WINUT_reg(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + tmp = ((Sdadc *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_WINUT_reg(const void *const hw, hri_sdadc_winut_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINUT.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_WINUT_reg(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINUT.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_WINUT_reg(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINUT.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winut_reg_t hri_sdadc_read_WINUT_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + return ((Sdadc *)hw)->WINUT.reg; +} + +static inline void hri_sdadc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_sdadc_offsetcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->OFFSETCORR.reg |= SDADC_OFFSETCORR_OFFSETCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_offsetcorr_reg_t hri_sdadc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, + hri_sdadc_offsetcorr_reg_t mask) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + tmp = ((Sdadc *)hw)->OFFSETCORR.reg; + tmp = (tmp & SDADC_OFFSETCORR_OFFSETCORR(mask)) >> SDADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_sdadc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_sdadc_offsetcorr_reg_t data) +{ + uint32_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->OFFSETCORR.reg; + tmp &= ~SDADC_OFFSETCORR_OFFSETCORR_Msk; + tmp |= SDADC_OFFSETCORR_OFFSETCORR(data); + ((Sdadc *)hw)->OFFSETCORR.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_sdadc_offsetcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->OFFSETCORR.reg &= ~SDADC_OFFSETCORR_OFFSETCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_sdadc_offsetcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->OFFSETCORR.reg ^= SDADC_OFFSETCORR_OFFSETCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_offsetcorr_reg_t hri_sdadc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + tmp = ((Sdadc *)hw)->OFFSETCORR.reg; + tmp = (tmp & SDADC_OFFSETCORR_OFFSETCORR_Msk) >> SDADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_sdadc_set_OFFSETCORR_reg(const void *const hw, hri_sdadc_offsetcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->OFFSETCORR.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_offsetcorr_reg_t hri_sdadc_get_OFFSETCORR_reg(const void *const hw, + hri_sdadc_offsetcorr_reg_t mask) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + tmp = ((Sdadc *)hw)->OFFSETCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_OFFSETCORR_reg(const void *const hw, hri_sdadc_offsetcorr_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->OFFSETCORR.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_OFFSETCORR_reg(const void *const hw, hri_sdadc_offsetcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->OFFSETCORR.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_OFFSETCORR_reg(const void *const hw, hri_sdadc_offsetcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->OFFSETCORR.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_offsetcorr_reg_t hri_sdadc_read_OFFSETCORR_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + return ((Sdadc *)hw)->OFFSETCORR.reg; +} + +static inline void hri_sdadc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_sdadc_gaincorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->GAINCORR.reg |= SDADC_GAINCORR_GAINCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_gaincorr_reg_t hri_sdadc_get_GAINCORR_GAINCORR_bf(const void *const hw, + hri_sdadc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + tmp = ((Sdadc *)hw)->GAINCORR.reg; + tmp = (tmp & SDADC_GAINCORR_GAINCORR(mask)) >> SDADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_sdadc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_sdadc_gaincorr_reg_t data) +{ + uint16_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->GAINCORR.reg; + tmp &= ~SDADC_GAINCORR_GAINCORR_Msk; + tmp |= SDADC_GAINCORR_GAINCORR(data); + ((Sdadc *)hw)->GAINCORR.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_sdadc_gaincorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->GAINCORR.reg &= ~SDADC_GAINCORR_GAINCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_sdadc_gaincorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->GAINCORR.reg ^= SDADC_GAINCORR_GAINCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_gaincorr_reg_t hri_sdadc_read_GAINCORR_GAINCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + tmp = ((Sdadc *)hw)->GAINCORR.reg; + tmp = (tmp & SDADC_GAINCORR_GAINCORR_Msk) >> SDADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_sdadc_set_GAINCORR_reg(const void *const hw, hri_sdadc_gaincorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->GAINCORR.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_gaincorr_reg_t hri_sdadc_get_GAINCORR_reg(const void *const hw, hri_sdadc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + tmp = ((Sdadc *)hw)->GAINCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_GAINCORR_reg(const void *const hw, hri_sdadc_gaincorr_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->GAINCORR.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_GAINCORR_reg(const void *const hw, hri_sdadc_gaincorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->GAINCORR.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_GAINCORR_reg(const void *const hw, hri_sdadc_gaincorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->GAINCORR.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_gaincorr_reg_t hri_sdadc_read_GAINCORR_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + return ((Sdadc *)hw)->GAINCORR.reg; +} + +static inline void hri_sdadc_set_SHIFTCORR_SHIFTCORR_bf(const void *const hw, hri_sdadc_shiftcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SHIFTCORR.reg |= SDADC_SHIFTCORR_SHIFTCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_shiftcorr_reg_t hri_sdadc_get_SHIFTCORR_SHIFTCORR_bf(const void *const hw, + hri_sdadc_shiftcorr_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + tmp = ((Sdadc *)hw)->SHIFTCORR.reg; + tmp = (tmp & SDADC_SHIFTCORR_SHIFTCORR(mask)) >> SDADC_SHIFTCORR_SHIFTCORR_Pos; + return tmp; +} + +static inline void hri_sdadc_write_SHIFTCORR_SHIFTCORR_bf(const void *const hw, hri_sdadc_shiftcorr_reg_t data) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->SHIFTCORR.reg; + tmp &= ~SDADC_SHIFTCORR_SHIFTCORR_Msk; + tmp |= SDADC_SHIFTCORR_SHIFTCORR(data); + ((Sdadc *)hw)->SHIFTCORR.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_SHIFTCORR_SHIFTCORR_bf(const void *const hw, hri_sdadc_shiftcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SHIFTCORR.reg &= ~SDADC_SHIFTCORR_SHIFTCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_SHIFTCORR_SHIFTCORR_bf(const void *const hw, hri_sdadc_shiftcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SHIFTCORR.reg ^= SDADC_SHIFTCORR_SHIFTCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_shiftcorr_reg_t hri_sdadc_read_SHIFTCORR_SHIFTCORR_bf(const void *const hw) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + tmp = ((Sdadc *)hw)->SHIFTCORR.reg; + tmp = (tmp & SDADC_SHIFTCORR_SHIFTCORR_Msk) >> SDADC_SHIFTCORR_SHIFTCORR_Pos; + return tmp; +} + +static inline void hri_sdadc_set_SHIFTCORR_reg(const void *const hw, hri_sdadc_shiftcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SHIFTCORR.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_shiftcorr_reg_t hri_sdadc_get_SHIFTCORR_reg(const void *const hw, + hri_sdadc_shiftcorr_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + tmp = ((Sdadc *)hw)->SHIFTCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_SHIFTCORR_reg(const void *const hw, hri_sdadc_shiftcorr_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SHIFTCORR.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_SHIFTCORR_reg(const void *const hw, hri_sdadc_shiftcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SHIFTCORR.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_SHIFTCORR_reg(const void *const hw, hri_sdadc_shiftcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SHIFTCORR.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_shiftcorr_reg_t hri_sdadc_read_SHIFTCORR_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + return ((Sdadc *)hw)->SHIFTCORR.reg; +} + +static inline void hri_sdadc_set_SWTRIG_FLUSH_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg |= SDADC_SWTRIG_FLUSH; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_SWTRIG_FLUSH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->SWTRIG.reg; + tmp = (tmp & SDADC_SWTRIG_FLUSH) >> SDADC_SWTRIG_FLUSH_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->SWTRIG.reg; + tmp &= ~SDADC_SWTRIG_FLUSH; + tmp |= value << SDADC_SWTRIG_FLUSH_Pos; + ((Sdadc *)hw)->SWTRIG.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_SWTRIG_FLUSH_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg &= ~SDADC_SWTRIG_FLUSH; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_SWTRIG_FLUSH_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg ^= SDADC_SWTRIG_FLUSH; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_SWTRIG_START_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg |= SDADC_SWTRIG_START; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_SWTRIG_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->SWTRIG.reg; + tmp = (tmp & SDADC_SWTRIG_START) >> SDADC_SWTRIG_START_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_SWTRIG_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->SWTRIG.reg; + tmp &= ~SDADC_SWTRIG_START; + tmp |= value << SDADC_SWTRIG_START_Pos; + ((Sdadc *)hw)->SWTRIG.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_SWTRIG_START_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg &= ~SDADC_SWTRIG_START; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_SWTRIG_START_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg ^= SDADC_SWTRIG_START; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_SWTRIG_reg(const void *const hw, hri_sdadc_swtrig_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_swtrig_reg_t hri_sdadc_get_SWTRIG_reg(const void *const hw, hri_sdadc_swtrig_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + tmp = ((Sdadc *)hw)->SWTRIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_SWTRIG_reg(const void *const hw, hri_sdadc_swtrig_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_SWTRIG_reg(const void *const hw, hri_sdadc_swtrig_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_SWTRIG_reg(const void *const hw, hri_sdadc_swtrig_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_swtrig_reg_t hri_sdadc_read_SWTRIG_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + return ((Sdadc *)hw)->SWTRIG.reg; +} + +static inline void hri_sdadc_set_SEQCTRL_SEQEN_bf(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SEQCTRL.reg |= SDADC_SEQCTRL_SEQEN(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_seqctrl_reg_t hri_sdadc_get_SEQCTRL_SEQEN_bf(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->SEQCTRL.reg; + tmp = (tmp & SDADC_SEQCTRL_SEQEN(mask)) >> SDADC_SEQCTRL_SEQEN_Pos; + return tmp; +} + +static inline void hri_sdadc_write_SEQCTRL_SEQEN_bf(const void *const hw, hri_sdadc_seqctrl_reg_t data) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->SEQCTRL.reg; + tmp &= ~SDADC_SEQCTRL_SEQEN_Msk; + tmp |= SDADC_SEQCTRL_SEQEN(data); + ((Sdadc *)hw)->SEQCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_SEQCTRL_SEQEN_bf(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SEQCTRL.reg &= ~SDADC_SEQCTRL_SEQEN(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_SEQCTRL_SEQEN_bf(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SEQCTRL.reg ^= SDADC_SEQCTRL_SEQEN(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_seqctrl_reg_t hri_sdadc_read_SEQCTRL_SEQEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->SEQCTRL.reg; + tmp = (tmp & SDADC_SEQCTRL_SEQEN_Msk) >> SDADC_SEQCTRL_SEQEN_Pos; + return tmp; +} + +static inline void hri_sdadc_set_SEQCTRL_reg(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SEQCTRL.reg |= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_seqctrl_reg_t hri_sdadc_get_SEQCTRL_reg(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->SEQCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_SEQCTRL_reg(const void *const hw, hri_sdadc_seqctrl_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SEQCTRL.reg = data; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_SEQCTRL_reg(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SEQCTRL.reg &= ~mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_SEQCTRL_reg(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SEQCTRL.reg ^= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_seqctrl_reg_t hri_sdadc_read_SEQCTRL_reg(const void *const hw) +{ + return ((Sdadc *)hw)->SEQCTRL.reg; +} + +static inline void hri_sdadc_set_ANACTRL_ONCHOP_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg |= SDADC_ANACTRL_ONCHOP; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_ANACTRL_ONCHOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp = (tmp & SDADC_ANACTRL_ONCHOP) >> SDADC_ANACTRL_ONCHOP_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_ANACTRL_ONCHOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp &= ~SDADC_ANACTRL_ONCHOP; + tmp |= value << SDADC_ANACTRL_ONCHOP_Pos; + ((Sdadc *)hw)->ANACTRL.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_ANACTRL_ONCHOP_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg &= ~SDADC_ANACTRL_ONCHOP; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_ANACTRL_ONCHOP_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg ^= SDADC_ANACTRL_ONCHOP; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_ANACTRL_BUFTEST_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg |= SDADC_ANACTRL_BUFTEST; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_ANACTRL_BUFTEST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp = (tmp & SDADC_ANACTRL_BUFTEST) >> SDADC_ANACTRL_BUFTEST_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_ANACTRL_BUFTEST_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp &= ~SDADC_ANACTRL_BUFTEST; + tmp |= value << SDADC_ANACTRL_BUFTEST_Pos; + ((Sdadc *)hw)->ANACTRL.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_ANACTRL_BUFTEST_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg &= ~SDADC_ANACTRL_BUFTEST; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_ANACTRL_BUFTEST_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg ^= SDADC_ANACTRL_BUFTEST; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_ANACTRL_CTRSDADC_bf(const void *const hw, hri_sdadc_anactrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg |= SDADC_ANACTRL_CTRSDADC(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_anactrl_reg_t hri_sdadc_get_ANACTRL_CTRSDADC_bf(const void *const hw, + hri_sdadc_anactrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp = (tmp & SDADC_ANACTRL_CTRSDADC(mask)) >> SDADC_ANACTRL_CTRSDADC_Pos; + return tmp; +} + +static inline void hri_sdadc_write_ANACTRL_CTRSDADC_bf(const void *const hw, hri_sdadc_anactrl_reg_t data) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp &= ~SDADC_ANACTRL_CTRSDADC_Msk; + tmp |= SDADC_ANACTRL_CTRSDADC(data); + ((Sdadc *)hw)->ANACTRL.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_ANACTRL_CTRSDADC_bf(const void *const hw, hri_sdadc_anactrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg &= ~SDADC_ANACTRL_CTRSDADC(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_ANACTRL_CTRSDADC_bf(const void *const hw, hri_sdadc_anactrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg ^= SDADC_ANACTRL_CTRSDADC(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_anactrl_reg_t hri_sdadc_read_ANACTRL_CTRSDADC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp = (tmp & SDADC_ANACTRL_CTRSDADC_Msk) >> SDADC_ANACTRL_CTRSDADC_Pos; + return tmp; +} + +static inline void hri_sdadc_set_ANACTRL_reg(const void *const hw, hri_sdadc_anactrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_anactrl_reg_t hri_sdadc_get_ANACTRL_reg(const void *const hw, hri_sdadc_anactrl_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_ANACTRL_reg(const void *const hw, hri_sdadc_anactrl_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_ANACTRL_reg(const void *const hw, hri_sdadc_anactrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_ANACTRL_reg(const void *const hw, hri_sdadc_anactrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_anactrl_reg_t hri_sdadc_read_ANACTRL_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + return ((Sdadc *)hw)->ANACTRL.reg; +} + +static inline void hri_sdadc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->DBGCTRL.reg |= SDADC_DBGCTRL_DBGRUN; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->DBGCTRL.reg; + tmp = (tmp & SDADC_DBGCTRL_DBGRUN) >> SDADC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->DBGCTRL.reg; + tmp &= ~SDADC_DBGCTRL_DBGRUN; + tmp |= value << SDADC_DBGCTRL_DBGRUN_Pos; + ((Sdadc *)hw)->DBGCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->DBGCTRL.reg &= ~SDADC_DBGCTRL_DBGRUN; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->DBGCTRL.reg ^= SDADC_DBGCTRL_DBGRUN; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_DBGCTRL_reg(const void *const hw, hri_sdadc_dbgctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->DBGCTRL.reg |= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_dbgctrl_reg_t hri_sdadc_get_DBGCTRL_reg(const void *const hw, hri_sdadc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_DBGCTRL_reg(const void *const hw, hri_sdadc_dbgctrl_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->DBGCTRL.reg = data; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_DBGCTRL_reg(const void *const hw, hri_sdadc_dbgctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->DBGCTRL.reg &= ~mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_DBGCTRL_reg(const void *const hw, hri_sdadc_dbgctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->DBGCTRL.reg ^= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_dbgctrl_reg_t hri_sdadc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sdadc *)hw)->DBGCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SDADC_C21_H_INCLUDED */ +#endif /* _SAMC21_SDADC_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_sercom_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_sercom_c21.h new file mode 100644 index 0000000..45d6580 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_sercom_c21.h @@ -0,0 +1,7754 @@ +/** + * \file + * + * \brief SAM SERCOM + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_SERCOM_COMPONENT_ +#ifndef _HRI_SERCOM_C21_H_INCLUDED_ +#define _HRI_SERCOM_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) +#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SERCOM_CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sercomi2cm_status_reg_t; +typedef uint16_t hri_sercomi2cs_status_reg_t; +typedef uint16_t hri_sercomspi_status_reg_t; +typedef uint16_t hri_sercomusart_baud_reg_t; +typedef uint16_t hri_sercomusart_data_reg_t; +typedef uint16_t hri_sercomusart_status_reg_t; +typedef uint32_t hri_sercomi2cm_addr_reg_t; +typedef uint32_t hri_sercomi2cm_baud_reg_t; +typedef uint32_t hri_sercomi2cm_ctrla_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; +typedef uint32_t hri_sercomi2cs_addr_reg_t; +typedef uint32_t hri_sercomi2cs_ctrla_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; +typedef uint32_t hri_sercomspi_addr_reg_t; +typedef uint32_t hri_sercomspi_ctrla_reg_t; +typedef uint32_t hri_sercomspi_ctrlb_reg_t; +typedef uint32_t hri_sercomspi_data_reg_t; +typedef uint32_t hri_sercomspi_syncbusy_reg_t; +typedef uint32_t hri_sercomusart_ctrla_reg_t; +typedef uint32_t hri_sercomusart_ctrlb_reg_t; +typedef uint32_t hri_sercomusart_ctrlc_reg_t; +typedef uint32_t hri_sercomusart_syncbusy_reg_t; +typedef uint8_t hri_sercomi2cm_data_reg_t; +typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; +typedef uint8_t hri_sercomi2cm_intenset_reg_t; +typedef uint8_t hri_sercomi2cm_intflag_reg_t; +typedef uint8_t hri_sercomi2cs_data_reg_t; +typedef uint8_t hri_sercomi2cs_intenset_reg_t; +typedef uint8_t hri_sercomi2cs_intflag_reg_t; +typedef uint8_t hri_sercomspi_baud_reg_t; +typedef uint8_t hri_sercomspi_dbgctrl_reg_t; +typedef uint8_t hri_sercomspi_intenset_reg_t; +typedef uint8_t hri_sercomspi_intflag_reg_t; +typedef uint8_t hri_sercomusart_dbgctrl_reg_t; +typedef uint8_t hri_sercomusart_intenset_reg_t; +typedef uint8_t hri_sercomusart_intflag_reg_t; +typedef uint8_t hri_sercomusart_rxpl_reg_t; + +static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTFLAG.reg; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cs_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTFLAG.reg; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; +} + +static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, + hri_sercomspi_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTFLAG.reg; +} + +static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = mask; +} + +static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, + hri_sercomusart_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTFLAG.reg; +} + +static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = mask; +} + +static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = mask; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, + hri_sercomi2cm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTENSET.reg; +} + +static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = data; + ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; +} + +static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = mask; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, + hri_sercomi2cs_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTENSET.reg; +} + +static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = data; + ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; +} + +static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; +} + +static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; + } +} + +static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; +} + +static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; + } +} + +static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; + } +} + +static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = mask; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, + hri_sercomspi_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTENSET.reg; +} + +static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = data; + ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; +} + +static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = mask; +} + +static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; +} + +static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; + } +} + +static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; + } +} + +static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; + } +} + +static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENSET.reg = mask; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, + hri_sercomusart_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTENSET.reg; +} + +static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) +{ + ((Sercom *)hw)->USART.INTENSET.reg = data; + ((Sercom *)hw)->USART.INTENCLR.reg = ~data; +} + +static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = mask; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cs_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, + hri_sercomspi_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, + hri_sercomusart_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg; +} + +static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CM_CTRLA_MODE(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CM_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; + tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->I2CM.CTRLA.reg; +} + +static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CS_CTRLA_MODE(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CS_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg = data; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + return ((Sercom *)hw)->I2CS.CTRLA.reg; +} + +static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_ENABLE; + tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_IBON; + tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPHA; + tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPOL; + tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DORD; + tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; + tmp |= SERCOM_SPI_CTRLA_MODE(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DOPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DIPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; + tmp |= SERCOM_SPI_CTRLA_FORM(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->SPI.CTRLA.reg; +} + +static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_ENABLE; + tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_IBON; + tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CMODE; + tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CPOL; + tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_DORD; + tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; + tmp |= SERCOM_USART_CTRLA_MODE(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPR(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; + tmp |= SERCOM_USART_CTRLA_TXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; + tmp |= SERCOM_USART_CTRLA_RXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPA(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; + tmp |= SERCOM_USART_CTRLA_FORM(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->USART.CTRLA.reg; +} + +static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_SMEN; + tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_QCEN; + tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CM_CTRLB_CMD(data); + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + return ((Sercom *)hw)->I2CM.CTRLB.reg; +} + +static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_SMEN; + tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_GCMD; + tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; + tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; + tmp |= SERCOM_I2CS_CTRLB_AMODE(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CS_CTRLB_CMD(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLB.reg; +} + +static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; + tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_SSDE; + tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_MSSEN; + tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_RXEN; + tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; + tmp |= SERCOM_SPI_CTRLB_AMODE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + return ((Sercom *)hw)->SPI.CTRLB.reg; +} + +static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SBMODE; + tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_COLDEN; + tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SFDE; + tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_ENC; + tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_PMODE; + tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_TXEN; + tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_RXEN; + tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_USART_CTRLB_CHSIZE(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_LINCMD_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_LINCMD(mask)) >> SERCOM_USART_CTRLB_LINCMD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_LINCMD_Msk; + tmp |= SERCOM_USART_CTRLB_LINCMD(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_LINCMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_LINCMD_Msk) >> SERCOM_USART_CTRLB_LINCMD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.CTRLB.reg; +} + +static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk; + tmp |= SERCOM_USART_CTRLC_GTIME(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_BRKLEN_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN(mask)) >> SERCOM_USART_CTRLC_BRKLEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_BRKLEN_Msk; + tmp |= SERCOM_USART_CTRLC_BRKLEN(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_BRKLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN_Msk) >> SERCOM_USART_CTRLC_BRKLEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_HDRDLY_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY(mask)) >> SERCOM_USART_CTRLC_HDRDLY_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_HDRDLY_Msk; + tmp |= SERCOM_USART_CTRLC_HDRDLY(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_HDRDLY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY_Msk) >> SERCOM_USART_CTRLC_HDRDLY_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.CTRLC.reg; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.BAUD.reg; +} + +static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; + tmp |= SERCOM_SPI_BAUD_BAUD(data); + ((Sercom *)hw)->SPI.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRAC_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; + tmp |= SERCOM_USART_RXPL_RXPL(data); + ((Sercom *)hw)->USART.RXPL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.RXPL.reg; +} + +static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LENEN; + tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_HS; + tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CM_ADDR_ADDR(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; + tmp |= SERCOM_I2CM_ADDR_LEN(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.ADDR.reg; +} + +static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_GENCEN; + tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDR(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.ADDR.reg; +} + +static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; + tmp |= SERCOM_SPI_ADDR_ADDR(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.ADDR.reg; +} + +static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; + tmp |= SERCOM_I2CM_DATA_DATA(data); + ((Sercom *)hw)->I2CM.DATA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint8_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.DATA.reg; +} + +static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; + tmp |= SERCOM_I2CS_DATA_DATA(data); + ((Sercom *)hw)->I2CS.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.DATA.reg; +} + +static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const hw, + hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= ~SERCOM_SPI_DATA_DATA_Msk; + tmp |= SERCOM_SPI_DATA_DATA(data); + ((Sercom *)hw)->SPI.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DATA.reg; +} + +static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= ~SERCOM_USART_DATA_DATA_Msk; + tmp |= SERCOM_USART_DATA_DATA(data); + ((Sercom *)hw)->USART.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DATA.reg; +} + +static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, + hri_sercomi2cm_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.DBGCTRL.reg; +} + +static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, + hri_sercomspi_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DBGCTRL.reg; +} + +static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, + hri_sercomusart_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DBGCTRL.reg; +} + +static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, + hri_sercomi2cs_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.STATUS.reg; +} + +static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, + hri_sercomspi_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.STATUS.reg; +} + +static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, + hri_sercomusart_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.STATUS.reg; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSERR; + tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; + tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_RXNACK; + tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; + tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; + tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LENERR; + tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; + tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg |= mask; +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.STATUS.reg; +} + +static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + ((Sercom *)hw)->I2CM.STATUS.reg = data; +} + +static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; +} + +static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_sercomusart_set_BAUD_FRAC_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRAC_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRAC_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRAC_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRAC_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRAC_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_FRACFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRACFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRACFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRACFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRACFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRACFP_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_USARTFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_USARTFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_USARTFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_USARTFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_USARTFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_USARTFP_reg(a) hri_sercomusart_read_BAUD_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SERCOM_C21_H_INCLUDED */ +#endif /* _SAMC21_SERCOM_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_supc_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_supc_c21.h new file mode 100644 index 0000000..23d7c42 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_supc_c21.h @@ -0,0 +1,1560 @@ +/** + * \file + * + * \brief SAM SUPC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_SUPC_COMPONENT_ +#ifndef _HRI_SUPC_C21_H_INCLUDED_ +#define _HRI_SUPC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) +#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SUPC_CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_supc_bodcore_reg_t; +typedef uint32_t hri_supc_bodvdd_reg_t; +typedef uint32_t hri_supc_intenset_reg_t; +typedef uint32_t hri_supc_intflag_reg_t; +typedef uint32_t hri_supc_status_reg_t; +typedef uint32_t hri_supc_vref_reg_t; +typedef uint32_t hri_supc_vreg_reg_t; + +static inline bool hri_supc_get_INTFLAG_BODVDDRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODVDDRDY) >> SUPC_INTFLAG_BODVDDRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BODVDDRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODVDDRDY; +} + +static inline bool hri_supc_get_INTFLAG_BODVDDDET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODVDDDET) >> SUPC_INTFLAG_BODVDDDET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BODVDDDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODVDDDET; +} + +static inline bool hri_supc_get_INTFLAG_BVDDSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BVDDSRDY) >> SUPC_INTFLAG_BVDDSRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BVDDSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BVDDSRDY; +} + +static inline bool hri_supc_get_INTFLAG_BODCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODCORERDY) >> SUPC_INTFLAG_BODCORERDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BODCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODCORERDY; +} + +static inline bool hri_supc_get_INTFLAG_BODCOREDET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODCOREDET) >> SUPC_INTFLAG_BODCOREDET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BODCOREDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODCOREDET; +} + +static inline bool hri_supc_get_INTFLAG_BCORESRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BCORESRDY) >> SUPC_INTFLAG_BCORESRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BCORESRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BCORESRDY; +} + +static inline bool hri_supc_get_interrupt_BODVDDRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODVDDRDY) >> SUPC_INTFLAG_BODVDDRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BODVDDRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODVDDRDY; +} + +static inline bool hri_supc_get_interrupt_BODVDDDET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODVDDDET) >> SUPC_INTFLAG_BODVDDDET_Pos; +} + +static inline void hri_supc_clear_interrupt_BODVDDDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODVDDDET; +} + +static inline bool hri_supc_get_interrupt_BVDDSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BVDDSRDY) >> SUPC_INTFLAG_BVDDSRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BVDDSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BVDDSRDY; +} + +static inline bool hri_supc_get_interrupt_BODCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODCORERDY) >> SUPC_INTFLAG_BODCORERDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BODCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODCORERDY; +} + +static inline bool hri_supc_get_interrupt_BODCOREDET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODCOREDET) >> SUPC_INTFLAG_BODCOREDET_Pos; +} + +static inline void hri_supc_clear_interrupt_BODCOREDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODCOREDET; +} + +static inline bool hri_supc_get_interrupt_BCORESRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BCORESRDY) >> SUPC_INTFLAG_BCORESRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BCORESRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BCORESRDY; +} + +static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) +{ + return ((Supc *)hw)->INTFLAG.reg; +} + +static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + ((Supc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_supc_set_INTEN_BODVDDRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODVDDRDY; +} + +static inline bool hri_supc_get_INTEN_BODVDDRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BODVDDRDY) >> SUPC_INTENSET_BODVDDRDY_Pos; +} + +static inline void hri_supc_write_INTEN_BODVDDRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODVDDRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODVDDRDY; + } +} + +static inline void hri_supc_clear_INTEN_BODVDDRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODVDDRDY; +} + +static inline void hri_supc_set_INTEN_BODVDDDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODVDDDET; +} + +static inline bool hri_supc_get_INTEN_BODVDDDET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BODVDDDET) >> SUPC_INTENSET_BODVDDDET_Pos; +} + +static inline void hri_supc_write_INTEN_BODVDDDET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODVDDDET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODVDDDET; + } +} + +static inline void hri_supc_clear_INTEN_BODVDDDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODVDDDET; +} + +static inline void hri_supc_set_INTEN_BVDDSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BVDDSRDY; +} + +static inline bool hri_supc_get_INTEN_BVDDSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BVDDSRDY) >> SUPC_INTENSET_BVDDSRDY_Pos; +} + +static inline void hri_supc_write_INTEN_BVDDSRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BVDDSRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BVDDSRDY; + } +} + +static inline void hri_supc_clear_INTEN_BVDDSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BVDDSRDY; +} + +static inline void hri_supc_set_INTEN_BODCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODCORERDY; +} + +static inline bool hri_supc_get_INTEN_BODCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BODCORERDY) >> SUPC_INTENSET_BODCORERDY_Pos; +} + +static inline void hri_supc_write_INTEN_BODCORERDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODCORERDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODCORERDY; + } +} + +static inline void hri_supc_clear_INTEN_BODCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODCORERDY; +} + +static inline void hri_supc_set_INTEN_BODCOREDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODCOREDET; +} + +static inline bool hri_supc_get_INTEN_BODCOREDET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BODCOREDET) >> SUPC_INTENSET_BODCOREDET_Pos; +} + +static inline void hri_supc_write_INTEN_BODCOREDET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODCOREDET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODCOREDET; + } +} + +static inline void hri_supc_clear_INTEN_BODCOREDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODCOREDET; +} + +static inline void hri_supc_set_INTEN_BCORESRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BCORESRDY; +} + +static inline bool hri_supc_get_INTEN_BCORESRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BCORESRDY) >> SUPC_INTENSET_BCORESRDY_Pos; +} + +static inline void hri_supc_write_INTEN_BCORESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BCORESRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BCORESRDY; + } +} + +static inline void hri_supc_clear_INTEN_BCORESRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BCORESRDY; +} + +static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENSET.reg = mask; +} + +static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) +{ + return ((Supc *)hw)->INTENSET.reg; +} + +static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) +{ + ((Supc *)hw)->INTENSET.reg = data; + ((Supc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_supc_get_STATUS_BODVDDRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BODVDDRDY) >> SUPC_STATUS_BODVDDRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BODVDDDET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BODVDDDET) >> SUPC_STATUS_BODVDDDET_Pos; +} + +static inline bool hri_supc_get_STATUS_BVDDSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BVDDSRDY) >> SUPC_STATUS_BVDDSRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BODCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BODCORERDY) >> SUPC_STATUS_BODCORERDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BODCOREDET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BODCOREDET) >> SUPC_STATUS_BODCOREDET_Pos; +} + +static inline bool hri_supc_get_STATUS_BCORESRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BCORESRDY) >> SUPC_STATUS_BCORESRDY_Pos; +} + +static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) +{ + return ((Supc *)hw)->STATUS.reg; +} + +static inline void hri_supc_set_BODVDD_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODVDD_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_ENABLE) >> SUPC_BODVDD_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODVDD_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_ENABLE; + tmp |= value << SUPC_BODVDD_ENABLE_Pos; + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODVDD_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODVDD_HYST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_HYST) >> SUPC_BODVDD_HYST_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODVDD_HYST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_HYST; + tmp |= value << SUPC_BODVDD_HYST_Pos; + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODVDD_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODVDD_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_STDBYCFG) >> SUPC_BODVDD_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODVDD_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_STDBYCFG; + tmp |= value << SUPC_BODVDD_STDBYCFG_Pos; + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODVDD_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODVDD_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_RUNSTDBY) >> SUPC_BODVDD_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODVDD_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_RUNSTDBY; + tmp |= value << SUPC_BODVDD_RUNSTDBY_Pos; + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODVDD_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODVDD_ACTCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_ACTCFG) >> SUPC_BODVDD_ACTCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODVDD_ACTCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_ACTCFG; + tmp |= value << SUPC_BODVDD_ACTCFG_Pos; + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODVDD_ACTION_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_get_BODVDD_ACTION_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_ACTION(mask)) >> SUPC_BODVDD_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BODVDD_ACTION_bf(const void *const hw, hri_supc_bodvdd_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_ACTION_Msk; + tmp |= SUPC_BODVDD_ACTION(data); + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_ACTION_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_ACTION_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_read_BODVDD_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_ACTION_Msk) >> SUPC_BODVDD_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BODVDD_PSEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_get_BODVDD_PSEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_PSEL(mask)) >> SUPC_BODVDD_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BODVDD_PSEL_bf(const void *const hw, hri_supc_bodvdd_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_PSEL_Msk; + tmp |= SUPC_BODVDD_PSEL(data); + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_PSEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_PSEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_read_BODVDD_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_PSEL_Msk) >> SUPC_BODVDD_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BODVDD_LEVEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_get_BODVDD_LEVEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_LEVEL(mask)) >> SUPC_BODVDD_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BODVDD_LEVEL_bf(const void *const hw, hri_supc_bodvdd_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_LEVEL_Msk; + tmp |= SUPC_BODVDD_LEVEL(data); + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_LEVEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_LEVEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_read_BODVDD_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_LEVEL_Msk) >> SUPC_BODVDD_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BODVDD_reg(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_get_BODVDD_reg(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BODVDD_reg(const void *const hw, hri_supc_bodvdd_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_reg(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_reg(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_read_BODVDD_reg(const void *const hw) +{ + return ((Supc *)hw)->BODVDD.reg; +} + +static inline void hri_supc_set_BODCORE_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODCORE_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_ENABLE) >> SUPC_BODCORE_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODCORE_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_ENABLE; + tmp |= value << SUPC_BODCORE_ENABLE_Pos; + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODCORE_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODCORE_HYST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_HYST) >> SUPC_BODCORE_HYST_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODCORE_HYST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_HYST; + tmp |= value << SUPC_BODCORE_HYST_Pos; + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODCORE_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODCORE_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_STDBYCFG) >> SUPC_BODCORE_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODCORE_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_STDBYCFG; + tmp |= value << SUPC_BODCORE_STDBYCFG_Pos; + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODCORE_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODCORE_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_RUNSTDBY) >> SUPC_BODCORE_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODCORE_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_RUNSTDBY; + tmp |= value << SUPC_BODCORE_RUNSTDBY_Pos; + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODCORE_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODCORE_ACTCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_ACTCFG) >> SUPC_BODCORE_ACTCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODCORE_ACTCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_ACTCFG; + tmp |= value << SUPC_BODCORE_ACTCFG_Pos; + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODCORE_ACTION_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_get_BODCORE_ACTION_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_ACTION(mask)) >> SUPC_BODCORE_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BODCORE_ACTION_bf(const void *const hw, hri_supc_bodcore_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_ACTION_Msk; + tmp |= SUPC_BODCORE_ACTION(data); + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_ACTION_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_ACTION_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_read_BODCORE_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_ACTION_Msk) >> SUPC_BODCORE_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BODCORE_PSEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_get_BODCORE_PSEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_PSEL(mask)) >> SUPC_BODCORE_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BODCORE_PSEL_bf(const void *const hw, hri_supc_bodcore_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_PSEL_Msk; + tmp |= SUPC_BODCORE_PSEL(data); + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_PSEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_PSEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_read_BODCORE_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_PSEL_Msk) >> SUPC_BODCORE_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BODCORE_LEVEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_get_BODCORE_LEVEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_LEVEL(mask)) >> SUPC_BODCORE_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BODCORE_LEVEL_bf(const void *const hw, hri_supc_bodcore_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_LEVEL_Msk; + tmp |= SUPC_BODCORE_LEVEL(data); + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_LEVEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_LEVEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_read_BODCORE_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_LEVEL_Msk) >> SUPC_BODCORE_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BODCORE_reg(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_get_BODCORE_reg(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BODCORE_reg(const void *const hw, hri_supc_bodcore_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_reg(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_reg(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_read_BODCORE_reg(const void *const hw) +{ + return ((Supc *)hw)->BODCORE.reg; +} + +static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_ENABLE; + tmp |= value << SUPC_VREG_ENABLE_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_RUNSTDBY) >> SUPC_VREG_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_RUNSTDBY; + tmp |= value << SUPC_VREG_RUNSTDBY_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) +{ + return ((Supc *)hw)->VREG.reg; +} + +static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSEN; + tmp |= value << SUPC_VREF_TSEN_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_VREFOE; + tmp |= value << SUPC_VREF_VREFOE_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_RUNSTDBY; + tmp |= value << SUPC_VREF_RUNSTDBY_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_ONDEMAND; + tmp |= value << SUPC_VREF_ONDEMAND_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_SEL_Msk; + tmp |= SUPC_VREF_SEL(data); + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) +{ + return ((Supc *)hw)->VREF.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SUPC_C21_H_INCLUDED */ +#endif /* _SAMC21_SUPC_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_systemcontrol_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_systemcontrol_c21.h new file mode 100644 index 0000000..9008baf --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_systemcontrol_c21.h @@ -0,0 +1,498 @@ +/** + * \file + * + * \brief SAM SystemControl + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_SystemControl_COMPONENT_ +#ifndef _HRI_SystemControl_C21_H_INCLUDED_ +#define _HRI_SystemControl_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS) +#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SystemControl_CRITICAL_SECTION_ENTER() +#define SystemControl_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_systemcontrol_aircr_reg_t; +typedef uint32_t hri_systemcontrol_ccr_reg_t; +typedef uint32_t hri_systemcontrol_cpuid_reg_t; +typedef uint32_t hri_systemcontrol_dfsr_reg_t; +typedef uint32_t hri_systemcontrol_icsr_reg_t; +typedef uint32_t hri_systemcontrol_scr_reg_t; +typedef uint32_t hri_systemcontrol_shcsr_reg_t; +typedef uint32_t hri_systemcontrol_shpr2_reg_t; +typedef uint32_t hri_systemcontrol_shpr3_reg_t; +typedef uint32_t hri_systemcontrol_vtor_reg_t; + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION(mask)) >> 0; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION_Msk) >> 0; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO(mask)) >> 4; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO_Msk) >> 4; +} + +static inline hri_systemcontrol_cpuid_reg_t +hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE(mask)) >> 16; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE_Msk) >> 16; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT(mask)) >> 20; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT_Msk) >> 20; +} + +static inline hri_systemcontrol_cpuid_reg_t +hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->CPUID.reg; +} + +static inline bool hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void *const hw) +{ + return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_UNALIGN_TRP) >> 3; +} + +static inline bool hri_systemcontrol_get_CCR_STKALIGN_bit(const void *const hw) +{ + return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_STKALIGN) >> 9; +} + +static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const hw, + hri_systemcontrol_ccr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CCR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->CCR.reg; +} + +static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const hw, + hri_systemcontrol_icsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->ICSR.reg; +} + +static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const hw, + hri_systemcontrol_vtor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->VTOR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->VTOR.reg; +} + +static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const hw, + hri_systemcontrol_aircr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->AIRCR.reg; +} + +static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const hw, + hri_systemcontrol_scr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SCR.reg; +} + +static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const hw, + hri_systemcontrol_shpr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHPR2.reg; +} + +static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const hw, + hri_systemcontrol_shpr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR3.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHPR3.reg; +} + +static inline void hri_systemcontrol_set_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_get_SHCSR_reg(const void *const hw, + hri_systemcontrol_shcsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHCSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_read_SHCSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHCSR.reg; +} + +static inline void hri_systemcontrol_set_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_get_DFSR_reg(const void *const hw, + hri_systemcontrol_dfsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->DFSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_read_DFSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->DFSR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SystemControl_C21_H_INCLUDED */ +#endif /* _SAMC21_SystemControl_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_systick_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_systick_c21.h new file mode 100644 index 0000000..9ef6146 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_systick_c21.h @@ -0,0 +1,219 @@ +/** + * \file + * + * \brief SAM SysTick + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_SysTick_COMPONENT_ +#ifndef _HRI_SysTick_C21_H_INCLUDED_ +#define _HRI_SysTick_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SysTick_CRITICAL_SECTIONS) +#define SysTick_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SysTick_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SysTick_CRITICAL_SECTION_ENTER() +#define SysTick_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_systick_calib_reg_t; +typedef uint32_t hri_systick_csr_reg_t; +typedef uint32_t hri_systick_cvr_reg_t; +typedef uint32_t hri_systick_rvr_reg_t; + +static inline bool hri_systick_get_CALIB_SKEW_bit(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_SKEW) >> 30; +} + +static inline bool hri_systick_get_CALIB_NOREF_bit(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_NOREF) >> 31; +} + +static inline hri_systick_calib_reg_t hri_systick_get_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS(mask)) >> 0; +} + +static inline hri_systick_calib_reg_t hri_systick_read_CALIB_TENMS_bf(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS_Msk) >> 0; +} + +static inline hri_systick_calib_reg_t hri_systick_get_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systick_calib_reg_t hri_systick_read_CALIB_reg(const void *const hw) +{ + return ((Systick *)hw)->CALIB.reg; +} + +static inline void hri_systick_set_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_csr_reg_t hri_systick_get_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_CSR_reg(const void *const hw, hri_systick_csr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_csr_reg_t hri_systick_read_CSR_reg(const void *const hw) +{ + return ((Systick *)hw)->CSR.reg; +} + +static inline void hri_systick_set_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_rvr_reg_t hri_systick_get_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->RVR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_RVR_reg(const void *const hw, hri_systick_rvr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_rvr_reg_t hri_systick_read_RVR_reg(const void *const hw) +{ + return ((Systick *)hw)->RVR.reg; +} + +static inline void hri_systick_set_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_cvr_reg_t hri_systick_get_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CVR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_CVR_reg(const void *const hw, hri_systick_cvr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_cvr_reg_t hri_systick_read_CVR_reg(const void *const hw) +{ + return ((Systick *)hw)->CVR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SysTick_C21_H_INCLUDED */ +#endif /* _SAMC21_SysTick_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_tc_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_tc_c21.h new file mode 100644 index 0000000..6f36089 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_tc_c21.h @@ -0,0 +1,2899 @@ +/** + * \file + * + * \brief SAM TC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_TC_COMPONENT_ +#ifndef _HRI_TC_C21_H_INCLUDED_ +#define _HRI_TC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TC_CRITICAL_SECTIONS) +#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TC_CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tc_evctrl_reg_t; +typedef uint16_t hri_tccount16_cc_reg_t; +typedef uint16_t hri_tccount16_ccbuf_reg_t; +typedef uint16_t hri_tccount16_count_reg_t; +typedef uint32_t hri_tc_ctrla_reg_t; +typedef uint32_t hri_tc_syncbusy_reg_t; +typedef uint32_t hri_tccount32_cc_reg_t; +typedef uint32_t hri_tccount32_ccbuf_reg_t; +typedef uint32_t hri_tccount32_count_reg_t; +typedef uint8_t hri_tc_ctrlbset_reg_t; +typedef uint8_t hri_tc_dbgctrl_reg_t; +typedef uint8_t hri_tc_drvctrl_reg_t; +typedef uint8_t hri_tc_intenset_reg_t; +typedef uint8_t hri_tc_intflag_reg_t; +typedef uint8_t hri_tc_status_reg_t; +typedef uint8_t hri_tc_wave_reg_t; +typedef uint8_t hri_tccount8_cc_reg_t; +typedef uint8_t hri_tccount8_ccbuf_reg_t; +typedef uint8_t hri_tccount8_count_reg_t; +typedef uint8_t hri_tccount8_per_reg_t; +typedef uint8_t hri_tccount8_perbuf_reg_t; + +static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; +} + +static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTFLAG.reg; +} + +static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = mask; +} + +static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; +} + +static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; + } +} + +static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; +} + +static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; +} + +static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; + } +} + +static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; +} + +static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; +} + +static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data); + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); +} + +static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); +} + +static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = mask; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.CTRLBSET.reg; +} + +static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = data; + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data; +} + +static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask; +} + +static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; +} + +static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; +} + +static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; + } +} + +static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; +} + +static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; +} + +static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; +} + +static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; + } +} + +static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; +} + +static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; +} + +static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; +} + +static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; + } +} + +static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; +} + +static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; +} + +static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; +} + +static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; + } +} + +static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; +} + +static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = mask; +} + +static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTENSET.reg; +} + +static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = data; + ((Tc *)hw)->COUNT16.INTENCLR.reg = ~data; +} + +static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = mask; +} + +static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.SYNCBUSY.reg; +} + +static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ENABLE; + tmp |= value << TC_CTRLA_ENABLE_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_RUNSTDBY; + tmp |= value << TC_CTRLA_RUNSTDBY_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ONDEMAND; + tmp |= value << TC_CTRLA_ONDEMAND_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ALOCK; + tmp |= value << TC_CTRLA_ALOCK_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN0; + tmp |= value << TC_CTRLA_CAPTEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN1; + tmp |= value << TC_CTRLA_CAPTEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN0; + tmp |= value << TC_CTRLA_COPEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN1; + tmp |= value << TC_CTRLA_COPEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_MODE_Msk; + tmp |= TC_CTRLA_MODE(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCSYNC_Msk; + tmp |= TC_CTRLA_PRESCSYNC(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCALER_Msk; + tmp |= TC_CTRLA_PRESCALER(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + return ((Tc *)hw)->COUNT16.CTRLA.reg; +} + +static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCINV; + tmp |= value << TC_EVCTRL_TCINV_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCEI; + tmp |= value << TC_EVCTRL_TCEI_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_OVFEO; + tmp |= value << TC_EVCTRL_OVFEO_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO0; + tmp |= value << TC_EVCTRL_MCEO0_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO1; + tmp |= value << TC_EVCTRL_MCEO1_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_EVACT_Msk; + tmp |= TC_EVCTRL_EVACT(data); + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.EVCTRL.reg; +} + +static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= ~TC_WAVE_WAVEGEN_Msk; + tmp |= TC_WAVE_WAVEGEN(data); + ((Tc *)hw)->COUNT16.WAVE.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.WAVE.reg; +} + +static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN0; + tmp |= value << TC_DRVCTRL_INVEN0_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN1; + tmp |= value << TC_DRVCTRL_INVEN1_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DRVCTRL.reg; +} + +static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= ~TC_DBGCTRL_DBGRUN; + tmp |= value << TC_DBGCTRL_DBGRUN_Pos; + ((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DBGCTRL.reg; +} + +static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; + tmp |= TC_COUNT8_COUNT_COUNT(data); + ((Tc *)hw)->COUNT8.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT8.COUNT.reg; +} + +static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; + tmp |= TC_COUNT16_COUNT_COUNT(data); + ((Tc *)hw)->COUNT16.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT16.COUNT.reg; +} + +static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; + tmp |= TC_COUNT32_COUNT_COUNT(data); + ((Tc *)hw)->COUNT32.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT32.COUNT.reg; +} + +static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= ~TC_COUNT8_PER_PER_Msk; + tmp |= TC_COUNT8_PER_PER(data); + ((Tc *)hw)->COUNT8.PER.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + return ((Tc *)hw)->COUNT8.PER.reg; +} + +static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= ~TC_COUNT8_CC_CC_Msk; + tmp |= TC_COUNT8_CC_CC(data); + ((Tc *)hw)->COUNT8.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT8.CC[index].reg; +} + +static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= ~TC_COUNT16_CC_CC_Msk; + tmp |= TC_COUNT16_CC_CC(data); + ((Tc *)hw)->COUNT16.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT16.CC[index].reg; +} + +static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= ~TC_COUNT32_CC_CC_Msk; + tmp |= TC_COUNT32_CC_CC(data); + ((Tc *)hw)->COUNT32.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT32.CC[index].reg; +} + +static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; + tmp |= TC_COUNT8_PERBUF_PERBUF(data); + ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.PERBUF.reg; +} + +static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT8_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.CCBUF[index].reg; +} + +static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT16_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.CCBUF[index].reg; +} + +static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT32_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT32.CCBUF[index].reg; +} + +static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; +} + +static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; +} + +static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b) +#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b) +#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b) +#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b) +#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b) +#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a) +#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b) +#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b) +#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b) +#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b) +#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b) +#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a) +#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b) +#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b) +#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b) +#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b) +#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b) +#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a) +#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b) +#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b) +#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b) +#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b) +#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b) +#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TC_C21_H_INCLUDED */ +#endif /* _SAMC21_TC_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_tcc_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_tcc_c21.h new file mode 100644 index 0000000..bbaa631 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_tcc_c21.h @@ -0,0 +1,9462 @@ +/** + * \file + * + * \brief SAM TCC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_TCC_COMPONENT_ +#ifndef _HRI_TCC_C21_H_INCLUDED_ +#define _HRI_TCC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TCC_CRITICAL_SECTIONS) +#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TCC_CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tcc_patt_reg_t; +typedef uint16_t hri_tcc_pattbuf_reg_t; +typedef uint32_t hri_tcc_cc_reg_t; +typedef uint32_t hri_tcc_ccbuf_reg_t; +typedef uint32_t hri_tcc_count_reg_t; +typedef uint32_t hri_tcc_ctrla_reg_t; +typedef uint32_t hri_tcc_drvctrl_reg_t; +typedef uint32_t hri_tcc_evctrl_reg_t; +typedef uint32_t hri_tcc_fctrla_reg_t; +typedef uint32_t hri_tcc_fctrlb_reg_t; +typedef uint32_t hri_tcc_intenset_reg_t; +typedef uint32_t hri_tcc_intflag_reg_t; +typedef uint32_t hri_tcc_per_reg_t; +typedef uint32_t hri_tcc_perbuf_reg_t; +typedef uint32_t hri_tcc_status_reg_t; +typedef uint32_t hri_tcc_syncbusy_reg_t; +typedef uint32_t hri_tcc_wave_reg_t; +typedef uint32_t hri_tcc_wexctrl_reg_t; +typedef uint8_t hri_tcc_ctrlbset_reg_t; +typedef uint8_t hri_tcc_dbgctrl_reg_t; + +static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + while (((Tcc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + return ((Tcc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTFLAG.reg; +} + +static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + ((Tcc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; +} + +static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; + } +} + +static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; +} + +static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; +} + +static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; + } +} + +static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; +} + +static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); +} + +static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); +} + +static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->CTRLBSET.reg; +} + +static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = data; + ((Tcc *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; +} + +static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; +} + +static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; + } +} + +static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; +} + +static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; +} + +static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; +} + +static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; + } +} + +static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; +} + +static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; +} + +static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; +} + +static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; + } +} + +static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; +} + +static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; +} + +static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; +} + +static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; + } +} + +static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; +} + +static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; +} + +static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos; +} + +static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; + } +} + +static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; +} + +static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; +} + +static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; +} + +static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; + } +} + +static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; +} + +static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; +} + +static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; +} + +static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; +} + +static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; +} + +static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; +} + +static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; +} + +static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; +} + +static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; +} + +static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; +} + +static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; +} + +static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; + } +} + +static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; +} + +static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; +} + +static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; +} + +static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; + } +} + +static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; +} + +static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; +} + +static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; +} + +static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; + } +} + +static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; +} + +static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; +} + +static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; +} + +static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; + } +} + +static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; +} + +static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENSET.reg = mask; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTENSET.reg; +} + +static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) +{ + ((Tcc *)hw)->INTENSET.reg = data; + ((Tcc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tcc *)hw)->SYNCBUSY.reg; +} + +static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ENABLE; + tmp |= value << TCC_CTRLA_ENABLE_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RUNSTDBY; + tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ALOCK; + tmp |= value << TCC_CTRLA_ALOCK_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_MSYNC; + tmp |= value << TCC_CTRLA_MSYNC_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_DMAOS; + tmp |= value << TCC_CTRLA_DMAOS_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN0; + tmp |= value << TCC_CTRLA_CPTEN0_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN1; + tmp |= value << TCC_CTRLA_CPTEN1_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN2; + tmp |= value << TCC_CTRLA_CPTEN2_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN3; + tmp |= value << TCC_CTRLA_CPTEN3_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RESOLUTION_Msk; + tmp |= TCC_CTRLA_RESOLUTION(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCALER_Msk; + tmp |= TCC_CTRLA_PRESCALER(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; + tmp |= TCC_CTRLA_PRESCSYNC(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + return ((Tcc *)hw)->CTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_KEEP; + tmp |= value << TCC_FCTRLA_KEEP_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_QUAL; + tmp |= value << TCC_FCTRLA_QUAL_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_RESTART; + tmp |= value << TCC_FCTRLA_RESTART_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKPRESC; + tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_SRC_Msk; + tmp |= TCC_FCTRLA_SRC(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANK_Msk; + tmp |= TCC_FCTRLA_BLANK(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_HALT_Msk; + tmp |= TCC_FCTRLA_HALT(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CHSEL_Msk; + tmp |= TCC_FCTRLA_CHSEL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CAPTURE_Msk; + tmp |= TCC_FCTRLA_CAPTURE(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; + tmp |= TCC_FCTRLA_BLANKVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; + tmp |= TCC_FCTRLA_FILTERVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_KEEP; + tmp |= value << TCC_FCTRLB_KEEP_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_QUAL; + tmp |= value << TCC_FCTRLB_QUAL_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_RESTART; + tmp |= value << TCC_FCTRLB_RESTART_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKPRESC; + tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_SRC_Msk; + tmp |= TCC_FCTRLB_SRC(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANK_Msk; + tmp |= TCC_FCTRLB_BLANK(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_HALT_Msk; + tmp |= TCC_FCTRLB_HALT(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CHSEL_Msk; + tmp |= TCC_FCTRLB_CHSEL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CAPTURE_Msk; + tmp |= TCC_FCTRLB_CAPTURE(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; + tmp |= TCC_FCTRLB_BLANKVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; + tmp |= TCC_FCTRLB_FILTERVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLB.reg; +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN0; + tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN1; + tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN2; + tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN3; + tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_OTMX_Msk; + tmp |= TCC_WEXCTRL_OTMX(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTLS_Msk; + tmp |= TCC_WEXCTRL_DTLS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTHS_Msk; + tmp |= TCC_WEXCTRL_DTHS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->WEXCTRL.reg; +} + +static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE0; + tmp |= value << TCC_DRVCTRL_NRE0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE1; + tmp |= value << TCC_DRVCTRL_NRE1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE2; + tmp |= value << TCC_DRVCTRL_NRE2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE3; + tmp |= value << TCC_DRVCTRL_NRE3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE4; + tmp |= value << TCC_DRVCTRL_NRE4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE5; + tmp |= value << TCC_DRVCTRL_NRE5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE6; + tmp |= value << TCC_DRVCTRL_NRE6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE7; + tmp |= value << TCC_DRVCTRL_NRE7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV0; + tmp |= value << TCC_DRVCTRL_NRV0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV1; + tmp |= value << TCC_DRVCTRL_NRV1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV2; + tmp |= value << TCC_DRVCTRL_NRV2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV3; + tmp |= value << TCC_DRVCTRL_NRV3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV4; + tmp |= value << TCC_DRVCTRL_NRV4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV5; + tmp |= value << TCC_DRVCTRL_NRV5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV6; + tmp |= value << TCC_DRVCTRL_NRV6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV7; + tmp |= value << TCC_DRVCTRL_NRV7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN0; + tmp |= value << TCC_DRVCTRL_INVEN0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN1; + tmp |= value << TCC_DRVCTRL_INVEN1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN2; + tmp |= value << TCC_DRVCTRL_INVEN2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN3; + tmp |= value << TCC_DRVCTRL_INVEN3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN4; + tmp |= value << TCC_DRVCTRL_INVEN4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN5; + tmp |= value << TCC_DRVCTRL_INVEN5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN6; + tmp |= value << TCC_DRVCTRL_INVEN6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN7; + tmp |= value << TCC_DRVCTRL_INVEN7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL0(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL1(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DRVCTRL.reg; +} + +static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_DBGRUN; + tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_FDDBD; + tmp |= value << TCC_DBGCTRL_FDDBD_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DBGCTRL.reg; +} + +static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_OVFEO; + tmp |= value << TCC_EVCTRL_OVFEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TRGEO; + tmp |= value << TCC_EVCTRL_TRGEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTEO; + tmp |= value << TCC_EVCTRL_CNTEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV0; + tmp |= value << TCC_EVCTRL_TCINV0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV1; + tmp |= value << TCC_EVCTRL_TCINV1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI0; + tmp |= value << TCC_EVCTRL_TCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI1; + tmp |= value << TCC_EVCTRL_TCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI0; + tmp |= value << TCC_EVCTRL_MCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI1; + tmp |= value << TCC_EVCTRL_MCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI2; + tmp |= value << TCC_EVCTRL_MCEI2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI3; + tmp |= value << TCC_EVCTRL_MCEI3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO0; + tmp |= value << TCC_EVCTRL_MCEO0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO1; + tmp |= value << TCC_EVCTRL_MCEO1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO2; + tmp |= value << TCC_EVCTRL_MCEO2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO3; + tmp |= value << TCC_EVCTRL_MCEO3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT0_Msk; + tmp |= TCC_EVCTRL_EVACT0(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT1_Msk; + tmp |= TCC_EVCTRL_EVACT1(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTSEL_Msk; + tmp |= TCC_EVCTRL_CNTSEL(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->EVCTRL.reg; +} + +static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE0; + tmp |= value << TCC_PATT_PGE0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE1; + tmp |= value << TCC_PATT_PGE1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE2; + tmp |= value << TCC_PATT_PGE2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE3; + tmp |= value << TCC_PATT_PGE3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE4; + tmp |= value << TCC_PATT_PGE4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE5; + tmp |= value << TCC_PATT_PGE5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE6; + tmp |= value << TCC_PATT_PGE6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE7; + tmp |= value << TCC_PATT_PGE7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV0; + tmp |= value << TCC_PATT_PGV0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV1; + tmp |= value << TCC_PATT_PGV1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV2; + tmp |= value << TCC_PATT_PGV2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV3; + tmp |= value << TCC_PATT_PGV3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV4; + tmp |= value << TCC_PATT_PGV4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV5; + tmp |= value << TCC_PATT_PGV5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV6; + tmp |= value << TCC_PATT_PGV6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV7; + tmp |= value << TCC_PATT_PGV7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + uint16_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->PATT.reg; +} + +static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CIPEREN; + tmp |= value << TCC_WAVE_CIPEREN_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN0; + tmp |= value << TCC_WAVE_CICCEN0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN1; + tmp |= value << TCC_WAVE_CICCEN1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN2; + tmp |= value << TCC_WAVE_CICCEN2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN3; + tmp |= value << TCC_WAVE_CICCEN3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL0; + tmp |= value << TCC_WAVE_POL0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL1; + tmp |= value << TCC_WAVE_POL1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL2; + tmp |= value << TCC_WAVE_POL2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL3; + tmp |= value << TCC_WAVE_POL3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP0; + tmp |= value << TCC_WAVE_SWAP0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP1; + tmp |= value << TCC_WAVE_SWAP1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP2; + tmp |= value << TCC_WAVE_SWAP2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP3; + tmp |= value << TCC_WAVE_SWAP3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_WAVEGEN_Msk; + tmp |= TCC_WAVE_WAVEGEN(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_RAMP_Msk; + tmp |= TCC_WAVE_RAMP(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->WAVE.reg; +} + +static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH4_DITHER_Msk; + tmp |= TCC_PER_DITH4_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH5_DITHER_Msk; + tmp |= TCC_PER_DITH5_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH6_DITHER_Msk; + tmp |= TCC_PER_DITH6_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH4_DITHER_Msk; + tmp |= TCC_CC_DITH4_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH5_DITHER_Msk; + tmp |= TCC_CC_DITH5_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH6_DITHER_Msk; + tmp |= TCC_CC_DITH6_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB0; + tmp |= value << TCC_PATTBUF_PGEB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB1; + tmp |= value << TCC_PATTBUF_PGEB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB2; + tmp |= value << TCC_PATTBUF_PGEB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB3; + tmp |= value << TCC_PATTBUF_PGEB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB4; + tmp |= value << TCC_PATTBUF_PGEB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB5; + tmp |= value << TCC_PATTBUF_PGEB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB6; + tmp |= value << TCC_PATTBUF_PGEB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB7; + tmp |= value << TCC_PATTBUF_PGEB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB0; + tmp |= value << TCC_PATTBUF_PGVB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB1; + tmp |= value << TCC_PATTBUF_PGVB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB2; + tmp |= value << TCC_PATTBUF_PGVB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB3; + tmp |= value << TCC_PATTBUF_PGVB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB4; + tmp |= value << TCC_PATTBUF_PGVB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB5; + tmp |= value << TCC_PATTBUF_PGVB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB6; + tmp |= value << TCC_PATTBUF_PGVB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB7; + tmp |= value << TCC_PATTBUF_PGVB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PATTBUF.reg; +} + +static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERBUF.reg; +} + +static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCBUF[index].reg; +} + +static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; +} + +static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; +} + +static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; +} + +static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TCC_C21_H_INCLUDED */ +#endif /* _SAMC21_TCC_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_tsens_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_tsens_c21.h new file mode 100644 index 0000000..596ad8a --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_tsens_c21.h @@ -0,0 +1,1396 @@ +/** + * \file + * + * \brief SAM TSENS + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_TSENS_COMPONENT_ +#ifndef _HRI_TSENS_C21_H_INCLUDED_ +#define _HRI_TSENS_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TSENS_CRITICAL_SECTIONS) +#define TSENS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TSENS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TSENS_CRITICAL_SECTION_ENTER() +#define TSENS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_tsens_cal_reg_t; +typedef uint32_t hri_tsens_gain_reg_t; +typedef uint32_t hri_tsens_offset_reg_t; +typedef uint32_t hri_tsens_syncbusy_reg_t; +typedef uint32_t hri_tsens_value_reg_t; +typedef uint32_t hri_tsens_winlt_reg_t; +typedef uint32_t hri_tsens_winut_reg_t; +typedef uint8_t hri_tsens_ctrla_reg_t; +typedef uint8_t hri_tsens_ctrlb_reg_t; +typedef uint8_t hri_tsens_ctrlc_reg_t; +typedef uint8_t hri_tsens_dbgctrl_reg_t; +typedef uint8_t hri_tsens_evctrl_reg_t; +typedef uint8_t hri_tsens_intenset_reg_t; +typedef uint8_t hri_tsens_intflag_reg_t; +typedef uint8_t hri_tsens_status_reg_t; + +static inline void hri_tsens_wait_for_sync(const void *const hw, hri_tsens_syncbusy_reg_t reg) +{ + while (((Tsens *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tsens_is_syncing(const void *const hw, hri_tsens_syncbusy_reg_t reg) +{ + return ((Tsens *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_tsens_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_RESRDY) >> TSENS_INTFLAG_RESRDY_Pos; +} + +static inline void hri_tsens_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_RESRDY; +} + +static inline bool hri_tsens_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_OVERRUN) >> TSENS_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_tsens_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_OVERRUN; +} + +static inline bool hri_tsens_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_WINMON) >> TSENS_INTFLAG_WINMON_Pos; +} + +static inline void hri_tsens_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_WINMON; +} + +static inline bool hri_tsens_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_OVF) >> TSENS_INTFLAG_OVF_Pos; +} + +static inline void hri_tsens_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_OVF; +} + +static inline bool hri_tsens_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_RESRDY) >> TSENS_INTFLAG_RESRDY_Pos; +} + +static inline void hri_tsens_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_RESRDY; +} + +static inline bool hri_tsens_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_OVERRUN) >> TSENS_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_tsens_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_OVERRUN; +} + +static inline bool hri_tsens_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_WINMON) >> TSENS_INTFLAG_WINMON_Pos; +} + +static inline void hri_tsens_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_WINMON; +} + +static inline bool hri_tsens_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_OVF) >> TSENS_INTFLAG_OVF_Pos; +} + +static inline void hri_tsens_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_OVF; +} + +static inline hri_tsens_intflag_reg_t hri_tsens_get_INTFLAG_reg(const void *const hw, hri_tsens_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tsens_intflag_reg_t hri_tsens_read_INTFLAG_reg(const void *const hw) +{ + return ((Tsens *)hw)->INTFLAG.reg; +} + +static inline void hri_tsens_clear_INTFLAG_reg(const void *const hw, hri_tsens_intflag_reg_t mask) +{ + ((Tsens *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_tsens_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_RESRDY; +} + +static inline bool hri_tsens_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTENSET.reg & TSENS_INTENSET_RESRDY) >> TSENS_INTENSET_RESRDY_Pos; +} + +static inline void hri_tsens_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_RESRDY; + } else { + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_RESRDY; + } +} + +static inline void hri_tsens_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_RESRDY; +} + +static inline void hri_tsens_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_OVERRUN; +} + +static inline bool hri_tsens_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTENSET.reg & TSENS_INTENSET_OVERRUN) >> TSENS_INTENSET_OVERRUN_Pos; +} + +static inline void hri_tsens_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_OVERRUN; + } else { + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_OVERRUN; + } +} + +static inline void hri_tsens_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_OVERRUN; +} + +static inline void hri_tsens_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_WINMON; +} + +static inline bool hri_tsens_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTENSET.reg & TSENS_INTENSET_WINMON) >> TSENS_INTENSET_WINMON_Pos; +} + +static inline void hri_tsens_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_WINMON; + } else { + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_WINMON; + } +} + +static inline void hri_tsens_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_WINMON; +} + +static inline void hri_tsens_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_OVF; +} + +static inline bool hri_tsens_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTENSET.reg & TSENS_INTENSET_OVF) >> TSENS_INTENSET_OVF_Pos; +} + +static inline void hri_tsens_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_OVF; + } else { + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_OVF; + } +} + +static inline void hri_tsens_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_OVF; +} + +static inline void hri_tsens_set_INTEN_reg(const void *const hw, hri_tsens_intenset_reg_t mask) +{ + ((Tsens *)hw)->INTENSET.reg = mask; +} + +static inline hri_tsens_intenset_reg_t hri_tsens_get_INTEN_reg(const void *const hw, hri_tsens_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tsens_intenset_reg_t hri_tsens_read_INTEN_reg(const void *const hw) +{ + return ((Tsens *)hw)->INTENSET.reg; +} + +static inline void hri_tsens_write_INTEN_reg(const void *const hw, hri_tsens_intenset_reg_t data) +{ + ((Tsens *)hw)->INTENSET.reg = data; + ((Tsens *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_tsens_clear_INTEN_reg(const void *const hw, hri_tsens_intenset_reg_t mask) +{ + ((Tsens *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_tsens_get_STATUS_OVF_bit(const void *const hw) +{ + return (((Tsens *)hw)->STATUS.reg & TSENS_STATUS_OVF) >> TSENS_STATUS_OVF_Pos; +} + +static inline hri_tsens_status_reg_t hri_tsens_get_STATUS_reg(const void *const hw, hri_tsens_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tsens_status_reg_t hri_tsens_read_STATUS_reg(const void *const hw) +{ + return ((Tsens *)hw)->STATUS.reg; +} + +static inline bool hri_tsens_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tsens *)hw)->SYNCBUSY.reg & TSENS_SYNCBUSY_SWRST) >> TSENS_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tsens_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tsens *)hw)->SYNCBUSY.reg & TSENS_SYNCBUSY_ENABLE) >> TSENS_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_tsens_syncbusy_reg_t hri_tsens_get_SYNCBUSY_reg(const void *const hw, hri_tsens_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tsens_syncbusy_reg_t hri_tsens_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tsens *)hw)->SYNCBUSY.reg; +} + +static inline hri_tsens_value_reg_t hri_tsens_get_VALUE_VALUE_bf(const void *const hw, hri_tsens_value_reg_t mask) +{ + return (((Tsens *)hw)->VALUE.reg & TSENS_VALUE_VALUE(mask)) >> TSENS_VALUE_VALUE_Pos; +} + +static inline hri_tsens_value_reg_t hri_tsens_read_VALUE_VALUE_bf(const void *const hw) +{ + return (((Tsens *)hw)->VALUE.reg & TSENS_VALUE_VALUE_Msk) >> TSENS_VALUE_VALUE_Pos; +} + +static inline hri_tsens_value_reg_t hri_tsens_get_VALUE_reg(const void *const hw, hri_tsens_value_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->VALUE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tsens_value_reg_t hri_tsens_read_VALUE_reg(const void *const hw) +{ + return ((Tsens *)hw)->VALUE.reg; +} + +static inline void hri_tsens_set_CTRLA_SWRST_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg |= TSENS_CTRLA_SWRST; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_SWRST); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_SWRST); + tmp = ((Tsens *)hw)->CTRLA.reg; + tmp = (tmp & TSENS_CTRLA_SWRST) >> TSENS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg |= TSENS_CTRLA_ENABLE; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_SWRST | TSENS_SYNCBUSY_ENABLE); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_SWRST | TSENS_SYNCBUSY_ENABLE); + tmp = ((Tsens *)hw)->CTRLA.reg; + tmp = (tmp & TSENS_CTRLA_ENABLE) >> TSENS_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->CTRLA.reg; + tmp &= ~TSENS_CTRLA_ENABLE; + tmp |= value << TSENS_CTRLA_ENABLE_Pos; + ((Tsens *)hw)->CTRLA.reg = tmp; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_SWRST | TSENS_SYNCBUSY_ENABLE); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg &= ~TSENS_CTRLA_ENABLE; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_SWRST | TSENS_SYNCBUSY_ENABLE); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg ^= TSENS_CTRLA_ENABLE; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_SWRST | TSENS_SYNCBUSY_ENABLE); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg |= TSENS_CTRLA_RUNSTDBY; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->CTRLA.reg; + tmp = (tmp & TSENS_CTRLA_RUNSTDBY) >> TSENS_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->CTRLA.reg; + tmp &= ~TSENS_CTRLA_RUNSTDBY; + tmp |= value << TSENS_CTRLA_RUNSTDBY_Pos; + ((Tsens *)hw)->CTRLA.reg = tmp; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg &= ~TSENS_CTRLA_RUNSTDBY; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg ^= TSENS_CTRLA_RUNSTDBY; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_set_CTRLA_reg(const void *const hw, hri_tsens_ctrla_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg |= mask; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_ctrla_reg_t hri_tsens_get_CTRLA_reg(const void *const hw, hri_tsens_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + tmp = ((Tsens *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_CTRLA_reg(const void *const hw, hri_tsens_ctrla_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg = data; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CTRLA_reg(const void *const hw, hri_tsens_ctrla_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg &= ~mask; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CTRLA_reg(const void *const hw, hri_tsens_ctrla_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg ^= mask; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_ctrla_reg_t hri_tsens_read_CTRLA_reg(const void *const hw) +{ + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + return ((Tsens *)hw)->CTRLA.reg; +} + +static inline void hri_tsens_set_CTRLC_FREERUN_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg |= TSENS_CTRLC_FREERUN; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_CTRLC_FREERUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->CTRLC.reg; + tmp = (tmp & TSENS_CTRLC_FREERUN) >> TSENS_CTRLC_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_write_CTRLC_FREERUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->CTRLC.reg; + tmp &= ~TSENS_CTRLC_FREERUN; + tmp |= value << TSENS_CTRLC_FREERUN_Pos; + ((Tsens *)hw)->CTRLC.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CTRLC_FREERUN_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg &= ~TSENS_CTRLC_FREERUN; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CTRLC_FREERUN_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg ^= TSENS_CTRLC_FREERUN; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_set_CTRLC_WINMODE_bf(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg |= TSENS_CTRLC_WINMODE(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_ctrlc_reg_t hri_tsens_get_CTRLC_WINMODE_bf(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->CTRLC.reg; + tmp = (tmp & TSENS_CTRLC_WINMODE(mask)) >> TSENS_CTRLC_WINMODE_Pos; + return tmp; +} + +static inline void hri_tsens_write_CTRLC_WINMODE_bf(const void *const hw, hri_tsens_ctrlc_reg_t data) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->CTRLC.reg; + tmp &= ~TSENS_CTRLC_WINMODE_Msk; + tmp |= TSENS_CTRLC_WINMODE(data); + ((Tsens *)hw)->CTRLC.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CTRLC_WINMODE_bf(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg &= ~TSENS_CTRLC_WINMODE(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CTRLC_WINMODE_bf(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg ^= TSENS_CTRLC_WINMODE(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_ctrlc_reg_t hri_tsens_read_CTRLC_WINMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->CTRLC.reg; + tmp = (tmp & TSENS_CTRLC_WINMODE_Msk) >> TSENS_CTRLC_WINMODE_Pos; + return tmp; +} + +static inline void hri_tsens_set_CTRLC_reg(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_ctrlc_reg_t hri_tsens_get_CTRLC_reg(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_CTRLC_reg(const void *const hw, hri_tsens_ctrlc_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CTRLC_reg(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CTRLC_reg(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_ctrlc_reg_t hri_tsens_read_CTRLC_reg(const void *const hw) +{ + return ((Tsens *)hw)->CTRLC.reg; +} + +static inline void hri_tsens_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg |= TSENS_EVCTRL_STARTEI; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->EVCTRL.reg; + tmp = (tmp & TSENS_EVCTRL_STARTEI) >> TSENS_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->EVCTRL.reg; + tmp &= ~TSENS_EVCTRL_STARTEI; + tmp |= value << TSENS_EVCTRL_STARTEI_Pos; + ((Tsens *)hw)->EVCTRL.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg &= ~TSENS_EVCTRL_STARTEI; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg ^= TSENS_EVCTRL_STARTEI; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_set_EVCTRL_STARTINV_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg |= TSENS_EVCTRL_STARTINV; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_EVCTRL_STARTINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->EVCTRL.reg; + tmp = (tmp & TSENS_EVCTRL_STARTINV) >> TSENS_EVCTRL_STARTINV_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->EVCTRL.reg; + tmp &= ~TSENS_EVCTRL_STARTINV; + tmp |= value << TSENS_EVCTRL_STARTINV_Pos; + ((Tsens *)hw)->EVCTRL.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_EVCTRL_STARTINV_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg &= ~TSENS_EVCTRL_STARTINV; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_EVCTRL_STARTINV_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg ^= TSENS_EVCTRL_STARTINV; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_set_EVCTRL_WINEO_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg |= TSENS_EVCTRL_WINEO; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_EVCTRL_WINEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->EVCTRL.reg; + tmp = (tmp & TSENS_EVCTRL_WINEO) >> TSENS_EVCTRL_WINEO_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_write_EVCTRL_WINEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->EVCTRL.reg; + tmp &= ~TSENS_EVCTRL_WINEO; + tmp |= value << TSENS_EVCTRL_WINEO_Pos; + ((Tsens *)hw)->EVCTRL.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_EVCTRL_WINEO_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg &= ~TSENS_EVCTRL_WINEO; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_EVCTRL_WINEO_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg ^= TSENS_EVCTRL_WINEO; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_set_EVCTRL_reg(const void *const hw, hri_tsens_evctrl_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_evctrl_reg_t hri_tsens_get_EVCTRL_reg(const void *const hw, hri_tsens_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_EVCTRL_reg(const void *const hw, hri_tsens_evctrl_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_EVCTRL_reg(const void *const hw, hri_tsens_evctrl_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_EVCTRL_reg(const void *const hw, hri_tsens_evctrl_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_evctrl_reg_t hri_tsens_read_EVCTRL_reg(const void *const hw) +{ + return ((Tsens *)hw)->EVCTRL.reg; +} + +static inline void hri_tsens_set_WINLT_WINLT_bf(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINLT.reg |= TSENS_WINLT_WINLT(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winlt_reg_t hri_tsens_get_WINLT_WINLT_bf(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->WINLT.reg; + tmp = (tmp & TSENS_WINLT_WINLT(mask)) >> TSENS_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_tsens_write_WINLT_WINLT_bf(const void *const hw, hri_tsens_winlt_reg_t data) +{ + uint32_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->WINLT.reg; + tmp &= ~TSENS_WINLT_WINLT_Msk; + tmp |= TSENS_WINLT_WINLT(data); + ((Tsens *)hw)->WINLT.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_WINLT_WINLT_bf(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINLT.reg &= ~TSENS_WINLT_WINLT(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_WINLT_WINLT_bf(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINLT.reg ^= TSENS_WINLT_WINLT(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winlt_reg_t hri_tsens_read_WINLT_WINLT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->WINLT.reg; + tmp = (tmp & TSENS_WINLT_WINLT_Msk) >> TSENS_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_tsens_set_WINLT_reg(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINLT.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winlt_reg_t hri_tsens_get_WINLT_reg(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_WINLT_reg(const void *const hw, hri_tsens_winlt_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINLT.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_WINLT_reg(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINLT.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_WINLT_reg(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINLT.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winlt_reg_t hri_tsens_read_WINLT_reg(const void *const hw) +{ + return ((Tsens *)hw)->WINLT.reg; +} + +static inline void hri_tsens_set_WINUT_WINUT_bf(const void *const hw, hri_tsens_winut_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINUT.reg |= TSENS_WINUT_WINUT(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winut_reg_t hri_tsens_get_WINUT_WINUT_bf(const void *const hw, hri_tsens_winut_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->WINUT.reg; + tmp = (tmp & TSENS_WINUT_WINUT(mask)) >> TSENS_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_tsens_write_WINUT_WINUT_bf(const void *const hw, hri_tsens_winut_reg_t data) +{ + uint32_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->WINUT.reg; + tmp &= ~TSENS_WINUT_WINUT_Msk; + tmp |= TSENS_WINUT_WINUT(data); + ((Tsens *)hw)->WINUT.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_WINUT_WINUT_bf(const void *const hw, hri_tsens_winut_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINUT.reg &= ~TSENS_WINUT_WINUT(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_WINUT_WINUT_bf(const void *const hw, hri_tsens_winut_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINUT.reg ^= TSENS_WINUT_WINUT(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winut_reg_t hri_tsens_read_WINUT_WINUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->WINUT.reg; + tmp = (tmp & TSENS_WINUT_WINUT_Msk) >> TSENS_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_tsens_set_WINUT_reg(const void *const hw, hri_tsens_winut_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINUT.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winut_reg_t hri_tsens_get_WINUT_reg(const void *const hw, hri_tsens_winut_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_WINUT_reg(const void *const hw, hri_tsens_winut_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINUT.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_WINUT_reg(const void *const hw, hri_tsens_winut_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINUT.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_WINUT_reg(const void *const hw, hri_tsens_winut_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINUT.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winut_reg_t hri_tsens_read_WINUT_reg(const void *const hw) +{ + return ((Tsens *)hw)->WINUT.reg; +} + +static inline void hri_tsens_set_GAIN_GAIN_bf(const void *const hw, hri_tsens_gain_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->GAIN.reg |= TSENS_GAIN_GAIN(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_gain_reg_t hri_tsens_get_GAIN_GAIN_bf(const void *const hw, hri_tsens_gain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->GAIN.reg; + tmp = (tmp & TSENS_GAIN_GAIN(mask)) >> TSENS_GAIN_GAIN_Pos; + return tmp; +} + +static inline void hri_tsens_write_GAIN_GAIN_bf(const void *const hw, hri_tsens_gain_reg_t data) +{ + uint32_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->GAIN.reg; + tmp &= ~TSENS_GAIN_GAIN_Msk; + tmp |= TSENS_GAIN_GAIN(data); + ((Tsens *)hw)->GAIN.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_GAIN_GAIN_bf(const void *const hw, hri_tsens_gain_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->GAIN.reg &= ~TSENS_GAIN_GAIN(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_GAIN_GAIN_bf(const void *const hw, hri_tsens_gain_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->GAIN.reg ^= TSENS_GAIN_GAIN(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_gain_reg_t hri_tsens_read_GAIN_GAIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->GAIN.reg; + tmp = (tmp & TSENS_GAIN_GAIN_Msk) >> TSENS_GAIN_GAIN_Pos; + return tmp; +} + +static inline void hri_tsens_set_GAIN_reg(const void *const hw, hri_tsens_gain_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->GAIN.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_gain_reg_t hri_tsens_get_GAIN_reg(const void *const hw, hri_tsens_gain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->GAIN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_GAIN_reg(const void *const hw, hri_tsens_gain_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->GAIN.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_GAIN_reg(const void *const hw, hri_tsens_gain_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->GAIN.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_GAIN_reg(const void *const hw, hri_tsens_gain_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->GAIN.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_gain_reg_t hri_tsens_read_GAIN_reg(const void *const hw) +{ + return ((Tsens *)hw)->GAIN.reg; +} + +static inline void hri_tsens_set_OFFSET_OFFSETC_bf(const void *const hw, hri_tsens_offset_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->OFFSET.reg |= TSENS_OFFSET_OFFSETC(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_offset_reg_t hri_tsens_get_OFFSET_OFFSETC_bf(const void *const hw, hri_tsens_offset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->OFFSET.reg; + tmp = (tmp & TSENS_OFFSET_OFFSETC(mask)) >> TSENS_OFFSET_OFFSETC_Pos; + return tmp; +} + +static inline void hri_tsens_write_OFFSET_OFFSETC_bf(const void *const hw, hri_tsens_offset_reg_t data) +{ + uint32_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->OFFSET.reg; + tmp &= ~TSENS_OFFSET_OFFSETC_Msk; + tmp |= TSENS_OFFSET_OFFSETC(data); + ((Tsens *)hw)->OFFSET.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_OFFSET_OFFSETC_bf(const void *const hw, hri_tsens_offset_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->OFFSET.reg &= ~TSENS_OFFSET_OFFSETC(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_OFFSET_OFFSETC_bf(const void *const hw, hri_tsens_offset_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->OFFSET.reg ^= TSENS_OFFSET_OFFSETC(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_offset_reg_t hri_tsens_read_OFFSET_OFFSETC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->OFFSET.reg; + tmp = (tmp & TSENS_OFFSET_OFFSETC_Msk) >> TSENS_OFFSET_OFFSETC_Pos; + return tmp; +} + +static inline void hri_tsens_set_OFFSET_reg(const void *const hw, hri_tsens_offset_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->OFFSET.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_offset_reg_t hri_tsens_get_OFFSET_reg(const void *const hw, hri_tsens_offset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->OFFSET.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_OFFSET_reg(const void *const hw, hri_tsens_offset_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->OFFSET.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_OFFSET_reg(const void *const hw, hri_tsens_offset_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->OFFSET.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_OFFSET_reg(const void *const hw, hri_tsens_offset_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->OFFSET.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_offset_reg_t hri_tsens_read_OFFSET_reg(const void *const hw) +{ + return ((Tsens *)hw)->OFFSET.reg; +} + +static inline void hri_tsens_set_CAL_FCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg |= TSENS_CAL_FCAL(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_cal_reg_t hri_tsens_get_CAL_FCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->CAL.reg; + tmp = (tmp & TSENS_CAL_FCAL(mask)) >> TSENS_CAL_FCAL_Pos; + return tmp; +} + +static inline void hri_tsens_write_CAL_FCAL_bf(const void *const hw, hri_tsens_cal_reg_t data) +{ + uint32_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->CAL.reg; + tmp &= ~TSENS_CAL_FCAL_Msk; + tmp |= TSENS_CAL_FCAL(data); + ((Tsens *)hw)->CAL.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CAL_FCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg &= ~TSENS_CAL_FCAL(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CAL_FCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg ^= TSENS_CAL_FCAL(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_cal_reg_t hri_tsens_read_CAL_FCAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->CAL.reg; + tmp = (tmp & TSENS_CAL_FCAL_Msk) >> TSENS_CAL_FCAL_Pos; + return tmp; +} + +static inline void hri_tsens_set_CAL_TCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg |= TSENS_CAL_TCAL(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_cal_reg_t hri_tsens_get_CAL_TCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->CAL.reg; + tmp = (tmp & TSENS_CAL_TCAL(mask)) >> TSENS_CAL_TCAL_Pos; + return tmp; +} + +static inline void hri_tsens_write_CAL_TCAL_bf(const void *const hw, hri_tsens_cal_reg_t data) +{ + uint32_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->CAL.reg; + tmp &= ~TSENS_CAL_TCAL_Msk; + tmp |= TSENS_CAL_TCAL(data); + ((Tsens *)hw)->CAL.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CAL_TCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg &= ~TSENS_CAL_TCAL(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CAL_TCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg ^= TSENS_CAL_TCAL(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_cal_reg_t hri_tsens_read_CAL_TCAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->CAL.reg; + tmp = (tmp & TSENS_CAL_TCAL_Msk) >> TSENS_CAL_TCAL_Pos; + return tmp; +} + +static inline void hri_tsens_set_CAL_reg(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_cal_reg_t hri_tsens_get_CAL_reg(const void *const hw, hri_tsens_cal_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->CAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_CAL_reg(const void *const hw, hri_tsens_cal_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CAL_reg(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CAL_reg(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_cal_reg_t hri_tsens_read_CAL_reg(const void *const hw) +{ + return ((Tsens *)hw)->CAL.reg; +} + +static inline void hri_tsens_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->DBGCTRL.reg |= TSENS_DBGCTRL_DBGRUN; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->DBGCTRL.reg; + tmp = (tmp & TSENS_DBGCTRL_DBGRUN) >> TSENS_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->DBGCTRL.reg; + tmp &= ~TSENS_DBGCTRL_DBGRUN; + tmp |= value << TSENS_DBGCTRL_DBGRUN_Pos; + ((Tsens *)hw)->DBGCTRL.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->DBGCTRL.reg &= ~TSENS_DBGCTRL_DBGRUN; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->DBGCTRL.reg ^= TSENS_DBGCTRL_DBGRUN; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_set_DBGCTRL_reg(const void *const hw, hri_tsens_dbgctrl_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->DBGCTRL.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_dbgctrl_reg_t hri_tsens_get_DBGCTRL_reg(const void *const hw, hri_tsens_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_DBGCTRL_reg(const void *const hw, hri_tsens_dbgctrl_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->DBGCTRL.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_DBGCTRL_reg(const void *const hw, hri_tsens_dbgctrl_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->DBGCTRL.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_DBGCTRL_reg(const void *const hw, hri_tsens_dbgctrl_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->DBGCTRL.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_dbgctrl_reg_t hri_tsens_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tsens *)hw)->DBGCTRL.reg; +} + +static inline void hri_tsens_write_CTRLB_reg(const void *const hw, hri_tsens_ctrlb_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLB.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TSENS_C21_H_INCLUDED */ +#endif /* _SAMC21_TSENS_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_wdt_c21.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_wdt_c21.h new file mode 100644 index 0000000..21ca738 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/hri/hri_wdt_c21.h @@ -0,0 +1,617 @@ +/** + * \file + * + * \brief SAM WDT + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_WDT_COMPONENT_ +#ifndef _HRI_WDT_C21_H_INCLUDED_ +#define _HRI_WDT_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_WDT_CRITICAL_SECTIONS) +#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define WDT_CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_wdt_syncbusy_reg_t; +typedef uint8_t hri_wdt_clear_reg_t; +typedef uint8_t hri_wdt_config_reg_t; +typedef uint8_t hri_wdt_ctrla_reg_t; +typedef uint8_t hri_wdt_ewctrl_reg_t; +typedef uint8_t hri_wdt_intenset_reg_t; +typedef uint8_t hri_wdt_intflag_reg_t; + +static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + while (((Wdt *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + return ((Wdt *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTFLAG.reg; +} + +static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + ((Wdt *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; +} + +static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; +} + +static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; + } else { + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; + } +} + +static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; +} + +static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENSET.reg = mask; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTENSET.reg; +} + +static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) +{ + ((Wdt *)hw)->INTENSET.reg = data; + ((Wdt *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Wdt *)hw)->SYNCBUSY.reg; +} + +static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ENABLE; + tmp |= value << WDT_CTRLA_ENABLE_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_WEN; + tmp |= value << WDT_CTRLA_WEN_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ALWAYSON; + tmp |= value << WDT_CTRLA_ALWAYSON_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) +{ + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + return ((Wdt *)hw)->CTRLA.reg; +} + +static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_PER_Msk; + tmp |= WDT_CONFIG_PER(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_WINDOW_Msk; + tmp |= WDT_CONFIG_WINDOW(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) +{ + return ((Wdt *)hw)->CONFIG.reg; +} + +static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; + tmp |= WDT_EWCTRL_EWOFFSET(data); + ((Wdt *)hw)->EWCTRL.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) +{ + return ((Wdt *)hw)->EWCTRL.reg; +} + +static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CLEAR.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR); + WDT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_WDT_C21_H_INCLUDED */ +#endif /* _SAMC21_WDT_COMPONENT_ */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/main.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/main.c new file mode 100644 index 0000000..0210859 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/main.c @@ -0,0 +1,112 @@ +#include +#include "hpl_dma.h" + +#define SLAVE_BUFFER_SIZE 32 +static uint8_t rx_buffer[SLAVE_BUFFER_SIZE] = {0}; +static uint8_t tx_buffer[SLAVE_BUFFER_SIZE] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17, + 18, 19,20,21,22,23,24,25,26,27,28,29,30,31}; +//static uint8_t tx_buffer[SLAVE_BUFFER_SIZE] = {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, 0xff, 0xff}; +/* DMA channel for SPI Slave TX and RX */ +#define CONF_SERCOM_5_RECEIVE_DMA_CHANNEL 0 +#define CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL 1 + +/* DMA channel Descriptor */ +extern DmacDescriptor _descriptor_section[DMAC_CH_NUM]; +extern DmacDescriptor _write_back_section[DMAC_CH_NUM]; + + +/* Enable SPI slave select interrupt */ +void spi_s_sync_enable_ss_detect(void *hw, bool state) +{ + NVIC_DisableIRQ((IRQn_Type)SERCOM5_IRQn); + NVIC_ClearPendingIRQ((IRQn_Type)SERCOM5_IRQn); + NVIC_EnableIRQ((IRQn_Type)SERCOM5_IRQn); + if (state) { + hri_sercomspi_set_INTEN_TXC_bit(hw); + //hri_sercomspi_set_INTEN_SSL_bit(hw); + //SERCOM_SPI_INTENSET_SSL + } else { + hri_sercomspi_clear_INTEN_TXC_bit(hw); + //hri_sercomspi_clear_INTEN_SSL_bit(hw); + } +} + +/* slave interrupt handler */ +void SERCOM5_Handler() +{ + SERCOM5->SPI.INTFLAG.bit.TXC= 0x01; + //_dma_enable_transaction(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, false); + tx_buffer[0] += 1; + tx_buffer[31] += 1; + _dma_enable_transaction(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, false); + _dma_enable_transaction(CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL, false); + //slave_select_high(); + //_dma_enable_transaction(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, false); + //_dma_enable_transaction(CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL, false); +} + + +static void spi_slave_rx_complete_cb(struct _dma_resource *const resource) +{ + //hri_sercomspi_clear_INTEN_RXC_bit((SercomSpi *)(SPI_0.dev.prvt)); + //tx_buffer[63] += 1; + //_dma_enable_transaction(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, false); + //_dma_enable_transaction(CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL, false); + //spi_slave_rx_complete = true; +} + +static void spi_slave_tx_complete_cb(struct _dma_resource *const resource) +{ + //hri_sercomspi_clear_INTEN_TC_bit((SercomSpi *)(SPI_0.dev.prvt)); + //tx_buffer[63] += 1; + //_dma_enable_transaction(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, false); + //_dma_enable_transaction(CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL, false); + //spi_slave_rx_complete = true; +} + +void init_spi_slave_dma_descriptors() +{ + _dma_set_source_address(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, + (uint32_t *)&(((SercomSpi *)(SPI_0.dev.prvt))->DATA.reg)); + _dma_set_destination_address(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, &rx_buffer[0]); + _dma_set_data_amount(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, SLAVE_BUFFER_SIZE); + + _dma_set_source_address(CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL, &tx_buffer[0]); + _dma_set_destination_address(CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL, + (uint32_t *)&(((SercomSpi *)(SPI_0.dev.prvt))->DATA.reg)); + _dma_set_data_amount(CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL, SLAVE_BUFFER_SIZE); + + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_5_RECEIVE_DMA_CHANNEL]); + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL]); + /* callback */ + struct _dma_resource *resource_rx, *resource_tx; + _dma_get_channel_resource(&resource_rx, CONF_SERCOM_5_RECEIVE_DMA_CHANNEL); + _dma_get_channel_resource(&resource_tx, CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL); + resource_rx->dma_cb.transfer_done = spi_slave_rx_complete_cb; + //resource_tx->dma_cb.transfer_done = spi_slave_tx_complete_cb; + + /* Enable DMA transfer complete interrupt */ + _dma_set_irq_state(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true); + +} + +void boardToBoardTransferInit(void) +{ + hri_sercomspi_set_CTRLB_PLOADEN_bit(SPI_0.dev.prvt); + spi_s_sync_enable(&SPI_0); +} + +int main(void) +{ + /* Initializes MCU, drivers and middleware */ + atmel_start_init(); + boardToBoardTransferInit(); + init_spi_slave_dma_descriptors(); + _dma_enable_transaction(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, false); + _dma_enable_transaction(CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL, false); + spi_s_sync_enable_ss_detect((SercomSpi *)(SPI_0.dev.prvt), true); + /* Replace with your application code */ + while (1) { + + } +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_redirect/gcc/read.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_redirect/gcc/read.c new file mode 100644 index 0000000..90e4618 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_redirect/gcc/read.c @@ -0,0 +1,53 @@ +/** + * \file + * + * \brief STDIO redirection + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +int __attribute__((weak)) _read(int file, char *ptr, int len); /* Remove GCC compiler warning */ + +int __attribute__((weak)) _read(int file, char *ptr, int len) +{ + int n = 0; + + if (file != 0) { + return -1; + } + + n = stdio_io_read((uint8_t *)ptr, len); + if (n < 0) { + return -1; + } + + return n; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_redirect/gcc/write.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_redirect/gcc/write.c new file mode 100644 index 0000000..44fa815 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_redirect/gcc/write.c @@ -0,0 +1,53 @@ +/** + * \file + * + * \brief STDIO redirection + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +int __attribute__((weak)) _write(int file, char *ptr, int len); /* Remove GCC compiler warning */ + +int __attribute__((weak)) _write(int file, char *ptr, int len) +{ + int n = 0; + + if ((file != 1) && (file != 2) && (file != 3)) { + return -1; + } + + n = stdio_io_write((const uint8_t *)ptr, len); + if (n < 0) { + return -1; + } + + return n; +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_redirect/stdio_io.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_redirect/stdio_io.c new file mode 100644 index 0000000..7659f3d --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_redirect/stdio_io.c @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief STDIO redirection terminal + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** IO descriptor for STDIO access. */ +static struct io_descriptor *stdio_io = NULL; + +void stdio_io_init(struct io_descriptor *io) +{ +#if defined(__GNUC__) + /* Specify that stdout and stdin should not be buffered. */ + setbuf(stdout, NULL); + setbuf(stdin, NULL); + /* Note: Already the case in IAR's Normal DLIB default configuration + * and AVR GCC library: + * - printf() emits one character at a time. + * - getchar() requests only 1 byte to exit. + */ +#endif + stdio_io = io; +} + +void stdio_io_set_io(struct io_descriptor *io) +{ + stdio_io = io; +} + +int32_t stdio_io_read(uint8_t *buf, const int32_t len) +{ + if (stdio_io == NULL) { + return 0; + } + return io_read(stdio_io, buf, len); +} + +int32_t stdio_io_write(const uint8_t *buf, const int32_t len) +{ + if (stdio_io == NULL) { + return 0; + } + return io_write(stdio_io, buf, len); +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_redirect/stdio_io.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_redirect/stdio_io.h new file mode 100644 index 0000000..973adad --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_redirect/stdio_io.h @@ -0,0 +1,81 @@ +/** + * \file + * + * \brief STDIO redirection terminal + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _STDIO_IO_H_INCLUDED +#define _STDIO_IO_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * \brief Initialize STDIO access + * \param[in] io Pointer to IO descriptor, + * NULL to discard R/W without any error. + */ +void stdio_io_init(struct io_descriptor *io); + +/** + * \brief Change IO descriptor for terminal to R/W data + * \param[in] io Pointer to IO descriptor, + * NULL to discard R/W without any error. + */ +void stdio_io_set_io(struct io_descriptor *io); + +/** + * \brief Read through specified terminal + * \param[out] buf Pointer to buffer to place read data + * \param[in] len Data length in number of bytes + * \return status + * \retval >=0 number of bytes read + * \retval <0 error + */ +int32_t stdio_io_read(uint8_t *buf, const int32_t len); + +/** + * \brief Write through specified terminal + * \param[in] buf Pointer to buffer to place data to write + * \param[in] len Data length in number of bytes + * \return status + * \retval >=0 number of bytes read + * \retval <0 error + */ +int32_t stdio_io_write(const uint8_t *buf, const int32_t len); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _STDIO_IO_H_INCLUDED */ diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_start.c b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_start.c new file mode 100644 index 0000000..db8d362 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_start.c @@ -0,0 +1,23 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file or main.c + * to avoid loosing it when reconfiguring. + */ + +#include "atmel_start.h" +#include "stdio_start.h" + +void STDIO_REDIRECT_0_example(void) +{ + /* Print welcome message */ + printf("\r\nHello ATMEL World!\r\n"); +} + +void stdio_redirect_init(void) +{ + + usart_sync_enable(&TARGET_IO); + stdio_io_init(&TARGET_IO.io); +} diff --git a/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_start.h b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_start.h new file mode 100644 index 0000000..bee5325 --- /dev/null +++ b/Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/stdio_start.h @@ -0,0 +1,31 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file or main.c + * to avoid loosing it when reconfiguring. + */ +#ifndef STDIO_MAIN_H +#define STDIO_MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include + +#include +#include + +void STDIO_REDIRECT_0_example(void); + +/** + * \brief Initialize STDIO Redirect + */ +void stdio_redirect_init(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STDIO_MAIN_H */ diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.gpdsc b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.gpdsc index 0fee133..dd24bce 100644 --- a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.gpdsc +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.gpdsc @@ -53,6 +53,7 @@ + @@ -162,17 +163,21 @@ + + + + @@ -192,6 +197,8 @@ + + @@ -208,6 +215,7 @@ + diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/atmel_start_config.atstart b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/atmel_start_config.atstart index e40c246..0890241 100644 --- a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/atmel_start_config.atstart +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/atmel_start_config.atstart @@ -1576,53 +1576,24 @@ drivers: slow_gclk_selection: Generic clock generator 3 TIMER_0: user_label: TIMER_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC0::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC0::driver_config_definition::Timer::HAL:Driver:Timer functionality: Timer - api: Lite:TC:Timer + api: HAL:Driver:Timer configuration: - cc_cc0: 12000 - cc_cc1: 6000 - cc_control: true - count_control: false - count_count: 0 - ctrla_alock: false - ctrla_capten0: false - ctrla_capten1: false - ctrla_captmode0: DEFAULT - ctrla_captmode1: DEFAULT - ctrla_control: true - ctrla_copen0: false - ctrla_copen1: false - ctrla_enable: true - ctrla_mode: 0 - ctrla_ondemand: false - ctrla_prescaler: DIV1 - ctrla_prescsync: GCLK - ctrla_runstdby: false - ctrlbset_cmd: NONE - ctrlbset_control: false - ctrlbset_dir: false - ctrlbset_lupd: false - ctrlbset_oneshot: false - ctrlc_inven0: false - ctrlc_inven1: false - dbgctrl_control: false - dbgctrl_dbgrun: false - drvctrl_control: false - evctrl_control: true - evctrl_evact: 'OFF' - evctrl_mceo0: true - evctrl_mceo1: true - evctrl_ovfeo: true - evctrl_tcei: false - evctrl_tcinv: false - intenset_control: true - intenset_err: false - intenset_mc0: false - intenset_mc1: true - intenset_ovf: true - wave_control: true - wave_wavegen: MFRQ + tc_arch_dbgrun: false + tc_arch_evact: Event action disabled + tc_arch_mceo0: false + tc_arch_mceo1: false + tc_arch_ondemand: false + tc_arch_ovfeo: false + tc_arch_presync: Reload or reset counter on next GCLK + tc_arch_runstdby: false + tc_arch_tcei: false + tc_arch_tcinv: false + timer_advanced_configuration: false + timer_event_control: false + timer_prescaler: Divide by 16 + timer_tick: 1000 optional_signals: [] variant: null clocks: diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_tc_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_tc_config.h new file mode 100644 index 0000000..8e20fb6 --- /dev/null +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_tc_config.h @@ -0,0 +1,180 @@ +/* Auto-generated config file hpl_tc_config.h */ +#ifndef HPL_TC_CONFIG_H +#define HPL_TC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef CONF_TC0_ENABLE +#define CONF_TC0_ENABLE 1 +#endif + +#include "peripheral_clk_config.h" + +// Basic configuration + +// Prescaler +// <0x0=> No division +// <0x1=> Divide by 2 +// <0x2=> Divide by 4 +// <0x3=> Divide by 8 +// <0x4=> Divide by 16 +// <0x5=> Divide by 64 +// <0x6=> Divide by 256 +// <0x7=> Divide by 1024 +// This defines the prescaler value +// timer_prescaler +#ifndef CONF_TC0_PRESCALER +#define CONF_TC0_PRESCALER 0x4 +#endif + +// Length of one timer tick in uS <0-4294967295> +// timer_tick +#ifndef CONF_TC0_TIMER_TICK +#define CONF_TC0_TIMER_TICK 1000 +#endif +// + +// Advanced configuration +// timer_advanced_configuration +#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE +#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 0 +#endif + +// Prescaler and Counter Synchronization Selection +// Reload or reset counter on next GCLK +// Reload or reset counter on next prescaler clock +// Reload or reset counter on next GCLK and reset prescaler counter +// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. +// tc_arch_presync +#ifndef CONF_TC0_PRESCSYNC +#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +// Run in standby +// Indicates whether the module will continue to run in standby sleep mode +// tc_arch_runstdby +#ifndef CONF_TC0_RUNSTDBY +#define CONF_TC0_RUNSTDBY 0 +#endif + +// Run in debug mode +// Indicates whether the module will run in debug mode +// tc_arch_dbgrun +#ifndef CONF_TC0_DBGRUN +#define CONF_TC0_DBGRUN 0 +#endif + +// Run on demand +// Run if requested by some other peripheral in the device +// tc_arch_ondemand +#ifndef CONF_TC0_ONDEMAND +#define CONF_TC0_ONDEMAND 0 +#endif + +// + +// Event control +// timer_event_control +#ifndef CONF_TC0_EVENT_CONTROL_ENABLE +#define CONF_TC0_EVENT_CONTROL_ENABLE 0 +#endif + +// Output Event On Match or Capture on Channel 0 +// Enable output of event on timer tick +// tc_arch_mceo0 +#ifndef CONF_TC0_MCEO0 +#define CONF_TC0_MCEO0 0 +#endif + +// Output Event On Match or Capture on Channel 1 +// Enable output of event on timer tick +// tc_arch_mceo1 +#ifndef CONF_TC0_MCEO1 +#define CONF_TC0_MCEO1 0 +#endif + +// Output Event On Timer Tick +// Enable output of event on timer tick +// tc_arch_ovfeo +#ifndef CONF_TC0_OVFEO +#define CONF_TC0_OVFEO 0 +#endif + +// Event Input +// Enable asynchronous input events +// tc_arch_tcei +#ifndef CONF_TC0_TCEI +#define CONF_TC0_TCEI 0 +#endif + +// Inverted Event Input +// Invert the asynchronous input events +// tc_arch_tcinv +#ifndef CONF_TC0_TCINV +#define CONF_TC0_TCINV 0 +#endif + +// Event action +// <0=> Event action disabled +// <1=> Start, restart or re-trigger TC on event +// <2=> Count on event +// <3=> Start on event +// <4=> Time stamp capture +// <5=> Period captured in CC0, pulse width in CC1 +// <6=> Period captured in CC1, pulse width in CC0 +// <7=> Pulse width capture +// Event which will be performed on an event +// tc_arch_evact +#ifndef CONF_TC0_EVACT +#define CONF_TC0_EVACT 0 +#endif +// + +// Default values which the driver needs in order to work correctly + +// Mode set to 32-bit +#ifndef CONF_TC0_MODE +#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val +#endif + +// CC 1 register set to 0 +#ifndef CONF_TC0_CC1 +#define CONF_TC0_CC1 0 +#endif + +#ifndef CONF_TC0_ALOCK +#define CONF_TC0_ALOCK 0 +#endif + +// Not used in 32-bit mode +#define CONF_TC0_PER 0 + +// Calculating correct top value based on requested tick interval. +#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER) + +// Prescaler set to 64 +#if CONF_TC0_PRESCALER > 0x4 +#undef CONF_TC0_PRESCALE +#define CONF_TC0_PRESCALE 64 +#endif + +// Prescaler set to 256 +#if CONF_TC0_PRESCALER > 0x5 +#undef CONF_TC0_PRESCALE +#define CONF_TC0_PRESCALE 256 +#endif + +// Prescaler set to 1024 +#if CONF_TC0_PRESCALER > 0x6 +#undef CONF_TC0_PRESCALE +#define CONF_TC0_PRESCALE 1024 +#endif + +#ifndef CONF_TC0_CC0 +#define CONF_TC0_CC0 \ + (uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE))) +#endif + +// <<< end of configuration section >>> + +#endif // HPL_TC_CONFIG_H diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj index 6eedaff..0d7d463 100644 --- a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj @@ -152,22 +152,26 @@ - - + + - - + + + + + + @@ -187,8 +191,10 @@ - - + + + + @@ -203,6 +209,7 @@ + @@ -481,6 +488,9 @@ compile + + compile + compile @@ -550,6 +560,9 @@ compile + + compile + compile @@ -592,6 +605,9 @@ compile + + compile + compile @@ -637,6 +653,9 @@ compile + + compile + compile @@ -676,6 +695,9 @@ compile + + compile + compile @@ -772,6 +794,12 @@ compile + + compile + + + compile + compile @@ -969,6 +997,9 @@ compile + + compile + compile diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.c index 3dddca0..c61dc24 100644 --- a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.c +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.c @@ -11,6 +11,8 @@ #include #include +struct timer_descriptor TIMER_0; + struct qspi_sync_descriptor QUAD_SPI_0; struct usart_sync_descriptor TARGET_IO; @@ -387,12 +389,17 @@ void SPI_1_init(void) SPI_1_PORT_init(); } -void TIMER_0_CLOCK_init(void) +/** + * \brief Timer initialization function + * + * Enables Timer peripheral, clocks and initializes Timer driver + */ +static void TIMER_0_init(void) { hri_mclk_set_APBAMASK_TC0_bit(MCLK); - - hri_mclk_set_APBAMASK_TC1_bit(MCLK); hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + timer_init(&TIMER_0, TC0, _tc_get_timer()); } void TC_ECAT_CLOCK_init(void) @@ -443,10 +450,7 @@ void system_init(void) SPI_1_init(); - TIMER_0_CLOCK_init(); - TIMER_0_init(); - TC_ECAT_CLOCK_init(); TC_ECAT_init(); diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.h index 20b72e2..7a90d23 100644 --- a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.h +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.h @@ -30,7 +30,8 @@ extern "C" { #include #include -#include +#include +#include #include extern struct qspi_sync_descriptor QUAD_SPI_0; @@ -40,6 +41,7 @@ extern struct usart_sync_descriptor TARGET_IO; extern struct spi_m_dma_descriptor SPI_0; extern struct spi_m_dma_descriptor SPI_1; +extern struct timer_descriptor TIMER_0; void QUAD_SPI_0_PORT_init(void); void QUAD_SPI_0_CLOCK_init(void); @@ -57,10 +59,6 @@ void SPI_1_PORT_init(void); void SPI_1_CLOCK_init(void); void SPI_1_init(void); -void TIMER_0_CLOCK_init(void); - -int8_t TIMER_0_init(void); - void TC_ECAT_CLOCK_init(void); int8_t TC_ECAT_init(void); diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.c index 37464f5..07c27b1 100644 --- a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.c +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.c @@ -96,3 +96,30 @@ void SPI_1_example(void) spi_m_dma_enable(&SPI_1); io_write(io, example_SPI_1, 12); } + +static struct timer_task TIMER_0_task1, TIMER_0_task2; + +/** + * Example of using TIMER_0. + */ +static void TIMER_0_task1_cb(const struct timer_task *const timer_task) +{ +} + +static void TIMER_0_task2_cb(const struct timer_task *const timer_task) +{ +} + +void TIMER_0_example(void) +{ + TIMER_0_task1.interval = 100; + TIMER_0_task1.cb = TIMER_0_task1_cb; + TIMER_0_task1.mode = TIMER_TASK_REPEAT; + TIMER_0_task2.interval = 200; + TIMER_0_task2.cb = TIMER_0_task2_cb; + TIMER_0_task2.mode = TIMER_TASK_REPEAT; + + timer_add_task(&TIMER_0, &TIMER_0_task1); + timer_add_task(&TIMER_0, &TIMER_0_task2); + timer_start(&TIMER_0); +} diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.h index 375f6b2..ae318cb 100644 --- a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.h +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.h @@ -20,6 +20,8 @@ void SPI_0_example(void); void SPI_1_example(void); +void TIMER_0_example(void); + #ifdef __cplusplus } #endif diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/timer.rst b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/timer.rst new file mode 100644 index 0000000..c5ca63d --- /dev/null +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/timer.rst @@ -0,0 +1,52 @@ +============================ +The Timer driver (bare-bone) +============================ + +The Timer driver provides means for delayed and periodical function invocation. + +A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has +been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a +configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically +changes execution delays and periods for all tasks in the timers task queue. + +A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue +and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on +the period set in the task configuration. +In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to +reuse the memory of expired task in the callback. + +Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available. + +Features +-------- +* Initialization and de-initialization +* Starting and stopping +* Timer tasks - periodical invocation of functions +* Changing and obtaining of the period of a timer + +Applications +------------ +* Delayed and periodical function execution for middle-ware stacks and applications. + +Dependencies +------------ +* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt. + +Concurrency +----------- +The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during +the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed +until the task adding or removing is complete. + +The task queue is not protected from the access by interrupts not used by the driver. Due to this +it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes +the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver. + +Limitations +----------- +* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts. +* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task. + +Knows issues and workarounds +---------------------------- +Not applicable diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_timer.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_timer.h new file mode 100644 index 0000000..43a1ff4 --- /dev/null +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_timer.h @@ -0,0 +1,206 @@ +/** + * \file + * + * \brief Timer task functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_TIMER_H_INCLUDED +#define _HAL_TIMER_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_timer + * + * @{ + */ + +/** + * \brief Timer mode type + */ +enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT }; + +/** + * \brief Timer task descriptor + * + * The timer task descriptor forward declaration. + */ +struct timer_task; + +/** + * \brief Timer task callback function type + */ +typedef void (*timer_cb_t)(const struct timer_task *const timer_task); + +/** + * \brief Timer task structure + */ +struct timer_task { + struct list_element elem; /*! List element. */ + uint32_t time_label; /*! Absolute timer start time. */ + + uint32_t interval; /*! Number of timer ticks before calling the task. */ + timer_cb_t cb; /*! Function pointer to the task. */ + enum timer_task_mode mode; /*! Task mode: one shot or repeat. */ +}; + +/** + * \brief Timer structure + */ +struct timer_descriptor { + struct _timer_device device; + uint32_t time; + struct list_descriptor tasks; /*! Timer tasks list. */ + volatile uint8_t flags; +}; + +/** + * \brief Initialize timer + * + * This function initializes the given timer. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[out] descr A timer descriptor to initialize + * \param[in] hw The pointer to the hardware instance + * \param[in] func The pointer to a set of function pointers + * + * \return Initialization status. + */ +int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func); + +/** + * \brief Deinitialize timer + * + * This function deinitializes the given timer. + * It checks if the given hardware is initialized and if the given hardware is + * permitted to be deinitialized. + * + * \param[in] descr A timer descriptor to deinitialize + * + * \return De-initialization status. + */ +int32_t timer_deinit(struct timer_descriptor *const descr); + +/** + * \brief Start timer + * + * This function starts the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to start + * + * \return Timer starting status. + */ +int32_t timer_start(struct timer_descriptor *const descr); + +/** + * \brief Stop timer + * + * This function stops the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to stop + * + * \return Timer stopping status. + */ +int32_t timer_stop(struct timer_descriptor *const descr); + +/** + * \brief Set amount of clock cycles per timer tick + * + * This function sets the amount of clock cycles per timer tick for the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to stop + * \param[in] clock_cycles The amount of clock cycles per tick to set + * + * \return Setting clock cycles amount status. + */ +int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles); + +/** + * \brief Retrieve the amount of clock cycles in a tick + * + * This function retrieves how many clock cycles there are in a single timer tick. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to convert ticks to + * clock cycles + * \param[out] cycles The amount of clock cycles + * + * \return The status of clock cycles retrieving. + */ +int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles); + +/** + * \brief Add timer task + * + * This function adds the given timer task to the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to add task to + * \param[in] task A task to add + * + * \return Timer's task adding status. + */ +int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task); + +/** + * \brief Remove timer task + * + * This function removes the given timer task from the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to remove task from + * \param[in] task A task to remove + * + * \return Timer's task removing status. + */ +int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t timer_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_TIMER_H_INCLUDED */ diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_pwm.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_pwm.h new file mode 100644 index 0000000..ff87052 --- /dev/null +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_pwm.h @@ -0,0 +1,193 @@ +/** + * \file + * + * \brief PWM related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_PWM_H_INCLUDED +#define _HPL_PWM_H_INCLUDED + +/** + * \addtogroup HPL PWM + * + * \section hpl_pwm_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief PWM callback types + */ +enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB }; + +/** + * \brief PWM pulse-width period + */ +typedef uint32_t pwm_period_t; + +/** + * \brief PWM device structure + * + * The PWM device structure forward declaration. + */ +struct _pwm_device; + +/** + * \brief PWM interrupt callbacks + */ +struct _pwm_callback { + void (*pwm_period_cb)(struct _pwm_device *device); + void (*pwm_error_cb)(struct _pwm_device *device); +}; + +/** + * \brief PWM descriptor device structure + */ +struct _pwm_device { + struct _pwm_callback callback; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief PWM functions, pointers to low-level functions + */ +struct _pwm_hpl_interface { + int32_t (*init)(struct _pwm_device *const device, void *const hw); + void (*deinit)(struct _pwm_device *const device); + void (*start_pwm)(struct _pwm_device *const device); + void (*stop_pwm)(struct _pwm_device *const device); + void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); + bool (*is_pwm_enabled)(const struct _pwm_device *const device); + pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device); + uint32_t (*pwm_get_duty)(const struct _pwm_device *const device); + void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); +}; +/** + * \brief Initialize TC + * + * This function does low level TC configuration. + * + * \param[in] device The pointer to PWM device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _pwm_init(struct _pwm_device *const device, void *const hw); + +/** + * \brief Deinitialize TC + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_deinit(struct _pwm_device *const device); + +/** + * \brief Retrieve offset of the given tc hardware instance + * + * \param[in] device The pointer to PWM device instance + * + * \return The offset of the given tc hardware instance + */ +uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device); + +/** + * \brief Start hardware pwm + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_enable(struct _pwm_device *const device); + +/** + * \brief Stop hardware pwm + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_disable(struct _pwm_device *const device); + +/** + * \brief Set pwm parameter + * + * \param[in] device The pointer to PWM device instance + * \param[in] period Total period of one PWM cycle. + * \param[in] duty_cycle Period of PWM first half during one cycle. + */ +void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); + +/** + * \brief Check if pwm is working + * + * \param[in] device The pointer to PWM device instance + * + * \return Check status. + * \retval true The given pwm is working + * \retval false The given pwm is not working + */ +bool _pwm_is_enabled(const struct _pwm_device *const device); + +/** + * \brief Get pwm waveform period value + * + * \param[in] device The pointer to PWM device instance + * + * \return Period value. + */ +pwm_period_t _pwm_get_period(const struct _pwm_device *const device); + +/** + * \brief Get pwm waveform duty cycle value + * + * \param[in] device The pointer to PWM device instance + * + * \return Duty cycle value + */ +uint32_t _pwm_get_duty(const struct _pwm_device *const device); + +/** + * \brief Enable/disable PWM interrupt + * + * param[in] device The pointer to PWM device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_PWM_H_INCLUDED */ diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_timer.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_timer.h new file mode 100644 index 0000000..9bdfbb7 --- /dev/null +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_timer.h @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief Timer related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_TIMER_H_INCLUDED +#define _HPL_TIMER_H_INCLUDED + +/** + * \addtogroup HPL Timer + * + * \section hpl_timer_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Timer device structure + * + * The Timer device structure forward declaration. + */ +struct _timer_device; + +/** + * \brief Timer interrupt callbacks + */ +struct _timer_callbacks { + void (*period_expired)(struct _timer_device *device); +}; + +/** + * \brief Timer device structure + */ +struct _timer_device { + struct _timer_callbacks timer_cb; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief Timer functions, pointers to low-level functions + */ +struct _timer_hpl_interface { + int32_t (*init)(struct _timer_device *const device, void *const hw); + void (*deinit)(struct _timer_device *const device); + void (*start_timer)(struct _timer_device *const device); + void (*stop_timer)(struct _timer_device *const device); + void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles); + uint32_t (*get_period)(const struct _timer_device *const device); + bool (*is_timer_started)(const struct _timer_device *const device); + void (*set_timer_irq)(struct _timer_device *const device); +}; +/** + * \brief Initialize TCC + * + * This function does low level TCC configuration. + * + * \param[in] device The pointer to timer device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _timer_init(struct _timer_device *const device, void *const hw); + +/** + * \brief Deinitialize TCC + * + * \param[in] device The pointer to timer device instance + */ +void _timer_deinit(struct _timer_device *const device); + +/** + * \brief Start hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_start(struct _timer_device *const device); + +/** + * \brief Stop hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_stop(struct _timer_device *const device); + +/** + * \brief Set timer period + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles); + +/** + * \brief Retrieve timer period + * + * \param[in] device The pointer to timer device instance + * + * \return Timer period + */ +uint32_t _timer_get_period(const struct _timer_device *const device); + +/** + * \brief Check if timer is running + * + * \param[in] device The pointer to timer device instance + * + * \return Check status. + * \retval true The given timer is running + * \retval false The given timer is not running + */ +bool _timer_is_started(const struct _timer_device *const device); + +/** + * \brief Set timer IRQ + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_irq(struct _timer_device *const device); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_TIMER_H_INCLUDED */ diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_timer.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_timer.c new file mode 100644 index 0000000..565c6db --- /dev/null +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_timer.c @@ -0,0 +1,250 @@ +/** + * \file + * + * \brief Timer functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_timer.h" +#include +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Timer flags + */ +#define TIMER_FLAG_QUEUE_IS_TAKEN 1 +#define TIMER_FLAG_INTERRUPT_TRIGERRED 2 + +static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time); +static void timer_process_counted(struct _timer_device *device); + +/** + * \brief Initialize timer + */ +int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func) +{ + ASSERT(descr && hw); + _timer_init(&descr->device, hw); + descr->time = 0; + descr->device.timer_cb.period_expired = timer_process_counted; + + return ERR_NONE; +} + +/** + * \brief Deinitialize timer + */ +int32_t timer_deinit(struct timer_descriptor *const descr) +{ + ASSERT(descr); + _timer_deinit(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Start timer + */ +int32_t timer_start(struct timer_descriptor *const descr) +{ + ASSERT(descr); + if (_timer_is_started(&descr->device)) { + return ERR_DENIED; + } + _timer_start(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Stop timer + */ +int32_t timer_stop(struct timer_descriptor *const descr) +{ + ASSERT(descr); + if (!_timer_is_started(&descr->device)) { + return ERR_DENIED; + } + _timer_stop(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Set amount of clock cycler per timer tick + */ +int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles) +{ + ASSERT(descr); + _timer_set_period(&descr->device, clock_cycles); + + return ERR_NONE; +} + +/** + * \brief Add timer task + */ +int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task) +{ + ASSERT(descr && task); + + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + if (is_list_element(&descr->tasks, task)) { + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + ASSERT(false); + return ERR_ALREADY_INITIALIZED; + } + task->time_label = descr->time; + timer_add_timer_task(&descr->tasks, task, descr->time); + + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { + CRITICAL_SECTION_ENTER() + descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; + _timer_set_irq(&descr->device); + CRITICAL_SECTION_LEAVE() + } + + return ERR_NONE; +} + +/** + * \brief Remove timer task + */ +int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task) +{ + ASSERT(descr && task); + + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + if (!is_list_element(&descr->tasks, task)) { + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + ASSERT(false); + return ERR_NOT_FOUND; + } + list_delete_element(&descr->tasks, task); + + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { + CRITICAL_SECTION_ENTER() + descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; + _timer_set_irq(&descr->device); + CRITICAL_SECTION_LEAVE() + } + + return ERR_NONE; +} + +/** + * \brief Retrieve the amount of clock cycles in a tick + */ +int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles) +{ + ASSERT(descr && cycles); + *cycles = _timer_get_period(&descr->device); + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t timer_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal Insert a timer task into sorted timer's list + * + * \param[in] head The pointer to the head of timer task list + * \param[in] task The pointer to task to add + * \param[in] time Current timer time + */ +static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time) +{ + struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); + + if (!head) { + list_insert_as_head(list, new_task); + return; + } + + for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { + uint32_t time_left; + + if (it->time_label <= time) { + time_left = it->interval - (time - it->time_label); + } else { + time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; + } + if (time_left >= new_task->interval) + break; + prev = it; + } + + if (it == head) { + list_insert_as_head(list, new_task); + } else { + list_insert_after(prev, new_task); + } +} + +/** + * \internal Process interrupts + */ +static void timer_process_counted(struct _timer_device *device) +{ + struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); + struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); + uint32_t time = ++timer->time; + + if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { + timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED; + return; + } + + while (it && ((time - it->time_label) >= it->interval)) { + struct timer_task *tmp = it; + + list_remove_head(&timer->tasks); + if (TIMER_TASK_REPEAT == tmp->mode) { + tmp->time_label = time; + timer_add_timer_task(&timer->tasks, tmp, time); + } + it = (struct timer_task *)list_get_head(&timer->tasks); + + tmp->cb(tmp); + } +} diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/hpl_tc.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/hpl_tc.c new file mode 100644 index 0000000..8e7730d --- /dev/null +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/hpl_tc.c @@ -0,0 +1,352 @@ + +/** + * \file + * + * \brief SAM TC + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#include + +#ifndef CONF_TC0_ENABLE +#define CONF_TC0_ENABLE 0 +#endif +#ifndef CONF_TC1_ENABLE +#define CONF_TC1_ENABLE 0 +#endif +#ifndef CONF_TC2_ENABLE +#define CONF_TC2_ENABLE 0 +#endif +#ifndef CONF_TC3_ENABLE +#define CONF_TC3_ENABLE 0 +#endif +#ifndef CONF_TC4_ENABLE +#define CONF_TC4_ENABLE 0 +#endif +#ifndef CONF_TC5_ENABLE +#define CONF_TC5_ENABLE 0 +#endif +#ifndef CONF_TC6_ENABLE +#define CONF_TC6_ENABLE 0 +#endif +#ifndef CONF_TC7_ENABLE +#define CONF_TC7_ENABLE 0 +#endif + +/** + * \brief Macro is used to fill usart configuration structure based on its + * number + * + * \param[in] n The number of structures + */ +#define TC_CONFIGURATION(n) \ + { \ + n, TC##n##_IRQn, \ + TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC) \ + | (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) | (CONF_TC##n##_ONDEMAND << TC_CTRLA_ONDEMAND_Pos) \ + | TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_ALOCK << TC_CTRLA_ALOCK_Pos), \ + (CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos) \ + | (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos) \ + | (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos), \ + (CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1, \ + } +/** + * \brief TC configuration type + */ +struct tc_configuration { + uint8_t number; + IRQn_Type irq; + hri_tc_ctrla_reg_t ctrl_a; + hri_tc_evctrl_reg_t event_ctrl; + hri_tc_dbgctrl_reg_t dbg_ctrl; + hri_tccount8_per_reg_t per; + hri_tccount32_cc_reg_t cc0; + hri_tccount32_cc_reg_t cc1; +}; + +/** + * \brief Array of TC configurations + */ +static struct tc_configuration _tcs[] = { +#if CONF_TC0_ENABLE == 1 + TC_CONFIGURATION(0), +#endif +#if CONF_TC1_ENABLE == 1 + TC_CONFIGURATION(1), +#endif +#if CONF_TC2_ENABLE == 1 + TC_CONFIGURATION(2), +#endif +#if CONF_TC3_ENABLE == 1 + TC_CONFIGURATION(3), +#endif +#if CONF_TC4_ENABLE == 1 + TC_CONFIGURATION(4), +#endif +#if CONF_TC5_ENABLE == 1 + TC_CONFIGURATION(5), +#endif +#if CONF_TC6_ENABLE == 1 + TC_CONFIGURATION(6), +#endif +#if CONF_TC7_ENABLE == 1 + TC_CONFIGURATION(7), +#endif +}; + +static struct _timer_device *_tc0_dev = NULL; + +static struct _pwm_device *_tc7_dev = NULL; + +static int8_t get_tc_index(const void *const hw); +static void _tc_init_irq_param(const void *const hw, void *dev); +static inline uint8_t _get_hardware_offset(const void *const hw); +/** + * \brief Initialize TC + */ +int32_t _timer_init(struct _timer_device *const device, void *const hw) +{ + int8_t i = get_tc_index(hw); + + device->hw = hw; + ASSERT(ARRAY_SIZE(_tcs)); + + if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) { + if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) { + hri_tc_clear_CTRLA_ENABLE_bit(hw); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE); + } + hri_tc_write_CTRLA_reg(hw, TC_CTRLA_SWRST); + } + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + + hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); + hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl); + hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl); + hri_tc_write_WAVE_reg(hw, TC_WAVE_WAVEGEN_MFRQ); + + if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { + hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); + hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1); + + } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) { + hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0); + hri_tccount16_write_CC_reg(hw, 1, (uint16_t)_tcs[i].cc1); + + } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT8) { + hri_tccount8_write_CC_reg(hw, 0, (uint8_t)_tcs[i].cc0); + hri_tccount8_write_CC_reg(hw, 1, (uint8_t)_tcs[i].cc1); + hri_tccount8_write_PER_reg(hw, _tcs[i].per); + } + hri_tc_set_INTEN_OVF_bit(hw); + + _tc_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ(_tcs[i].irq); + NVIC_ClearPendingIRQ(_tcs[i].irq); + NVIC_EnableIRQ(_tcs[i].irq); + + return ERR_NONE; +} +/** + * \brief De-initialize TC + */ +void _timer_deinit(struct _timer_device *const device) +{ + void *const hw = device->hw; + int8_t i = get_tc_index(hw); + ASSERT(ARRAY_SIZE(_tcs)); + + NVIC_DisableIRQ(_tcs[i].irq); + + hri_tc_clear_CTRLA_ENABLE_bit(hw); + hri_tc_set_CTRLA_SWRST_bit(hw); +} +/** + * \brief Start hardware timer + */ +void _timer_start(struct _timer_device *const device) +{ + hri_tc_set_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Stop hardware timer + */ +void _timer_stop(struct _timer_device *const device) +{ + hri_tc_clear_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Set timer period + */ +void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles) +{ + void *const hw = device->hw; + + if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + hri_tccount32_write_CC_reg(hw, 0, clock_cycles); + } else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + hri_tccount16_write_CC_reg(hw, 0, (uint16_t)clock_cycles); + } else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + hri_tccount8_write_PER_reg(hw, clock_cycles); + } +} +/** + * \brief Retrieve timer period + */ +uint32_t _timer_get_period(const struct _timer_device *const device) +{ + void *const hw = device->hw; + + if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + return hri_tccount32_read_CC_reg(hw, 0); + } else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + return hri_tccount16_read_CC_reg(hw, 0); + } else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + return hri_tccount8_read_PER_reg(hw); + } + + return 0; +} +/** + * \brief Check if timer is running + */ +bool _timer_is_started(const struct _timer_device *const device) +{ + return hri_tc_get_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Retrieve timer helper functions + */ +struct _timer_hpl_interface *_tc_get_timer(void) +{ + return NULL; +} + +/** + * \brief Retrieve pwm helper functions + */ +struct _pwm_hpl_interface *_tc_get_pwm(void) +{ + return NULL; +} +/** + * \brief Set timer IRQ + * + * \param[in] hw The pointer to hardware instance + */ +void _timer_set_irq(struct _timer_device *const device) +{ + void *const hw = device->hw; + int8_t i = get_tc_index(hw); + ASSERT(ARRAY_SIZE(_tcs)); + + _irq_set(_tcs[i].irq); +} +/** + * \internal TC interrupt handler for Timer + * + * \param[in] instance TC instance number + */ +static void tc_interrupt_handler(struct _timer_device *device) +{ + void *const hw = device->hw; + + if (hri_tc_get_interrupt_OVF_bit(hw)) { + hri_tc_clear_interrupt_OVF_bit(hw); + device->timer_cb.period_expired(device); + } +} + +/** + * \brief TC interrupt handler + */ +void TC0_Handler(void) +{ + tc_interrupt_handler(_tc0_dev); +} + +/** + * \internal Retrieve TC index + * + * \param[in] hw The pointer to hardware instance + * + * \return The index of TC configuration + */ +static int8_t get_tc_index(const void *const hw) +{ + uint8_t index = _get_hardware_offset(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_tcs); i++) { + if (_tcs[i].number == index) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \brief Init irq param with the given tc hardware instance + */ +static void _tc_init_irq_param(const void *const hw, void *dev) +{ + if (hw == TC0) { + _tc0_dev = (struct _timer_device *)dev; + } + if (hw == TC7) { + _tc7_dev = (struct _pwm_device *)dev; + } +} + +/** + * \internal Retrieve TC hardware index + * + * \param[in] hw The pointer to hardware instance + */ +static inline uint8_t _get_hardware_offset(const void *const hw) +{ + /* List of available TC modules. */ + Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; + + /* Find index for TC instance. */ + for (uint32_t i = 0; i < TC_INST_NUM; i++) { + if ((uint32_t)hw == (uint32_t)tc_modules[i]) { + return i; + } + } + return 0; +} diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/hpl_tc_base.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/hpl_tc_base.h new file mode 100644 index 0000000..ae77c90 --- /dev/null +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/hpl_tc_base.h @@ -0,0 +1,77 @@ +/** + * \file + * + * \brief SAM Timer/Counter + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HPL_TC_BASE_H_INCLUDED +#define _HPL_TC_BASE_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup tc_group TC Hardware Proxy Layer + * + * \section tc_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Retrieve timer helper functions + * + * \return A pointer to set of timer helper functions + */ +struct _timer_hpl_interface *_tc_get_timer(void); + +/** + * \brief Retrieve pwm helper functions + * + * \return A pointer to set of pwm helper functions + */ +struct _pwm_hpl_interface *_tc_get_pwm(void); + +//@} +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_TC_BASE_H_INCLUDED */ diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.c index 6c181c2..48db768 100644 --- a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.c +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.c @@ -34,72 +34,6 @@ #include "tc_lite.h" -/** - * \brief Initialize TC interface - */ -int8_t TIMER_0_init() -{ - - if (!hri_tc_is_syncing(TC0, TC_SYNCBUSY_SWRST)) { - if (hri_tc_get_CTRLA_reg(TC0, TC_CTRLA_ENABLE)) { - hri_tc_clear_CTRLA_ENABLE_bit(TC0); - hri_tc_wait_for_sync(TC0, TC_SYNCBUSY_ENABLE); - } - hri_tc_write_CTRLA_reg(TC0, TC_CTRLA_SWRST); - } - hri_tc_wait_for_sync(TC0, TC_SYNCBUSY_SWRST); - - // hri_tc_write_CTRLA_reg(TC0,0 << TC_CTRLA_CAPTMODE0_Pos /* Capture mode Channel 0: 0 */ - // | 0 << TC_CTRLA_CAPTMODE1_Pos /* Capture mode Channel 1: 0 */ - // | 0 << TC_CTRLA_COPEN0_Pos /* Capture Pin 0 Enable: disabled */ - // | 0 << TC_CTRLA_COPEN1_Pos /* Capture Pin 1 Enable: disabled */ - // | 0 << TC_CTRLA_CAPTEN0_Pos /* Capture Channel 0 Enable: disabled */ - // | 0 << TC_CTRLA_CAPTEN1_Pos /* Capture Channel 1 Enable: disabled */ - // | 0 << TC_CTRLA_ALOCK_Pos /* Auto Lock: disabled */ - // | 0 << TC_CTRLA_PRESCSYNC_Pos /* Prescaler and Counter Synchronization: 0 */ - // | 0 << TC_CTRLA_ONDEMAND_Pos /* Clock On Demand: disabled */ - // | 0 << TC_CTRLA_RUNSTDBY_Pos /* Run in Standby: disabled */ - // | 0 << TC_CTRLA_PRESCALER_Pos /* Setting: 0 */ - // | 0x0 << TC_CTRLA_MODE_Pos); /* Operating Mode: 0x0 */ - - hri_tc_write_CTRLB_reg(TC0, - 0 << TC_CTRLBSET_CMD_Pos /* Command: 0 */ - | 0 << TC_CTRLBSET_ONESHOT_Pos /* One-Shot: disabled */ - | 0 << TC_CTRLBCLR_LUPD_Pos /* Setting: disabled */ - | 0 << TC_CTRLBSET_DIR_Pos); /* Counter Direction: disabled */ - - hri_tc_write_WAVE_reg(TC0, 1); /* Waveform Generation Mode: 1 */ - - // hri_tc_write_DRVCTRL_reg(TC0,0 << TC_DRVCTRL_INVEN1_Pos /* Output Waveform 1 Invert Enable: disabled */ - // | 0 << TC_DRVCTRL_INVEN0_Pos); /* Output Waveform 0 Invert Enable: disabled */ - - // hri_tc_write_DBGCTRL_reg(TC0,0); /* Run in debug: 0 */ - - hri_tccount32_write_CC_reg(TC0, 0, 0x2ee0); /* Compare/Capture Value: 0x2ee0 */ - - hri_tccount32_write_CC_reg(TC0, 1, 0x1770); /* Compare/Capture Value: 0x1770 */ - - // hri_tccount32_write_COUNT_reg(TC0,0x0); /* Counter Value: 0x0 */ - - hri_tc_write_EVCTRL_reg(TC0, - 1 << TC_EVCTRL_MCEO0_Pos /* Match or Capture Channel 0 Event Output Enable: enabled */ - | 1 << TC_EVCTRL_MCEO1_Pos /* Match or Capture Channel 1 Event Output Enable: enabled */ - | 1 << TC_EVCTRL_OVFEO_Pos /* Overflow/Underflow Event Output Enable: enabled */ - | 0 << TC_EVCTRL_TCEI_Pos /* TC Event Input: disabled */ - | 0 << TC_EVCTRL_TCINV_Pos /* TC Inverted Event Input: disabled */ - | 0); /* Event Action: 0 */ - - hri_tc_write_INTEN_reg(TC0, - 0 << TC_INTENSET_MC0_Pos /* Match or Capture Channel 0 Interrupt Enable: disabled */ - | 1 << TC_INTENSET_MC1_Pos /* Match or Capture Channel 1 Interrupt Enable: enabled */ - | 0 << TC_INTENSET_ERR_Pos /* Error Interrupt Enable: disabled */ - | 1 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: enabled */ - - hri_tc_write_CTRLA_ENABLE_bit(TC0, 1 << TC_CTRLA_ENABLE_Pos); /* Enable: enabled */ - - return 0; -} - /** * \brief Initialize TC interface */ diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.h index a2c0e77..4b4781e 100644 --- a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.h +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.h @@ -51,12 +51,6 @@ extern "C" { #endif -/** - * \brief Initialize tc interface - * \return Initialization status. - */ -int8_t TIMER_0_init(); - /** * \brief Initialize tc interface * \return Initialization status. diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c index 96d6f8f..301349a 100644 --- a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c +++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c @@ -27,7 +27,7 @@ volatile uint8_t received_data_len = 0; static uint8_t rx_buffer[SLAVE_BUFFER_SIZE] = {0}; static uint8_t tx_buffer[SLAVE_BUFFER_SIZE] = {63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48,47,46,45,44,43,42, - 41,40,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20, + 41,40,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20, 19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0}; @@ -50,7 +50,7 @@ static void spi_master_rx_complete_cb(struct _dma_resource *resource) } /* Start SPI master data transfer */ -void spi_master_tx(uint8_t *buffer, uint8_t length) +void spi_master_transfer(uint8_t *buffer, uint8_t length) { //spi_m_dma_enable(&SPI_0); gpio_set_pin_level(SPI_CS, false); @@ -59,14 +59,6 @@ void spi_master_tx(uint8_t *buffer, uint8_t length) } -/* Start SPI master data Reception from Slave */ -void spi_master_rx(uint8_t *buffer, uint8_t length) -{ - spi_m_dma_enable(&SPI_0); - gpio_set_pin_level(SPI_CS, false); - io_read(io_spi_master, buffer, length); -} - /* SPI master IO and Callback Initialization */ void spi_master_init(void) { @@ -106,7 +98,7 @@ int main(void) /* Initialize SPI master IO and Callback */ spi_master_init(); spi_m_dma_enable(&SPI_0); - configure_ethercat_dma_descriptors(); + //configure_ethercat_dma_descriptors(); enable_NVIC_IRQ(); /* Start SPI Master data transfer using DMA */ @@ -115,33 +107,9 @@ int main(void) /* Start SPI Master data reception using DMA */ //spi_master_rx(tx_buffer, BUFFER_LEN); printf("Init Complete\n\r"); + /* Replace with your application code */ while (1) { - //delay_ms(500); - ////tx_buffer[4] = tx_buffer[4]+1; - ////spi_master_rx(rx_buffer, BUFFER_LEN); - //tx_buffer[63] += 1; - //spi_master_tx(tx_buffer, SLAVE_BUFFER_SIZE); - // - //if (spi_master_tx_complete) { - //spi_master_rx_complete = false; - //printf("Master Sent DATA = "); - ///* Print Received data by SPI Master from SPI Slave on Console */ - //for (int i = 0; i < SLAVE_BUFFER_SIZE; i++) { - //printf("%u, ", tx_buffer[i]); - //} - //printf("\n\r"); - // - //} - ///* Check for SPI Master is received data from SPI Slave */ - //if (spi_master_rx_complete) { - //spi_master_rx_complete = false; - //printf("Master Recieved DATA = "); - ///* Print Received data by SPI Master from SPI Slave on Console */ - //for (int i = 0; i < SLAVE_BUFFER_SIZE; i++) { - //printf("%u, ", rx_buffer[i]); - //} - //printf("\n\r"); - //} + } } diff --git a/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/A1335.c b/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/A1335.c index c05287c..579d542 100644 --- a/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/A1335.c +++ b/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/A1335.c @@ -6,8 +6,6 @@ */ #include "A1335.h" - - //--- Normal Write Registers ---// #define EWA (0x02U) // Extended Write Address #define EWD (0x04U) // Extended Write Data @@ -25,11 +23,14 @@ #define ERM (0x34U) // Device error status masking #define XERM (0x36U) // Extended error status masking +const uint32_t WRITE = 0x40; +const uint32_t READ = 0x00; +const uint32_t COMMAND_MASK = 0xC0; +const uint32_t ADDRESS_MASK = 0x3F; + //--- Extended Write Registers ---// #define ORATE (0xFFD0) // Output Rate - //--- Errors ---// - #define kNOERROR 0 #define kPRIMARYREADERROR 1 #define kEXTENDEDREADTIMEOUTERROR 2 @@ -38,23 +39,11 @@ #define kCRCERROR 5 #define kUNABLETOCHANGEPROCESSORSTATE 6 -const uint16_t ChipSelectPin = 5; -const uint16_t LEDPin = 13; +bool debugPrint = true; -const uint32_t WRITE = 0x40; -const uint32_t READ = 0x00; -const uint32_t COMMAND_MASK = 0xC0; -const uint32_t ADDRESS_MASK = 0x3F; - -unsigned long nextTime; -bool ledOn = false; -bool includeCRC = false; - -bool debugPrint = false; - -struct SPI_S A1 = { - .SPI_angleSensor_n = NULL, - .io = NULL, +struct SPI_A1335 A1 = { + .SPI_descr = NULL, + .io_descr = NULL, .state = 0, .SS_pin = Angle_SS, .tx_buffer = NULL, @@ -62,13 +51,17 @@ struct SPI_S A1 = { }; -void angleSensor_init(struct spi_m_sync_descriptor *spi, struct SPI_S *Sn) +void a1335_init(struct spi_m_sync_descriptor *spi, struct SPI_A1335 *Sn) { - Sn->SPI_angleSensor_n = spi; - spi_m_sync_get_io_descriptor(Sn->SPI_angleSensor_n, &Sn->io); - spi_m_sync_enable(Sn->SPI_angleSensor_n); + Sn->SPI_descr = spi; + // Set Mode 3 : CPOL = 1; CPHA = 1; + hri_sercomspi_write_CTRLA_CPOL_bit(spi->dev.prvt, true); + hri_sercomspi_write_CTRLA_CPHA_bit(spi->dev.prvt, true); + //Get IO descriptor + spi_m_sync_get_io_descriptor(Sn->SPI_descr, &Sn->io_descr); + spi_m_sync_enable(Sn->SPI_descr); gpio_set_pin_level(Sn->SS_pin, true); - if(Sn->io == NULL || Sn->SPI_angleSensor_n == NULL) + if(Sn->io_descr == NULL || Sn->SPI_descr == NULL) { Sn->state = 4; } else { @@ -76,7 +69,7 @@ void angleSensor_init(struct spi_m_sync_descriptor *spi, struct SPI_S *Sn) } } -void angleSensor_State_Machine(struct SPI_S *Sn) +void a1335_State_Machine(struct SPI_A1335 *Sn) { volatile uint16_t angle; switch(Sn->state){ @@ -85,19 +78,8 @@ void angleSensor_State_Machine(struct SPI_S *Sn) case 1: // State After angleSensor_init. Configure Sensor Sn->state++; break; - case 2: // Syncronouse blocking read - PrimaryRead(Sn, 0x20, &angle); - if (CalculateParity(angle)) - { - volatile float read_angle = (float)(angle & 0x0FFF) * 360.0 / 4096.0; - printf("Angle = "); - printf("%f", read_angle); - printf(" Degrees\n\r"); - } - else - { - printf("Parity error on Angle read\n\r"); - } + case 2: // Synchronous blocking read + a1335_getRotationInDegrees(Sn); break; case 3: // Continuously Read Angle (DMA) break; @@ -106,6 +88,44 @@ void angleSensor_State_Machine(struct SPI_S *Sn) } } +/* + * getRawRotation + * + * Read Raw Angle Register Value + */ +uint16_t a1335_getRawRotation(struct SPI_A1335 *Sn) +{ + uint16_t rawAngle; + PrimaryRead(Sn, ANG, &rawAngle); + return rawAngle; +} + +/* + * getRotationInDegrees + * + * Read angle register and return angle in Degrees + */ +float a1335_getRotationInDegrees(struct SPI_A1335 *Sn) +{ + uint16_t rawAngle = a1335_getRawRotation(Sn); + float angleDegrees; + if (CalculateParity(rawAngle)) + { + angleDegrees = (float)(rawAngle & 0x0FFF) * 360.0 / 4096.0; + if (debugPrint) + { + printf("Angle = "); + printf("%f", angleDegrees); + printf(" Degrees\n\r"); + } + } + else + { + printf("Parity error on Angle read\n\r"); + } + return angleDegrees; +} + /* * CalculateParity * @@ -166,7 +186,7 @@ uint8_t CalculateCRC(uint16_t input) * * Read from the primary serial registers */ -uint16_t PrimaryRead(struct SPI_S *Sn, uint16_t address, uint16_t* value) +uint16_t PrimaryRead(struct SPI_A1335 *Sn, uint16_t address, uint16_t* value) { uint8_t in_buf[2], out_buf[2]; @@ -177,11 +197,12 @@ uint16_t PrimaryRead(struct SPI_S *Sn, uint16_t address, uint16_t* value) out_buf[1] = command & 0xFF; out_buf[0] = ( command >> 8 ) & 0xFF; gpio_set_pin_level(Sn->SS_pin, false); - transfer16(Sn, command); + a1335_transfer16(Sn, command); gpio_set_pin_level(Sn->SS_pin, true); - + + /* Send again to Get Response */ gpio_set_pin_level(Sn->SS_pin, false); - returnedVal = transfer16(Sn, command); + returnedVal = a1335_transfer16(Sn, command); gpio_set_pin_level(Sn->SS_pin, true); // printf("In_buff= "); @@ -200,7 +221,7 @@ uint16_t PrimaryRead(struct SPI_S *Sn, uint16_t address, uint16_t* value) return kNOERROR; } -uint16_t transfer16(struct SPI_S *Sn, uint16_t value) +uint16_t a1335_transfer16(struct SPI_A1335 *Sn, uint16_t value) { uint8_t in_buf[2], out_buf[2]; uint16_t wordRead; @@ -211,12 +232,11 @@ uint16_t transfer16(struct SPI_S *Sn, uint16_t value) xfer.rxbuf = in_buf; xfer.txbuf = (uint8_t *)out_buf; xfer.size = 2; - spi_m_sync_transfer(Sn->SPI_angleSensor_n, &xfer); + spi_m_sync_transfer(Sn->SPI_descr, &xfer); wordRead = (uint16_t)((in_buf[0] << 8) | in_buf[1]); return wordRead; } - /* * PrimaryWrite * diff --git a/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/A1335.h b/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/A1335.h index 069951f..043c609 100644 --- a/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/A1335.h +++ b/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/A1335.h @@ -10,9 +10,9 @@ #define A1335_H_ #include -struct SPI_S { - struct spi_m_sync_descriptor *SPI_angleSensor_n; - struct io_descriptor *io; +struct SPI_A1335 { + struct spi_m_sync_descriptor *SPI_descr; + struct io_descriptor *io_descr; uint8_t state; uint32_t SS_pin; struct spi_xfer xfer; @@ -20,22 +20,26 @@ struct SPI_S { uint8_t *rx_buffer; }; -struct SPI_S A1; +struct SPI_A1335 A1; struct io_descriptor *io; -void angleSensor_init(struct spi_m_sync_descriptor *spi, struct SPI_S *Sn); -void angleSensor_State_Machine(struct SPI_S *Sn); +void a1335_init(struct spi_m_sync_descriptor *spi, struct SPI_A1335 *Sn); +void a1335_State_Machine(struct SPI_A1335 *Sn); -bool CalculateParity(uint16_t input); -uint8_t CalculateCRC(uint16_t input); -uint16_t PrimaryRead(struct SPI_S *Sn, uint16_t address, uint16_t* value); +uint16_t PrimaryRead(struct SPI_A1335 *Sn, uint16_t address, uint16_t* value); uint16_t PrimaryWrite(uint16_t cs, uint16_t address, uint16_t value); uint16_t ExtendedRead(uint16_t cs, uint16_t address, uint32_t value); uint16_t ExtendedWrite(uint16_t cs, uint16_t address, uint32_t value); uint16_t SetProcessorStateToRun(uint8_t cs); uint16_t SetProcessorStateToIdle(uint8_t cs); uint16_t SetProcessorStateToRun(uint8_t cs); -uint16_t transfer16(struct SPI_S *Sn, uint16_t value); +bool CalculateParity(uint16_t input); +uint8_t CalculateCRC(uint16_t input); +uint16_t a1335_transfer16(struct SPI_A1335 *Sn, uint16_t value); + +uint16_t a1335_getRawRotation(struct SPI_A1335 *Sn); +float a1335_getRotationInDegrees(struct SPI_A1335 *Sn); +uint16_t getErrors(void); #endif /* A1335_H_ */ \ No newline at end of file diff --git a/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/AS5048.c b/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/AS5048.c new file mode 100644 index 0000000..4e04fd4 --- /dev/null +++ b/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/AS5048.c @@ -0,0 +1,186 @@ +/* + * AS5048.c + * + * Created: 27/07/2021 16:13:20 + * Author: Nick-XMG + */ + +#include "AS5048.h" + +#define AS5048A_CMD_NOP (0x0000) +#define AS5048A_READ (0x4000) +#define AS5048A_CLEAR_ERROR_FLAG (0x0001) +#define AS5048A_PROGRAMMING_CONTROL (0x0003) +#define AS5048A_OTP_REGISTER_ZERO_POS_HIGH (0x0016) +#define AS5048A_OTP_REGISTER_ZERO_POS_LOW (0x0017) +#define AS5048A_DIAG_AGC (0x3FFD) +#define AS5048A_MAGNITUDE (0x3FFE) +#define AS5048A_ANGLE (0x3FFF) + + +#define AS5048A_MAX_VALUE (8191.0f) + +static bool debugPrint = true; + +struct SPI_AS5048 AS_1 = { + .SPI_descr = NULL, + .io_descr = NULL, + .flags = 0, + .state = 0, + .SS_pin = Angle_SS, + .tx_buffer = NULL, + .rx_buffer = NULL, + +}; + +void as5048a_State_Machine(struct SPI_AS5048 *Sn) +{ + volatile uint16_t angle; + switch(Sn->state) { + case 0: // Default un-initialized State + break; + case 1: // State After angleSensor_init. Configure Sensor + Sn->state++; + break; + case 2: // Synchronous blocking read + as5048a_getRotationInDegrees(Sn); + break; + case 3: // Continuously Read Angle (DMA) + break; + case 4: // Error State + break; + } +} + +void as5048a_init(struct spi_m_sync_descriptor *spi, struct SPI_AS5048 *Sn) +{ + Sn->SPI_descr = spi; + spi_m_sync_disable(&SPI_1); + + // Set Mode 1 : CPOL = 0; CPHA = 1; + hri_sercomspi_write_CTRLA_CPOL_bit(&SPI_1, false); + hri_sercomspi_write_CTRLA_CPHA_bit(&SPI_1, true); + + //Get IO descriptor + spi_m_sync_get_io_descriptor(Sn->SPI_descr, &Sn->io_descr); + spi_m_sync_enable(&SPI_1); + gpio_set_pin_level(Sn->SS_pin, true); + if(Sn->io_descr == NULL || Sn->SPI_descr == NULL) { + Sn->state = 4; + } else { + Sn->state = 1; + } +} + +uint16_t as5048a_read(struct SPI_AS5048 *Sn, uint16_t address) +{ + uint8_t in_buf[2], out_buf[2]; + uint16_t returnedVal; + + volatile uint16_t command = 0b0100000000000000; // PAR=0 R/W=R + command = command | address; + + //Add a parity bit on the the MSB + command |= ((uint16_t)as5048a_CalcEvenParity(command)<<15); + + //Split the command into two bytes + out_buf[1] = command & 0xFF; + out_buf[0] = ( command >> 8 ) & 0xFF; + + /* Send Command */ + gpio_set_pin_level(Sn->SS_pin, false); + as5048a_transfer16(Sn, command); + gpio_set_pin_level(Sn->SS_pin, true); + + /* Send again to Get Response */ + gpio_set_pin_level(Sn->SS_pin, false); + returnedVal = as5048a_transfer16(Sn, command); + gpio_set_pin_level(Sn->SS_pin, true); + + // printf("In_buff= "); + // /* Print Received data by SPI Master from SPI Slave on Console */ + // for (int i = 0; i < 2; i++) { + // printf("%u", in_buf[i]); + // } + // printf("\n\r"); if(debugPrint) { + printf("Returned val = %u \n\r", returnedVal); + } + + + if (returnedVal & 0x4000) { + Sn->flags = 1; + } else { + Sn->flags = 0; + } + + //Return the data, stripping the parity and error bits + return (( ( in_buf[1] & 0xFF ) << 8 ) | ( in_buf[0] & 0xFF )) & ~0xC000; +} + +/* + * getRawRotation + * + * Read Raw Angle Register Value + */ +uint16_t as5048a_getRawRotation(struct SPI_AS5048 *Sn) +{ + volatile uint16_t rawAngle = as5048a_read(Sn, AS5048A_ANGLE); + return rawAngle; +} + +int16_t as5048a_getRotation(struct SPI_AS5048 *Sn) +{ + uint16_t data; + int16_t rotation; + + data = as5048a_getRawRotation(Sn); + rotation = (int16_t)(data); //- static_cast(this->position); + if (rotation > AS5048A_MAX_VALUE) { + rotation = -((0x3FFF) - rotation); //more than -180 + } + + return rotation; + +} + +/* +* getRotationInDegrees +* +* Read angle register and return angle in Degrees +*/ +float as5048a_getRotationInDegrees(struct SPI_AS5048 *Sn) +{ + uint16_t rawAngle = as5048a_getRotation(Sn); + float angleDegrees = 360.0 * (rawAngle + AS5048A_MAX_VALUE) / (AS5048A_MAX_VALUE * 2.0);; + + return angleDegrees; +} + + +uint16_t as5048a_transfer16(struct SPI_AS5048 *Sn, uint16_t value) +{ + uint8_t in_buf[2], out_buf[2]; + uint16_t wordRead; + + out_buf[1] = value & 0xFF; + out_buf[0] = ( value >> 8 ) & 0xFF; + struct spi_xfer xfer; + xfer.rxbuf = in_buf; + xfer.txbuf = (uint8_t *)out_buf; + xfer.size = 2; + spi_m_sync_transfer(Sn->SPI_descr, &xfer); + wordRead = (uint16_t)((in_buf[0] << 8) | in_buf[1]); + return wordRead; +} + +uint8_t as5048a_CalcEvenParity(uint16_t value) { + uint8_t cnt = 0; + uint8_t i; + for (i = 0; i < 16; i++) { + if (value & 0x1) { + cnt++; + } + value >>= 1; + } + return cnt & 0x1; +} \ No newline at end of file diff --git a/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/AS5048.h b/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/AS5048.h new file mode 100644 index 0000000..533d944 --- /dev/null +++ b/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/AS5048.h @@ -0,0 +1,38 @@ +/* + * AS5048.h + * + * Created: 27/07/2021 16:12:53 + * Author: Nick-XMG + */ + +#ifndef AS5048_H_ +#define AS5048_H_ +#include + + +struct SPI_AS5048 { + struct spi_m_sync_descriptor *SPI_descr; + struct io_descriptor *io_descr; + uint8_t state; + uint8_t flags; + uint32_t SS_pin; + uint8_t *tx_buffer; + uint8_t *rx_buffer; +}; + +struct SPI_AS5048 AS_1; + +void as5048a_init(struct spi_m_sync_descriptor *spi, struct SPI_AS5048 *Sn); +void as5048a_State_Machine(struct SPI_AS5048 *Sn); +// +///* Sensor Specific Read Functions */ +uint16_t as5048a_read(struct SPI_AS5048 *Sn, uint16_t address); +uint16_t as5048a_getRawRotation(struct SPI_AS5048 *Sn); +int16_t as5048a_getRotation(struct SPI_AS5048 *Sn); +float as5048a_getRotationInDegrees(struct SPI_AS5048 *Sn); +// +///* Support Functions */ +uint16_t as5048a_transfer16(struct SPI_AS5048 *Sn, uint16_t value); +uint8_t as5048a_CalcEvenParity(uint16_t value); + +#endif /* AS5048_H_ */ \ No newline at end of file diff --git a/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj b/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj index 72d2831..e4351ef 100644 --- a/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj +++ b/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj @@ -442,6 +442,12 @@ compile + + compile + + + compile + compile diff --git a/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c b/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c index 3b81afa..c6750db 100644 --- a/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c +++ b/Examples/SPI_Data_Mirroring_Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c @@ -1,6 +1,7 @@ #include #include "spi_slave_dma_config.h" #include "A1335.h" +#include "AS5048.h" /* Buffer length to transfer/receive */ #define BUFFER_LEN (6) @@ -25,7 +26,8 @@ static struct timer_task TIMER_0_task1; static void task1_cb(const struct timer_task *const timer_task) { volatile int i = 0; - angleSensor_State_Machine(&A1); + //a1335_State_Machine(&A1); + as5048a_State_Machine(&AS_1); } @@ -89,7 +91,8 @@ int main(void) atmel_start_init(); /* Initialize SPI master IO and Callback */ //spi_master_init(); - angleSensor_init(&SPI_1, &A1); + //a1335_init(&SPI_1, &A1); + as5048a_init(&SPI_1, &AS_1); TIMER_0_init(); //spi_m_dma_enable(&SPI_0);