diff --git a/2_Motor_Master_D51/Two_Motor_D51.atstart b/2_Motor_Master_D51/Two_Motor_D51.atstart new file mode 100644 index 0000000..0c35b4c --- /dev/null +++ b/2_Motor_Master_D51/Two_Motor_D51.atstart @@ -0,0 +1,2712 @@ +format_version: '2' +name: Two_Motor_D51 +versions: + api: '1.0' + backend: 1.8.580 + commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c + content: unknown + content_pack_name: unknown + format: '2' + frontend: 1.8.580 + packs_version_avr8: 1.0.1463 + packs_version_qtouch: unknown + packs_version_sam: 1.0.1726 + version_backend: 1.8.580 + version_frontend: '' +board: + identifier: CustomBoard + device: SAMD51J18A-MF +details: null +application: null +middlewares: {} +drivers: + ADC_0: + user_label: ADC_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::ADC0::driver_config_definition::ADC::HAL:Driver:ADC.Sync + functionality: ADC + api: HAL:Driver:ADC_Sync + configuration: + adc_advanced_settings: false + adc_arch_adjres: 0 + adc_arch_corren: false + adc_arch_dbgrun: false + adc_arch_event_settings: false + adc_arch_flushei: false + adc_arch_flushinv: false + adc_arch_gaincorr: 0 + adc_arch_leftadj: false + adc_arch_offcomp: false + adc_arch_offsetcorr: 0 + adc_arch_ondemand: false + adc_arch_refcomp: false + adc_arch_resrdyeo: false + adc_arch_runstdby: false + adc_arch_samplen: 0 + adc_arch_samplenum: 1 sample + adc_arch_seqen: 0 + adc_arch_startei: false + adc_arch_startinv: false + adc_arch_winlt: 0 + adc_arch_winmode: No window mode + adc_arch_winmoneo: false + adc_arch_winut: 0 + adc_differential_mode: false + adc_freerunning_mode: false + adc_pinmux_negative: ADC AIN0 pin + adc_pinmux_positive: ADC AIN0 pin + adc_prescaler: Peripheral clock divided by 2 + adc_reference: Internal bandgap reference + adc_resolution: 12-bit + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: ADC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + adc_gclk_selection: Generic clock generator 0 + ADC_1: + user_label: ADC_1 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::ADC1::driver_config_definition::ADC::HAL:Driver:ADC.Sync + functionality: ADC + api: HAL:Driver:ADC_Sync + configuration: + adc_advanced_settings: true + adc_arch_adjres: 0 + adc_arch_corren: false + adc_arch_dbgrun: false + adc_arch_event_settings: true + adc_arch_flushei: false + adc_arch_flushinv: false + adc_arch_gaincorr: 0 + adc_arch_leftadj: false + adc_arch_offcomp: false + adc_arch_offsetcorr: 0 + adc_arch_ondemand: false + adc_arch_refcomp: false + adc_arch_resrdyeo: true + adc_arch_runstdby: false + adc_arch_samplen: 2 + adc_arch_samplenum: 1 sample + adc_arch_seqen: 0 + adc_arch_startei: false + adc_arch_startinv: false + adc_arch_winlt: 0 + adc_arch_winmode: No window mode + adc_arch_winmoneo: false + adc_arch_winut: 0 + adc_differential_mode: true + adc_freerunning_mode: false + adc_pinmux_negative: ADC AIN0 pin + adc_pinmux_positive: ADC AIN6 pin + adc_prescaler: Peripheral clock divided by 8 + adc_reference: External reference A + adc_resolution: 12-bit + optional_signals: + - identifier: ADC_1:AIN/0 + pad: PB08 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.0 + name: ADC1/AIN/0 + label: AIN/0 + - identifier: ADC_1:AIN/6 + pad: PB04 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.6 + name: ADC1/AIN/6 + label: AIN/6 + - identifier: ADC_1:AIN/7 + pad: PB05 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.7 + name: ADC1/AIN/7 + label: AIN/7 + - identifier: ADC_1:AIN/8 + pad: PB06 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.8 + name: ADC1/AIN/8 + label: AIN/8 + - identifier: ADC_1:AIN/9 + pad: PB07 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.9 + name: ADC1/AIN/9 + label: AIN/9 + variant: null + clocks: + domain_group: + nodes: + - name: ADC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + adc_gclk_selection: Generic clock generator 0 + DIGITAL_GLUE_LOGIC_0: + user_label: DIGITAL_GLUE_LOGIC_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::CCL::driver_config_definition::CCL::HAL:Driver:CCL + functionality: Digital_Glue_Logic + api: HAL:Driver:CCL + configuration: + ccl_arch_advanced_settings: false + ccl_arch_edgesel_0: false + ccl_arch_edgesel_1: false + ccl_arch_edgesel_2: false + ccl_arch_edgesel_3: false + ccl_arch_filtsel_0: Disabled + ccl_arch_filtsel_1: Disabled + ccl_arch_filtsel_2: Disabled + ccl_arch_filtsel_3: Disabled + ccl_arch_insel0_0: IO pin input source + ccl_arch_insel0_1: IO pin input source + ccl_arch_insel0_2: IO pin input source + ccl_arch_insel0_3: IO pin input source + ccl_arch_insel1_0: IO pin input source + ccl_arch_insel1_1: IO pin input source + ccl_arch_insel1_2: IO pin input source + ccl_arch_insel1_3: IO pin input source + ccl_arch_insel2_0: IO pin input source + ccl_arch_insel2_1: IO pin input source + ccl_arch_insel2_2: IO pin input source + ccl_arch_insel2_3: IO pin input source + ccl_arch_invei_0: false + ccl_arch_invei_1: false + ccl_arch_invei_2: false + ccl_arch_invei_3: false + ccl_arch_lutctrl0: true + ccl_arch_lutctrl1: false + ccl_arch_lutctrl2: true + ccl_arch_lutctrl3: false + ccl_arch_lutei_0: false + ccl_arch_lutei_1: false + ccl_arch_lutei_2: false + ccl_arch_lutei_3: false + ccl_arch_luteo_0: true + ccl_arch_luteo_1: false + ccl_arch_luteo_2: true + ccl_arch_luteo_3: false + ccl_arch_runstdby: false + ccl_arch_seqsel_0: Sequential logic is disabled + ccl_arch_seqsel_1: Sequential logic is disabled + ccl_arch_truth_0: 150 + ccl_arch_truth_1: 0 + ccl_arch_truth_2: 150 + ccl_arch_truth_3: 0 + ccl_e_persistance_0: '' + ccl_e_persistance_1: '' + ccl_e_persistance_2: '' + ccl_e_persistance_3: '' + ccl_l_persistance_0: '' + ccl_l_persistance_1: '' + ccl_l_persistance_2: '' + ccl_l_persistance_3: '' + optional_signals: + - identifier: DIGITAL_GLUE_LOGIC_0:IN/0 + pad: PA04 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.0 + name: CCL/IN/0 + label: IN/0 + - identifier: DIGITAL_GLUE_LOGIC_0:IN/1 + pad: PA05 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.1 + name: CCL/IN/1 + label: IN/1 + - identifier: DIGITAL_GLUE_LOGIC_0:IN/2 + pad: PA06 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.2 + name: CCL/IN/2 + label: IN/2 + - identifier: DIGITAL_GLUE_LOGIC_0:IN/6 + pad: PA22 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.6 + name: CCL/IN/6 + label: IN/6 + - identifier: DIGITAL_GLUE_LOGIC_0:IN/7 + pad: PA23 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.7 + name: CCL/IN/7 + label: IN/7 + - identifier: DIGITAL_GLUE_LOGIC_0:IN/8 + pad: PA24 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.8 + name: CCL/IN/8 + label: IN/8 + variant: null + clocks: + domain_group: + nodes: + - name: CCL + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + ccl_gclk_selection: Generic clock generator 0 + CMCC: + user_label: CMCC + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC + functionality: System + api: HAL:HPL:CMCC + configuration: + cache_size: 4 KB + cmcc_advanced_configuration: false + cmcc_clock_gating_disable: false + cmcc_data_cache_disable: false + cmcc_enable: false + cmcc_inst_cache_disable: false + optional_signals: [] + variant: null + clocks: + domain_group: null + DMAC: + user_label: DMAC + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + functionality: System + api: HAL:HPL:DMAC + configuration: + dmac_beatsize_0: 32-bit bus transfer + dmac_beatsize_1: 32-bit bus transfer + dmac_beatsize_10: 8-bit bus transfer + dmac_beatsize_11: 8-bit bus transfer + dmac_beatsize_12: 8-bit bus transfer + dmac_beatsize_13: 8-bit bus transfer + dmac_beatsize_14: 8-bit bus transfer + dmac_beatsize_15: 8-bit bus transfer + dmac_beatsize_16: 8-bit bus transfer + dmac_beatsize_17: 8-bit bus transfer + dmac_beatsize_18: 8-bit bus transfer + dmac_beatsize_19: 8-bit bus transfer + dmac_beatsize_2: 32-bit bus transfer + dmac_beatsize_20: 8-bit bus transfer + dmac_beatsize_21: 8-bit bus transfer + dmac_beatsize_22: 8-bit bus transfer + dmac_beatsize_23: 8-bit bus transfer + dmac_beatsize_24: 8-bit bus transfer + dmac_beatsize_25: 8-bit bus transfer + dmac_beatsize_26: 8-bit bus transfer + dmac_beatsize_27: 8-bit bus transfer + dmac_beatsize_28: 8-bit bus transfer + dmac_beatsize_29: 8-bit bus transfer + dmac_beatsize_3: 16-bit bus transfer + dmac_beatsize_30: 8-bit bus transfer + dmac_beatsize_31: 8-bit bus transfer + dmac_beatsize_4: 32-bit bus transfer + dmac_beatsize_5: 32-bit bus transfer + dmac_beatsize_6: 32-bit bus transfer + dmac_beatsize_7: 32-bit bus transfer + dmac_beatsize_8: 8-bit bus transfer + dmac_beatsize_9: 8-bit bus transfer + dmac_blockact_0: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_1: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_10: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_11: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_12: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_13: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_14: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_15: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_16: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_17: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_18: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_19: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_2: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_20: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_21: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_22: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_23: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_24: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_25: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_26: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_27: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_28: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_29: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_3: Channel will be disabled if it is the last block transfer in + the transaction and block interrupt + dmac_blockact_30: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_31: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_4: Channel suspend operation is complete + dmac_blockact_5: Channel suspend operation is complete + dmac_blockact_6: Channel suspend operation is complete + dmac_blockact_7: Channel suspend operation is complete + dmac_blockact_8: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_9: Channel will be disabled if it is the last block transfer in + the transaction + dmac_channel_0_settings: true + dmac_channel_10_settings: false + dmac_channel_11_settings: false + dmac_channel_12_settings: false + dmac_channel_13_settings: false + dmac_channel_14_settings: false + dmac_channel_15_settings: false + dmac_channel_16_settings: false + dmac_channel_17_settings: false + dmac_channel_18_settings: false + dmac_channel_19_settings: false + dmac_channel_1_settings: true + dmac_channel_20_settings: false + dmac_channel_21_settings: false + dmac_channel_22_settings: false + dmac_channel_23_settings: false + dmac_channel_24_settings: false + dmac_channel_25_settings: false + dmac_channel_26_settings: false + dmac_channel_27_settings: false + dmac_channel_28_settings: false + dmac_channel_29_settings: false + dmac_channel_2_settings: true + dmac_channel_30_settings: false + dmac_channel_31_settings: false + dmac_channel_3_settings: true + dmac_channel_4_settings: true + dmac_channel_5_settings: true + dmac_channel_6_settings: true + dmac_channel_7_settings: true + dmac_channel_8_settings: false + dmac_channel_9_settings: false + dmac_dbgrun: false + dmac_dstinc_0: true + dmac_dstinc_1: true + dmac_dstinc_10: false + dmac_dstinc_11: false + dmac_dstinc_12: false + dmac_dstinc_13: false + dmac_dstinc_14: false + dmac_dstinc_15: false + dmac_dstinc_16: false + dmac_dstinc_17: false + dmac_dstinc_18: false + dmac_dstinc_19: false + dmac_dstinc_2: true + dmac_dstinc_20: false + dmac_dstinc_21: false + dmac_dstinc_22: false + dmac_dstinc_23: false + dmac_dstinc_24: false + dmac_dstinc_25: false + dmac_dstinc_26: false + dmac_dstinc_27: false + dmac_dstinc_28: false + dmac_dstinc_29: false + dmac_dstinc_3: true + dmac_dstinc_30: false + dmac_dstinc_31: false + dmac_dstinc_4: false + dmac_dstinc_5: false + dmac_dstinc_6: false + dmac_dstinc_7: false + dmac_dstinc_8: false + dmac_dstinc_9: false + dmac_enable: true + dmac_evact_0: No action + dmac_evact_1: No action + dmac_evact_10: No action + dmac_evact_11: No action + dmac_evact_12: No action + dmac_evact_13: No action + dmac_evact_14: No action + dmac_evact_15: No action + dmac_evact_16: No action + dmac_evact_17: No action + dmac_evact_18: No action + dmac_evact_19: No action + dmac_evact_2: No action + dmac_evact_20: No action + dmac_evact_21: No action + dmac_evact_22: No action + dmac_evact_23: No action + dmac_evact_24: No action + dmac_evact_25: No action + dmac_evact_26: No action + dmac_evact_27: No action + dmac_evact_28: No action + dmac_evact_29: No action + dmac_evact_3: No action + dmac_evact_30: No action + dmac_evact_31: No action + dmac_evact_4: Channel resume operation + dmac_evact_5: Channel resume operation + dmac_evact_6: Channel resume operation + dmac_evact_7: No action + dmac_evact_8: No action + dmac_evact_9: No action + dmac_evie_0: false + dmac_evie_1: false + dmac_evie_10: false + dmac_evie_11: false + dmac_evie_12: false + dmac_evie_13: false + dmac_evie_14: false + dmac_evie_15: false + dmac_evie_16: false + dmac_evie_17: false + dmac_evie_18: false + dmac_evie_19: false + dmac_evie_2: false + dmac_evie_20: false + dmac_evie_21: false + dmac_evie_22: false + dmac_evie_23: false + dmac_evie_24: false + dmac_evie_25: false + dmac_evie_26: false + dmac_evie_27: false + dmac_evie_28: false + dmac_evie_29: false + dmac_evie_3: false + dmac_evie_30: false + dmac_evie_31: false + dmac_evie_4: true + dmac_evie_5: true + dmac_evie_6: true + dmac_evie_7: true + dmac_evie_8: false + dmac_evie_9: false + dmac_evoe_0: true + dmac_evoe_1: true + dmac_evoe_10: false + dmac_evoe_11: false + dmac_evoe_12: false + dmac_evoe_13: false + dmac_evoe_14: false + dmac_evoe_15: false + dmac_evoe_16: false + dmac_evoe_17: false + dmac_evoe_18: false + dmac_evoe_19: false + dmac_evoe_2: true + dmac_evoe_20: false + dmac_evoe_21: false + dmac_evoe_22: false + dmac_evoe_23: false + dmac_evoe_24: false + dmac_evoe_25: false + dmac_evoe_26: false + dmac_evoe_27: false + dmac_evoe_28: false + dmac_evoe_29: false + dmac_evoe_3: false + dmac_evoe_30: false + dmac_evoe_31: false + dmac_evoe_4: false + dmac_evoe_5: false + dmac_evoe_6: false + dmac_evoe_7: false + dmac_evoe_8: false + dmac_evoe_9: false + dmac_evosel_0: Event strobe when block transfer complete + dmac_evosel_1: Event strobe when block transfer complete + dmac_evosel_10: Event generation disabled + dmac_evosel_11: Event generation disabled + dmac_evosel_12: Event generation disabled + dmac_evosel_13: Event generation disabled + dmac_evosel_14: Event generation disabled + dmac_evosel_15: Event generation disabled + dmac_evosel_16: Event generation disabled + dmac_evosel_17: Event generation disabled + dmac_evosel_18: Event generation disabled + dmac_evosel_19: Event generation disabled + dmac_evosel_2: Event strobe when block transfer complete + dmac_evosel_20: Event generation disabled + dmac_evosel_21: Event generation disabled + dmac_evosel_22: Event generation disabled + dmac_evosel_23: Event generation disabled + dmac_evosel_24: Event generation disabled + dmac_evosel_25: Event generation disabled + dmac_evosel_26: Event generation disabled + dmac_evosel_27: Event generation disabled + dmac_evosel_28: Event generation disabled + dmac_evosel_29: Event generation disabled + dmac_evosel_3: Event generation disabled + dmac_evosel_30: Event generation disabled + dmac_evosel_31: Event generation disabled + dmac_evosel_4: Event generation disabled + dmac_evosel_5: Event generation disabled + dmac_evosel_6: Event generation disabled + dmac_evosel_7: Event generation disabled + dmac_evosel_8: Event generation disabled + dmac_evosel_9: Event generation disabled + dmac_lvl_0: Channel priority 0 + dmac_lvl_1: Channel priority 0 + dmac_lvl_10: Channel priority 0 + dmac_lvl_11: Channel priority 0 + dmac_lvl_12: Channel priority 0 + dmac_lvl_13: Channel priority 0 + dmac_lvl_14: Channel priority 0 + dmac_lvl_15: Channel priority 0 + dmac_lvl_16: Channel priority 0 + dmac_lvl_17: Channel priority 0 + dmac_lvl_18: Channel priority 0 + dmac_lvl_19: Channel priority 0 + dmac_lvl_2: Channel priority 0 + dmac_lvl_20: Channel priority 0 + dmac_lvl_21: Channel priority 0 + dmac_lvl_22: Channel priority 0 + dmac_lvl_23: Channel priority 0 + dmac_lvl_24: Channel priority 0 + dmac_lvl_25: Channel priority 0 + dmac_lvl_26: Channel priority 0 + dmac_lvl_27: Channel priority 0 + dmac_lvl_28: Channel priority 0 + dmac_lvl_29: Channel priority 0 + dmac_lvl_3: Channel priority 0 + dmac_lvl_30: Channel priority 0 + dmac_lvl_31: Channel priority 0 + dmac_lvl_4: Channel priority 0 + dmac_lvl_5: Channel priority 0 + dmac_lvl_6: Channel priority 0 + dmac_lvl_7: Channel priority 0 + dmac_lvl_8: Channel priority 0 + dmac_lvl_9: Channel priority 0 + dmac_lvlen0: true + dmac_lvlen1: false + dmac_lvlen2: false + dmac_lvlen3: false + dmac_lvlpri0: 0 + dmac_lvlpri1: 0 + dmac_lvlpri2: 0 + dmac_lvlpri3: 0 + dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 + dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 + dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 + dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 + dmac_runstdby_0: true + dmac_runstdby_1: true + dmac_runstdby_10: false + dmac_runstdby_11: false + dmac_runstdby_12: false + dmac_runstdby_13: false + dmac_runstdby_14: false + dmac_runstdby_15: false + dmac_runstdby_16: false + dmac_runstdby_17: false + dmac_runstdby_18: false + dmac_runstdby_19: false + dmac_runstdby_2: false + dmac_runstdby_20: false + dmac_runstdby_21: false + dmac_runstdby_22: false + dmac_runstdby_23: false + dmac_runstdby_24: false + dmac_runstdby_25: false + dmac_runstdby_26: false + dmac_runstdby_27: false + dmac_runstdby_28: false + dmac_runstdby_29: false + dmac_runstdby_3: true + dmac_runstdby_30: false + dmac_runstdby_31: false + dmac_runstdby_4: true + dmac_runstdby_5: true + dmac_runstdby_6: true + dmac_runstdby_7: true + dmac_runstdby_8: false + dmac_runstdby_9: false + dmac_srcinc_0: false + dmac_srcinc_1: false + dmac_srcinc_10: false + dmac_srcinc_11: false + dmac_srcinc_12: false + dmac_srcinc_13: false + dmac_srcinc_14: false + dmac_srcinc_15: false + dmac_srcinc_16: false + dmac_srcinc_17: false + dmac_srcinc_18: false + dmac_srcinc_19: false + dmac_srcinc_2: false + dmac_srcinc_20: false + dmac_srcinc_21: false + dmac_srcinc_22: false + dmac_srcinc_23: false + dmac_srcinc_24: false + dmac_srcinc_25: false + dmac_srcinc_26: false + dmac_srcinc_27: false + dmac_srcinc_28: false + dmac_srcinc_29: false + dmac_srcinc_3: false + dmac_srcinc_30: false + dmac_srcinc_31: false + dmac_srcinc_4: true + dmac_srcinc_5: true + dmac_srcinc_6: true + dmac_srcinc_7: true + dmac_srcinc_8: false + dmac_srcinc_9: false + dmac_stepsel_0: Step size settings apply to the destination address + dmac_stepsel_1: Step size settings apply to the destination address + dmac_stepsel_10: Step size settings apply to the destination address + dmac_stepsel_11: Step size settings apply to the destination address + dmac_stepsel_12: Step size settings apply to the destination address + dmac_stepsel_13: Step size settings apply to the destination address + dmac_stepsel_14: Step size settings apply to the destination address + dmac_stepsel_15: Step size settings apply to the destination address + dmac_stepsel_16: Step size settings apply to the destination address + dmac_stepsel_17: Step size settings apply to the destination address + dmac_stepsel_18: Step size settings apply to the destination address + dmac_stepsel_19: Step size settings apply to the destination address + dmac_stepsel_2: Step size settings apply to the destination address + dmac_stepsel_20: Step size settings apply to the destination address + dmac_stepsel_21: Step size settings apply to the destination address + dmac_stepsel_22: Step size settings apply to the destination address + dmac_stepsel_23: Step size settings apply to the destination address + dmac_stepsel_24: Step size settings apply to the destination address + dmac_stepsel_25: Step size settings apply to the destination address + dmac_stepsel_26: Step size settings apply to the destination address + dmac_stepsel_27: Step size settings apply to the destination address + dmac_stepsel_28: Step size settings apply to the destination address + dmac_stepsel_29: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_30: Step size settings apply to the destination address + dmac_stepsel_31: Step size settings apply to the destination address + dmac_stepsel_4: Step size settings apply to the source address + dmac_stepsel_5: Step size settings apply to the source address + dmac_stepsel_6: Step size settings apply to the source address + dmac_stepsel_7: Step size settings apply to the source address + dmac_stepsel_8: Step size settings apply to the destination address + dmac_stepsel_9: Step size settings apply to the destination address + dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_trifsrc_0: SERCOM1 RX Trigger + dmac_trifsrc_1: SERCOM5 RX Trigger + dmac_trifsrc_10: Only software/event triggers + dmac_trifsrc_11: Only software/event triggers + dmac_trifsrc_12: Only software/event triggers + dmac_trifsrc_13: Only software/event triggers + dmac_trifsrc_14: Only software/event triggers + dmac_trifsrc_15: Only software/event triggers + dmac_trifsrc_16: Only software/event triggers + dmac_trifsrc_17: Only software/event triggers + dmac_trifsrc_18: Only software/event triggers + dmac_trifsrc_19: Only software/event triggers + dmac_trifsrc_2: SERCOM2 RX Trigger + dmac_trifsrc_20: Only software/event triggers + dmac_trifsrc_21: Only software/event triggers + dmac_trifsrc_22: Only software/event triggers + dmac_trifsrc_23: Only software/event triggers + dmac_trifsrc_24: Only software/event triggers + dmac_trifsrc_25: Only software/event triggers + dmac_trifsrc_26: Only software/event triggers + dmac_trifsrc_27: Only software/event triggers + dmac_trifsrc_28: Only software/event triggers + dmac_trifsrc_29: Only software/event triggers + dmac_trifsrc_3: ADC1 Result Ready Trigger + dmac_trifsrc_30: Only software/event triggers + dmac_trifsrc_31: Only software/event triggers + dmac_trifsrc_4: ADC1 Sequencing Trigger + dmac_trifsrc_5: SERCOM2 TX Trigger + dmac_trifsrc_6: SERCOM5 TX Trigger + dmac_trifsrc_7: SERCOM1 TX Trigger + dmac_trifsrc_8: Only software/event triggers + dmac_trifsrc_9: Only software/event triggers + dmac_trigact_0: One trigger required for each beat transfer + dmac_trigact_1: One trigger required for each beat transfer + dmac_trigact_10: One trigger required for each block transfer + dmac_trigact_11: One trigger required for each block transfer + dmac_trigact_12: One trigger required for each block transfer + dmac_trigact_13: One trigger required for each block transfer + dmac_trigact_14: One trigger required for each block transfer + dmac_trigact_15: One trigger required for each block transfer + dmac_trigact_16: One trigger required for each block transfer + dmac_trigact_17: One trigger required for each block transfer + dmac_trigact_18: One trigger required for each block transfer + dmac_trigact_19: One trigger required for each block transfer + dmac_trigact_2: One trigger required for each beat transfer + dmac_trigact_20: One trigger required for each block transfer + dmac_trigact_21: One trigger required for each block transfer + dmac_trigact_22: One trigger required for each block transfer + dmac_trigact_23: One trigger required for each block transfer + dmac_trigact_24: One trigger required for each block transfer + dmac_trigact_25: One trigger required for each block transfer + dmac_trigact_26: One trigger required for each block transfer + dmac_trigact_27: One trigger required for each block transfer + dmac_trigact_28: One trigger required for each block transfer + dmac_trigact_29: One trigger required for each block transfer + dmac_trigact_3: One trigger required for each beat transfer + dmac_trigact_30: One trigger required for each block transfer + dmac_trigact_31: One trigger required for each block transfer + dmac_trigact_4: One trigger required for each beat transfer + dmac_trigact_5: One trigger required for each beat transfer + dmac_trigact_6: One trigger required for each beat transfer + dmac_trigact_7: One trigger required for each beat transfer + dmac_trigact_8: One trigger required for each block transfer + dmac_trigact_9: One trigger required for each block transfer + optional_signals: [] + variant: null + clocks: + domain_group: null + EXTERNAL_IRQ_0: + user_label: EXTERNAL_IRQ_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ + functionality: External_IRQ + api: HAL:Driver:Ext_IRQ + configuration: + eic_arch_asynch0: false + eic_arch_asynch1: false + eic_arch_asynch10: false + eic_arch_asynch11: false + eic_arch_asynch12: false + eic_arch_asynch13: false + eic_arch_asynch14: false + eic_arch_asynch15: false + eic_arch_asynch2: true + eic_arch_asynch3: false + eic_arch_asynch4: false + eic_arch_asynch5: false + eic_arch_asynch6: false + eic_arch_asynch7: false + eic_arch_asynch8: false + eic_arch_asynch9: false + eic_arch_cksel: Clocked by GCLK + eic_arch_debounce_enable0: false + eic_arch_debounce_enable1: false + eic_arch_debounce_enable10: false + eic_arch_debounce_enable11: false + eic_arch_debounce_enable12: false + eic_arch_debounce_enable13: false + eic_arch_debounce_enable14: false + eic_arch_debounce_enable15: false + eic_arch_debounce_enable2: false + eic_arch_debounce_enable3: false + eic_arch_debounce_enable4: false + eic_arch_debounce_enable5: false + eic_arch_debounce_enable6: false + eic_arch_debounce_enable7: false + eic_arch_debounce_enable8: false + eic_arch_debounce_enable9: false + eic_arch_enable_irq_setting0: false + eic_arch_enable_irq_setting1: false + eic_arch_enable_irq_setting10: false + eic_arch_enable_irq_setting11: false + eic_arch_enable_irq_setting12: false + eic_arch_enable_irq_setting13: false + eic_arch_enable_irq_setting14: true + eic_arch_enable_irq_setting15: true + eic_arch_enable_irq_setting2: true + eic_arch_enable_irq_setting3: false + eic_arch_enable_irq_setting4: false + eic_arch_enable_irq_setting5: false + eic_arch_enable_irq_setting6: false + eic_arch_enable_irq_setting7: false + eic_arch_enable_irq_setting8: false + eic_arch_enable_irq_setting9: false + eic_arch_extinteo0: false + eic_arch_extinteo1: false + eic_arch_extinteo10: false + eic_arch_extinteo11: false + eic_arch_extinteo12: false + eic_arch_extinteo13: false + eic_arch_extinteo14: false + eic_arch_extinteo15: false + eic_arch_extinteo2: true + eic_arch_extinteo3: false + eic_arch_extinteo4: false + eic_arch_extinteo5: false + eic_arch_extinteo6: false + eic_arch_extinteo7: false + eic_arch_extinteo8: false + eic_arch_extinteo9: false + eic_arch_filten0: false + eic_arch_filten1: false + eic_arch_filten10: false + eic_arch_filten11: false + eic_arch_filten12: false + eic_arch_filten13: false + eic_arch_filten14: true + eic_arch_filten15: true + eic_arch_filten2: false + eic_arch_filten3: false + eic_arch_filten4: false + eic_arch_filten5: false + eic_arch_filten6: false + eic_arch_filten7: false + eic_arch_filten8: false + eic_arch_filten9: false + eic_arch_nmi_ctrl: false + eic_arch_nmiasynch: false + eic_arch_nmifilten: false + eic_arch_nmisense: No detection + eic_arch_prescaler0: Divided by 2 + eic_arch_prescaler1: Divided by 2 + eic_arch_sense0: No detection + eic_arch_sense1: No detection + eic_arch_sense10: No detection + eic_arch_sense11: No detection + eic_arch_sense12: No detection + eic_arch_sense13: No detection + eic_arch_sense14: Falling-edge detection + eic_arch_sense15: Falling-edge detection + eic_arch_sense2: Falling-edge detection + eic_arch_sense3: No detection + eic_arch_sense4: No detection + eic_arch_sense5: No detection + eic_arch_sense6: No detection + eic_arch_sense7: No detection + eic_arch_sense8: No detection + eic_arch_sense9: No detection + eic_arch_states0: '3' + eic_arch_states1: '3' + eic_arch_tickon: The sampling rate is EIC clock + optional_signals: + - identifier: EXTERNAL_IRQ_0:EXTINT/2 + pad: PA02 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::EIC.EXTINT.2 + name: EIC/EXTINT/2 + label: EXTINT/2 + - identifier: EXTERNAL_IRQ_0:EXTINT/7 + pad: PA07 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::EIC.EXTINT.7 + name: EIC/EXTINT/7 + label: EXTINT/7 + - identifier: EXTERNAL_IRQ_0:EXTINT/14 + pad: PB30 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::EIC.EXTINT.14 + name: EIC/EXTINT/14 + label: EXTINT/14 + - identifier: EXTERNAL_IRQ_0:EXTINT/15 + pad: PB31 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::EIC.EXTINT.15 + name: EIC/EXTINT/15 + label: EXTINT/15 + variant: null + clocks: + domain_group: + nodes: + - name: EIC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + eic_gclk_selection: Generic clock generator 0 + EVENT_SYSTEM_0: + user_label: EVENT_SYSTEM_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::EVSYS::driver_config_definition::Event.System::HAL:Driver:Event.system + functionality: Event_System + api: HAL:Driver:Event_system + configuration: + evsys_channel_0: No channel output selected + evsys_channel_1: Channel 1 + evsys_channel_10: Channel 5 + evsys_channel_11: Channel 2 + evsys_channel_12: Channel 3 + evsys_channel_17: No channel output selected + evsys_channel_18: No channel output selected + evsys_channel_19: No channel output selected + evsys_channel_2: Channel 6 + evsys_channel_20: No channel output selected + evsys_channel_21: No channel output selected + evsys_channel_22: No channel output selected + evsys_channel_23: No channel output selected + evsys_channel_24: No channel output selected + evsys_channel_25: No channel output selected + evsys_channel_26: No channel output selected + evsys_channel_27: No channel output selected + evsys_channel_28: No channel output selected + evsys_channel_29: No channel output selected + evsys_channel_3: Channel 5 + evsys_channel_30: No channel output selected + evsys_channel_31: No channel output selected + evsys_channel_32: No channel output selected + evsys_channel_33: No channel output selected + evsys_channel_34: No channel output selected + evsys_channel_35: No channel output selected + evsys_channel_36: No channel output selected + evsys_channel_37: No channel output selected + evsys_channel_38: No channel output selected + evsys_channel_39: No channel output selected + evsys_channel_4: Channel 8 + evsys_channel_40: No channel output selected + evsys_channel_41: No channel output selected + evsys_channel_42: No channel output selected + evsys_channel_43: No channel output selected + evsys_channel_44: No channel output selected + evsys_channel_45: No channel output selected + evsys_channel_46: Channel 11 + evsys_channel_47: No channel output selected + evsys_channel_48: Channel 12 + evsys_channel_49: No channel output selected + evsys_channel_5: No channel output selected + evsys_channel_50: No channel output selected + evsys_channel_51: No channel output selected + evsys_channel_52: No channel output selected + evsys_channel_53: No channel output selected + evsys_channel_54: No channel output selected + evsys_channel_55: No channel output selected + evsys_channel_56: No channel output selected + evsys_channel_57: No channel output selected + evsys_channel_58: No channel output selected + evsys_channel_59: No channel output selected + evsys_channel_6: No channel output selected + evsys_channel_60: No channel output selected + evsys_channel_61: No channel output selected + evsys_channel_62: No channel output selected + evsys_channel_63: No channel output selected + evsys_channel_64: No channel output selected + evsys_channel_65: No channel output selected + evsys_channel_66: No channel output selected + evsys_channel_7: No channel output selected + evsys_channel_8: No channel output selected + evsys_channel_9: Channel 0 + evsys_channel_setting_0: true + evsys_channel_setting_1: true + evsys_channel_setting_10: false + evsys_channel_setting_11: true + evsys_channel_setting_12: true + evsys_channel_setting_13: false + evsys_channel_setting_14: false + evsys_channel_setting_15: false + evsys_channel_setting_16: false + evsys_channel_setting_17: false + evsys_channel_setting_18: false + evsys_channel_setting_19: false + evsys_channel_setting_2: true + evsys_channel_setting_20: false + evsys_channel_setting_21: false + evsys_channel_setting_22: false + evsys_channel_setting_23: false + evsys_channel_setting_24: false + evsys_channel_setting_25: false + evsys_channel_setting_26: false + evsys_channel_setting_27: false + evsys_channel_setting_28: false + evsys_channel_setting_29: false + evsys_channel_setting_3: true + evsys_channel_setting_30: false + evsys_channel_setting_31: false + evsys_channel_setting_4: true + evsys_channel_setting_5: true + evsys_channel_setting_6: true + evsys_channel_setting_7: true + evsys_channel_setting_8: true + evsys_channel_setting_9: false + evsys_edgsel_0: No event output when using the resynchronized or synchronous + path + evsys_edgsel_1: Event is detected on the rising edge of the signal from event + generator + evsys_edgsel_10: No event output when using the resynchronized or synchronous + path + evsys_edgsel_11: Event is detected on the rising edge of the signal from event + generator + evsys_edgsel_12: Event is detected on the rising edge of the signal from event + generator + evsys_edgsel_13: No event output when using the resynchronized or synchronous + path + evsys_edgsel_14: No event output when using the resynchronized or synchronous + path + evsys_edgsel_15: No event output when using the resynchronized or synchronous + path + evsys_edgsel_16: No event output when using the resynchronized or synchronous + path + evsys_edgsel_17: No event output when using the resynchronized or synchronous + path + evsys_edgsel_18: No event output when using the resynchronized or synchronous + path + evsys_edgsel_19: No event output when using the resynchronized or synchronous + path + evsys_edgsel_2: Event is detected on the rising edge of the signal from event + generator + evsys_edgsel_20: No event output when using the resynchronized or synchronous + path + evsys_edgsel_21: No event output when using the resynchronized or synchronous + path + evsys_edgsel_22: No event output when using the resynchronized or synchronous + path + evsys_edgsel_23: No event output when using the resynchronized or synchronous + path + evsys_edgsel_24: No event output when using the resynchronized or synchronous + path + evsys_edgsel_25: No event output when using the resynchronized or synchronous + path + evsys_edgsel_26: No event output when using the resynchronized or synchronous + path + evsys_edgsel_27: No event output when using the resynchronized or synchronous + path + evsys_edgsel_28: No event output when using the resynchronized or synchronous + path + evsys_edgsel_29: No event output when using the resynchronized or synchronous + path + evsys_edgsel_3: No event output when using the resynchronized or synchronous + path + evsys_edgsel_30: No event output when using the resynchronized or synchronous + path + evsys_edgsel_31: No event output when using the resynchronized or synchronous + path + evsys_edgsel_4: No event output when using the resynchronized or synchronous + path + evsys_edgsel_5: Event is detected on the rising edge of the signal from event + generator + evsys_edgsel_6: Event is detected on the rising edge of the signal from event + generator + evsys_edgsel_7: Event is detected on the rising edge of the signal from event + generator + evsys_edgsel_8: Event is detected on the rising edge of the signal from event + generator + evsys_edgsel_9: No event output when using the resynchronized or synchronous + path + evsys_evd_0: false + evsys_evd_1: false + evsys_evd_10: false + evsys_evd_11: false + evsys_evd_12: false + evsys_evd_13: false + evsys_evd_14: false + evsys_evd_15: false + evsys_evd_16: false + evsys_evd_17: false + evsys_evd_18: false + evsys_evd_19: false + evsys_evd_2: false + evsys_evd_20: false + evsys_evd_21: false + evsys_evd_22: false + evsys_evd_23: false + evsys_evd_24: false + evsys_evd_25: false + evsys_evd_26: false + evsys_evd_27: false + evsys_evd_28: false + evsys_evd_29: false + evsys_evd_3: false + evsys_evd_30: false + evsys_evd_31: false + evsys_evd_4: false + evsys_evd_5: false + evsys_evd_6: true + evsys_evd_7: true + evsys_evd_8: false + evsys_evd_9: false + evsys_evgen_0: TCC0 overflow + evsys_evgen_1: TC0 match/capture 0 + evsys_evgen_10: No event generator + evsys_evgen_11: CCL LUT output 0 + evsys_evgen_12: CCL LUT output 2 + evsys_evgen_13: No event generator + evsys_evgen_14: No event generator + evsys_evgen_15: No event generator + evsys_evgen_16: No event generator + evsys_evgen_17: No event generator + evsys_evgen_18: No event generator + evsys_evgen_19: No event generator + evsys_evgen_2: TC0 match/capture 1 + evsys_evgen_20: No event generator + evsys_evgen_21: No event generator + evsys_evgen_22: No event generator + evsys_evgen_23: No event generator + evsys_evgen_24: No event generator + evsys_evgen_25: No event generator + evsys_evgen_26: No event generator + evsys_evgen_27: No event generator + evsys_evgen_28: No event generator + evsys_evgen_29: No event generator + evsys_evgen_3: TC1 match/capture 1 + evsys_evgen_30: No event generator + evsys_evgen_31: No event generator + evsys_evgen_4: No event generator + evsys_evgen_5: EIC external interrupt 2 + evsys_evgen_6: DMAC channel 0 + evsys_evgen_7: DMAC channel 1 + evsys_evgen_8: DMAC channel 2 + evsys_evgen_9: No event generator + evsys_ondemand_0: false + evsys_ondemand_1: false + evsys_ondemand_10: false + evsys_ondemand_11: false + evsys_ondemand_12: false + evsys_ondemand_13: false + evsys_ondemand_14: false + evsys_ondemand_15: false + evsys_ondemand_16: false + evsys_ondemand_17: false + evsys_ondemand_18: false + evsys_ondemand_19: false + evsys_ondemand_2: false + evsys_ondemand_20: false + evsys_ondemand_21: false + evsys_ondemand_22: false + evsys_ondemand_23: false + evsys_ondemand_24: false + evsys_ondemand_25: false + evsys_ondemand_26: false + evsys_ondemand_27: false + evsys_ondemand_28: false + evsys_ondemand_29: false + evsys_ondemand_3: false + evsys_ondemand_30: false + evsys_ondemand_31: false + evsys_ondemand_4: false + evsys_ondemand_5: false + evsys_ondemand_6: false + evsys_ondemand_7: false + evsys_ondemand_8: false + evsys_ondemand_9: false + evsys_ovr_0: false + evsys_ovr_1: false + evsys_ovr_10: false + evsys_ovr_11: false + evsys_ovr_12: false + evsys_ovr_13: false + evsys_ovr_14: false + evsys_ovr_15: false + evsys_ovr_16: false + evsys_ovr_17: false + evsys_ovr_18: false + evsys_ovr_19: false + evsys_ovr_2: false + evsys_ovr_20: false + evsys_ovr_21: false + evsys_ovr_22: false + evsys_ovr_23: false + evsys_ovr_24: false + evsys_ovr_25: false + evsys_ovr_26: false + evsys_ovr_27: false + evsys_ovr_28: false + evsys_ovr_29: false + evsys_ovr_3: false + evsys_ovr_30: false + evsys_ovr_31: false + evsys_ovr_4: false + evsys_ovr_5: false + evsys_ovr_6: false + evsys_ovr_7: false + evsys_ovr_8: false + evsys_ovr_9: false + evsys_path_0: Asynchronous path + evsys_path_1: Asynchronous path + evsys_path_10: Synchronous path + evsys_path_11: Asynchronous path + evsys_path_12: Asynchronous path + evsys_path_13: Synchronous path + evsys_path_14: Synchronous path + evsys_path_15: Synchronous path + evsys_path_16: Synchronous path + evsys_path_17: Synchronous path + evsys_path_18: Synchronous path + evsys_path_19: Synchronous path + evsys_path_2: Asynchronous path + evsys_path_20: Synchronous path + evsys_path_21: Synchronous path + evsys_path_22: Synchronous path + evsys_path_23: Synchronous path + evsys_path_24: Synchronous path + evsys_path_25: Synchronous path + evsys_path_26: Synchronous path + evsys_path_27: Synchronous path + evsys_path_28: Synchronous path + evsys_path_29: Synchronous path + evsys_path_3: Synchronous path + evsys_path_30: Synchronous path + evsys_path_31: Synchronous path + evsys_path_4: Synchronous path + evsys_path_5: Asynchronous path + evsys_path_6: Synchronous path + evsys_path_7: Synchronous path + evsys_path_8: Synchronous path + evsys_path_9: Synchronous path + evsys_runstdby_0: false + evsys_runstdby_1: false + evsys_runstdby_10: false + evsys_runstdby_11: false + evsys_runstdby_12: false + evsys_runstdby_13: false + evsys_runstdby_14: false + evsys_runstdby_15: false + evsys_runstdby_16: false + evsys_runstdby_17: false + evsys_runstdby_18: false + evsys_runstdby_19: false + evsys_runstdby_2: false + evsys_runstdby_20: false + evsys_runstdby_21: false + evsys_runstdby_22: false + evsys_runstdby_23: false + evsys_runstdby_24: false + evsys_runstdby_25: false + evsys_runstdby_26: false + evsys_runstdby_27: false + evsys_runstdby_28: false + evsys_runstdby_29: false + evsys_runstdby_3: false + evsys_runstdby_30: false + evsys_runstdby_31: false + evsys_runstdby_4: false + evsys_runstdby_5: false + evsys_runstdby_6: false + evsys_runstdby_7: false + evsys_runstdby_8: false + evsys_runstdby_9: false + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: Channel 0 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 1 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 2 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 3 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 4 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 5 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 6 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 7 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 8 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 9 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 10 + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Channel 11 + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + evsys_clk_selection_0: Generic clock generator 0 + evsys_clk_selection_1: Generic clock generator 0 + evsys_clk_selection_10: Generic clock generator 0 + evsys_clk_selection_11: Generic clock generator 0 + evsys_clk_selection_2: Generic clock generator 0 + evsys_clk_selection_3: Generic clock generator 0 + evsys_clk_selection_4: Generic clock generator 0 + evsys_clk_selection_5: Generic clock generator 0 + evsys_clk_selection_6: Generic clock generator 0 + evsys_clk_selection_7: Generic clock generator 0 + evsys_clk_selection_8: Generic clock generator 0 + evsys_clk_selection_9: Generic clock generator 0 + GCLK: + user_label: GCLK + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + functionality: System + api: HAL:HPL:GCLK + configuration: + $input: 12000000 + $input_id: External Crystal Oscillator 8-48MHz (XOSC1) + RESERVED_InputFreq: 12000000 + RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1) + _$freq_output_Generic clock generator 0: 100000000 + _$freq_output_Generic clock generator 1: 2000000 + _$freq_output_Generic clock generator 10: 12000000 + _$freq_output_Generic clock generator 11: 12000000 + _$freq_output_Generic clock generator 2: 32768 + _$freq_output_Generic clock generator 3: 32768 + _$freq_output_Generic clock generator 4: 12000000 + _$freq_output_Generic clock generator 5: 12000000 + _$freq_output_Generic clock generator 6: 12000000 + _$freq_output_Generic clock generator 7: 12000000 + _$freq_output_Generic clock generator 8: 12000000 + _$freq_output_Generic clock generator 9: 12000000 + enable_gclk_gen_0: true + enable_gclk_gen_0__externalclock: 1000000 + enable_gclk_gen_1: true + enable_gclk_gen_10: false + enable_gclk_gen_10__externalclock: 1000000 + enable_gclk_gen_11: false + enable_gclk_gen_11__externalclock: 1000000 + enable_gclk_gen_1__externalclock: 1000000 + enable_gclk_gen_2: true + enable_gclk_gen_2__externalclock: 1000000 + enable_gclk_gen_3: false + enable_gclk_gen_3__externalclock: 1000000 + enable_gclk_gen_4: false + enable_gclk_gen_4__externalclock: 1000000 + enable_gclk_gen_5: false + enable_gclk_gen_5__externalclock: 1000000 + enable_gclk_gen_6: false + enable_gclk_gen_6__externalclock: 1000000 + enable_gclk_gen_7: false + enable_gclk_gen_7__externalclock: 1000000 + enable_gclk_gen_8: false + enable_gclk_gen_8__externalclock: 1000000 + enable_gclk_gen_9: false + enable_gclk_gen_9__externalclock: 1000000 + gclk_arch_gen_0_enable: true + gclk_arch_gen_0_idc: false + gclk_arch_gen_0_oe: true + gclk_arch_gen_0_oov: false + gclk_arch_gen_0_runstdby: false + gclk_arch_gen_10_enable: false + gclk_arch_gen_10_idc: false + gclk_arch_gen_10_oe: false + gclk_arch_gen_10_oov: false + gclk_arch_gen_10_runstdby: false + gclk_arch_gen_11_enable: false + gclk_arch_gen_11_idc: false + gclk_arch_gen_11_oe: false + gclk_arch_gen_11_oov: false + gclk_arch_gen_11_runstdby: false + gclk_arch_gen_1_enable: true + gclk_arch_gen_1_idc: false + gclk_arch_gen_1_oe: true + gclk_arch_gen_1_oov: false + gclk_arch_gen_1_runstdby: false + gclk_arch_gen_2_enable: true + gclk_arch_gen_2_idc: false + gclk_arch_gen_2_oe: true + gclk_arch_gen_2_oov: false + gclk_arch_gen_2_runstdby: false + gclk_arch_gen_3_enable: false + gclk_arch_gen_3_idc: false + gclk_arch_gen_3_oe: false + gclk_arch_gen_3_oov: false + gclk_arch_gen_3_runstdby: false + gclk_arch_gen_4_enable: false + gclk_arch_gen_4_idc: false + gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oov: false + gclk_arch_gen_4_runstdby: false + gclk_arch_gen_5_enable: false + gclk_arch_gen_5_idc: false + gclk_arch_gen_5_oe: false + gclk_arch_gen_5_oov: false + gclk_arch_gen_5_runstdby: false + gclk_arch_gen_6_enable: false + gclk_arch_gen_6_idc: false + gclk_arch_gen_6_oe: false + gclk_arch_gen_6_oov: false + gclk_arch_gen_6_runstdby: false + gclk_arch_gen_7_enable: false + gclk_arch_gen_7_idc: false + gclk_arch_gen_7_oe: false + gclk_arch_gen_7_oov: false + gclk_arch_gen_7_runstdby: false + gclk_arch_gen_8_enable: false + gclk_arch_gen_8_idc: false + gclk_arch_gen_8_oe: false + gclk_arch_gen_8_oov: false + gclk_arch_gen_8_runstdby: false + gclk_arch_gen_9_enable: false + gclk_arch_gen_9_idc: false + gclk_arch_gen_9_oe: false + gclk_arch_gen_9_oov: false + gclk_arch_gen_9_runstdby: false + gclk_gen_0_div: 1 + gclk_gen_0_div_sel: false + gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL1) + gclk_gen_10_div: 1 + gclk_gen_10_div_sel: false + gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_11_div: 1 + gclk_gen_11_div_sel: false + gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_1_div: 24 + gclk_gen_1_div_sel: false + gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) + gclk_gen_2_div: 1 + gclk_gen_2_div_sel: false + gclk_gen_2_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + gclk_gen_3_div: 1 + gclk_gen_3_div_sel: false + gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) + gclk_gen_4_div: 1 + gclk_gen_4_div_sel: false + gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_5_div: 1 + gclk_gen_5_div_sel: false + gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_6_div: 1 + gclk_gen_6_div_sel: false + gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_7_div: 1 + gclk_gen_7_div_sel: false + gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_8_div: 1 + gclk_gen_8_div_sel: false + gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_9_div: 1 + gclk_gen_9_div_sel: false + gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + optional_signals: [] + variant: null + clocks: + domain_group: null + MCLK: + user_label: MCLK + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + functionality: System + api: HAL:HPL:MCLK + configuration: + $input: 100000000 + $input_id: Generic clock generator 0 + RESERVED_InputFreq: 100000000 + RESERVED_InputFreq_id: Generic clock generator 0 + _$freq_output_CPU: 100000000 + cpu_clock_source: Generic clock generator 0 + cpu_div: '1' + enable_cpu_clock: true + mclk_arch_bupdiv: Divide by 8 + mclk_arch_hsdiv: Divide by 1 + mclk_arch_lpdiv: Divide by 4 + nvm_wait_states: '0' + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: CPU + input: CPU + external: false + external_frequency: 0 + configuration: {} + OSC32KCTRL: + user_label: OSC32KCTRL + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + functionality: System + api: HAL:HPL:OSC32KCTRL + configuration: + $input: 32768 + $input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + RESERVED_InputFreq: 32768 + RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + _$freq_output_RTC source: 32768 + enable_osculp32k: true + enable_rtc_source: false + enable_xosc32k: false + osculp32k_calib: 0 + osculp32k_calib_enable: false + rtc_1khz_selection: false + rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + xosc32k_arch_cfden: false + xosc32k_arch_cfdeo: false + xosc32k_arch_cgm: Standard mode + xosc32k_arch_en1k: false + xosc32k_arch_en32k: false + xosc32k_arch_enable: false + xosc32k_arch_ondemand: true + xosc32k_arch_runstdby: false + xosc32k_arch_startup: 62592us + xosc32k_arch_swben: false + xosc32k_arch_xtalen: true + optional_signals: [] + variant: null + clocks: + domain_group: null + OSCCTRL: + user_label: OSCCTRL + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + functionality: System + api: HAL:HPL:OSCCTRL + configuration: + $input: 2000000 + $input_id: Generic clock generator 1 + RESERVED_InputFreq: 2000000 + RESERVED_InputFreq_id: Generic clock generator 1 + _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000 + _$freq_output_Digital Phase Locked Loop (DPLL0): 47985664 + _$freq_output_Digital Phase Locked Loop (DPLL1): 100000000 + _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): '12000000' + _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): '12000000' + dfll_arch_bplckc: false + dfll_arch_calibration: false + dfll_arch_ccdis: false + dfll_arch_coarse: 31 + dfll_arch_cstep: 1 + dfll_arch_enable: true + dfll_arch_fine: 128 + dfll_arch_fstep: 1 + dfll_arch_llaw: false + dfll_arch_ondemand: false + dfll_arch_qldis: false + dfll_arch_runstdby: false + dfll_arch_stable: false + dfll_arch_usbcrm: false + dfll_arch_waitlock: true + dfll_mode: Open Loop Mode + dfll_mul: 0 + dfll_ref_clock: Generic clock generator 2 + enable_dfll: true + enable_fdpll0: false + enable_fdpll1: true + enable_xosc0: false + enable_xosc1: true + fdpll0_arch_dcoen: false + fdpll0_arch_enable: false + fdpll0_arch_filter: 0 + fdpll0_arch_lbypass: false + fdpll0_arch_ltime: No time-out, automatic lock + fdpll0_arch_ondemand: false + fdpll0_arch_refclk: XOSC32K clock reference + fdpll0_arch_runstdby: false + fdpll0_arch_wuf: false + fdpll0_clock_dcofilter: 0 + fdpll0_clock_div: 0 + fdpll0_ldr: 1463 + fdpll0_ldrfrac: 13 + fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + fdpll1_arch_dcoen: false + fdpll1_arch_enable: true + fdpll1_arch_filter: 0 + fdpll1_arch_lbypass: false + fdpll1_arch_ltime: No time-out, automatic lock + fdpll1_arch_ondemand: false + fdpll1_arch_refclk: GCLK clock reference + fdpll1_arch_runstdby: false + fdpll1_arch_wuf: false + fdpll1_clock_dcofilter: 0 + fdpll1_clock_div: 0 + fdpll1_ldr: 49 + fdpll1_ldrfrac: 0 + fdpll1_ref_clock: Generic clock generator 1 + xosc0_arch_cfden: false + xosc0_arch_enable: false + xosc0_arch_enalc: false + xosc0_arch_lowbufgain: false + xosc0_arch_ondemand: false + xosc0_arch_runstdby: false + xosc0_arch_startup: 31us + xosc0_arch_swben: false + xosc0_arch_xtalen: false + xosc0_frequency: 12000000 + xosc1_arch_cfden: false + xosc1_arch_enable: true + xosc1_arch_enalc: false + xosc1_arch_lowbufgain: false + xosc1_arch_ondemand: false + xosc1_arch_runstdby: false + xosc1_arch_startup: 31us + xosc1_arch_swben: false + xosc1_arch_xtalen: true + xosc1_frequency: 12000000 + optional_signals: [] + variant: null + clocks: + domain_group: null + PORT: + user_label: PORT + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::PORT::driver_config_definition::PORT::HAL:HPL:PORT + functionality: System + api: HAL:HPL:PORT + configuration: + enable_port_input_event_0: true + enable_port_input_event_1: true + enable_port_input_event_2: true + enable_port_input_event_3: true + porta_event_action_0: Output register of pin will be set to level of event + porta_event_action_1: Output register of pin will be set to level of event + porta_event_action_2: Clear output register of pin on event + porta_event_action_3: Set output register of pin on event + porta_event_pin_identifier_0: 0 + porta_event_pin_identifier_1: 0 + porta_event_pin_identifier_2: 14 + porta_event_pin_identifier_3: 14 + porta_input_event_enable_0: false + porta_input_event_enable_1: false + porta_input_event_enable_2: true + porta_input_event_enable_3: true + portb_event_action_0: Clear output register of pin on event + portb_event_action_1: Set output register of pin on event + portb_event_action_2: Output register of pin will be set to level of event + portb_event_action_3: Output register of pin will be set to level of event + portb_event_pin_identifier_0: 22 + portb_event_pin_identifier_1: 22 + portb_event_pin_identifier_2: 0 + portb_event_pin_identifier_3: 0 + portb_input_event_enable_0: true + portb_input_event_enable_1: true + portb_input_event_enable_2: false + portb_input_event_enable_3: false + optional_signals: [] + variant: null + clocks: + domain_group: null + ECAT_QSPI: + user_label: ECAT_QSPI + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::QSPI::driver_config_definition::QSPI.Master::HAL:Driver:QSPI.DMA + functionality: Quad_SPI + api: HAL:Driver:QSPI_DMA + configuration: + qspi_advanced: false + qspi_baud_rate: 6000000 + qspi_cpha: Data is changed on the leading edge of SPCK and captured on the following + edge of SPCK. + qspi_cpol: The inactive state value of SPCK is logic level zero. + qspi_dlybs: 0 + qspi_dlycs: 0 + qspi_dma_rx_channel: 0 + qspi_dma_tx_channel: 1 + optional_signals: + - identifier: ECAT_QSPI:CS + pad: PB11 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.CS + name: QSPI/CS + label: CS + - identifier: ECAT_QSPI:DATA/0 + pad: PA08 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.DATA.0 + name: QSPI/DATA/0 + label: DATA/0 + - identifier: ECAT_QSPI:DATA/1 + pad: PA09 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.DATA.1 + name: QSPI/DATA/1 + label: DATA/1 + - identifier: ECAT_QSPI:DATA/2 + pad: PA10 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.DATA.2 + name: QSPI/DATA/2 + label: DATA/2 + - identifier: ECAT_QSPI:DATA/3 + pad: PA11 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.DATA.3 + name: QSPI/DATA/3 + label: DATA/3 + - identifier: ECAT_QSPI:SCK + pad: PB10 + mode: Enabled + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.SCK + name: QSPI/SCK + label: SCK + variant: null + clocks: + domain_group: null + RAMECC: + user_label: RAMECC + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC + functionality: System + api: HAL:HPL:RAMECC + configuration: {} + optional_signals: [] + variant: null + clocks: + domain_group: null + I2C_0: + user_label: I2C_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::SERCOM0::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Async + functionality: I2C + api: HAL:Driver:I2C_Master_Async + configuration: + i2c_master_advanced: false + i2c_master_arch_dbgstop: Keep running + i2c_master_arch_inactout: Disabled + i2c_master_arch_lowtout: false + i2c_master_arch_mexttoen: false + i2c_master_arch_runstdby: false + i2c_master_arch_sdahold: 300-600ns hold time + i2c_master_arch_sexttoen: false + i2c_master_arch_trise: 215 + i2c_master_baud_rate: 100000 + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + SPI_1_MSIF: + user_label: SPI_1_MSIF + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::SERCOM1::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.DMA + functionality: SPI + api: HAL:Driver:SPI_Master_DMA + configuration: + spi_master_advanced: true + spi_master_arch_cpha: Sample input on leading edge + spi_master_arch_cpol: SCK is low when idle + spi_master_arch_dbgstop: Keep running + spi_master_arch_dord: MSB first + spi_master_arch_ibon: In data stream + spi_master_arch_runstdby: false + spi_master_baud_rate: 1000000 + spi_master_character_size: 8 bits + spi_master_dma_rx_channel: 0 + spi_master_dma_tx_channel: 7 + spi_master_dummybyte: 511 + spi_master_rx_channel: true + spi_master_rx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=3 + required_signals: + - name: SERCOM1/PAD/0 + pad: PA00 + label: MOSI + - name: SERCOM1/PAD/1 + pad: PA01 + label: SCK + - name: SERCOM1/PAD/3 + pad: PB23 + label: MISO + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + SPI_2: + user_label: SPI_2 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::SERCOM2::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.Sync + functionality: SPI + api: HAL:Driver:SPI_Master_Sync + configuration: + spi_master_advanced: true + spi_master_arch_cpha: Sample input on trailing edge + spi_master_arch_cpol: SCK is low when idle + spi_master_arch_dbgstop: Keep running + spi_master_arch_dord: MSB first + spi_master_arch_ibon: On buffer overflow + spi_master_arch_runstdby: false + spi_master_baud_rate: 1000000 + spi_master_character_size: 8 bits + spi_master_dummybyte: 511 + spi_master_rx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=3 + required_signals: + - name: SERCOM2/PAD/0 + pad: PA12 + label: MOSI + - name: SERCOM2/PAD/1 + pad: PA13 + label: SCK + - name: SERCOM2/PAD/3 + pad: PA15 + label: MISO + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + SPI_3: + user_label: SPI_3 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::SERCOM5::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.Sync + functionality: SPI + api: HAL:Driver:SPI_Master_Sync + configuration: + spi_master_advanced: false + spi_master_arch_cpha: Sample input on leading edge + spi_master_arch_cpol: SCK is low when idle + spi_master_arch_dbgstop: Keep running + spi_master_arch_dord: MSB first + spi_master_arch_ibon: In data stream + spi_master_arch_runstdby: false + spi_master_baud_rate: 1000000 + spi_master_character_size: 8 bits + spi_master_dummybyte: 511 + spi_master_rx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=3 + required_signals: + - name: SERCOM5/PAD/0 + pad: PB02 + label: MOSI + - name: SERCOM5/PAD/1 + pad: PB03 + label: SCK + - name: SERCOM5/PAD/3 + pad: PB01 + label: MISO + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + TIMER_0: + user_label: TIMER_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TC0::driver_config_definition::8-bit.Counter.Mode::Lite:TC:Timer + functionality: Timer + api: Lite:TC:Timer + configuration: + cc_cc0: 10 + cc_cc1: 60 + cc_control: true + count_control: false + count_count: 0 + ctrla_alock: false + ctrla_capten0: false + ctrla_capten1: false + ctrla_captmode0: DEFAULT + ctrla_captmode1: DEFAULT + ctrla_control: true + ctrla_copen0: false + ctrla_copen1: false + ctrla_enable: true + ctrla_mode: 1 + ctrla_ondemand: false + ctrla_prescaler: DIV8 + ctrla_prescsync: GCLK + ctrla_runstdby: false + ctrlbset_cmd: NONE + ctrlbset_control: false + ctrlbset_dir: false + ctrlbset_lupd: false + ctrlbset_oneshot: false + ctrlc_inven0: false + ctrlc_inven1: false + dbgctrl_control: false + dbgctrl_dbgrun: false + drvctrl_control: false + evctrl_control: true + evctrl_evact: 'OFF' + evctrl_mceo0: true + evctrl_mceo1: true + evctrl_ovfeo: true + evctrl_tcei: false + evctrl_tcinv: false + intenset_control: true + intenset_err: false + intenset_mc0: false + intenset_mc1: true + intenset_ovf: true + per_control: true + per_per: 250 + wave_control: true + wave_wavegen: NFRQ + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: TC + input: Generic clock generator 1 + external: false + external_frequency: 0 + configuration: + tc_gclk_selection: Generic clock generator 1 + TIMER_SPARE: + user_label: TIMER_SPARE + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TC1::driver_config_definition::8-bit.Counter.Mode::Lite:TC:Timer + functionality: Timer + api: Lite:TC:Timer + configuration: + cc_cc0: 10 + cc_cc1: 60 + cc_control: true + count_control: false + count_count: 0 + ctrla_alock: false + ctrla_capten0: false + ctrla_capten1: false + ctrla_captmode0: DEFAULT + ctrla_captmode1: DEFAULT + ctrla_control: true + ctrla_copen0: false + ctrla_copen1: false + ctrla_enable: false + ctrla_mode: 1 + ctrla_ondemand: false + ctrla_prescaler: DIV4 + ctrla_prescsync: GCLK + ctrla_runstdby: false + ctrlbset_cmd: NONE + ctrlbset_control: false + ctrlbset_dir: false + ctrlbset_lupd: false + ctrlbset_oneshot: false + ctrlc_inven0: false + ctrlc_inven1: false + dbgctrl_control: false + dbgctrl_dbgrun: false + drvctrl_control: false + evctrl_control: true + evctrl_evact: 'OFF' + evctrl_mceo0: true + evctrl_mceo1: true + evctrl_ovfeo: true + evctrl_tcei: false + evctrl_tcinv: false + intenset_control: true + intenset_err: false + intenset_mc0: false + intenset_mc1: true + intenset_ovf: true + per_control: true + per_per: 250 + wave_control: true + wave_wavegen: NFRQ + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: TC + input: Generic clock generator 1 + external: false + external_frequency: 0 + configuration: + tc_gclk_selection: Generic clock generator 1 + TC_SPEED_M1: + user_label: TC_SPEED_M1 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TC2::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer + functionality: Timer + api: Lite:TC:Timer + configuration: + cc_cc0: 0 + cc_cc1: 0 + cc_control: false + count_control: false + count_count: 0 + ctrla_alock: false + ctrla_capten0: true + ctrla_capten1: true + ctrla_captmode0: DEFAULT + ctrla_captmode1: DEFAULT + ctrla_control: true + ctrla_copen0: false + ctrla_copen1: false + ctrla_enable: true + ctrla_mode: 2 + ctrla_ondemand: false + ctrla_prescaler: DIV4 + ctrla_prescsync: GCLK + ctrla_runstdby: false + ctrlbset_cmd: NONE + ctrlbset_control: false + ctrlbset_dir: false + ctrlbset_lupd: false + ctrlbset_oneshot: false + ctrlc_inven0: false + ctrlc_inven1: false + dbgctrl_control: false + dbgctrl_dbgrun: false + drvctrl_control: false + evctrl_control: true + evctrl_evact: PPW + evctrl_mceo0: false + evctrl_mceo1: false + evctrl_ovfeo: true + evctrl_tcei: true + evctrl_tcinv: false + intenset_control: true + intenset_err: false + intenset_mc0: false + intenset_mc1: false + intenset_ovf: true + wave_control: true + wave_wavegen: NFRQ + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: TC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + tc_gclk_selection: Generic clock generator 0 + TC_SPEED_M2: + user_label: TC_SPEED_M2 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TC4::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer + functionality: Timer + api: Lite:TC:Timer + configuration: + cc_cc0: 0 + cc_cc1: 0 + cc_control: false + count_control: false + count_count: 0 + ctrla_alock: false + ctrla_capten0: true + ctrla_capten1: true + ctrla_captmode0: DEFAULT + ctrla_captmode1: DEFAULT + ctrla_control: true + ctrla_copen0: false + ctrla_copen1: false + ctrla_enable: true + ctrla_mode: 2 + ctrla_ondemand: false + ctrla_prescaler: DIV4 + ctrla_prescsync: GCLK + ctrla_runstdby: false + ctrlbset_cmd: NONE + ctrlbset_control: false + ctrlbset_dir: false + ctrlbset_lupd: false + ctrlbset_oneshot: false + ctrlc_inven0: false + ctrlc_inven1: false + dbgctrl_control: false + dbgctrl_dbgrun: false + drvctrl_control: false + evctrl_control: true + evctrl_evact: PPW + evctrl_mceo0: false + evctrl_mceo1: false + evctrl_ovfeo: true + evctrl_tcei: true + evctrl_tcinv: false + intenset_control: true + intenset_err: false + intenset_mc0: false + intenset_mc1: false + intenset_ovf: true + wave_control: true + wave_wavegen: NFRQ + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: TC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + tc_gclk_selection: Generic clock generator 0 + PWM_0: + user_label: PWM_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TCC0::driver_config_definition::PWM::HAL:Driver:PWM + functionality: PWM + api: HAL:Driver:PWM + configuration: + tcc_arch_alock: false + tcc_arch_cc0: 0 + tcc_arch_cc1: 0 + tcc_arch_cc2: 0 + tcc_arch_cc3: 0 + tcc_arch_cc4: 0 + tcc_arch_cc5: 0 + tcc_arch_cnteo: false + tcc_arch_cntsel: An interrupt/event is generated when a new counter cycle starts + tcc_arch_cpten0: false + tcc_arch_cpten1: false + tcc_arch_cpten2: false + tcc_arch_cpten3: false + tcc_arch_cpten4: false + tcc_arch_cpten5: false + tcc_arch_cpten6: false + tcc_arch_cpten7: false + tcc_arch_dbgrun: false + tcc_arch_evact0: Event action disabled + tcc_arch_evact1: Event action disabled + tcc_arch_lupd: false + tcc_arch_mcei0: false + tcc_arch_mcei1: false + tcc_arch_mcei2: false + tcc_arch_mcei3: false + tcc_arch_mcei4: false + tcc_arch_mcei5: false + tcc_arch_mceo0: false + tcc_arch_mceo1: false + tcc_arch_mceo2: false + tcc_arch_mceo3: false + tcc_arch_mceo4: false + tcc_arch_mceo5: false + tcc_arch_ovfeo: true + tcc_arch_prescsync: Reload or reset counter on next GCLK + tcc_arch_runstdby: false + tcc_arch_sel_ch: 2 + tcc_arch_tcei0: false + tcc_arch_tcei1: false + tcc_arch_tceinv0: false + tcc_arch_tceinv1: false + tcc_arch_trgeo: false + tcc_arch_wave_duty_val: 500 + tcc_arch_wave_per_val: 48 + tcc_arch_wavegen: Dual-slope, interrupt/event at ZERO (DSBOTTOM) + tcc_per: 10000 + tcc_prescaler: Divide by 2 + timer_event_control: true + optional_signals: + - identifier: PWM_0:WO/0 + pad: PB12 + mode: PWM output + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.0 + name: TCC0/WO/0 + label: WO/0 + - identifier: PWM_0:WO/1 + pad: PB13 + mode: PWM output + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.1 + name: TCC0/WO/1 + label: WO/1 + - identifier: PWM_0:WO/2 + pad: PB14 + mode: PWM output + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.2 + name: TCC0/WO/2 + label: WO/2 + - identifier: PWM_0:WO/3 + pad: PB15 + mode: PWM output + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.3 + name: TCC0/WO/3 + label: WO/3 + - identifier: PWM_0:WO/4 + pad: PB16 + mode: PWM output + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.4 + name: TCC0/WO/4 + label: WO/4 + - identifier: PWM_0:WO/5 + pad: PB17 + mode: PWM output + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.5 + name: TCC0/WO/5 + label: WO/5 + variant: null + clocks: + domain_group: + nodes: + - name: TCC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + tcc_gclk_selection: Generic clock generator 0 + PWM_1: + user_label: PWM_1 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TCC1::driver_config_definition::PWM::HAL:Driver:PWM + functionality: PWM + api: HAL:Driver:PWM + configuration: + tcc_arch_alock: false + tcc_arch_cc0: 0 + tcc_arch_cc1: 0 + tcc_arch_cc2: 0 + tcc_arch_cc3: 0 + tcc_arch_cnteo: false + tcc_arch_cntsel: An interrupt/event is generated when a new counter cycle starts + tcc_arch_cpten0: false + tcc_arch_cpten1: false + tcc_arch_cpten2: false + tcc_arch_cpten3: false + tcc_arch_cpten4: false + tcc_arch_cpten5: false + tcc_arch_cpten6: false + tcc_arch_cpten7: false + tcc_arch_dbgrun: false + tcc_arch_evact0: Event action disabled + tcc_arch_evact1: Event action disabled + tcc_arch_lupd: false + tcc_arch_mcei0: false + tcc_arch_mcei1: false + tcc_arch_mcei2: false + tcc_arch_mcei3: false + tcc_arch_mceo0: false + tcc_arch_mceo1: false + tcc_arch_mceo2: false + tcc_arch_mceo3: false + tcc_arch_ovfeo: false + tcc_arch_prescsync: Reload or reset counter on next GCLK + tcc_arch_runstdby: false + tcc_arch_sel_ch: 2 + tcc_arch_tcei0: false + tcc_arch_tcei1: false + tcc_arch_tceinv0: false + tcc_arch_tceinv1: false + tcc_arch_trgeo: false + tcc_arch_wave_duty_val: 500 + tcc_arch_wave_per_val: 48 + tcc_arch_wavegen: Dual-slope, interrupt/event at Top and ZERO (DSBOTH) + tcc_per: 10000 + tcc_prescaler: Divide by 2 + timer_event_control: true + optional_signals: + - identifier: PWM_1:WO/0 + pad: PA16 + mode: PWM output + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.0 + name: TCC1/WO/0 + label: WO/0 + - identifier: PWM_1:WO/1 + pad: PA17 + mode: PWM output + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.1 + name: TCC1/WO/1 + label: WO/1 + - identifier: PWM_1:WO/2 + pad: PA18 + mode: PWM output + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.2 + name: TCC1/WO/2 + label: WO/2 + - identifier: PWM_1:WO/3 + pad: PA19 + mode: PWM output + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.3 + name: TCC1/WO/3 + label: WO/3 + - identifier: PWM_1:WO/4 + pad: PA20 + mode: PWM output + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.4 + name: TCC1/WO/4 + label: WO/4 + - identifier: PWM_1:WO/5 + pad: PA21 + mode: PWM output + configuration: null + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.5 + name: TCC1/WO/5 + label: WO/5 + variant: null + clocks: + domain_group: + nodes: + - name: TCC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + tcc_gclk_selection: Generic clock generator 0 +pads: + SPI1_MOSI: + name: PA00 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA00 + mode: Digital output + user_label: SPI1_MOSI + configuration: null + SPI1_SCK: + name: PA01 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA01 + mode: Digital output + user_label: SPI1_SCK + configuration: null + ADS_DATA_RDY: + name: PA02 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA02 + mode: Digital input + user_label: ADS_DATA_RDY + configuration: null + ANAREF_3V: + name: PA03 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA03 + mode: Analog + user_label: ANAREF_3V + configuration: null + M1_IA: + name: PB04 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB04 + mode: Analog + user_label: M1_IA + configuration: null + M1_IB: + name: PB05 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB05 + mode: Analog + user_label: M1_IB + configuration: null + M2_IA: + name: PB06 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB06 + mode: Analog + user_label: M2_IA + configuration: null + M2_IB: + name: PB07 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB07 + mode: Analog + user_label: M2_IB + configuration: null + half_VREF: + name: PB08 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB08 + mode: Analog + user_label: half_VREF + configuration: null + ADS_RESET: + name: PB09 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB09 + mode: Digital output + user_label: ADS_RESET + configuration: + pad_initial_level: High + M1_HALLA: + name: PA04 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA04 + mode: Peripheral IO + user_label: M1_HALLA + configuration: null + M1_HALLB: + name: PA05 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA05 + mode: Peripheral IO + user_label: M1_HALLB + configuration: null + M1_HALLC: + name: PA06 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA06 + mode: Peripheral IO + user_label: M1_HALLC + configuration: null + ECAT_SYNC: + name: PA07 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA07 + mode: Digital input + user_label: ECAT_SYNC + configuration: null + ECAT_QSPI_MOSI: + name: PA08 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA08 + mode: Advanced + user_label: ECAT_QSPI_MOSI + configuration: null + ECAT_QSPI_MISO: + name: PA09 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA09 + mode: Advanced + user_label: ECAT_QSPI_MISO + configuration: null + ECAT_QSPI_DATA2: + name: PA10 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA10 + mode: Advanced + user_label: ECAT_QSPI_DATA2 + configuration: null + ECAT_QSPI_DATA3: + name: PA11 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA11 + mode: Advanced + user_label: ECAT_QSPI_DATA3 + configuration: null + ECAT_QSPI_SCK: + name: PB10 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB10 + mode: Digital input + user_label: ECAT_QSPI_SCK + configuration: null + ECAT_QSPI_CS: + name: PB11 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB11 + mode: Digital input + user_label: ECAT_QSPI_CS + configuration: null + M1_PWMA: + name: PB12 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB12 + mode: Peripheral IO + user_label: M1_PWMA + configuration: null + M1_PWMB: + name: PB13 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB13 + mode: Peripheral IO + user_label: M1_PWMB + configuration: null + M1_PWMC: + name: PB14 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB14 + mode: Peripheral IO + user_label: M1_PWMC + configuration: null + M1_ENA: + name: PB15 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB15 + mode: Peripheral IO + user_label: M1_ENA + configuration: null + SPI2_MOSI: + name: PA12 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA12 + mode: Digital output + user_label: SPI2_MOSI + configuration: null + SPI2_SCK: + name: PA13 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA13 + mode: Digital output + user_label: SPI2_SCK + configuration: null + SPI2_SS: + name: PA14 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA14 + mode: Digital output + user_label: SPI2_SS + configuration: + pad_initial_level: High + SPI2_MISO: + name: PA15 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA15 + mode: Digital input + user_label: SPI2_MISO + configuration: null + M2_PWMA: + name: PA16 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA16 + mode: Peripheral IO + user_label: M2_PWMA + configuration: null + M2_PWMB: + name: PA17 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA17 + mode: Peripheral IO + user_label: M2_PWMB + configuration: null + M2_PWMC: + name: PA18 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA18 + mode: Peripheral IO + user_label: M2_PWMC + configuration: null + M2_ENA: + name: PA19 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA19 + mode: Peripheral IO + user_label: M2_ENA + configuration: null + M1_ENB: + name: PB16 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB16 + mode: Peripheral IO + user_label: M1_ENB + configuration: null + M1_ENC: + name: PB17 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB17 + mode: Peripheral IO + user_label: M1_ENC + configuration: null + M2_ENB: + name: PA20 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA20 + mode: Peripheral IO + user_label: M2_ENB + configuration: null + M2_ENC: + name: PA21 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA21 + mode: Peripheral IO + user_label: M2_ENC + configuration: null + M2_HALLA: + name: PA22 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA22 + mode: Peripheral IO + user_label: M2_HALLA + configuration: null + M2_HALLB: + name: PA23 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA23 + mode: Peripheral IO + user_label: M2_HALLB + configuration: null + M2_HALLC: + name: PA24 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA24 + mode: Peripheral IO + user_label: M2_HALLC + configuration: null + M1_RST: + name: PA25 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA25 + mode: Digital output + user_label: M1_RST + configuration: null + SPI1_CS: + name: PB22 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB22 + mode: Digital output + user_label: SPI1_CS + configuration: + pad_initial_level: High + SPI1_MISO: + name: PB23 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB23 + mode: Digital input + user_label: SPI1_MISO + configuration: null + M2_RST: + name: PA27 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA27 + mode: Digital output + user_label: M2_RST + configuration: null + M1_RST_Bar: + name: PB30 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB30 + mode: Digital input + user_label: M1_RST_Bar + configuration: null + M2_RST_Bar: + name: PB31 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB31 + mode: Digital input + user_label: M2_RST_Bar + configuration: null + SPI3_SS: + name: PB00 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB00 + mode: Digital output + user_label: SPI3_SS + configuration: + pad_initial_level: High + SPI3_MISO: + name: PB01 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB01 + mode: Digital input + user_label: SPI3_MISO + configuration: null + SPI3_MOSI: + name: PB02 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB02 + mode: Digital output + user_label: SPI3_MOSI + configuration: null + SPI3_SCK: + name: PB03 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB03 + mode: Digital output + user_label: SPI3_SCK + configuration: null +toolchain_options: [] +static_files: [] diff --git a/2_Motor_Master_D51/Two_Motor_D51.atzip b/2_Motor_Master_D51/Two_Motor_D51.atzip new file mode 100644 index 0000000..f745ecf Binary files /dev/null and b/2_Motor_Master_D51/Two_Motor_D51.atzip differ