init commit of examples
This commit is contained in:
Nicolas Trimborn
54
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/RTE_Components.h
Normal file
54
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/RTE_Components.h
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@@ -0,0 +1,54 @@
|
||||
/**
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||||
* \file
|
||||
*
|
||||
* \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME)
|
||||
*
|
||||
* Copyright (c) 2012 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \acme_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \acme_license_stop
|
||||
*
|
||||
* Project: SPISLAVEDMA(3)
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||||
* Target: ATSAME54P20A
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||||
*
|
||||
**/
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||||
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||||
|
||||
#ifndef RTE_COMPONENTS_H
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#define RTE_COMPONENTS_H
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#define ATMEL_START
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||||
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#endif /* RTE_COMPONENTS_H */
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||||
54
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/hpl_cmcc_config.h
Normal file
54
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/hpl_cmcc_config.h
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@@ -0,0 +1,54 @@
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||||
/* Auto-generated config file hpl_cmcc_config.h */
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||||
#ifndef HPL_CMCC_CONFIG_H
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||||
#define HPL_CMCC_CONFIG_H
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||||
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||||
// <<< Use Configuration Wizard in Context Menu >>>
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||||
|
||||
// <h> Basic Configuration
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||||
|
||||
// <q> Cache enable
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||||
//<i> Defines the cache should be enabled or not.
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||||
// <id> cmcc_enable
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||||
#ifndef CONF_CMCC_ENABLE
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#define CONF_CMCC_ENABLE 0x0
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||||
#endif
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||||
|
||||
// <o> Cache Size
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||||
//<i> Defines the cache memory size to be configured.
|
||||
// <0x0=>1 KB
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||||
// <0x1=>2 KB
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||||
// <0x2=>4 KB
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||||
// <id> cache_size
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||||
#ifndef CONF_CMCC_CACHE_SIZE
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||||
#define CONF_CMCC_CACHE_SIZE 0x2
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||||
#endif
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||||
|
||||
// <e> Advanced Configuration
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||||
// <id> cmcc_advanced_configuration
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||||
// <q> Data cache disable
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//<i> Defines the data cache should be disabled or not.
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||||
// <id> cmcc_data_cache_disable
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||||
#ifndef CONF_CMCC_DATA_CACHE_DISABLE
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||||
#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
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||||
#endif
|
||||
|
||||
// <q> Instruction cache disable
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||||
//<i> Defines the Instruction cache should be disabled or not.
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||||
// <id> cmcc_inst_cache_disable
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||||
#ifndef CONF_CMCC_INST_CACHE_DISABLE
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||||
#define CONF_CMCC_INST_CACHE_DISABLE 0x0
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||||
#endif
|
||||
|
||||
// <q> Clock Gating disable
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||||
//<i> Defines the clock gating should be disabled or not.
|
||||
// <id> cmcc_clock_gating_disable
|
||||
#ifndef CONF_CMCC_CLK_GATING_DISABLE
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||||
#define CONF_CMCC_CLK_GATING_DISABLE 0x0
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||||
#endif
|
||||
|
||||
// </e>
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||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_CMCC_CONFIG_H
|
||||
7277
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/hpl_dmac_config.h
Normal file
7277
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/hpl_dmac_config.h
Normal file
File diff suppressed because it is too large
Load Diff
920
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/hpl_gclk_config.h
Normal file
920
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/hpl_gclk_config.h
Normal file
@@ -0,0 +1,920 @@
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||||
/* Auto-generated config file hpl_gclk_config.h */
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||||
#ifndef HPL_GCLK_CONFIG_H
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||||
#define HPL_GCLK_CONFIG_H
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||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> Generic clock generator 0 configuration
|
||||
// <i> Indicates whether generic clock 0 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_0
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||||
#ifndef CONF_GCLK_GENERATOR_0_CONFIG
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||||
#define CONF_GCLK_GENERATOR_0_CONFIG 1
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||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
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||||
// <y> Generic clock generator 0 source
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||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
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||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 0
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||||
// <id> gclk_gen_0_oscillator
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||||
#ifndef CONF_GCLK_GEN_0_SOURCE
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||||
#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_XOSC1
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||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_0_runstdby
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||||
#ifndef CONF_GCLK_GEN_0_RUNSTDBY
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||||
#define CONF_GCLK_GEN_0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_0_div_sel
|
||||
#ifndef CONF_GCLK_GEN_0_DIVSEL
|
||||
#define CONF_GCLK_GEN_0_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_0_oe
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||||
#ifndef CONF_GCLK_GEN_0_OE
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||||
#define CONF_GCLK_GEN_0_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_0_oov
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||||
#ifndef CONF_GCLK_GEN_0_OOV
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||||
#define CONF_GCLK_GEN_0_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_0_idc
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||||
#ifndef CONF_GCLK_GEN_0_IDC
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||||
#define CONF_GCLK_GEN_0_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_0_enable
|
||||
#ifndef CONF_GCLK_GEN_0_GENEN
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||||
#define CONF_GCLK_GEN_0_GENEN 1
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 0 division <0x0000-0xFFFF>
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||||
// <id> gclk_gen_0_div
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||||
#ifndef CONF_GCLK_GEN_0_DIV
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||||
#define CONF_GCLK_GEN_0_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 1 configuration
|
||||
// <i> Indicates whether generic clock 1 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_1
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||||
#ifndef CONF_GCLK_GENERATOR_1_CONFIG
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||||
#define CONF_GCLK_GENERATOR_1_CONFIG 0
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||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 1 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 1
|
||||
// <id> gclk_gen_1_oscillator
|
||||
#ifndef CONF_GCLK_GEN_1_SOURCE
|
||||
#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_1_runstdby
|
||||
#ifndef CONF_GCLK_GEN_1_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_1_div_sel
|
||||
#ifndef CONF_GCLK_GEN_1_DIVSEL
|
||||
#define CONF_GCLK_GEN_1_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_1_oe
|
||||
#ifndef CONF_GCLK_GEN_1_OE
|
||||
#define CONF_GCLK_GEN_1_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_1_oov
|
||||
#ifndef CONF_GCLK_GEN_1_OOV
|
||||
#define CONF_GCLK_GEN_1_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_1_idc
|
||||
#ifndef CONF_GCLK_GEN_1_IDC
|
||||
#define CONF_GCLK_GEN_1_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_1_enable
|
||||
#ifndef CONF_GCLK_GEN_1_GENEN
|
||||
#define CONF_GCLK_GEN_1_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 1 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_1_div
|
||||
#ifndef CONF_GCLK_GEN_1_DIV
|
||||
#define CONF_GCLK_GEN_1_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 2 configuration
|
||||
// <i> Indicates whether generic clock 2 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_2
|
||||
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_2_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 2 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 2
|
||||
// <id> gclk_gen_2_oscillator
|
||||
#ifndef CONF_GCLK_GEN_2_SOURCE
|
||||
#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_2_runstdby
|
||||
#ifndef CONF_GCLK_GEN_2_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_2_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_2_div_sel
|
||||
#ifndef CONF_GCLK_GEN_2_DIVSEL
|
||||
#define CONF_GCLK_GEN_2_DIVSEL 1
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_2_oe
|
||||
#ifndef CONF_GCLK_GEN_2_OE
|
||||
#define CONF_GCLK_GEN_2_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_2_oov
|
||||
#ifndef CONF_GCLK_GEN_2_OOV
|
||||
#define CONF_GCLK_GEN_2_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_2_idc
|
||||
#ifndef CONF_GCLK_GEN_2_IDC
|
||||
#define CONF_GCLK_GEN_2_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_2_enable
|
||||
#ifndef CONF_GCLK_GEN_2_GENEN
|
||||
#define CONF_GCLK_GEN_2_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 2 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_2_div
|
||||
#ifndef CONF_GCLK_GEN_2_DIV
|
||||
#define CONF_GCLK_GEN_2_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 3 configuration
|
||||
// <i> Indicates whether generic clock 3 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_3
|
||||
#ifndef CONF_GCLK_GENERATOR_3_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_3_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 3 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 3
|
||||
// <id> gclk_gen_3_oscillator
|
||||
#ifndef CONF_GCLK_GEN_3_SOURCE
|
||||
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_3_runstdby
|
||||
#ifndef CONF_GCLK_GEN_3_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_3_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_3_div_sel
|
||||
#ifndef CONF_GCLK_GEN_3_DIVSEL
|
||||
#define CONF_GCLK_GEN_3_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_3_oe
|
||||
#ifndef CONF_GCLK_GEN_3_OE
|
||||
#define CONF_GCLK_GEN_3_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_3_oov
|
||||
#ifndef CONF_GCLK_GEN_3_OOV
|
||||
#define CONF_GCLK_GEN_3_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_3_idc
|
||||
#ifndef CONF_GCLK_GEN_3_IDC
|
||||
#define CONF_GCLK_GEN_3_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_3_enable
|
||||
#ifndef CONF_GCLK_GEN_3_GENEN
|
||||
#define CONF_GCLK_GEN_3_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 3 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_3_div
|
||||
#ifndef CONF_GCLK_GEN_3_DIV
|
||||
#define CONF_GCLK_GEN_3_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 4 configuration
|
||||
// <i> Indicates whether generic clock 4 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_4
|
||||
#ifndef CONF_GCLK_GENERATOR_4_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_4_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 4 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 4
|
||||
// <id> gclk_gen_4_oscillator
|
||||
#ifndef CONF_GCLK_GEN_4_SOURCE
|
||||
#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_4_runstdby
|
||||
#ifndef CONF_GCLK_GEN_4_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_4_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_4_div_sel
|
||||
#ifndef CONF_GCLK_GEN_4_DIVSEL
|
||||
#define CONF_GCLK_GEN_4_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_4_oe
|
||||
#ifndef CONF_GCLK_GEN_4_OE
|
||||
#define CONF_GCLK_GEN_4_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_4_oov
|
||||
#ifndef CONF_GCLK_GEN_4_OOV
|
||||
#define CONF_GCLK_GEN_4_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_4_idc
|
||||
#ifndef CONF_GCLK_GEN_4_IDC
|
||||
#define CONF_GCLK_GEN_4_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_4_enable
|
||||
#ifndef CONF_GCLK_GEN_4_GENEN
|
||||
#define CONF_GCLK_GEN_4_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 4 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_4_div
|
||||
#ifndef CONF_GCLK_GEN_4_DIV
|
||||
#define CONF_GCLK_GEN_4_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 5 configuration
|
||||
// <i> Indicates whether generic clock 5 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_5
|
||||
#ifndef CONF_GCLK_GENERATOR_5_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_5_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 5 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 5
|
||||
// <id> gclk_gen_5_oscillator
|
||||
#ifndef CONF_GCLK_GEN_5_SOURCE
|
||||
#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_5_runstdby
|
||||
#ifndef CONF_GCLK_GEN_5_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_5_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_5_div_sel
|
||||
#ifndef CONF_GCLK_GEN_5_DIVSEL
|
||||
#define CONF_GCLK_GEN_5_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_5_oe
|
||||
#ifndef CONF_GCLK_GEN_5_OE
|
||||
#define CONF_GCLK_GEN_5_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_5_oov
|
||||
#ifndef CONF_GCLK_GEN_5_OOV
|
||||
#define CONF_GCLK_GEN_5_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_5_idc
|
||||
#ifndef CONF_GCLK_GEN_5_IDC
|
||||
#define CONF_GCLK_GEN_5_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_5_enable
|
||||
#ifndef CONF_GCLK_GEN_5_GENEN
|
||||
#define CONF_GCLK_GEN_5_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 5 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_5_div
|
||||
#ifndef CONF_GCLK_GEN_5_DIV
|
||||
#define CONF_GCLK_GEN_5_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 6 configuration
|
||||
// <i> Indicates whether generic clock 6 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_6
|
||||
#ifndef CONF_GCLK_GENERATOR_6_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_6_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 6 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 6
|
||||
// <id> gclk_gen_6_oscillator
|
||||
#ifndef CONF_GCLK_GEN_6_SOURCE
|
||||
#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_6_runstdby
|
||||
#ifndef CONF_GCLK_GEN_6_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_6_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_6_div_sel
|
||||
#ifndef CONF_GCLK_GEN_6_DIVSEL
|
||||
#define CONF_GCLK_GEN_6_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_6_oe
|
||||
#ifndef CONF_GCLK_GEN_6_OE
|
||||
#define CONF_GCLK_GEN_6_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_6_oov
|
||||
#ifndef CONF_GCLK_GEN_6_OOV
|
||||
#define CONF_GCLK_GEN_6_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_6_idc
|
||||
#ifndef CONF_GCLK_GEN_6_IDC
|
||||
#define CONF_GCLK_GEN_6_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_6_enable
|
||||
#ifndef CONF_GCLK_GEN_6_GENEN
|
||||
#define CONF_GCLK_GEN_6_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 6 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_6_div
|
||||
#ifndef CONF_GCLK_GEN_6_DIV
|
||||
#define CONF_GCLK_GEN_6_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 7 configuration
|
||||
// <i> Indicates whether generic clock 7 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_7
|
||||
#ifndef CONF_GCLK_GENERATOR_7_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_7_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 7 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 7
|
||||
// <id> gclk_gen_7_oscillator
|
||||
#ifndef CONF_GCLK_GEN_7_SOURCE
|
||||
#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_7_runstdby
|
||||
#ifndef CONF_GCLK_GEN_7_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_7_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_7_div_sel
|
||||
#ifndef CONF_GCLK_GEN_7_DIVSEL
|
||||
#define CONF_GCLK_GEN_7_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_7_oe
|
||||
#ifndef CONF_GCLK_GEN_7_OE
|
||||
#define CONF_GCLK_GEN_7_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_7_oov
|
||||
#ifndef CONF_GCLK_GEN_7_OOV
|
||||
#define CONF_GCLK_GEN_7_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_7_idc
|
||||
#ifndef CONF_GCLK_GEN_7_IDC
|
||||
#define CONF_GCLK_GEN_7_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_7_enable
|
||||
#ifndef CONF_GCLK_GEN_7_GENEN
|
||||
#define CONF_GCLK_GEN_7_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 7 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_7_div
|
||||
#ifndef CONF_GCLK_GEN_7_DIV
|
||||
#define CONF_GCLK_GEN_7_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 8 configuration
|
||||
// <i> Indicates whether generic clock 8 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_8
|
||||
#ifndef CONF_GCLK_GENERATOR_8_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_8_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 8 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 8
|
||||
// <id> gclk_gen_8_oscillator
|
||||
#ifndef CONF_GCLK_GEN_8_SOURCE
|
||||
#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_8_runstdby
|
||||
#ifndef CONF_GCLK_GEN_8_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_8_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_8_div_sel
|
||||
#ifndef CONF_GCLK_GEN_8_DIVSEL
|
||||
#define CONF_GCLK_GEN_8_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_8_oe
|
||||
#ifndef CONF_GCLK_GEN_8_OE
|
||||
#define CONF_GCLK_GEN_8_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_8_oov
|
||||
#ifndef CONF_GCLK_GEN_8_OOV
|
||||
#define CONF_GCLK_GEN_8_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_8_idc
|
||||
#ifndef CONF_GCLK_GEN_8_IDC
|
||||
#define CONF_GCLK_GEN_8_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_8_enable
|
||||
#ifndef CONF_GCLK_GEN_8_GENEN
|
||||
#define CONF_GCLK_GEN_8_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 8 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_8_div
|
||||
#ifndef CONF_GCLK_GEN_8_DIV
|
||||
#define CONF_GCLK_GEN_8_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 9 configuration
|
||||
// <i> Indicates whether generic clock 9 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_9
|
||||
#ifndef CONF_GCLK_GENERATOR_9_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_9_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 9 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 9
|
||||
// <id> gclk_gen_9_oscillator
|
||||
#ifndef CONF_GCLK_GEN_9_SOURCE
|
||||
#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_9_runstdby
|
||||
#ifndef CONF_GCLK_GEN_9_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_9_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_9_div_sel
|
||||
#ifndef CONF_GCLK_GEN_9_DIVSEL
|
||||
#define CONF_GCLK_GEN_9_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_9_oe
|
||||
#ifndef CONF_GCLK_GEN_9_OE
|
||||
#define CONF_GCLK_GEN_9_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_9_oov
|
||||
#ifndef CONF_GCLK_GEN_9_OOV
|
||||
#define CONF_GCLK_GEN_9_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_9_idc
|
||||
#ifndef CONF_GCLK_GEN_9_IDC
|
||||
#define CONF_GCLK_GEN_9_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_9_enable
|
||||
#ifndef CONF_GCLK_GEN_9_GENEN
|
||||
#define CONF_GCLK_GEN_9_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 9 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_9_div
|
||||
#ifndef CONF_GCLK_GEN_9_DIV
|
||||
#define CONF_GCLK_GEN_9_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 10 configuration
|
||||
// <i> Indicates whether generic clock 10 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_10
|
||||
#ifndef CONF_GCLK_GENERATOR_10_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_10_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 10 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 10
|
||||
// <id> gclk_gen_10_oscillator
|
||||
#ifndef CONF_GCLK_GEN_10_SOURCE
|
||||
#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_10_runstdby
|
||||
#ifndef CONF_GCLK_GEN_10_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_10_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_10_div_sel
|
||||
#ifndef CONF_GCLK_GEN_10_DIVSEL
|
||||
#define CONF_GCLK_GEN_10_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_10_oe
|
||||
#ifndef CONF_GCLK_GEN_10_OE
|
||||
#define CONF_GCLK_GEN_10_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_10_oov
|
||||
#ifndef CONF_GCLK_GEN_10_OOV
|
||||
#define CONF_GCLK_GEN_10_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_10_idc
|
||||
#ifndef CONF_GCLK_GEN_10_IDC
|
||||
#define CONF_GCLK_GEN_10_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_10_enable
|
||||
#ifndef CONF_GCLK_GEN_10_GENEN
|
||||
#define CONF_GCLK_GEN_10_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 10 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_10_div
|
||||
#ifndef CONF_GCLK_GEN_10_DIV
|
||||
#define CONF_GCLK_GEN_10_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 11 configuration
|
||||
// <i> Indicates whether generic clock 11 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_11
|
||||
#ifndef CONF_GCLK_GENERATOR_11_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_11_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 11 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 11
|
||||
// <id> gclk_gen_11_oscillator
|
||||
#ifndef CONF_GCLK_GEN_11_SOURCE
|
||||
#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_11_runstdby
|
||||
#ifndef CONF_GCLK_GEN_11_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_11_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_11_div_sel
|
||||
#ifndef CONF_GCLK_GEN_11_DIVSEL
|
||||
#define CONF_GCLK_GEN_11_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_11_oe
|
||||
#ifndef CONF_GCLK_GEN_11_OE
|
||||
#define CONF_GCLK_GEN_11_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_11_oov
|
||||
#ifndef CONF_GCLK_GEN_11_OOV
|
||||
#define CONF_GCLK_GEN_11_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_11_idc
|
||||
#ifndef CONF_GCLK_GEN_11_IDC
|
||||
#define CONF_GCLK_GEN_11_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_11_enable
|
||||
#ifndef CONF_GCLK_GEN_11_GENEN
|
||||
#define CONF_GCLK_GEN_11_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 11 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_11_div
|
||||
#ifndef CONF_GCLK_GEN_11_DIV
|
||||
#define CONF_GCLK_GEN_11_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_GCLK_CONFIG_H
|
||||
104
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/hpl_mclk_config.h
Normal file
104
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/hpl_mclk_config.h
Normal file
@@ -0,0 +1,104 @@
|
||||
/* Auto-generated config file hpl_mclk_config.h */
|
||||
#ifndef HPL_MCLK_CONFIG_H
|
||||
#define HPL_MCLK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
// <e> System Configuration
|
||||
// <i> Indicates whether configuration for system is enabled or not
|
||||
// <id> enable_cpu_clock
|
||||
#ifndef CONF_SYSTEM_CONFIG
|
||||
#define CONF_SYSTEM_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> Basic settings
|
||||
// <y> CPU Clock source
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <i> This defines the clock source for the CPU
|
||||
// <id> cpu_clock_source
|
||||
#ifndef CONF_CPU_SRC
|
||||
#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> CPU Clock Division Factor
|
||||
// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
|
||||
// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
|
||||
// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
|
||||
// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
|
||||
// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
|
||||
// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
|
||||
// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
|
||||
// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
|
||||
// <i> Prescalar for CPU clock
|
||||
// <id> cpu_div
|
||||
#ifndef CONF_MCLK_CPUDIV
|
||||
#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
|
||||
#endif
|
||||
// <y> Low Power Clock Division
|
||||
// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
|
||||
// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
|
||||
// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
|
||||
// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
|
||||
// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
|
||||
// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
|
||||
// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
|
||||
// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
|
||||
// <id> mclk_arch_lpdiv
|
||||
#ifndef CONF_MCLK_LPDIV
|
||||
#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
|
||||
#endif
|
||||
|
||||
// <y> Backup Clock Division
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
|
||||
// <id> mclk_arch_bupdiv
|
||||
#ifndef CONF_MCLK_BUPDIV
|
||||
#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
|
||||
#endif
|
||||
// <y> High-Speed Clock Division
|
||||
// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
|
||||
// <id> mclk_arch_hsdiv
|
||||
#ifndef CONF_MCLK_HSDIV
|
||||
#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <h> NVM Settings
|
||||
// <o> NVM Wait States
|
||||
// <i> These bits select the number of wait states for a read operation.
|
||||
// <0=> 0
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
// <8=> 8
|
||||
// <9=> 9
|
||||
// <10=> 10
|
||||
// <11=> 11
|
||||
// <12=> 12
|
||||
// <13=> 13
|
||||
// <14=> 14
|
||||
// <15=> 15
|
||||
// <id> nvm_wait_states
|
||||
#ifndef CONF_NVM_WAIT_STATE
|
||||
#define CONF_NVM_WAIT_STATE 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_MCLK_CONFIG_H
|
||||
@@ -0,0 +1,165 @@
|
||||
/* Auto-generated config file hpl_osc32kctrl_config.h */
|
||||
#ifndef HPL_OSC32KCTRL_CONFIG_H
|
||||
#define HPL_OSC32KCTRL_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> RTC Source configuration
|
||||
// <id> enable_rtc_source
|
||||
#ifndef CONF_RTCCTRL_CONFIG
|
||||
#define CONF_RTCCTRL_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> RTC source control
|
||||
// <y> RTC Clock Source Selection
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <i> This defines the clock source for RTC
|
||||
// <id> rtc_source_oscillator
|
||||
#ifndef CONF_RTCCTRL_SRC
|
||||
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
|
||||
#endif
|
||||
|
||||
// <q> Use 1 kHz output
|
||||
// <id> rtc_1khz_selection
|
||||
#ifndef CONF_RTCCTRL_1KHZ
|
||||
|
||||
#define CONF_RTCCTRL_1KHZ 0
|
||||
|
||||
#endif
|
||||
|
||||
#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
|
||||
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
|
||||
#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
|
||||
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
|
||||
#else
|
||||
#error unexpected CONF_RTCCTRL_SRC
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> 32kHz External Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for External 32K Osc is enabled or not
|
||||
// <id> enable_xosc32k
|
||||
#ifndef CONF_XOSC32K_CONFIG
|
||||
#define CONF_XOSC32K_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> 32kHz External Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
|
||||
// <id> xosc32k_arch_enable
|
||||
#ifndef CONF_XOSC32K_ENABLE
|
||||
#define CONF_XOSC32K_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>62592us
|
||||
// <0x1=>125092us
|
||||
// <0x2=>500092us
|
||||
// <0x3=>1000092us
|
||||
// <0x4=>2000092us
|
||||
// <0x5=>4000092us
|
||||
// <0x6=>8000092us
|
||||
// <id> xosc32k_arch_startup
|
||||
#ifndef CONF_XOSC32K_STARTUP
|
||||
#define CONF_XOSC32K_STARTUP 0x0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc32k_arch_ondemand
|
||||
#ifndef CONF_XOSC32K_ONDEMAND
|
||||
#define CONF_XOSC32K_ONDEMAND 1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc32k_arch_runstdby
|
||||
#ifndef CONF_XOSC32K_RUNSTDBY
|
||||
#define CONF_XOSC32K_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> 1kHz Output Enable
|
||||
// <i> Indicates whether 1kHz Output is enabled or not
|
||||
// <id> xosc32k_arch_en1k
|
||||
#ifndef CONF_XOSC32K_EN1K
|
||||
#define CONF_XOSC32K_EN1K 0
|
||||
#endif
|
||||
|
||||
// <q> 32kHz Output Enable
|
||||
// <i> Indicates whether 32kHz Output is enabled or not
|
||||
// <id> xosc32k_arch_en32k
|
||||
#ifndef CONF_XOSC32K_EN32K
|
||||
#define CONF_XOSC32K_EN32K 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc32k_arch_swben
|
||||
#ifndef CONF_XOSC32K_SWBEN
|
||||
#define CONF_XOSC32K_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc32k_arch_cfden
|
||||
#ifndef CONF_XOSC32K_CFDEN
|
||||
#define CONF_XOSC32K_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector Event Out
|
||||
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
|
||||
// <id> xosc32k_arch_cfdeo
|
||||
#ifndef CONF_XOSC32K_CFDEO
|
||||
#define CONF_XOSC32K_CFDEO 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN32/XOUT32 Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc32k_arch_xtalen
|
||||
#ifndef CONF_XOSC32K_XTALEN
|
||||
#define CONF_XOSC32K_XTALEN 0
|
||||
#endif
|
||||
|
||||
// <o> Control Gain Mode
|
||||
// <0x0=>Low Power mode
|
||||
// <0x1=>Standard mode
|
||||
// <0x2=>High Speed mode
|
||||
// <id> xosc32k_arch_cgm
|
||||
#ifndef CONF_XOSC32K_CGM
|
||||
#define CONF_XOSC32K_CGM 0x1
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for OSCULP32K is enabled or not
|
||||
// <id> enable_osculp32k
|
||||
#ifndef CONF_OSCULP32K_CONFIG
|
||||
#define CONF_OSCULP32K_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> 32kHz Ultra Low Power Internal Oscillator Control
|
||||
|
||||
// <q> Oscillator Calibration Control
|
||||
// <i> Indicates whether Oscillator Calibration is enabled or not
|
||||
// <id> osculp32k_calib_enable
|
||||
#ifndef CONF_OSCULP32K_CALIB_ENABLE
|
||||
#define CONF_OSCULP32K_CALIB_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Oscillator Calibration <0x0-0x3F>
|
||||
// <id> osculp32k_calib
|
||||
#ifndef CONF_OSCULP32K_CALIB
|
||||
#define CONF_OSCULP32K_CALIB 0x0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_OSC32KCTRL_CONFIG_H
|
||||
640
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/hpl_oscctrl_config.h
Normal file
640
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/hpl_oscctrl_config.h
Normal file
@@ -0,0 +1,640 @@
|
||||
/* Auto-generated config file hpl_oscctrl_config.h */
|
||||
#ifndef HPL_OSCCTRL_CONFIG_H
|
||||
#define HPL_OSCCTRL_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> External Multipurpose Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for XOSC0 is enabled or not
|
||||
// <id> enable_xosc0
|
||||
#ifndef CONF_XOSC0_CONFIG
|
||||
#define CONF_XOSC0_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <o> Frequency <8000000-48000000>
|
||||
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
|
||||
// <id> xosc0_frequency
|
||||
#ifndef CONF_XOSC_FREQUENCY
|
||||
#define CONF_XOSC0_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
// <h> External Multipurpose Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
|
||||
// <id> xosc0_arch_enable
|
||||
#ifndef CONF_XOSC0_ENABLE
|
||||
#define CONF_XOSC0_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>31us
|
||||
// <0x1=>61us
|
||||
// <0x2=>122us
|
||||
// <0x3=>244us
|
||||
// <0x4=>488us
|
||||
// <0x5=>977us
|
||||
// <0x6=>1953us
|
||||
// <0x7=>3906us
|
||||
// <0x8=>7813us
|
||||
// <0x9=>15625us
|
||||
// <0xA=>31250us
|
||||
// <0xB=>62500us
|
||||
// <0xC=>125000us
|
||||
// <0xD=>250000us
|
||||
// <0xE=>500000us
|
||||
// <0xF=>1000000us
|
||||
// <id> xosc0_arch_startup
|
||||
#ifndef CONF_XOSC0_STARTUP
|
||||
#define CONF_XOSC0_STARTUP 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc0_arch_swben
|
||||
#ifndef CONF_XOSC0_SWBEN
|
||||
#define CONF_XOSC0_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc0_arch_cfden
|
||||
#ifndef CONF_XOSC0_CFDEN
|
||||
#define CONF_XOSC0_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Automatic Loop Control Enable
|
||||
// <i> Indicates whether Automatic Loop Control is enabled or not
|
||||
// <id> xosc0_arch_enalc
|
||||
#ifndef CONF_XOSC0_ENALC
|
||||
#define CONF_XOSC0_ENALC 0
|
||||
#endif
|
||||
|
||||
// <q> Low Buffer Gain Enable
|
||||
// <i> Indicates whether Low Buffer Gain is enabled or not
|
||||
// <id> xosc0_arch_lowbufgain
|
||||
#ifndef CONF_XOSC0_LOWBUFGAIN
|
||||
#define CONF_XOSC0_LOWBUFGAIN 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc0_arch_ondemand
|
||||
#ifndef CONF_XOSC0_ONDEMAND
|
||||
#define CONF_XOSC0_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc0_arch_runstdby
|
||||
#ifndef CONF_XOSC0_RUNSTDBY
|
||||
#define CONF_XOSC0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN/XOUT Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc0_arch_xtalen
|
||||
#ifndef CONF_XOSC0_XTALEN
|
||||
#define CONF_XOSC0_XTALEN 0
|
||||
#endif
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
#if CONF_XOSC0_FREQUENCY >= 32000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x0
|
||||
#define CONF_XOSC0_IMULT 0x7
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 24000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x1
|
||||
#define CONF_XOSC0_IMULT 0x6
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 16000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x2
|
||||
#define CONF_XOSC0_IMULT 0x5
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 8000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x3
|
||||
#define CONF_XOSC0_IMULT 0x4
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#endif
|
||||
|
||||
// <e> External Multipurpose Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for XOSC1 is enabled or not
|
||||
// <id> enable_xosc1
|
||||
#ifndef CONF_XOSC1_CONFIG
|
||||
#define CONF_XOSC1_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <o> Frequency <8000000-48000000>
|
||||
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
|
||||
// <id> xosc1_frequency
|
||||
#ifndef CONF_XOSC_FREQUENCY
|
||||
#define CONF_XOSC1_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
// <h> External Multipurpose Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
|
||||
// <id> xosc1_arch_enable
|
||||
#ifndef CONF_XOSC1_ENABLE
|
||||
#define CONF_XOSC1_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>31us
|
||||
// <0x1=>61us
|
||||
// <0x2=>122us
|
||||
// <0x3=>244us
|
||||
// <0x4=>488us
|
||||
// <0x5=>977us
|
||||
// <0x6=>1953us
|
||||
// <0x7=>3906us
|
||||
// <0x8=>7813us
|
||||
// <0x9=>15625us
|
||||
// <0xA=>31250us
|
||||
// <0xB=>62500us
|
||||
// <0xC=>125000us
|
||||
// <0xD=>250000us
|
||||
// <0xE=>500000us
|
||||
// <0xF=>1000000us
|
||||
// <id> xosc1_arch_startup
|
||||
#ifndef CONF_XOSC1_STARTUP
|
||||
#define CONF_XOSC1_STARTUP 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc1_arch_swben
|
||||
#ifndef CONF_XOSC1_SWBEN
|
||||
#define CONF_XOSC1_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc1_arch_cfden
|
||||
#ifndef CONF_XOSC1_CFDEN
|
||||
#define CONF_XOSC1_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Automatic Loop Control Enable
|
||||
// <i> Indicates whether Automatic Loop Control is enabled or not
|
||||
// <id> xosc1_arch_enalc
|
||||
#ifndef CONF_XOSC1_ENALC
|
||||
#define CONF_XOSC1_ENALC 0
|
||||
#endif
|
||||
|
||||
// <q> Low Buffer Gain Enable
|
||||
// <i> Indicates whether Low Buffer Gain is enabled or not
|
||||
// <id> xosc1_arch_lowbufgain
|
||||
#ifndef CONF_XOSC1_LOWBUFGAIN
|
||||
#define CONF_XOSC1_LOWBUFGAIN 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc1_arch_ondemand
|
||||
#ifndef CONF_XOSC1_ONDEMAND
|
||||
#define CONF_XOSC1_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc1_arch_runstdby
|
||||
#ifndef CONF_XOSC1_RUNSTDBY
|
||||
#define CONF_XOSC1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN/XOUT Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc1_arch_xtalen
|
||||
#ifndef CONF_XOSC1_XTALEN
|
||||
#define CONF_XOSC1_XTALEN 1
|
||||
#endif
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
#if CONF_XOSC1_FREQUENCY >= 32000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x0
|
||||
#define CONF_XOSC1_IMULT 0x7
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 24000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x1
|
||||
#define CONF_XOSC1_IMULT 0x6
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 16000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x2
|
||||
#define CONF_XOSC1_IMULT 0x5
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 8000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x3
|
||||
#define CONF_XOSC1_IMULT 0x4
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#endif
|
||||
|
||||
// <e> DFLL Configuration
|
||||
// <i> Indicates whether configuration for DFLL is enabled or not
|
||||
// <id> enable_dfll
|
||||
#ifndef CONF_DFLL_CONFIG
|
||||
#define CONF_DFLL_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source
|
||||
// <id> dfll_ref_clock
|
||||
#ifndef CONF_DFLL_GCLK
|
||||
#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
// <h> Digital Frequency Locked Loop Control
|
||||
// <q> DFLL Enable
|
||||
// <i> Indicates whether DFLL is enabled or not
|
||||
// <id> dfll_arch_enable
|
||||
#ifndef CONF_DFLL_ENABLE
|
||||
#define CONF_DFLL_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> dfll_arch_ondemand
|
||||
#ifndef CONF_DFLL_ONDEMAND
|
||||
#define CONF_DFLL_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> dfll_arch_runstdby
|
||||
#ifndef CONF_DFLL_RUNSTDBY
|
||||
#define CONF_DFLL_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> USB Clock Recovery Mode
|
||||
// <i> Indicates whether USB Clock Recovery Mode is enabled or not
|
||||
// <id> dfll_arch_usbcrm
|
||||
#ifndef CONF_DFLL_USBCRM
|
||||
#define CONF_DFLL_USBCRM 0
|
||||
#endif
|
||||
|
||||
// <q> Wait Lock
|
||||
// <i> Indicates whether Wait Lock is enabled or not
|
||||
// <id> dfll_arch_waitlock
|
||||
#ifndef CONF_DFLL_WAITLOCK
|
||||
#define CONF_DFLL_WAITLOCK 1
|
||||
#endif
|
||||
|
||||
// <q> Bypass Coarse Lock
|
||||
// <i> Indicates whether Bypass Coarse Lock is enabled or not
|
||||
// <id> dfll_arch_bplckc
|
||||
#ifndef CONF_DFLL_BPLCKC
|
||||
#define CONF_DFLL_BPLCKC 0
|
||||
#endif
|
||||
|
||||
// <q> Quick Lock Disable
|
||||
// <i> Indicates whether Quick Lock Disable is enabled or not
|
||||
// <id> dfll_arch_qldis
|
||||
#ifndef CONF_DFLL_QLDIS
|
||||
#define CONF_DFLL_QLDIS 0
|
||||
#endif
|
||||
|
||||
// <q> Chill Cycle Disable
|
||||
// <i> Indicates whether Chill Cycle Disable is enabled or not
|
||||
// <id> dfll_arch_ccdis
|
||||
#ifndef CONF_DFLL_CCDIS
|
||||
#define CONF_DFLL_CCDIS 0
|
||||
#endif
|
||||
|
||||
// <q> Lose Lock After Wake
|
||||
// <i> Indicates whether Lose Lock After Wake is enabled or not
|
||||
// <id> dfll_arch_llaw
|
||||
#ifndef CONF_DFLL_LLAW
|
||||
#define CONF_DFLL_LLAW 0
|
||||
#endif
|
||||
|
||||
// <q> Stable DFLL Frequency
|
||||
// <i> Indicates whether Stable DFLL Frequency is enabled or not
|
||||
// <id> dfll_arch_stable
|
||||
#ifndef CONF_DFLL_STABLE
|
||||
#define CONF_DFLL_STABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Operating Mode Selection
|
||||
// <0=>Open Loop Mode
|
||||
// <1=>Closed Loop Mode
|
||||
// <id> dfll_mode
|
||||
#ifndef CONF_DFLL_MODE
|
||||
#define CONF_DFLL_MODE 0x0
|
||||
#endif
|
||||
|
||||
// <o> Coarse Maximum Step <0x0-0x1F>
|
||||
// <id> dfll_arch_cstep
|
||||
#ifndef CONF_DFLL_CSTEP
|
||||
#define CONF_DFLL_CSTEP 0x1
|
||||
#endif
|
||||
|
||||
// <o> Fine Maximum Step <0x0-0xFF>
|
||||
// <id> dfll_arch_fstep
|
||||
#ifndef CONF_DFLL_FSTEP
|
||||
#define CONF_DFLL_FSTEP 0x1
|
||||
#endif
|
||||
|
||||
// <o> DFLL Multiply Factor <0x0-0xFFFF>
|
||||
// <id> dfll_mul
|
||||
#ifndef CONF_DFLL_MUL
|
||||
#define CONF_DFLL_MUL 0x0
|
||||
#endif
|
||||
|
||||
// <e> DFLL Calibration Overwrite
|
||||
// <i> Indicates whether Overwrite Calibration value of DFLL
|
||||
// <id> dfll_arch_calibration
|
||||
#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
|
||||
#define CONF_DFLL_OVERWRITE_CALIBRATION 0
|
||||
#endif
|
||||
|
||||
// <o> Coarse Value <0x0-0x3F>
|
||||
// <id> dfll_arch_coarse
|
||||
#ifndef CONF_DFLL_COARSE
|
||||
#define CONF_DFLL_COARSE (0x1f / 4)
|
||||
#endif
|
||||
|
||||
// <o> Fine Value <0x0-0xFF>
|
||||
// <id> dfll_arch_fine
|
||||
#ifndef CONF_DFLL_FINE
|
||||
#define CONF_DFLL_FINE (0x80)
|
||||
#endif
|
||||
|
||||
//</e>
|
||||
|
||||
//</h>
|
||||
|
||||
//</e>
|
||||
|
||||
// <e> FDPLL0 Configuration
|
||||
// <i> Indicates whether configuration for FDPLL0 is enabled or not
|
||||
// <id> enable_fdpll0
|
||||
#ifndef CONF_FDPLL0_CONFIG
|
||||
#define CONF_FDPLL0_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source.
|
||||
// <id> fdpll0_ref_clock
|
||||
#ifndef CONF_FDPLL0_GCLK
|
||||
#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// <h> Digital Phase Locked Loop Control
|
||||
// <q> Enable
|
||||
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
|
||||
// <id> fdpll0_arch_enable
|
||||
#ifndef CONF_FDPLL0_ENABLE
|
||||
#define CONF_FDPLL0_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> fdpll0_arch_ondemand
|
||||
#ifndef CONF_FDPLL0_ONDEMAND
|
||||
#define CONF_FDPLL0_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> fdpll0_arch_runstdby
|
||||
#ifndef CONF_FDPLL0_RUNSTDBY
|
||||
#define CONF_FDPLL0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
|
||||
// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll0_ldrfrac
|
||||
#ifndef CONF_FDPLL0_LDRFRAC
|
||||
#define CONF_FDPLL0_LDRFRAC 0xd
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
|
||||
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll0_ldr
|
||||
#ifndef CONF_FDPLL0_LDR
|
||||
#define CONF_FDPLL0_LDR 0x5b7
|
||||
#endif
|
||||
|
||||
// <o> Clock Divider <0x0-0x7FF>
|
||||
// <i> This Clock divider is only for XOSC clock input to DPLL
|
||||
// <id> fdpll0_clock_div
|
||||
#ifndef CONF_FDPLL0_DIV
|
||||
#define CONF_FDPLL0_DIV 0x0
|
||||
#endif
|
||||
|
||||
// <q> DCO Filter Enable
|
||||
// <i> Indicates whether DCO Filter Enable is enabled or not
|
||||
// <id> fdpll0_arch_dcoen
|
||||
#ifndef CONF_FDPLL0_DCOEN
|
||||
#define CONF_FDPLL0_DCOEN 0
|
||||
#endif
|
||||
|
||||
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
|
||||
// <id> fdpll0_clock_dcofilter
|
||||
#ifndef CONF_FDPLL0_DCOFILTER
|
||||
#define CONF_FDPLL0_DCOFILTER 0x0
|
||||
#endif
|
||||
|
||||
// <q> Lock Bypass
|
||||
// <i> Indicates whether Lock Bypass is enabled or not
|
||||
// <id> fdpll0_arch_lbypass
|
||||
#ifndef CONF_FDPLL0_LBYPASS
|
||||
#define CONF_FDPLL0_LBYPASS 0
|
||||
#endif
|
||||
|
||||
// <o> Lock Time
|
||||
// <0x0=>No time-out, automatic lock
|
||||
// <0x4=>The Time-out if no lock within 800 us
|
||||
// <0x5=>The Time-out if no lock within 900 us
|
||||
// <0x6=>The Time-out if no lock within 1 ms
|
||||
// <0x7=>The Time-out if no lock within 11 ms
|
||||
// <id> fdpll0_arch_ltime
|
||||
#ifndef CONF_FDPLL0_LTIME
|
||||
#define CONF_FDPLL0_LTIME 0x0
|
||||
#endif
|
||||
|
||||
// <o> Reference Clock Selection
|
||||
// <0x0=>GCLK clock reference
|
||||
// <0x1=>XOSC32K clock reference
|
||||
// <0x2=>XOSC0 clock reference
|
||||
// <0x3=>XOSC1 clock reference
|
||||
// <id> fdpll0_arch_refclk
|
||||
#ifndef CONF_FDPLL0_REFCLK
|
||||
#define CONF_FDPLL0_REFCLK 0x1
|
||||
#endif
|
||||
|
||||
// <q> Wake Up Fast
|
||||
// <i> Indicates whether Wake Up Fast is enabled or not
|
||||
// <id> fdpll0_arch_wuf
|
||||
#ifndef CONF_FDPLL0_WUF
|
||||
#define CONF_FDPLL0_WUF 0
|
||||
#endif
|
||||
|
||||
// <o> Proportional Integral Filter Selection <0x0-0xF>
|
||||
// <id> fdpll0_arch_filter
|
||||
#ifndef CONF_FDPLL0_FILTER
|
||||
#define CONF_FDPLL0_FILTER 0x0
|
||||
#endif
|
||||
|
||||
//</h>
|
||||
//</e>
|
||||
// <e> FDPLL1 Configuration
|
||||
// <i> Indicates whether configuration for FDPLL1 is enabled or not
|
||||
// <id> enable_fdpll1
|
||||
#ifndef CONF_FDPLL1_CONFIG
|
||||
#define CONF_FDPLL1_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source.
|
||||
// <id> fdpll1_ref_clock
|
||||
#ifndef CONF_FDPLL1_GCLK
|
||||
#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// <h> Digital Phase Locked Loop Control
|
||||
// <q> Enable
|
||||
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
|
||||
// <id> fdpll1_arch_enable
|
||||
#ifndef CONF_FDPLL1_ENABLE
|
||||
#define CONF_FDPLL1_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> fdpll1_arch_ondemand
|
||||
#ifndef CONF_FDPLL1_ONDEMAND
|
||||
#define CONF_FDPLL1_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> fdpll1_arch_runstdby
|
||||
#ifndef CONF_FDPLL1_RUNSTDBY
|
||||
#define CONF_FDPLL1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
|
||||
// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll1_ldrfrac
|
||||
#ifndef CONF_FDPLL1_LDRFRAC
|
||||
#define CONF_FDPLL1_LDRFRAC 0xd
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
|
||||
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll1_ldr
|
||||
#ifndef CONF_FDPLL1_LDR
|
||||
#define CONF_FDPLL1_LDR 0x5b7
|
||||
#endif
|
||||
|
||||
// <o> Clock Divider <0x0-0x7FF>
|
||||
// <i> This Clock divider is only for XOSC clock input to DPLL
|
||||
// <id> fdpll1_clock_div
|
||||
#ifndef CONF_FDPLL1_DIV
|
||||
#define CONF_FDPLL1_DIV 0x0
|
||||
#endif
|
||||
|
||||
// <q> DCO Filter Enable
|
||||
// <i> Indicates whether DCO Filter Enable is enabled or not
|
||||
// <id> fdpll1_arch_dcoen
|
||||
#ifndef CONF_FDPLL1_DCOEN
|
||||
#define CONF_FDPLL1_DCOEN 0
|
||||
#endif
|
||||
|
||||
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
|
||||
// <id> fdpll1_clock_dcofilter
|
||||
#ifndef CONF_FDPLL1_DCOFILTER
|
||||
#define CONF_FDPLL1_DCOFILTER 0x0
|
||||
#endif
|
||||
|
||||
// <q> Lock Bypass
|
||||
// <i> Indicates whether Lock Bypass is enabled or not
|
||||
// <id> fdpll1_arch_lbypass
|
||||
#ifndef CONF_FDPLL1_LBYPASS
|
||||
#define CONF_FDPLL1_LBYPASS 0
|
||||
#endif
|
||||
|
||||
// <o> Lock Time
|
||||
// <0x0=>No time-out, automatic lock
|
||||
// <0x4=>The Time-out if no lock within 800 us
|
||||
// <0x5=>The Time-out if no lock within 900 us
|
||||
// <0x6=>The Time-out if no lock within 1 ms
|
||||
// <0x7=>The Time-out if no lock within 11 ms
|
||||
// <id> fdpll1_arch_ltime
|
||||
#ifndef CONF_FDPLL1_LTIME
|
||||
#define CONF_FDPLL1_LTIME 0x0
|
||||
#endif
|
||||
|
||||
// <o> Reference Clock Selection
|
||||
// <0x0=>GCLK clock reference
|
||||
// <0x1=>XOSC32K clock reference
|
||||
// <0x2=>XOSC0 clock reference
|
||||
// <0x3=>XOSC1 clock reference
|
||||
// <id> fdpll1_arch_refclk
|
||||
#ifndef CONF_FDPLL1_REFCLK
|
||||
#define CONF_FDPLL1_REFCLK 0x1
|
||||
#endif
|
||||
|
||||
// <q> Wake Up Fast
|
||||
// <i> Indicates whether Wake Up Fast is enabled or not
|
||||
// <id> fdpll1_arch_wuf
|
||||
#ifndef CONF_FDPLL1_WUF
|
||||
#define CONF_FDPLL1_WUF 0
|
||||
#endif
|
||||
|
||||
// <o> Proportional Integral Filter Selection <0x0-0xF>
|
||||
// <id> fdpll1_arch_filter
|
||||
#ifndef CONF_FDPLL1_FILTER
|
||||
#define CONF_FDPLL1_FILTER 0x0
|
||||
#endif
|
||||
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_OSCCTRL_CONFIG_H
|
||||
522
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/hpl_port_config.h
Normal file
522
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/hpl_port_config.h
Normal file
@@ -0,0 +1,522 @@
|
||||
/* Auto-generated config file hpl_port_config.h */
|
||||
#ifndef HPL_PORT_CONFIG_H
|
||||
#define HPL_PORT_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> PORT Input Event 0 configuration
|
||||
// <id> enable_port_input_event_0
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_0
|
||||
#define CONF_PORT_EVCTRL_PORT_0 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 0 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
|
||||
// <id> porta_input_event_enable_0
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_0
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_0
|
||||
#define CONF_PORTA_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 0
|
||||
// <id> porta_event_action_0
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_0
|
||||
#define CONF_PORTA_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 0 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
|
||||
// <id> portb_input_event_enable_0
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_0
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_0
|
||||
#define CONF_PORTB_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 0
|
||||
// <id> portb_event_action_0
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_0
|
||||
#define CONF_PORTB_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 0 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 0 configuration is enabled
|
||||
// <id> portc_input_event_enable_0
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_0
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_0
|
||||
#define CONF_PORTC_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 0
|
||||
// <id> portc_event_action_0
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_0
|
||||
#define CONF_PORTC_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 0 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 0 configuration is enabled
|
||||
// <id> portd_input_event_enable_0
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_0
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_0
|
||||
#define CONF_PORTD_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 0
|
||||
// <id> portd_event_action_0
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_0
|
||||
#define CONF_PORTD_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 1 configuration
|
||||
// <id> enable_port_input_event_1
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_1
|
||||
#define CONF_PORT_EVCTRL_PORT_1 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 1 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
|
||||
// <id> porta_input_event_enable_1
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_1
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_1
|
||||
#define CONF_PORTA_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 1
|
||||
// <id> porta_event_action_1
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_1
|
||||
#define CONF_PORTA_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 1 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
|
||||
// <id> portb_input_event_enable_1
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_1
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_1
|
||||
#define CONF_PORTB_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 1
|
||||
// <id> portb_event_action_1
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_1
|
||||
#define CONF_PORTB_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 1 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 1 configuration is enabled
|
||||
// <id> portc_input_event_enable_1
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_1
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_1
|
||||
#define CONF_PORTC_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 1
|
||||
// <id> portc_event_action_1
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_1
|
||||
#define CONF_PORTC_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 1 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 1 configuration is enabled
|
||||
// <id> portd_input_event_enable_1
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_1
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_1
|
||||
#define CONF_PORTD_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 1
|
||||
// <id> portd_event_action_1
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_1
|
||||
#define CONF_PORTD_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 2 configuration
|
||||
// <id> enable_port_input_event_2
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_2
|
||||
#define CONF_PORT_EVCTRL_PORT_2 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 2 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
|
||||
// <id> porta_input_event_enable_2
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_2
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_2
|
||||
#define CONF_PORTA_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 2
|
||||
// <id> porta_event_action_2
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_2
|
||||
#define CONF_PORTA_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 2 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
|
||||
// <id> portb_input_event_enable_2
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_2
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_2
|
||||
#define CONF_PORTB_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 2
|
||||
// <id> portb_event_action_2
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_2
|
||||
#define CONF_PORTB_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 2 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 2 configuration is enabled
|
||||
// <id> portc_input_event_enable_2
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_2
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_2
|
||||
#define CONF_PORTC_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 2
|
||||
// <id> portc_event_action_2
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_2
|
||||
#define CONF_PORTC_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 2 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 2 configuration is enabled
|
||||
// <id> portd_input_event_enable_2
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_2
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_2
|
||||
#define CONF_PORTD_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 2
|
||||
// <id> portd_event_action_2
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_2
|
||||
#define CONF_PORTD_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 3 configuration
|
||||
// <id> enable_port_input_event_3
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_3
|
||||
#define CONF_PORT_EVCTRL_PORT_3 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 3 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
|
||||
// <id> porta_input_event_enable_3
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_3
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_3
|
||||
#define CONF_PORTA_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 3
|
||||
// <id> porta_event_action_3
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_3
|
||||
#define CONF_PORTA_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 3 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
|
||||
// <id> portb_input_event_enable_3
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_3
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_3
|
||||
#define CONF_PORTB_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 3
|
||||
// <id> portb_event_action_3
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_3
|
||||
#define CONF_PORTB_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 3 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 3 configuration is enabled
|
||||
// <id> portc_input_event_enable_3
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_3
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_3
|
||||
#define CONF_PORTC_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 3
|
||||
// <id> portc_event_action_3
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_3
|
||||
#define CONF_PORTC_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 3 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 3 configuration is enabled
|
||||
// <id> portd_input_event_enable_3
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_3
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_3
|
||||
#define CONF_PORTD_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 3
|
||||
// <id> portd_event_action_3
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_3
|
||||
#define CONF_PORTD_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
#define CONF_PORTA_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
|
||||
#define CONF_PORTB_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
|
||||
#define CONF_PORTC_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3))
|
||||
#define CONF_PORTD_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTD_EVCTRL_EVACT_0) | CONF_PORTD_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTD_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTD_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTD_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTD_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTD_EVCTRL_EVACT_2) | CONF_PORTD_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTD_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTD_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTD_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTD_EVCTRL_PID_3))
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_PORT_CONFIG_H
|
||||
627
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/hpl_sercom_config.h
Normal file
627
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/Config/hpl_sercom_config.h
Normal file
@@ -0,0 +1,627 @@
|
||||
/* Auto-generated config file hpl_sercom_config.h */
|
||||
#ifndef HPL_SERCOM_CONFIG_H
|
||||
#define HPL_SERCOM_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
#ifndef CONF_SERCOM_2_USART_ENABLE
|
||||
#define CONF_SERCOM_2_USART_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <h> Basic Configuration
|
||||
|
||||
// <q> Receive buffer enable
|
||||
// <i> Enable input buffer in SERCOM module
|
||||
// <id> usart_rx_enable
|
||||
#ifndef CONF_SERCOM_2_USART_RXEN
|
||||
#define CONF_SERCOM_2_USART_RXEN 1
|
||||
#endif
|
||||
|
||||
// <q> Transmitt buffer enable
|
||||
// <i> Enable output buffer in SERCOM module
|
||||
// <id> usart_tx_enable
|
||||
#ifndef CONF_SERCOM_2_USART_TXEN
|
||||
#define CONF_SERCOM_2_USART_TXEN 1
|
||||
#endif
|
||||
|
||||
// <o> Frame parity
|
||||
// <0x0=>No parity
|
||||
// <0x1=>Even parity
|
||||
// <0x2=>Odd parity
|
||||
// <i> Parity bit mode for USART frame
|
||||
// <id> usart_parity
|
||||
#ifndef CONF_SERCOM_2_USART_PARITY
|
||||
#define CONF_SERCOM_2_USART_PARITY 0x0
|
||||
#endif
|
||||
|
||||
// <o> Character Size
|
||||
// <0x0=>8 bits
|
||||
// <0x1=>9 bits
|
||||
// <0x5=>5 bits
|
||||
// <0x6=>6 bits
|
||||
// <0x7=>7 bits
|
||||
// <i> Data character size in USART frame
|
||||
// <id> usart_character_size
|
||||
#ifndef CONF_SERCOM_2_USART_CHSIZE
|
||||
#define CONF_SERCOM_2_USART_CHSIZE 0x0
|
||||
#endif
|
||||
|
||||
// <o> Stop Bit
|
||||
// <0=>One stop bit
|
||||
// <1=>Two stop bits
|
||||
// <i> Number of stop bits in USART frame
|
||||
// <id> usart_stop_bit
|
||||
#ifndef CONF_SERCOM_2_USART_SBMODE
|
||||
#define CONF_SERCOM_2_USART_SBMODE 0
|
||||
#endif
|
||||
|
||||
// <o> Baud rate <1-6250000>
|
||||
// <i> USART baud rate setting
|
||||
// <id> usart_baud_rate
|
||||
#ifndef CONF_SERCOM_2_USART_BAUD
|
||||
#define CONF_SERCOM_2_USART_BAUD 9600
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced configuration
|
||||
// <id> usart_advanced
|
||||
#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
|
||||
#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <q> Run in stand-by
|
||||
// <i> Keep the module running in standby sleep mode
|
||||
// <id> usart_arch_runstdby
|
||||
#ifndef CONF_SERCOM_2_USART_RUNSTDBY
|
||||
#define CONF_SERCOM_2_USART_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Immediate Buffer Overflow Notification
|
||||
// <i> Controls when the BUFOVF status bit is asserted
|
||||
// <id> usart_arch_ibon
|
||||
#ifndef CONF_SERCOM_2_USART_IBON
|
||||
#define CONF_SERCOM_2_USART_IBON 0
|
||||
#endif
|
||||
|
||||
// <q> Start of Frame Detection Enable
|
||||
// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
|
||||
// <id> usart_arch_sfde
|
||||
#ifndef CONF_SERCOM_2_USART_SFDE
|
||||
#define CONF_SERCOM_2_USART_SFDE 0
|
||||
#endif
|
||||
|
||||
// <q> Collision Detection Enable
|
||||
// <i> Collision detection enable
|
||||
// <id> usart_arch_cloden
|
||||
#ifndef CONF_SERCOM_2_USART_CLODEN
|
||||
#define CONF_SERCOM_2_USART_CLODEN 0
|
||||
#endif
|
||||
|
||||
// <o> Operating Mode
|
||||
// <0x0=>USART with external clock
|
||||
// <0x1=>USART with internal clock
|
||||
// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
|
||||
// <id> usart_arch_clock_mode
|
||||
#ifndef CONF_SERCOM_2_USART_MODE
|
||||
#define CONF_SERCOM_2_USART_MODE 0x1
|
||||
#endif
|
||||
|
||||
// <o> Sample Rate
|
||||
// <0x0=>16x arithmetic
|
||||
// <0x1=>16x fractional
|
||||
// <0x2=>8x arithmetic
|
||||
// <0x3=>8x fractional
|
||||
// <0x4=>3x arithmetic
|
||||
// <i> How many over-sampling bits used when sampling data state
|
||||
// <id> usart_arch_sampr
|
||||
#ifndef CONF_SERCOM_2_USART_SAMPR
|
||||
#define CONF_SERCOM_2_USART_SAMPR 0x0
|
||||
#endif
|
||||
|
||||
// <o> Sample Adjustment
|
||||
// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
|
||||
// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
|
||||
// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
|
||||
// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
|
||||
// <i> Adjust which samples to use for data sampling in asynchronous mode
|
||||
// <id> usart_arch_sampa
|
||||
#ifndef CONF_SERCOM_2_USART_SAMPA
|
||||
#define CONF_SERCOM_2_USART_SAMPA 0x0
|
||||
#endif
|
||||
|
||||
// <o> Fractional Part <0-7>
|
||||
// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
|
||||
// <id> usart_arch_fractional
|
||||
#ifndef CONF_SERCOM_2_USART_FRACTIONAL
|
||||
#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
|
||||
#endif
|
||||
|
||||
// <o> Data Order
|
||||
// <0=>MSB is transmitted first
|
||||
// <1=>LSB is transmitted first
|
||||
// <i> Data order of the data bits in the frame
|
||||
// <id> usart_arch_dord
|
||||
#ifndef CONF_SERCOM_2_USART_DORD
|
||||
#define CONF_SERCOM_2_USART_DORD 1
|
||||
#endif
|
||||
|
||||
// Does not do anything in UART mode
|
||||
#define CONF_SERCOM_2_USART_CPOL 0
|
||||
|
||||
// <o> Encoding Format
|
||||
// <0=>No encoding
|
||||
// <1=>IrDA encoded
|
||||
// <id> usart_arch_enc
|
||||
#ifndef CONF_SERCOM_2_USART_ENC
|
||||
#define CONF_SERCOM_2_USART_ENC 0
|
||||
#endif
|
||||
|
||||
// <o> LIN Slave Enable
|
||||
// <i> Break Character Detection and Auto-Baud/LIN Slave Enable.
|
||||
// <i> Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1).
|
||||
// <0=>Disable
|
||||
// <1=>Enable
|
||||
// <id> usart_arch_lin_slave_enable
|
||||
#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE
|
||||
#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Debug Stop Mode
|
||||
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
|
||||
// <0=>Keep running
|
||||
// <1=>Halt
|
||||
// <id> usart_arch_dbgstop
|
||||
#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
|
||||
#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
#ifndef CONF_SERCOM_2_USART_INACK
|
||||
#define CONF_SERCOM_2_USART_INACK 0x0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_2_USART_DSNACK
|
||||
#define CONF_SERCOM_2_USART_DSNACK 0x0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_2_USART_MAXITER
|
||||
#define CONF_SERCOM_2_USART_MAXITER 0x7
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_2_USART_GTIME
|
||||
#define CONF_SERCOM_2_USART_GTIME 0x2
|
||||
#endif
|
||||
|
||||
#define CONF_SERCOM_2_USART_RXINV 0x0
|
||||
#define CONF_SERCOM_2_USART_TXINV 0x0
|
||||
|
||||
#ifndef CONF_SERCOM_2_USART_CMODE
|
||||
#define CONF_SERCOM_2_USART_CMODE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_2_USART_RXPO
|
||||
#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_2_USART_TXPO
|
||||
#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */
|
||||
#endif
|
||||
|
||||
/* Set correct parity settings in register interface based on PARITY setting */
|
||||
#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1
|
||||
#if CONF_SERCOM_2_USART_PARITY == 0
|
||||
#define CONF_SERCOM_2_USART_PMODE 0
|
||||
#define CONF_SERCOM_2_USART_FORM 4
|
||||
#else
|
||||
#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
|
||||
#define CONF_SERCOM_2_USART_FORM 5
|
||||
#endif
|
||||
#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */
|
||||
#if CONF_SERCOM_2_USART_PARITY == 0
|
||||
#define CONF_SERCOM_2_USART_PMODE 0
|
||||
#define CONF_SERCOM_2_USART_FORM 0
|
||||
#else
|
||||
#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
|
||||
#define CONF_SERCOM_2_USART_FORM 1
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Calculate BAUD register value in UART mode
|
||||
#if CONF_SERCOM_2_USART_SAMPR == 0
|
||||
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
|
||||
#define CONF_SERCOM_2_USART_BAUD_RATE \
|
||||
65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
|
||||
#endif
|
||||
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
|
||||
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
|
||||
#endif
|
||||
#elif CONF_SERCOM_2_USART_SAMPR == 1
|
||||
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
|
||||
#define CONF_SERCOM_2_USART_BAUD_RATE \
|
||||
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
|
||||
#endif
|
||||
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
|
||||
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
|
||||
#endif
|
||||
#elif CONF_SERCOM_2_USART_SAMPR == 2
|
||||
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
|
||||
#define CONF_SERCOM_2_USART_BAUD_RATE \
|
||||
65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
|
||||
#endif
|
||||
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
|
||||
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
|
||||
#endif
|
||||
#elif CONF_SERCOM_2_USART_SAMPR == 3
|
||||
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
|
||||
#define CONF_SERCOM_2_USART_BAUD_RATE \
|
||||
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
|
||||
#endif
|
||||
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
|
||||
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
|
||||
#endif
|
||||
#elif CONF_SERCOM_2_USART_SAMPR == 4
|
||||
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
|
||||
#define CONF_SERCOM_2_USART_BAUD_RATE \
|
||||
65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
|
||||
#endif
|
||||
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
|
||||
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
// Enable configuration of module
|
||||
#ifndef CONF_SERCOM_4_SPI_ENABLE
|
||||
#define CONF_SERCOM_4_SPI_ENABLE 1
|
||||
#endif
|
||||
|
||||
//<o> SPI DMA TX Channel <0-32>
|
||||
//<i> This defines DMA channel to be used
|
||||
//<id> spi_master_dma_tx_channel
|
||||
#ifndef CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL
|
||||
#define CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL 0
|
||||
#endif
|
||||
|
||||
// <e> SPI RX Channel Enable
|
||||
// <id> spi_master_rx_channel
|
||||
#ifndef CONF_SERCOM_4_SPI_RX_CHANNEL
|
||||
#define CONF_SERCOM_4_SPI_RX_CHANNEL 1
|
||||
#endif
|
||||
|
||||
//<o> DMA Channel <0-32>
|
||||
//<i> This defines DMA channel to be used
|
||||
//<id> spi_master_dma_rx_channel
|
||||
#ifndef CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL
|
||||
#define CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// Set module in SPI Master mode
|
||||
#ifndef CONF_SERCOM_4_SPI_MODE
|
||||
#define CONF_SERCOM_4_SPI_MODE 0x03
|
||||
#endif
|
||||
|
||||
// <h> Basic Configuration
|
||||
|
||||
// <q> Receive buffer enable
|
||||
// <i> Enable receive buffer to receive data from slave (RXEN)
|
||||
// <id> spi_master_rx_enable
|
||||
#ifndef CONF_SERCOM_4_SPI_RXEN
|
||||
#define CONF_SERCOM_4_SPI_RXEN 0x1
|
||||
#endif
|
||||
|
||||
// <o> Character Size
|
||||
// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
|
||||
// <0x0=>8 bits
|
||||
// <0x1=>9 bits
|
||||
// <id> spi_master_character_size
|
||||
#ifndef CONF_SERCOM_4_SPI_CHSIZE
|
||||
#define CONF_SERCOM_4_SPI_CHSIZE 0x0
|
||||
#endif
|
||||
// <o> Baud rate <1-18000000>
|
||||
// <i> The SPI data transfer rate
|
||||
// <id> spi_master_baud_rate
|
||||
#ifndef CONF_SERCOM_4_SPI_BAUD
|
||||
#define CONF_SERCOM_4_SPI_BAUD 1000000
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced Configuration
|
||||
// <id> spi_master_advanced
|
||||
#ifndef CONF_SERCOM_4_SPI_ADVANCED
|
||||
#define CONF_SERCOM_4_SPI_ADVANCED 0
|
||||
#endif
|
||||
|
||||
// <o> Dummy byte <0x00-0x1ff>
|
||||
// <id> spi_master_dummybyte
|
||||
// <i> Dummy byte used when reading data from the slave without sending any data
|
||||
#ifndef CONF_SERCOM_4_SPI_DUMMYBYTE
|
||||
#define CONF_SERCOM_4_SPI_DUMMYBYTE 0x1ff
|
||||
#endif
|
||||
|
||||
// <o> Data Order
|
||||
// <0=>MSB first
|
||||
// <1=>LSB first
|
||||
// <i> I least significant or most significant bit is shifted out first (DORD)
|
||||
// <id> spi_master_arch_dord
|
||||
#ifndef CONF_SERCOM_4_SPI_DORD
|
||||
#define CONF_SERCOM_4_SPI_DORD 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Polarity
|
||||
// <0=>SCK is low when idle
|
||||
// <1=>SCK is high when idle
|
||||
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
|
||||
// <id> spi_master_arch_cpol
|
||||
#ifndef CONF_SERCOM_4_SPI_CPOL
|
||||
#define CONF_SERCOM_4_SPI_CPOL 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Phase
|
||||
// <0x0=>Sample input on leading edge
|
||||
// <0x1=>Sample input on trailing edge
|
||||
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
|
||||
// <id> spi_master_arch_cpha
|
||||
#ifndef CONF_SERCOM_4_SPI_CPHA
|
||||
#define CONF_SERCOM_4_SPI_CPHA 0x0
|
||||
#endif
|
||||
|
||||
// <o> Immediate Buffer Overflow Notification
|
||||
// <i> Controls when OVF is asserted (IBON)
|
||||
// <0x0=>In data stream
|
||||
// <0x1=>On buffer overflow
|
||||
// <id> spi_master_arch_ibon
|
||||
#ifndef CONF_SERCOM_4_SPI_IBON
|
||||
#define CONF_SERCOM_4_SPI_IBON 0x0
|
||||
#endif
|
||||
|
||||
// <q> Run in stand-by
|
||||
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
|
||||
// <id> spi_master_arch_runstdby
|
||||
#ifndef CONF_SERCOM_4_SPI_RUNSTDBY
|
||||
#define CONF_SERCOM_4_SPI_RUNSTDBY 0x0
|
||||
#endif
|
||||
|
||||
// <o> Debug Stop Mode
|
||||
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
|
||||
// <0=>Keep running
|
||||
// <1=>Halt
|
||||
// <id> spi_master_arch_dbgstop
|
||||
#ifndef CONF_SERCOM_4_SPI_DBGSTOP
|
||||
#define CONF_SERCOM_4_SPI_DBGSTOP 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// Address mode disabled in master mode
|
||||
#ifndef CONF_SERCOM_4_SPI_AMODE_EN
|
||||
#define CONF_SERCOM_4_SPI_AMODE_EN 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_4_SPI_AMODE
|
||||
#define CONF_SERCOM_4_SPI_AMODE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_4_SPI_ADDR
|
||||
#define CONF_SERCOM_4_SPI_ADDR 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_4_SPI_ADDRMASK
|
||||
#define CONF_SERCOM_4_SPI_ADDRMASK 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_4_SPI_SSDE
|
||||
#define CONF_SERCOM_4_SPI_SSDE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_4_SPI_MSSEN
|
||||
#define CONF_SERCOM_4_SPI_MSSEN 0x0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_4_SPI_PLOADEN
|
||||
#define CONF_SERCOM_4_SPI_PLOADEN 0
|
||||
#endif
|
||||
|
||||
// <o> Receive Data Pinout
|
||||
// <0x0=>PAD[0]
|
||||
// <0x1=>PAD[1]
|
||||
// <0x2=>PAD[2]
|
||||
// <0x3=>PAD[3]
|
||||
// <id> spi_master_rxpo
|
||||
#ifndef CONF_SERCOM_4_SPI_RXPO
|
||||
#define CONF_SERCOM_4_SPI_RXPO 3
|
||||
#endif
|
||||
|
||||
// <o> Transmit Data Pinout
|
||||
// <0x0=>PAD[0,1]_DO_SCK
|
||||
// <0x1=>PAD[2,3]_DO_SCK
|
||||
// <0x2=>PAD[3,1]_DO_SCK
|
||||
// <0x3=>PAD[0,3]_DO_SCK
|
||||
// <id> spi_master_txpo
|
||||
#ifndef CONF_SERCOM_4_SPI_TXPO
|
||||
#define CONF_SERCOM_4_SPI_TXPO 0
|
||||
#endif
|
||||
|
||||
// Calculate baud register value from requested baudrate value
|
||||
#ifndef CONF_SERCOM_4_SPI_BAUD_RATE
|
||||
#define CONF_SERCOM_4_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM4_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_4_SPI_BAUD)) - 1
|
||||
#endif
|
||||
|
||||
// Enable configuration of module
|
||||
#ifndef CONF_SERCOM_6_SPI_ENABLE
|
||||
#define CONF_SERCOM_6_SPI_ENABLE 1
|
||||
#endif
|
||||
|
||||
// Set module in SPI Slave mode
|
||||
#ifndef CONF_SERCOM_6_SPI_MODE
|
||||
#define CONF_SERCOM_6_SPI_MODE 0x02
|
||||
#endif
|
||||
|
||||
// <h> Basic Configuration
|
||||
|
||||
// <q> Receive buffer enable
|
||||
// <i> Enable receive buffer to receive data from slave. (RXEN)
|
||||
// <id> spi_slave_rx_enable
|
||||
#ifndef CONF_SERCOM_6_SPI_RXEN
|
||||
#define CONF_SERCOM_6_SPI_RXEN 0x1
|
||||
#endif
|
||||
|
||||
// <o> Character Size
|
||||
// <i> Bit size for all characters sent over the SPI bus. (CHSIZE)
|
||||
// <0x0=>8 bits
|
||||
// <0x1=>9 bits
|
||||
// <id> spi_slave_character_size
|
||||
#ifndef CONF_SERCOM_6_SPI_CHSIZE
|
||||
#define CONF_SERCOM_6_SPI_CHSIZE 0x0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced Configuration
|
||||
// <id> spi_slave_advanced
|
||||
#ifndef CONF_SERCOM_6_SPI_ADVANCED
|
||||
#define CONF_SERCOM_6_SPI_ADVANCED 1
|
||||
#endif
|
||||
|
||||
// <o> Data Order
|
||||
// <0=>MSB first
|
||||
// <1=>LSB first
|
||||
// <i> I least significant or most significant bit is shifted out first. (DORD)
|
||||
// <id> spi_slave_arch_dord
|
||||
#ifndef CONF_SERCOM_6_SPI_DORD
|
||||
#define CONF_SERCOM_6_SPI_DORD 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Polarity
|
||||
// <0=>SCK is low when idle
|
||||
// <1=>SCK is high when idle
|
||||
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
|
||||
// <id> spi_slave_arch_cpol
|
||||
#ifndef CONF_SERCOM_6_SPI_CPOL
|
||||
#define CONF_SERCOM_6_SPI_CPOL 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Phase
|
||||
// <0x0=>Sample input on leading edge
|
||||
// <0x1=>Sample input on trailing edge
|
||||
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
|
||||
// <id> spi_slave_arch_cpha
|
||||
#ifndef CONF_SERCOM_6_SPI_CPHA
|
||||
#define CONF_SERCOM_6_SPI_CPHA 0x0
|
||||
#endif
|
||||
|
||||
// <o> Immediate Buffer Overflow Notification
|
||||
// <i> Controls when OVF is asserted. (IBON)
|
||||
// <0x0=>In data stream
|
||||
// <0x1=>On buffer overflow
|
||||
// <id> spi_slave_arch_ibon
|
||||
#ifndef CONF_SERCOM_6_SPI_IBON
|
||||
#define CONF_SERCOM_6_SPI_IBON 0x0
|
||||
#endif
|
||||
|
||||
// <q> Slave Select Low Detect Enable
|
||||
// <i> This bit enables wake up when the slave select (_SS) pin transitions from high to low. (SSDE)
|
||||
// <id> spi_slave_arch_ssde
|
||||
#ifndef CONF_SERCOM_6_SPI_SSDE
|
||||
#define CONF_SERCOM_6_SPI_SSDE 0
|
||||
#endif
|
||||
|
||||
// <q> Slave Detect Preload Enable
|
||||
// <i> Setting this bit will enable preloading of the slave shift register when there is no transfer in progress. (PLOADEN)
|
||||
// <id> spi_slave_arch_ploaden
|
||||
#ifndef CONF_SERCOM_6_SPI_PLOADEN
|
||||
#define CONF_SERCOM_6_SPI_PLOADEN 0
|
||||
#endif
|
||||
|
||||
// <q> Enable SPI address mode
|
||||
// <i> This will enable SPI frames with address, first received character is treated as address. (FORM=SPI_ADDR)
|
||||
// <id> spi_slave_arch_amode_en
|
||||
#ifndef CONF_SERCOM_6_SPI_AMODE_EN
|
||||
#define CONF_SERCOM_6_SPI_AMODE_EN 0
|
||||
#endif
|
||||
|
||||
// <o> Address Mode
|
||||
// <0x0=>Address mask
|
||||
// <0x1=>Two unique addresses
|
||||
// <0x2=>Address range
|
||||
// <i> These bits set the slave addressing mode when the frame format with address is used. (AMODE)
|
||||
// <id> spi_slave_arch_amode
|
||||
#ifndef CONF_SERCOM_6_SPI_AMODE
|
||||
#define CONF_SERCOM_6_SPI_AMODE 0
|
||||
#endif
|
||||
|
||||
// <o> Address <0-255>
|
||||
// <i> These bits hold the address when SPI address modes is enabled. (ADDR)
|
||||
// <id> spi_slave_arch_addr
|
||||
#ifndef CONF_SERCOM_6_SPI_ADDR
|
||||
#define CONF_SERCOM_6_SPI_ADDR 0
|
||||
#endif
|
||||
|
||||
// <o> Address mask <0-255>
|
||||
// <i> These bits hold the address mask when SPI address mode is enabled. (ADDRMASK)
|
||||
// <id> spi_slave_arch_addrmask
|
||||
#ifndef CONF_SERCOM_6_SPI_ADDRMASK
|
||||
#define CONF_SERCOM_6_SPI_ADDRMASK 0
|
||||
#endif
|
||||
|
||||
// <q> Run in stand-by
|
||||
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
|
||||
// <id> spi_slave_arch_runstdby
|
||||
#ifndef CONF_SERCOM_6_SPI_RUNSTDBY
|
||||
#define CONF_SERCOM_6_SPI_RUNSTDBY 0x0
|
||||
#endif
|
||||
|
||||
// <o> Debug Stop Mode
|
||||
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
|
||||
// <0=>Keep running
|
||||
// <1=>Halt
|
||||
// <id> spi_slave_arch_dbgstop
|
||||
#ifndef CONF_SERCOM_6_SPI_DBGSTOP
|
||||
#define CONF_SERCOM_6_SPI_DBGSTOP 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// This bit is not applicable in slave mode
|
||||
#ifndef CONF_SERCOM_6_SPI_MSSEN
|
||||
#define CONF_SERCOM_6_SPI_MSSEN 0x0
|
||||
#endif
|
||||
|
||||
// <o> Receive Data Pinout
|
||||
// <0x0=>PAD[0]
|
||||
// <0x1=>PAD[1]
|
||||
// <0x2=>PAD[2]
|
||||
// <0x3=>PAD[3]
|
||||
// <id> spi_slave_rxpo
|
||||
#ifndef CONF_SERCOM_6_SPI_RXPO
|
||||
#define CONF_SERCOM_6_SPI_RXPO 0
|
||||
#endif
|
||||
|
||||
// <o> Transmit Data Pinout
|
||||
// <0x0=>PAD[0,1]_DO_SCK
|
||||
// <0x1=>PAD[2,3]_DO_SCK
|
||||
// <0x2=>PAD[3,1]_DO_SCK
|
||||
// <0x3=>PAD[0,3]_DO_SCK
|
||||
// <id> spi_slave_txpo
|
||||
#ifndef CONF_SERCOM_6_SPI_TXPO
|
||||
#define CONF_SERCOM_6_SPI_TXPO 2
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_6_SPI_BAUD_RATE
|
||||
#define CONF_SERCOM_6_SPI_BAUD_RATE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_6_SPI_DUMMYBYTE
|
||||
#define CONF_SERCOM_6_SPI_DUMMYBYTE 0x0
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_SERCOM_CONFIG_H
|
||||
@@ -0,0 +1,257 @@
|
||||
/* Auto-generated config file peripheral_clk_config.h */
|
||||
#ifndef PERIPHERAL_CLK_CONFIG_H
|
||||
#define PERIPHERAL_CLK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
/**
|
||||
* \def CONF_CPU_FREQUENCY
|
||||
* \brief CPU's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_CPU_FREQUENCY
|
||||
#define CONF_CPU_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
// <y> Core Clock Source
|
||||
// <id> core_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for CORE.
|
||||
#ifndef CONF_GCLK_SERCOM2_CORE_SRC
|
||||
#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> Slow Clock Source
|
||||
// <id> slow_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the slow clock source.
|
||||
#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
|
||||
#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
|
||||
* \brief SERCOM2's Core Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
|
||||
* \brief SERCOM2's Slow Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
|
||||
#endif
|
||||
|
||||
// <y> Core Clock Source
|
||||
// <id> core_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for CORE.
|
||||
#ifndef CONF_GCLK_SERCOM4_CORE_SRC
|
||||
#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> Slow Clock Source
|
||||
// <id> slow_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the slow clock source.
|
||||
#ifndef CONF_GCLK_SERCOM4_SLOW_SRC
|
||||
#define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM4_CORE_FREQUENCY
|
||||
* \brief SERCOM4's Core Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM4_SLOW_FREQUENCY
|
||||
* \brief SERCOM4's Slow Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM4_SLOW_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 32768
|
||||
#endif
|
||||
|
||||
// <y> Core Clock Source
|
||||
// <id> core_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for CORE.
|
||||
#ifndef CONF_GCLK_SERCOM6_CORE_SRC
|
||||
#define CONF_GCLK_SERCOM6_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> Slow Clock Source
|
||||
// <id> slow_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the slow clock source.
|
||||
#ifndef CONF_GCLK_SERCOM6_SLOW_SRC
|
||||
#define CONF_GCLK_SERCOM6_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM6_CORE_FREQUENCY
|
||||
* \brief SERCOM6's Core Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM6_CORE_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM6_SLOW_FREQUENCY
|
||||
* \brief SERCOM6's Slow Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM6_SLOW_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM6_SLOW_FREQUENCY 32768
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // PERIPHERAL_CLK_CONFIG_H
|
||||
@@ -0,0 +1,47 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Application implement
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef SPI_SLAVE_DMA_CONFIG_H
|
||||
#define SPI_SLAVE_DMA_CONFIG_H
|
||||
|
||||
// <o> Delay in Micro Seconds <1-1000>
|
||||
// <i> Delay in microseconds to hold CS low after data transfer completion by DMA
|
||||
// <id> delay_in_us_cs_low
|
||||
#ifndef CONF_DELAY_US
|
||||
#define CONF_DELAY_US 20
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,9 @@
|
||||
/* Auto-generated config file stdio_redirect_config.h */
|
||||
#ifndef STDIO_REDIRECT_CONFIG_H
|
||||
#define STDIO_REDIRECT_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // STDIO_REDIRECT_CONFIG_H
|
||||
Reference in New Issue
Block a user