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This commit is contained in:
Nicolas Trimborn
2021-07-13 12:25:44 +02:00
parent a74d1a099d
commit 5b57fb9584
666 changed files with 599088 additions and 42 deletions
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120
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/hal/include/hal_atomic.h Normal file
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/**
* \file
*
* \brief Critical sections related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_ATOMIC_H_INCLUDED
#define _HAL_ATOMIC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_atomic
*
*@{
*/
/**
* \brief Type for the register holding global interrupt enable flag
*/
typedef uint32_t hal_atomic_t;
/**
* \brief Helper macro for entering critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_enterCritical() function to enter critical
* sections. No semicolon is required after the macro.
*
* \section atomic_usage Usage Example
* \code
* CRITICAL_SECTION_ENTER()
* Critical code
* CRITICAL_SECTION_LEAVE()
* \endcode
*/
#define CRITICAL_SECTION_ENTER() \
{ \
volatile hal_atomic_t __atomic; \
atomic_enter_critical(&__atomic);
/**
* \brief Helper macro for leaving critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_leaveCritical() function to leave critical
* sections. No semicolon is required after the macro.
*/
#define CRITICAL_SECTION_LEAVE() \
atomic_leave_critical(&__atomic); \
}
/**
* \brief Disable interrupts, enter critical section
*
* Disables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[out] atomic The pointer to a variable to store the value of global
* interrupt enable flag
*/
void atomic_enter_critical(hal_atomic_t volatile *atomic);
/**
* \brief Exit atomic section
*
* Enables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[in] atomic The pointer to a variable, which stores the latest stored
* value of the global interrupt enable flag
*/
void atomic_leave_critical(hal_atomic_t volatile *atomic);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t atomic_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_ATOMIC_H_INCLUDED */

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Examples/SPISLAVEDMA/SPISLAVEDMA(3)/hal/include/hal_cache.h Normal file
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/**
* \file
*
* \brief HAL cache functionality implementation.
*
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef HAL_CACHE_H_
#define HAL_CACHE_H_
#include <hpl_cmcc.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Enable cache module
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_enable(const void *hw);
/**
* \brief Disable cache module
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_disable(const void *hw);
/**
* \brief Initialize cache module
*
* This function initialize cache module configuration.
*
* \return status of operation
*/
int32_t cache_init(void);
/**
* \brief Configure cache module
*
* \param[in] pointer pointing to the starting address of cache module
* \param[in] cache configuration structure pointer
*
* \return status of operation
*/
int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
/**
* \brief Invalidate entire cache entries
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_invalidate_all(const void *hw);
#ifdef __cplusplus
}
#endif
#endif /* HAL_CACHE_H_ */

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Examples/SPISLAVEDMA/SPISLAVEDMA(3)/hal/include/hal_delay.h Normal file
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/**
* \file
*
* \brief HAL delay related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_irq.h>
#include <hpl_reset.h>
#include <hpl_sleep.h>
#ifndef _HAL_DELAY_H_INCLUDED
#define _HAL_DELAY_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_delay Delay Driver
*
*@{
*/
/**
* \brief Initialize Delay driver
*
* \param[in] hw The pointer to hardware instance
*/
void delay_init(void *const hw);
/**
* \brief Perform delay in us
*
* This function performs delay for the given amount of microseconds.
*
* \param[in] us The amount delay in us
*/
void delay_us(const uint16_t us);
/**
* \brief Perform delay in ms
*
* This function performs delay for the given amount of milliseconds.
*
* \param[in] ms The amount delay in ms
*/
void delay_ms(const uint16_t ms);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t delay_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_DELAY_H_INCLUDED */

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Examples/SPISLAVEDMA/SPISLAVEDMA(3)/hal/include/hal_gpio.h Normal file
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/**
* \file
*
* \brief Port
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*/
#ifndef _HAL_GPIO_INCLUDED_
#define _HAL_GPIO_INCLUDED_
#include <hpl_gpio.h>
#include <utils_assert.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Set gpio pull mode
*
* Set pin pull mode, non existing pull modes throws an fatal assert
*
* \param[in] pin The pin number for device
* \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor
* GPIO_PULL_UP = Pull pin high with internal resistor
* GPIO_PULL_OFF = Disable pin pull mode
*/
static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode)
{
_gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode);
}
/**
* \brief Set pin function
*
* Select which function a pin will be used for
*
* \param[in] pin The pin number for device
* \param[in] function The pin function is given by a 32-bit wide bitfield
* found in the header files for the device
*
*/
static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function)
{
_gpio_set_pin_function(pin, function);
}
/**
* \brief Set port data direction
*
* Select if the pin data direction is input, output or disabled.
* If disabled state is not possible, this function throws an assert.
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to the
* corresponding pin
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
* GPIO_DIRECTION_OUT = Data direction out
* GPIO_DIRECTION_OFF = Disables the pin
* (low power state)
*/
static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask,
const enum gpio_direction direction)
{
_gpio_set_direction(port, mask, direction);
}
/**
* \brief Set gpio data direction
*
* Select if the pin data direction is input, output or disabled.
* If disabled state is not possible, this function throws an assert.
*
* \param[in] pin The pin number for device
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
* GPIO_DIRECTION_OUT = Data direction out
* GPIO_DIRECTION_OFF = Disables the pin
* (low power state)
*/
static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
{
_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
}
/**
* \brief Set port level
*
* Sets output level on the pins defined by the bit mask
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply port level to the corresponding
* pin
* \param[in] level true = Pin levels set to "high" state
* false = Pin levels set to "low" state
*/
static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level)
{
_gpio_set_level(port, mask, level);
}
/**
* \brief Set gpio level
*
* Sets output level on a pin
*
* \param[in] pin The pin number for device
* \param[in] level true = Pin level set to "high" state
* false = Pin level set to "low" state
*/
static inline void gpio_set_pin_level(const uint8_t pin, const bool level)
{
_gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level);
}
/**
* \brief Toggle out level on pins
*
* Toggle the pin levels on pins defined by bit mask
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means toggle pin level to the corresponding
* pin
*/
static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask)
{
_gpio_toggle_level(port, mask);
}
/**
* \brief Toggle output level on pin
*
* Toggle the pin levels on pins defined by bit mask
*
* \param[in] pin The pin number for device
*/
static inline void gpio_toggle_pin_level(const uint8_t pin)
{
_gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin));
}
/**
* \brief Get input level on pins
*
* Read the input level on pins connected to a port
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
*/
static inline uint32_t gpio_get_port_level(const enum gpio_port port)
{
return _gpio_get_level(port);
}
/**
* \brief Get level on pin
*
* Reads the level on pins connected to a port
*
* \param[in] pin The pin number for device
*/
static inline bool gpio_get_pin_level(const uint8_t pin)
{
return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin)));
}
/**
* \brief Get current driver version
*/
uint32_t gpio_get_version(void);
#ifdef __cplusplus
}
#endif
#endif

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/**
* \file
*
* \brief HAL initialization related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_INIT_H_INCLUDED
#define _HAL_INIT_H_INCLUDED
#include <hpl_init.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_init Init Driver
*
*@{
*/
/**
* \brief Initialize the hardware abstraction layer
*
* This function calls the various initialization functions.
* Currently the following initialization functions are supported:
* - System clock initialization
*/
static inline void init_mcu(void)
{
_init_chip();
}
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t init_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_INIT_H_INCLUDED */

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Examples/SPISLAVEDMA/SPISLAVEDMA(3)/hal/include/hal_io.h Normal file
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/**
* \file
*
* \brief I/O related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_IO_INCLUDED
#define _HAL_IO_INCLUDED
/**
* \addtogroup doc_driver_hal_helper_io I/O Driver
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief I/O descriptor
*
* The I/O descriptor forward declaration.
*/
struct io_descriptor;
/**
* \brief I/O write function pointer type
*/
typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
/**
* \brief I/O read function pointer type
*/
typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
/**
* \brief I/O descriptor
*/
struct io_descriptor {
io_write_t write; /*! The write function pointer. */
io_read_t read; /*! The read function pointer. */
};
/**
* \brief I/O write interface
*
* This function writes up to \p length of bytes to a given I/O descriptor.
* It returns the number of bytes actually write.
*
* \param[in] descr An I/O descriptor to write
* \param[in] buf The buffer pointer to story the write data
* \param[in] length The number of bytes to write
*
* \return The number of bytes written
*/
int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
/**
* \brief I/O read interface
*
* This function reads up to \p length bytes from a given I/O descriptor, and
* stores it in the buffer pointed to by \p buf. It returns the number of bytes
* actually read.
*
* \param[in] descr An I/O descriptor to read
* \param[in] buf The buffer pointer to story the read data
* \param[in] length The number of bytes to read
*
* \return The number of bytes actually read. This number can be less than the
* requested length. E.g., in a driver that uses ring buffer for
* reception, it may depend on the availability of data in the
* ring buffer.
*/
int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HAL_IO_INCLUDED */

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/**
* \file
*
* \brief Sleep related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SLEEP_H_INCLUDED
#define _HAL_SLEEP_H_INCLUDED
#include <hpl_sleep.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_sleep
*
*@{
*/
/**
* \brief Set the sleep mode of the device and put the MCU to sleep
*
* For an overview of which systems are disabled in sleep for the different
* sleep modes, see the data sheet.
*
* \param[in] mode Sleep mode to use
*
* \return The status of a sleep request
* \retval -1 The requested sleep mode was invalid or not available
* \retval 0 The operation completed successfully, returned after leaving the
* sleep
*/
int sleep(const uint8_t mode);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t sleep_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_SLEEP_H_INCLUDED */

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/**
* \file
*
* \brief SPI DMA related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SPI_M_DMA_H_INCLUDED
#define _HAL_SPI_M_DMA_H_INCLUDED
#include <hal_io.h>
#include <hpl_spi_m_dma.h>
/**
* \addtogroup doc_driver_hal_spi_master_dma
*
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/* Forward declaration of spi_descriptor. */
struct spi_m_dma_descriptor;
/** The callback types */
enum spi_m_dma_cb_type {
/** Callback type for DMA transfer buffer done */
SPI_M_DMA_CB_TX_DONE,
/** Callback type for DMA receive buffer done */
SPI_M_DMA_CB_RX_DONE,
/** Callback type for DMA errors */
SPI_M_DMA_CB_ERROR,
SPI_M_DMA_CB_N
};
/**
* \brief SPI Master DMA callback type
*/
typedef void (*spi_m_dma_cb_t)(struct _dma_resource *resource);
/** \brief SPI HAL driver struct for DMA access
*/
struct spi_m_dma_descriptor {
struct _spi_m_dma_hpl_interface *func;
/** Pointer to SPI device instance */
struct _spi_m_dma_dev dev;
/** I/O read/write */
struct io_descriptor io;
/** DMA resource */
struct _dma_resource *resource;
};
/** \brief Set the SPI HAL instance function pointer for HPL APIs.
*
* Set SPI HAL instance function pointer for HPL APIs.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] func Pointer to the HPL api structure.
*
*/
void spi_m_dma_set_func_ptr(struct spi_m_dma_descriptor *spi, void *const func);
/** \brief Initialize the SPI HAL instance and hardware for DMA mode
*
* Initialize SPI HAL with dma mode.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] hw Pointer to the hardware base.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_INVALID_DATA Error, initialized.
*/
int32_t spi_m_dma_init(struct spi_m_dma_descriptor *spi, void *const hw);
/** \brief Deinitialize the SPI HAL instance
*
* Abort transfer, disable and reset SPI, de-init software.
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_dma_deinit(struct spi_m_dma_descriptor *spi);
/** \brief Enable SPI
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_dma_enable(struct spi_m_dma_descriptor *spi);
/** \brief Disable SPI
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_dma_disable(struct spi_m_dma_descriptor *spi);
/** \brief Set SPI baudrate
*
* Works if SPI is initialized as master.
* In the function a sanity check is used to confirm it's called in the correct mode.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] baud_val The target baudrate value
* (See "baudrate calculation" for calculating the value).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy.
*
* note: This api should be used to write the baudrate register with the given baud_val
* paramter, the user has to calculate the baud_val for required baud rate and pass it as
* argument(baud_val) to this api
*/
int32_t spi_m_dma_set_baudrate(struct spi_m_dma_descriptor *spi, const uint32_t baud_val);
/** \brief Set SPI mode
*
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase:
* - Mode 0: leading edge is rising edge, data sample on leading edge.
* - Mode 1: leading edge is rising edge, data sample on trailing edge.
* - Mode 2: leading edge is falling edge, data sample on leading edge.
* - Mode 3: leading edge is falling edge, data sample on trailing edge.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] mode The mode (\ref spi_transfer_mode).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy, CS activated.
*/
int32_t spi_m_dma_set_mode(struct spi_m_dma_descriptor *spi, const enum spi_transfer_mode mode);
/** \brief Set the SPI transfer character size in number of bits
*
* The character size (\ref spi_char_size) influence the way the data is
* sent/received.
* For char size <= 8-bit, data is stored byte by byte.
* For char size between 9-bit ~ 16-bit, data is stored in 2-byte length.
* Note that the default and recommended char size is 8-bit since it's
* supported by all system.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] char_size The char size (\ref spi_char_size).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy, CS activated.
* \retval ERR_INVALID_ARG The char size is not supported.
*/
int32_t spi_m_dma_set_char_size(struct spi_m_dma_descriptor *spi, const enum spi_char_size char_size);
/** \brief Set SPI transfer data order
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] dord The data order: send LSB/MSB first.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy, CS activated.
* \retval ERR_INVALID The data order is not supported.
*/
int32_t spi_m_dma_set_data_order(struct spi_m_dma_descriptor *spi, const enum spi_data_order dord);
/** \brief Perform the SPI data transfer (TX and RX) with the DMA
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] txbuf Pointer to the transfer information.
* \param[out] rxbuf Pointer to the receiver information.
* \param[in] length SPI transfer data length.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy.
*/
int32_t spi_m_dma_transfer(struct spi_m_dma_descriptor *spi, uint8_t const *txbuf, uint8_t *const rxbuf,
const uint16_t length);
/** \brief Register a function as an SPI transfer completion callback
*
* Register a callback function specified by its \c type.
* - SPI_CB_COMPLETE: set the function that will be called on the SPI transfer
* completion including deactivating the CS.
* - SPI_CB_XFER: set the function that will be called on the SPI buffer transfer
* completion.
* Register a NULL function to not use the callback.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] type Callback type (\ref spi_m_dma_cb_type).
* \param[in] func Pointer to callback function.
*/
void spi_m_dma_register_callback(struct spi_m_dma_descriptor *spi, const enum spi_m_dma_cb_type type,
spi_m_dma_cb_t func);
/**
* \brief Return I/O descriptor for this SPI instance
*
* This function will return an I/O instance for this SPI driver instance
*
* \param[in] spi An SPI master descriptor, which is used to communicate through
* SPI
* \param[in, out] io A pointer to an I/O descriptor pointer type
*
* \retval ERR_NONE
*/
int32_t spi_m_dma_get_io_descriptor(struct spi_m_dma_descriptor *const spi, struct io_descriptor **io);
/** \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t spi_m_dma_get_version(void);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HAL_SPI_M_DMA_H_INCLUDED */

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/**
* \file
*
* \brief SPI Slave functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SPI_S_SYNC_H_INCLUDED
#define _HAL_SPI_S_SYNC_H_INCLUDED
#include "hpl_spi_s_sync.h"
#include "utils.h"
#include "hal_io.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_spi_slave_sync
*
* @{
*/
/** \brief SPI Slave HAL driver struct for synchronous access
*/
struct spi_s_sync_descriptor {
struct _spi_s_sync_hpl_interface *func;
/** SPI device instance */
struct _spi_sync_dev dev;
/** I/O read/write */
struct io_descriptor io;
/** Break on SS desert detection. */
uint8_t break_on_ss_det;
};
/** \brief Set the SPI HAL instance function pointer for HPL APIs.
*
* Set SPI HAL instance function pointer for HPL APIs.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] func Pointer to the HPL api structure.
*
*/
void spi_s_sync_set_func_ptr(struct spi_s_sync_descriptor *spi, void *const func);
/** \brief Initialize the SPI Slave HAL instance and hardware
*
* Initialize SPI Slave HAL with polling mode.
*
* \param[in, out] spi Pointer to the SPI Slave HAL instance.
* \param[in] hw Pointer to the hardware base.
*
* \return Operation status.
* \retval 0 Success.
* \retval <0 Error.
*/
int32_t spi_s_sync_init(struct spi_s_sync_descriptor *spi, void *const hw);
/** \brief Deinitialize the SPI HAL instance
*
* Disable and reset SPI, de-init software.
*
* \param[in,out] spi Pointer to the SPI Slave HAL instance.
*/
void spi_s_sync_deinit(struct spi_s_sync_descriptor *spi);
/** \brief Enable SPI
*
* \param[in,out] spi Pointer to the SPI Slave HAL instance.
*/
void spi_s_sync_enable(struct spi_s_sync_descriptor *spi);
/** \brief Disable SPI
*
* \param[in,out] spi Pointer to the SPI Slave HAL instance.
*/
void spi_s_sync_disable(struct spi_s_sync_descriptor *spi);
/** \brief Set SPI mode
*
* Set the SPI transfer mode (\ref spi_transfer_mode_t),
* which controls the clock polarity and clock phase:
* - Mode 0: leading edge is rising edge, data sample on leading edge.
* - Mode 1: leading edge is rising edge, data sample on trailing edge.
* - Mode 2: leading edge is falling edge, data sample on leading edge.
* - Mode 3: leading edge is falling edge, data sample on trailing edge.
* Note that SPI must be disabled to change mode.
*
* \param[in,out] spi Pointer to the HAL SPI instance.
* \param[in] mode The mode (\ref spi_transfer_mode_t).
*
* \return Operation status.
* \retval 0 Success.
* \retval <0 Error.
*/
int32_t spi_s_sync_set_mode(struct spi_s_sync_descriptor *spi, const enum spi_transfer_mode mode);
/** \brief Set SPI transfer character size in number of bits
*
* The character size (\ref spi_char_size_t) influence the way the data is
* sent/received.
* For char size <= 8-bit, data is stored byte by byte.
* For char size between 9-bit ~ 16-bit, data is stored in 2-byte length.
* Note that the default and recommended char size is 8-bit since it's
* supported by all system.
* Note that the SPI must be disabled to change character size. Also it affects
* buffer accessing, the ring buffer should be flushed before changing it to
* avoid conflicts.
*
* \param[in,out] spi Pointer to the HAL SPI instance.
* \param[in] char_size The char size (~32, recommended 8).
*
* \return Operation status.
* \retval 0 Success.
* \retval <0 Error.
*/
int32_t spi_s_sync_set_char_size(struct spi_s_sync_descriptor *spi, const enum spi_char_size char_size);
/** \brief Set SPI transfer data order
*
* Note that the SPI must be disabled to change data order.
*
* \param[in,out] spi Pointer to the HAL SPI instance.
* \param[in] dord The data order: send LSB/MSB first.
*
* \return Operation status.
* \retval 0 Success.
* \retval <0 Error.
*/
int32_t spi_s_sync_set_data_order(struct spi_s_sync_descriptor *spi, const enum spi_data_order dord);
/** \brief Enable/disable break on SS desert detection
*
* \param[in,out] spi Pointer to the HAL SPI instance.
* \param[in] enable Set to \c true to break R/W loop on SS desert.
*/
void spi_s_sync_break_on_ss_detect(struct spi_s_sync_descriptor *spi, const bool enable);
/** \brief Write/read at the same time
*
* \param[in,out] spi Pointer to the HAL SPI instance.
* \param[in] xfer Pointer to the transfer information (\ref spi_xfer).
*
* \return Operation result.
* \retval <0 Error.
* \retval >=0 Number of characters transferred.
*/
int32_t spi_s_sync_transfer(struct spi_s_sync_descriptor *spi, const struct spi_xfer *xfer);
/**
* \brief Return I/O descriptor for this SPI instance
*
* This function will return an I/O instance for this SPI driver instance
*
* \param[in] spi An SPI slave descriptor, which is used to communicate through
* SPI
* \param[in] io A pointer to an I/O descriptor pointer type
*
* \return Error code.
* \retval 0 No error detected
* \retval <0 Error code
*/
int32_t spi_s_sync_get_io_descriptor(struct spi_s_sync_descriptor *spi, struct io_descriptor **io);
/** \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t spi_s_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_SPI_S_SYNC_H_INCLUDED */

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/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SYNC_USART_H_INCLUDED
#define _HAL_SYNC_USART_H_INCLUDED
#include "hal_io.h"
#include <hpl_usart_sync.h>
/**
* \addtogroup doc_driver_hal_usart_sync
*
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Synchronous USART descriptor
*/
struct usart_sync_descriptor {
struct io_descriptor io;
struct _usart_sync_device device;
};
/**
* \brief Initialize USART interface
*
* This function initializes the given I/O descriptor to be used
* as USART interface descriptor.
* It checks if the given hardware is not initialized and
* if the given hardware is permitted to be initialized.
*
* \param[out] descr A USART descriptor which is used to communicate via USART
* \param[in] hw The pointer to hardware instance
* \param[in] func The pointer to as set of functions pointers
*
* \return Initialization status.
*/
int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func);
/**
* \brief Deinitialize USART interface
*
* This function deinitializes the given I/O descriptor.
* It checks if the given hardware is initialized and
* if the given hardware is permitted to be deinitialized.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return De-initialization status.
*/
int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr);
/**
* \brief Enable USART interface
*
* Enables the USART interface
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return Enabling status.
*/
int32_t usart_sync_enable(struct usart_sync_descriptor *const descr);
/**
* \brief Disable USART interface
*
* Disables the USART interface
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return Disabling status.
*/
int32_t usart_sync_disable(struct usart_sync_descriptor *const descr);
/**
* \brief Retrieve I/O descriptor
*
* This function retrieves the I/O descriptor of the given USART descriptor.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] io An I/O descriptor to retrieve
*
* \return The status of the I/O descriptor retrieving.
*/
int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io);
/**
* \brief Specify action for flow control pins
*
* This function sets the action (or state) for the flow control pins
* if the flow control is enabled.
* It sets the state of flow control pins only if the automatic support of
* the flow control is not supported by the hardware.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] state A state to set the flow control pins
*
* \return The status of flow control action setup.
*/
int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr,
const union usart_flow_control_state state);
/**
* \brief Set USART baud rate
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] baud_rate A baud rate to set
*
* \return The status of baud rate setting.
*/
int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate);
/**
* \brief Set USART data order
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] data_order A data order to set
*
* \return The status of data order setting.
*/
int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order);
/**
* \brief Set USART mode
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] mode A mode to set
*
* \return The status of mode setting.
*/
int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode);
/**
* \brief Set USART parity
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] parity A parity to set
*
* \return The status of parity setting.
*/
int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity);
/**
* \brief Set USART stop bits
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] stop_bits Stop bits to set
*
* \return The status of stop bits setting.
*/
int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits);
/**
* \brief Set USART character size
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] size A character size to set
*
* \return The status of character size setting.
*/
int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size);
/**
* \brief Retrieve the state of flow control pins
*
* This function retrieves the of flow control pins
* if the flow control is enabled.
* Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case
* if the flow control is done by the hardware
* and the pins state cannot be read out.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] state The state of flow control pins
*
* \return The status of flow control state reading.
*/
int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr,
union usart_flow_control_state *const state);
/**
* \brief Check if the USART transmitter is empty
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return The status of USART TX empty checking.
* \retval 0 The USART transmitter is not empty
* \retval 1 The USART transmitter is empty
*/
int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr);
/**
* \brief Check if the USART receiver is not empty
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return The status of USART RX empty checking.
* \retval 1 The USART receiver is not empty
* \retval 0 The USART receiver is empty
*/
int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t usart_sync_get_version(void);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HAL_SYNC_USART_H_INCLUDED */

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/**
* \file
*
* \brief Generic CMCC(Cortex M Cache Controller) related functionality.
*
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef HPL_CMCC_H_
#define HPL_CMCC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
/**
* \Cache driver MACROS
*/
#define CMCC_DISABLE 0U
#define CMCC_ENABLE 1U
#define IS_CMCC_DISABLED 0U
#define IS_CMCC_ENABLED 1U
#define CMCC_WAY_NOS 4U
#define CMCC_LINE_NOS 64U
#define CMCC_MONITOR_DISABLE 0U
/**
* \brief Cache size configurations
*/
enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB };
/**
* \brief Way Numbers
*/
enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 };
/**
* \brief Cache monitor configurations
*/
enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT };
/**
* \brief Cache configuration structure
*/
struct _cache_cfg {
enum conf_cache_size cache_size;
bool data_cache_disable;
bool inst_cache_disable;
bool gclk_gate_disable;
};
/**
* \brief Cache enable status
*/
static inline bool _is_cache_enabled(const void *hw)
{
return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false);
}
/**
* \brief Cache disable status
*/
static inline bool _is_cache_disabled(const void *hw)
{
return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false);
}
/**
* \brief Cache enable
*/
static inline int32_t _cmcc_enable(const void *hw)
{
int32_t return_value;
if (_is_cache_disabled(hw)) {
hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN);
return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE;
} else {
return_value = ERR_NO_CHANGE;
}
return return_value;
}
/**
* \brief Cache disable
*/
static inline int32_t _cmcc_disable(const void *hw)
{
hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos));
while (!(_is_cache_disabled(hw)))
;
return ERR_NONE;
}
/**
* \brief Initialize Cache Module
*
* This function initialize low level cmcc module configuration.
*
* \return initialize status
*/
int32_t _cmcc_init(void);
/**
* \brief Configure CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] cache configuration structure pointer
*
* \return status of operation
*/
int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl);
/**
* \brief Enable data cache in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache
*
* \return status of operation
*/
int32_t _cmcc_enable_data_cache(const void *hw, bool value);
/**
* \brief Enable instruction cache in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache
*
* \return status of operation
*/
int32_t _cmcc_enable_inst_cache(const void *hw, bool value);
/**
* \brief Enable clock gating in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate
*
* \return status of operation
*/
int32_t _cmcc_enable_clock_gating(const void *hw, bool value);
/**
* \brief Configure the cache size in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from cache size configuration enumerator
* 0->1K, 1->2K, 2->4K(default)
*
* \return status of operation
*/
int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size);
/**
* \brief Lock the mentioned WAY in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num_index" enumerator
*
* \return status of operation
*/
int32_t _cmcc_lock_way(const void *hw, enum way_num_index);
/**
* \brief Unlock the mentioned WAY in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num_index" enumerator
*
* \return status of operation
*/
int32_t _cmcc_unlock_way(const void *hw, enum way_num_index);
/**
* \brief Invalidate the mentioned cache line in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num" enumerator (valid arg is 0-3)
* \param[in] line number (valid arg is 0-63 as each way will have 64 lines)
*
* \return status of operation
*/
int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num);
/**
* \brief Invalidate entire cache entries in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_invalidate_all(const void *hw);
/**
* \brief Configure cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from cache monitor configurations enumerator
*
* \return status of operation
*/
int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg);
/**
* \brief Enable cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_enable_monitor(const void *hw);
/**
* \brief Disable cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_disable_monitor(const void *hw);
/**
* \brief Reset cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_reset_monitor(const void *hw);
/**
* \brief Get cache monitor event counter value from CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return event counter value
*/
uint32_t _cmcc_get_monitor_event_count(const void *hw);
#ifdef __cplusplus
}
#endif
#endif /* HPL_CMCC_H_ */

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/**
* \file
*
* \brief CPU core related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_CORE_H_INCLUDED
#define _HPL_CORE_H_INCLUDED
/**
* \addtogroup HPL Core
*
* \section hpl_core_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "hpl_core_port.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_CORE_H_INCLUDED */

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/**
* \file
*
* \brief Delay related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_DELAY_H_INCLUDED
#define _HPL_DELAY_H_INCLUDED
/**
* \addtogroup HPL Delay
*
* \section hpl_delay_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifndef _UNIT_TEST_
#include <compiler.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize delay functionality
*
* \param[in] hw The pointer to hardware instance
*/
void _delay_init(void *const hw);
/**
* \brief Retrieve the amount of cycles to delay for the given amount of us
*
* \param[in] us The amount of us to delay for
*
* \return The amount of cycles
*/
uint32_t _get_cycles_for_us(const uint16_t us);
/**
* \brief Retrieve the amount of cycles to delay for the given amount of ms
*
* \param[in] ms The amount of ms to delay for
*
* \return The amount of cycles
*/
uint32_t _get_cycles_for_ms(const uint16_t ms);
/**
* \brief Delay loop to delay n number of cycles
*
* \param[in] hw The pointer to hardware instance
* \param[in] cycles The amount of cycles to delay for
*/
void _delay_cycles(void *const hw, uint32_t cycles);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_DELAY_H_INCLUDED */

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/**
* \file
*
* \brief DMA related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_DMA_H_INCLUDED
#define _HPL_DMA_H_INCLUDED
/**
* \addtogroup HPL DMA
*
* \section hpl_dma_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include <hpl_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
struct _dma_resource;
/**
* \brief DMA callback types
*/
enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB };
/**
* \brief DMA interrupt callbacks
*/
struct _dma_callbacks {
void (*transfer_done)(struct _dma_resource *resource);
void (*error)(struct _dma_resource *resource);
};
/**
* \brief DMA resource structure
*/
struct _dma_resource {
struct _dma_callbacks dma_cb;
void * back;
};
/**
* \brief Initialize DMA
*
* This function does low level DMA configuration.
*
* \return initialize status
*/
int32_t _dma_init(void);
/**
* \brief Set destination address
*
* \param[in] channel DMA channel to set destination address for
* \param[in] dst Destination address
*
* \return setting status
*/
int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst);
/**
* \brief Set source address
*
* \param[in] channel DMA channel to set source address for
* \param[in] src Source address
*
* \return setting status
*/
int32_t _dma_set_source_address(const uint8_t channel, const void *const src);
/**
* \brief Set next descriptor address
*
* \param[in] current_channel Current DMA channel to set next descriptor address
* \param[in] next_channel Next DMA channel used as next descriptor
*
* \return setting status
*/
int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel);
/**
* \brief Enable/disable source address incrementation during DMA transaction
*
* \param[in] channel DMA channel to set source address for
* \param[in] enable True to enable, false to disable
*
* \return status of operation
*/
int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable);
/**
* \brief Enable/disable Destination address incrementation during DMA transaction
*
* \param[in] channel DMA channel to set destination address for
* \param[in] enable True to enable, false to disable
*
* \return status of operation
*/
int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable);
/**
* \brief Set the amount of data to be transfered per transaction
*
* \param[in] channel DMA channel to set data amount for
* \param[in] amount Data amount
*
* \return status of operation
*/
int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount);
/**
* \brief Trigger DMA transaction on the given channel
*
* \param[in] channel DMA channel to trigger transaction on
*
* \return status of operation
*/
int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger);
/**
* \brief Retrieves DMA resource structure
*
* \param[out] resource The resource to be retrieved
* \param[in] channel DMA channel to retrieve structure for
*
* \return status of operation
*/
int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel);
/**
* \brief Enable/disable DMA interrupt
*
* \param[in] channel DMA channel to enable/disable interrupt for
* \param[in] type The type of interrupt to disable/enable if applicable
* \param[in] state Enable or disable
*/
void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state);
#ifdef __cplusplus
}
#endif
#endif /* HPL_DMA_H_INCLUDED */

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/**
* \file
*
* \brief Port related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_GPIO_H_INCLUDED
#define _HPL_GPIO_H_INCLUDED
/**
* \addtogroup HPL Port
*
* \section hpl_port_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Macros for the pin and port group, lower 5
* bits stands for pin number in the group, higher 3
* bits stands for port group
*/
#define GPIO_PIN(n) (((n)&0x1Fu) << 0)
#define GPIO_PORT(n) ((n) >> 5)
#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu))
#define GPIO_PIN_FUNCTION_OFF 0xffffffff
/**
* \brief PORT pull mode settings
*/
enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN };
/**
* \brief PORT direction settins
*/
enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT };
/**
* \brief PORT group abstraction
*/
enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE };
/**
* \name HPL functions
*/
//@{
/**
* \brief Port initialization function
*
* Port initialization function should setup the port module based
* on a static configuration file, this function should normally
* not be called directly, but is a part of hal_init()
*/
void _gpio_init(void);
/**
* \brief Set direction on port with mask
*
* Set data direction for each pin, or disable the pin
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to the
* corresponding pin
* \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input
* and disable input buffer to disable the pin
* GPIO_DIRECTION_IN = set pin direction to input
* and enable input buffer to enable the pin
* GPIO_DIRECTION_OUT = set pin direction to output
* and disable input buffer
*/
static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
const enum gpio_direction direction);
/**
* \brief Set output level on port with mask
*
* Sets output state on pin to high or low with pin masking
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to
* the corresponding pin
* \param[in] level true = pin level is set to 1
* false = pin level is set to 0
*/
static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level);
/**
* \brief Change output level to the opposite with mask
*
* Change pin output level to the opposite with pin masking
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to
* the corresponding pin
*/
static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask);
/**
* \brief Get input levels on all port pins
*
* Get input level on all port pins, will read IN register if configured to
* input and OUT register if configured as output
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
*/
static inline uint32_t _gpio_get_level(const enum gpio_port port);
/**
* \brief Set pin pull mode
*
* Set pull mode on a single pin
*
* \notice This function will automatically change pin direction to input
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] pin The pin in the group that pull mode should be selected
* for
* \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled
* GPIO_PULL_DOWN = pull resistor on pin will pull pin
* level to ground level
* GPIO_PULL_UP = pull resistor on pin will pull pin
* level to VCC
*/
static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin,
const enum gpio_pull_mode pull_mode);
/**
* \brief Set gpio function
*
* Select which function a gpio is used for
*
* \param[in] gpio The gpio to set function for
* \param[in] function The gpio function is given by a 32-bit wide bitfield
* found in the header files for the device
*
*/
static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function);
#include <hpl_gpio_base.h>
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_GPIO_H_INCLUDED */

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/**
* \file
*
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED
#define _HPL_I2C_M_ASYNC_H_INCLUDED
#include "hpl_i2c_m_sync.h"
#include "hpl_irq.h"
#include "utils.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c master callback names
*/
enum _i2c_m_async_callback_type {
I2C_M_ASYNC_DEVICE_ERROR,
I2C_M_ASYNC_DEVICE_TX_COMPLETE,
I2C_M_ASYNC_DEVICE_RX_COMPLETE
};
struct _i2c_m_async_device;
typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev);
typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode);
/**
* \brief i2c callback pointers structure
*/
struct _i2c_m_async_callback {
_i2c_error_cb_t error;
_i2c_complete_cb_t tx_complete;
_i2c_complete_cb_t rx_complete;
};
/**
* \brief i2c device structure
*/
struct _i2c_m_async_device {
struct _i2c_m_service service;
void * hw;
struct _i2c_m_async_callback cb;
struct _irq_descriptor irq;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize I2C in interrupt mode
*
* This function does low level I2C configuration.
*
* \param[in] i2c_dev The pointer to i2c interrupt device structure
* \param[in] hw The pointer to hardware instance
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw);
/**
* \brief Deinitialize I2C in interrupt mode
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Transfer data by I2C
*
* This function does low level I2C data transfer.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] msg The pointer to i2c msg structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg);
/**
* \brief Set baud rate of I2C
*
* This function does low level I2C set baud rate.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] clkrate The clock rate(KHz) input to i2c module
* \param[in] baudrate The demand baud rate(KHz) of i2c module
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Register callback to I2C
*
* This function does low level I2C callback register.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] cb_type The callback type request
* \param[in] func The callback function pointer
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type,
FUNC_PTR func);
/**
* \brief Generate stop condition on the I2C bus
*
* This function will generate a stop condition on the I2C bus
*
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
*
* \return Operation status
* \retval 0 Operation executed successfully
* \retval <0 Operation failed
*/
int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Returns the number of bytes left or not used in the I2C message buffer
*
* This function will return the number of bytes left (not written to the bus) or still free
* (not received from the bus) in the message buffer, depending on direction of transmission.
*
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
*
* \return Number of bytes or error code
* \retval >0 Positive number indicating bytes left
* \retval 0 Buffer is full/empty depending on direction
* \retval <0 Error code
*/
int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Enable/disable I2C master interrupt
*
* param[in] device The pointer to I2C master device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type,
const bool state);
#ifdef __cplusplus
}
#endif
#endif

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/**
* \file
*
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_M_SYNC_H_INCLUDED
#define _HPL_I2C_M_SYNC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c flags
*/
#define I2C_M_RD 0x0001 /* read data, from slave to master */
#define I2C_M_BUSY 0x0100
#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */
#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */
#define I2C_M_FAIL 0x1000
#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
/**
* \brief i2c Return codes
*/
#define I2C_OK 0 /* Operation successful */
#define I2C_ACK -1 /* Received ACK from device on I2C bus */
#define I2C_NACK -2 /* Received NACK from device on I2C bus */
#define I2C_ERR_ARBLOST -3 /* Arbitration lost */
#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */
#define I2C_ERR_BUS -5 /* Bus error */
#define I2C_ERR_BUSY -6 /* Device busy */
#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */
/**
* \brief i2c I2C Modes
*/
#define I2C_STANDARD_MODE 0x00
#define I2C_FASTMODE 0x01
#define I2C_HIGHSPEED_MODE 0x02
/**
* \brief i2c master message structure
*/
struct _i2c_m_msg {
uint16_t addr;
volatile uint16_t flags;
int32_t len;
uint8_t * buffer;
};
/**
* \brief i2c master service
*/
struct _i2c_m_service {
struct _i2c_m_msg msg;
uint16_t mode;
uint16_t trise;
};
/**
* \brief i2c sync master device structure
*/
struct _i2c_m_sync_device {
struct _i2c_m_service service;
void * hw;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize I2C
*
* This function does low level I2C configuration.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] hw The pointer to hardware instance
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw);
/**
* \brief Deinitialize I2C
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Transfer data by I2C
*
* This function does low level I2C data transfer.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] msg The pointer to i2c msg structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg);
/**
* \brief Set baud rate of I2C
*
* This function does low level I2C set baud rate.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] clkrate The clock rate(KHz) input to i2c module
* \param[in] baudrate The demand baud rate(KHz) of i2c module
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Send send condition on the I2C bus
*
* This function will generate a stop condition on the I2C bus
*
* \param[in] i2c_dev The pointer to i2c device struct
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev);
#ifdef __cplusplus
}
#endif
#endif

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/**
* \file
*
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED
#define _HPL_I2C_S_ASYNC_H_INCLUDED
#include "hpl_i2c_s_sync.h"
#include "hpl_irq.h"
#include "utils.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c callback types
*/
enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE };
/**
* \brief Forward declaration of I2C Slave device
*/
struct _i2c_s_async_device;
/**
* \brief i2c slave callback function type
*/
typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device);
/**
* \brief i2c slave callback pointers structure
*/
struct _i2c_s_async_callback {
void (*error)(struct _i2c_s_async_device *const device);
void (*tx)(struct _i2c_s_async_device *const device);
void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data);
};
/**
* \brief i2c slave device structure
*/
struct _i2c_s_async_device {
void * hw;
struct _i2c_s_async_callback cb;
struct _irq_descriptor irq;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize asynchronous I2C slave
*
* This function does low level I2C configuration.
*
* \param[in] device The pointer to i2c interrupt device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw);
/**
* \brief Deinitialize asynchronous I2C in interrupt mode
*
* \param[in] device The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device);
/**
* \brief Check if 10-bit addressing mode is on
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Cheking status
* \retval 1 10-bit addressing mode is on
* \retval 0 10-bit addressing mode is off
*/
int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device);
/**
* \brief Set I2C slave address
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] address Address to set
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address);
/**
* \brief Write a byte to the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] data Data to write
*/
void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data);
/**
* \brief Retrieve I2C slave status
*
* \param[in] device The pointer to i2c slave device structure
*
*\return I2C slave status
*/
i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device);
/**
* \brief Abort data transmission
*
* \param[in] device The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device);
/**
* \brief Enable/disable I2C slave interrupt
*
* param[in] device The pointer to I2C slave device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] disable Enable or disable
*/
int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type,
const bool disable);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */

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/**
* \file
*
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_S_SYNC_H_INCLUDED
#define _HPL_I2C_S_SYNC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief I2C Slave status type
*/
typedef uint32_t i2c_s_status_t;
/**
* \brief i2c slave device structure
*/
struct _i2c_s_sync_device {
void *hw;
};
#include <compiler.h>
/**
* \name HPL functions
*/
/**
* \brief Initialize synchronous I2C slave
*
* This function does low level I2C configuration.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw);
/**
* \brief Deinitialize synchronous I2C slave
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device);
/**
* \brief Check if 10-bit addressing mode is on
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Cheking status
* \retval 1 10-bit addressing mode is on
* \retval 0 10-bit addressing mode is off
*/
int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device);
/**
* \brief Set I2C slave address
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] address Address to set
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address);
/**
* \brief Write a byte to the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] data Data to write
*/
void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data);
/**
* \brief Retrieve I2C slave status
*
* \param[in] device The pointer to i2c slave device structure
*
*\return I2C slave status
*/
i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device);
/**
* \brief Clear the Data Ready interrupt flag
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device);
/**
* \brief Read a byte from the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Data received via I2C interface.
*/
uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device);
/**
* \brief Check if I2C is ready to send next byte
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Status of the ready check.
* \retval true if the I2C is ready to send next byte
* \retval false if the I2C is not ready to send next byte
*/
bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device);
/**
* \brief Check if there is data received by I2C
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Status of the data received check.
* \retval true if the I2C has received a byte
* \retval false if the I2C has not received a byte
*/
bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */

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/**
* \file
*
* \brief Init related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_INIT_H_INCLUDED
#define _HPL_INIT_H_INCLUDED
/**
* \addtogroup HPL Init
*
* \section hpl_init_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Initializes clock sources
*/
void _sysctrl_init_sources(void);
/**
* \brief Initializes Power Manager
*/
void _pm_init(void);
/**
* \brief Initialize generators
*/
void _gclk_init_generators(void);
/**
* \brief Initialize 32 kHz clock sources
*/
void _osc32kctrl_init_sources(void);
/**
* \brief Initialize clock sources
*/
void _oscctrl_init_sources(void);
/**
* \brief Initialize clock sources that need input reference clocks
*/
void _sysctrl_init_referenced_generators(void);
/**
* \brief Initialize clock sources that need input reference clocks
*/
void _oscctrl_init_referenced_generators(void);
/**
* \brief Initialize master clock generator
*/
void _mclk_init(void);
/**
* \brief Initialize clock generator
*/
void _lpmcu_misc_regs_init(void);
/**
* \brief Initialize clock generator
*/
void _pmc_init(void);
/**
* \brief Set performance level
*
* \param[in] level The performance level to set
*/
void _set_performance_level(const uint8_t level);
/**
* \brief Initialize the chip
*/
void _init_chip(void);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_INIT_H_INCLUDED */

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/**
* \file
*
* \brief IRQ related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_IRQ_H_INCLUDED
#define _HPL_IRQ_H_INCLUDED
/**
* \addtogroup HPL IRQ
*
* \section hpl_irq_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief IRQ descriptor
*/
struct _irq_descriptor {
void (*handler)(void *parameter);
void *parameter;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Retrieve current IRQ number
*
* \return The current IRQ number
*/
uint8_t _irq_get_current(void);
/**
* \brief Disable the given IRQ
*
* \param[in] n The number of IRQ to disable
*/
void _irq_disable(uint8_t n);
/**
* \brief Set the given IRQ
*
* \param[in] n The number of IRQ to set
*/
void _irq_set(uint8_t n);
/**
* \brief Clear the given IRQ
*
* \param[in] n The number of IRQ to clear
*/
void _irq_clear(uint8_t n);
/**
* \brief Enable the given IRQ
*
* \param[in] n The number of IRQ to enable
*/
void _irq_enable(uint8_t n);
/**
* \brief Register IRQ handler
*
* \param[in] number The number registered IRQ
* \param[in] irq The pointer to irq handler to register
*
* \return The status of IRQ handler registering
* \retval -1 Passed parameters were invalid
* \retval 0 The registering is completed successfully
*/
void _irq_register(const uint8_t number, struct _irq_descriptor *const irq);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_IRQ_H_INCLUDED */

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/**
* \file
*
* \brief Family-dependent missing features expected by HAL
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_MISSING_FEATURES
#define _HPL_MISSING_FEATURES
#endif /* _HPL_MISSING_FEATURES */

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/**
* \file
*
* \brief RAMECC related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_RAMECC_H_INCLUDED
#define _HPL_RAMECC_H_INCLUDED
/**
* \addtogroup HPL RAMECC
*
* \section hpl_ramecc_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include <hpl_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief RAMECC callback type
*/
typedef void (*ramecc_cb_t)(const uint32_t data);
/**
* \brief RAMECC callback types
*/
enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB };
/**
* \brief RAMECC interrupt callbacks
*/
struct _ramecc_callbacks {
ramecc_cb_t dual_bit_err;
ramecc_cb_t single_bit_err;
};
/**
* \brief RAMECC device structure
*/
struct _ramecc_device {
struct _ramecc_callbacks ramecc_cb;
struct _irq_descriptor irq;
};
/**
* \brief Initialize RAMECC
*
* This function does low level RAMECC configuration.
*
* \return initialize status
*/
int32_t _ramecc_init(void);
/**
* \brief Register RAMECC callback
*
* \param[in] type The type of callback
* \param[in] cb A callback function
*/
void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_RAMECC_H_INCLUDED */

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/**
* \file
*
* \brief Reset related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_RESET_H_INCLUDED
#define _HPL_RESET_H_INCLUDED
/**
* \addtogroup HPL Reset
*
* \section hpl_reset_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifndef _UNIT_TEST_
#include <compiler.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Reset reason enumeration
*
* The list of possible reset reasons.
*/
enum reset_reason {
RESET_REASON_POR = 1,
RESET_REASON_BOD12 = 2,
RESET_REASON_BOD33 = 4,
RESET_REASON_NVM = 8,
RESET_REASON_EXT = 16,
RESET_REASON_WDT = 32,
RESET_REASON_SYST = 64,
RESET_REASON_BACKUP = 128
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Retrieve the reset reason
*
* Retrieves the reset reason of the last MCU reset.
*
*\return An enum value indicating the reason of the last reset.
*/
enum reset_reason _get_reset_reason(void);
/**
* \brief Reset MCU
*/
void _reset_mcu(void);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_RESET_H_INCLUDED */

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/**
* \file
*
* \brief Sleep related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SLEEP_H_INCLUDED
#define _HPL_SLEEP_H_INCLUDED
/**
* \addtogroup HPL Sleep
*
* \section hpl_sleep_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifndef _UNIT_TEST_
#include <compiler.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Set the sleep mode for the device
*
* This function sets the sleep mode for the device.
* For an overview of which systems are disabled in sleep for the different
* sleep modes see datasheet.
*
* \param[in] mode Sleep mode to use
*
* \return the status of a sleep request
* \retval -1 The requested sleep mode was invalid
* \retval 0 The operation completed successfully, sleep mode is set
*/
int32_t _set_sleep_mode(const uint8_t mode);
/**
* \brief Reset MCU
*/
void _reset_mcu(void);
/**
* \brief Put MCU to sleep
*/
void _go_to_sleep(void);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_SLEEP_H_INCLUDED */

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/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_H_INCLUDED
#define _HPL_SPI_H_INCLUDED
#include <compiler.h>
#include <utils.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief SPI Dummy char is used when reading data from the SPI slave
*/
#define SPI_DUMMY_CHAR 0x1ff
/**
* \brief SPI message to let driver to process
*/
//@{
struct spi_msg {
/** Pointer to the output data buffer */
uint8_t *txbuf;
/** Pointer to the input data buffer */
uint8_t *rxbuf;
/** Size of the message data in SPI characters */
uint32_t size;
};
//@}
/**
* \brief SPI transfer modes
* SPI transfer mode controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
*/
enum spi_transfer_mode {
/** Leading edge is rising edge, data sample on leading edge. */
SPI_MODE_0,
/** Leading edge is rising edge, data sample on trailing edge. */
SPI_MODE_1,
/** Leading edge is falling edge, data sample on leading edge. */
SPI_MODE_2,
/** Leading edge is falling edge, data sample on trailing edge. */
SPI_MODE_3
};
/**
* \brief SPI character sizes
* The character size influence the way the data is sent/received.
* For char size <= 8 data is stored byte by byte.
* For char size between 9 ~ 16 data is stored in 2-byte length.
* Note that the default and recommended char size is 8 bit since it's
* supported by all system.
*/
enum spi_char_size {
/** Character size is 8 bit. */
SPI_CHAR_SIZE_8 = 0,
/** Character size is 9 bit. */
SPI_CHAR_SIZE_9 = 1,
/** Character size is 10 bit. */
SPI_CHAR_SIZE_10 = 2,
/** Character size is 11 bit. */
SPI_CHAR_SIZE_11 = 3,
/** Character size is 12 bit. */
SPI_CHAR_SIZE_12 = 4,
/** Character size is 13 bit. */
SPI_CHAR_SIZE_13 = 5,
/** Character size is 14 bit. */
SPI_CHAR_SIZE_14 = 6,
/** Character size is 15 bit. */
SPI_CHAR_SIZE_15 = 7,
/** Character size is 16 bit. */
SPI_CHAR_SIZE_16 = 8
};
/**
* \brief SPI data order
*/
enum spi_data_order {
/** MSB goes first. */
SPI_DATA_ORDER_MSB_1ST = 0,
/** LSB goes first. */
SPI_DATA_ORDER_LSB_1ST = 1
};
/** \brief Transfer descriptor for SPI
* Transfer descriptor holds TX and RX buffers
*/
struct spi_xfer {
/** Pointer to data buffer to TX */
uint8_t *txbuf;
/** Pointer to data buffer to RX */
uint8_t *rxbuf;
/** Size of data characters to TX & RX */
uint32_t size;
};
/** SPI generic driver. */
struct spi_dev {
/** Pointer to the hardware base or private data for special device. */
void *prvt;
/** Reference start of sync/async variables */
uint32_t sync_async_misc[1];
};
/**
* \brief Calculate the baudrate value for hardware to use to set baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] clk Clock frequency (Hz) for baudrate generation.
* \param[in] baud Target baudrate (bps).
* \return Error or baudrate value.
* \retval >0 Baudrate value.
* \retval ERR_INVALID_ARG Calculation fail.
*/
int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_H_INCLUDED */

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/**
* \file
*
* \brief Common SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_ASYNC_H_INCLUDED
#define _HPL_SPI_ASYNC_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_irq.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Callbacks the SPI driver must offer in async mode
*/
//@{
/** The callback types */
enum _spi_async_dev_cb_type {
/** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */
SPI_DEV_CB_TX,
/** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */
SPI_DEV_CB_RX,
/** Callback type for \ref _spi_async_dev_cb_complete_t. */
SPI_DEV_CB_COMPLETE,
/** Callback type for error */
SPI_DEV_CB_ERROR,
/** Number of callbacks. */
SPI_DEV_CB_N
};
struct _spi_async_dev;
/** \brief The prototype for callback on SPI transfer error.
* If status code is zero, it indicates the normal completion, that is,
* SS deactivation.
* If status code belows zero, it indicates complete.
*/
typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status);
/** \brief The prototype for callback on SPI transmit/receive event
* For TX, the callback is invoked when transmit is done or ready to start
* transmit.
* For RX, the callback is invoked when receive is done or ready to read data,
* see \ref _spi_async_dev_read_one_t on data reading.
* Without DMA enabled, the callback is invoked on each character event.
* With DMA enabled, the callback is invoked on DMA buffer done.
*/
typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev);
/**
* \brief The callbacks offered by SPI driver
*/
struct _spi_async_dev_callbacks {
/** TX callback, see \ref _spi_async_dev_cb_xfer_t. */
_spi_async_dev_cb_xfer_t tx;
/** RX callback, see \ref _spi_async_dev_cb_xfer_t. */
_spi_async_dev_cb_xfer_t rx;
/** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */
_spi_async_dev_cb_xfer_t complete;
/** Error callback, see \ref */
_spi_async_dev_cb_error_t err;
};
//@}
/**
* \brief SPI async driver
*/
//@{
/** SPI driver to support async HAL */
struct _spi_async_dev {
/** Pointer to the hardware base or private data for special device. */
void *prvt;
/** Data size, number of bytes for each character */
uint8_t char_size;
/** Dummy byte used in master mode when reading the slave */
uint16_t dummy_byte;
/** \brief Pointer to callback functions, ignored for polling mode
* Pointer to the callback functions so that initialize the driver to
* handle interrupts.
*/
struct _spi_async_dev_callbacks callbacks;
/** IRQ instance for SPI device. */
struct _irq_descriptor irq;
};
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */

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/**
* \file
*
* \brief Common SPI DMA related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_DMA_H_INCLUDED
#define _HPL_SPI_DMA_H_INCLUDED
#include <hpl_irq.h>
#include <hpl_dma.h>
#ifdef __cplusplus
extern "C" {
#endif
/** The callback types */
enum _spi_dma_dev_cb_type {
/** Callback type for DMA transmit. */
SPI_DEV_CB_DMA_TX,
/** Callback type for DMA receive. */
SPI_DEV_CB_DMA_RX,
/** Callback type for DMA error. */
SPI_DEV_CB_DMA_ERROR,
/** Number of callbacks. */
SPI_DEV_CB_DMA_N
};
struct _spi_dma_dev;
/**
* \brief The prototype for callback on SPI DMA.
*/
typedef void (*_spi_dma_cb_t)(struct _dma_resource *resource);
/**
* \brief The callbacks offered by SPI driver
*/
struct _spi_dma_dev_callbacks {
_spi_dma_cb_t tx;
_spi_dma_cb_t rx;
_spi_dma_cb_t error;
};
/** SPI driver to support DMA HAL */
struct _spi_dma_dev {
/** Pointer to the hardware base or private data for special device. */
void *prvt;
/** Pointer to callback functions */
struct _spi_dma_dev_callbacks callbacks;
/** IRQ instance for SPI device. */
struct _irq_descriptor irq;
/** DMA resource */
struct _dma_resource *resource;
};
#ifdef __cplusplus
}
#endif
#endif /* ifndef _HPL_SPI_DMA_H_INCLUDED */

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/**
* \file
*
* \brief SPI Slave Async related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED
#define _HPL_SPI_M_ASYNC_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_spi_async.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI async device driver. */
#define _spi_m_async_dev _spi_async_dev
#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type
/** Uses common SPI async device driver complete callback type. */
#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
/** Uses common SPI async device driver transfer callback type. */
#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access with interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev);
/**
* \brief Enable SPI for access with interrupts
* Enable the SPI and enable callback generation of receive and error
* interrupts.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
* how it's generated.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord);
/**
* \brief Enable interrupt on character output
*
* Enable interrupt when a new character can be written
* to the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable output interrupt
* false = disable output interrupt
*
* \return Status code
* \retval 0 Ok status
*/
int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state);
/**
* \brief Enable interrupt on character input
*
* Enable interrupt when a new character is ready to be
* read from the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state);
/**
* \brief Enable interrupt on after data transmission complate
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state);
/**
* \brief Read one character to SPI device instance
* \param[in, out] dev Pointer to the SPI device instance.
*
* \return Character read from SPI module
*/
uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev);
/**
* \brief Write one character to assigned buffer
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] data
*
* \return Status code of write operation
* \retval 0 Write operation OK
*/
int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data);
/**
* \brief Register the SPI device callback
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] cb_type The callback type.
* \param[in] func The callback function to register. NULL to disable callback.
* \return Always 0.
*/
int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type,
const FUNC_PTR func);
/**
* \brief Enable/disable SPI master interrupt
*
* param[in] device The pointer to SPI master device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type,
const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */

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/**
* \file
*
* \brief SPI Master DMA related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_M_DMA_H_INCLUDED
#define _HPL_SPI_M_DMA_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_spi_dma.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI dma device driver. */
#define _spi_m_dma_dev _spi_dma_dev
#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access with interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev);
/**
* \brief Enable SPI for access with interrupts
* Enable the SPI and enable callback generation of receive and error
* interrupts.
* \param[in] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
* \param[in] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in] dev Pointer to the SPI device instance.
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
* how it's generated.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord);
/**
* \brief Register the SPI device callback
* \param[in] dev Pointer to the SPI device instance.
* \param[in] cb_type The callback type.
* \param[in] func The callback function to register. NULL to disable callback.
* \return Always 0.
*/
void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func);
/** \brief Do SPI data transfer (TX & RX) with DMA
* Log the TX & RX buffers and transfer them in background. It never blocks.
*
* \param[in] dev Pointer to the SPI device instance.
* \param[in] txbuf Pointer to the transfer information (\ref spi_transfer).
* \param[out] rxbuf Pointer to the receiver information (\ref spi_receive).
* \param[in] length spi transfer data length.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy.
*/
int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf,
const uint16_t length);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */

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/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_M_SYNC_H_INCLUDED
#define _HPL_SPI_M_SYNC_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_spi_sync.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI sync device driver. */
#define _spi_m_sync_dev _spi_sync_dev
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access without interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw);
/**
* \brief Deinitialize SPI
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev);
/**
* \brief Enable SPI for access without interrupts
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
* how it's generated.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val);
/**
* \brief Set SPI char size
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord);
/**
* \brief Transfer the whole message without interrupt
* Transfer the message, it will keep waiting until the message finish or
* error.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] msg Pointer to the message instance to process.
* \return Error or number of characters transferred.
* \retval ERR_BUSY SPI hardware is not ready to start transfer (not
* enabled, busy applying settings, ...).
* \retval SPI_ERR_OVERFLOW Overflow error.
* \retval >=0 Number of characters transferred.
*/
int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */

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/**
* \file
*
* \brief SPI Slave Async related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED
#define _HPL_SPI_S_ASYNC_H_INCLUDED
#include <hpl_spi_async.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI async device driver. */
#define _spi_s_async_dev _spi_async_dev
#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type
/** Uses common SPI async device driver complete callback type. */
#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
/** Uses common SPI async device driver transfer callback type. */
#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access with interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev);
/**
* \brief Enable SPI for access with interrupts
* Enable the SPI and enable callback generation of receive and error
* interrupts.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord);
/**
* \brief Enable interrupt on character output
*
* Enable interrupt when a new character can be written
* to the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable output interrupt
* false = disable output interrupt
*
* \return Status code
* \retval 0 Ok status
*/
int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state);
/**
* \brief Enable interrupt on character input
*
* Enable interrupt when a new character is ready to be
* read from the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state);
/**
* \brief Enable interrupt on Slave Select (SS) rising
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state);
/**
* \brief Read one character to SPI device instance
* \param[in, out] dev Pointer to the SPI device instance.
*
* \return Character read from SPI module
*/
uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev);
/**
* \brief Write one character to assigned buffer
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] data
*
* \return Status code of write operation
* \retval 0 Write operation OK
*/
int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data);
/**
* \brief Register the SPI device callback
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] cb_type The callback type.
* \param[in] func The callback function to register. NULL to disable callback.
* \return Always 0.
*/
int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type,
const FUNC_PTR func);
/**
* \brief Enable/disable SPI slave interrupt
*
* param[in] device The pointer to SPI slave device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type,
const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */

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/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_S_SYNC_H_INCLUDED
#define _HPL_SPI_S_SYNC_H_INCLUDED
#include <hpl_spi_sync.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI sync device driver. */
#define _spi_s_sync_dev _spi_sync_dev
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access without interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev);
/**
* \brief Enable SPI for access without interrupts
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord);
/**
* \brief Enable interrupt on character output
*
* Enable interrupt when a new character can be written
* to the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable output interrupt
* false = disable output interrupt
*
* \return Status code
* \retval 0 Ok status
*/
int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state);
/**
* \brief Enable interrupt on character input
*
* Enable interrupt when a new character is ready to be
* read from the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retval 0 OK Status
*/
int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state);
/**
* \brief Read one character to SPI device instance
* \param[in, out] dev Pointer to the SPI device instance.
*
* \return Character read from SPI module
*/
uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev);
/**
* \brief Write one character to assigned buffer
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] data
*
* \return Status code of write operation
* \retval 0 Write operation OK
*/
int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data);
/**
* \brief Check if TX ready
*
* \param[in] dev Pointer to the SPI device instance
*
* \return TX ready state
* \retval true TX ready
* \retval false TX not ready
*/
bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev);
/**
* \brief Check if RX character ready
*
* \param[in] dev Pointer to the SPI device instance
*
* \return RX character ready state
* \retval true RX character ready
* \retval false RX character not ready
*/
bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev);
/**
* \brief Check if SS deactiviation detected
*
* \param[in] dev Pointer to the SPI device instance
*
* \return SS deactiviation state
* \retval true SS deactiviation detected
* \retval false SS deactiviation not detected
*/
bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev);
/**
* \brief Check if error is detected
*
* \param[in] dev Pointer to the SPI device instance
*
* \return Error detection state
* \retval true Error detected
* \retval false Error not detected
*/
bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */

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/**
* \file
*
* \brief Common SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_SYNC_H_INCLUDED
#define _HPL_SPI_SYNC_H_INCLUDED
#include <compiler.h>
#include <utils.h>
#include <hpl_spi.h>
/**
* \addtogroup hpl_spi HPL SPI
*
* \section hpl_spi_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** SPI driver to support sync HAL */
struct _spi_sync_dev {
/** Pointer to the hardware base or private data for special device. */
void *prvt;
/** Data size, number of bytes for each character */
uint8_t char_size;
/** Dummy byte used in master mode when reading the slave */
uint16_t dummy_byte;
};
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */

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/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_USART_H_INCLUDED
#define _HPL_USART_H_INCLUDED
/**
* \addtogroup HPL USART SYNC
*
* \section hpl_usart_sync_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART flow control state
*/
union usart_flow_control_state {
struct {
uint8_t cts : 1;
uint8_t rts : 1;
uint8_t unavailable : 1;
uint8_t reserved : 5;
} bit;
uint8_t value;
};
/**
* \brief USART baud rate mode
*/
enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH };
/**
* \brief USART data order
*/
enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 };
/**
* \brief USART mode
*/
enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 };
/**
* \brief USART parity
*/
enum usart_parity {
USART_PARITY_EVEN = 0,
USART_PARITY_ODD = 1,
USART_PARITY_NONE = 2,
USART_PARITY_SPACE = 3,
USART_PARITY_MARK = 4
};
/**
* \brief USART stop bits mode
*/
enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 };
/**
* \brief USART character size
*/
enum usart_character_size {
USART_CHARACTER_SIZE_8BITS = 0,
USART_CHARACTER_SIZE_9BITS = 1,
USART_CHARACTER_SIZE_5BITS = 5,
USART_CHARACTER_SIZE_6BITS = 6,
USART_CHARACTER_SIZE_7BITS = 7
};
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_USART_H_INCLUDED */

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/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_USART_ASYNC_H_INCLUDED
#define _HPL_USART_ASYNC_H_INCLUDED
/**
* \addtogroup HPL USART
*
* \section hpl_usart_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "hpl_usart.h"
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART callback types
*/
enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR };
/**
* \brief USART device structure
*
* The USART device structure forward declaration.
*/
struct _usart_async_device;
/**
* \brief USART interrupt callbacks
*/
struct _usart_async_callbacks {
void (*tx_byte_sent)(struct _usart_async_device *device);
void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data);
void (*tx_done_cb)(struct _usart_async_device *device);
void (*error_cb)(struct _usart_async_device *device);
};
/**
* \brief USART descriptor device structure
*/
struct _usart_async_device {
struct _usart_async_callbacks usart_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize asynchronous USART
*
* This function does low level USART configuration.
*
* \param[in] device The pointer to USART device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw);
/**
* \brief Deinitialize USART
*
* This function closes the given USART by disabling its clock.
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_deinit(struct _usart_async_device *const device);
/**
* \brief Enable usart module
*
* This function will enable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_enable(struct _usart_async_device *const device);
/**
* \brief Disable usart module
*
* This function will disable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_disable(struct _usart_async_device *const device);
/**
* \brief Calculate baud rate register value
*
* \param[in] baud Required baud rate
* \param[in] clock_rate clock frequency
* \param[in] samples The number of samples
* \param[in] mode USART mode
* \param[in] fraction A fraction value
*
* \return Calculated baud rate register value
*/
uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
const enum usart_baud_rate_mode mode, const uint8_t fraction);
/**
* \brief Set baud rate
*
* \param[in] device The pointer to USART device instance
* \param[in] baud_rate A baud rate to set
*/
void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate);
/**
* \brief Set data order
*
* \param[in] device The pointer to USART device instance
* \param[in] order A data order to set
*/
void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order);
/**
* \brief Set mode
*
* \param[in] device The pointer to USART device instance
* \param[in] mode A mode to set
*/
void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode);
/**
* \brief Set parity
*
* \param[in] device The pointer to USART device instance
* \param[in] parity A parity to set
*/
void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity);
/**
* \brief Set stop bits mode
*
* \param[in] device The pointer to USART device instance
* \param[in] stop_bits A stop bits mode to set
*/
void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits);
/**
* \brief Set character size
*
* \param[in] device The pointer to USART device instance
* \param[in] size A character size to set
*/
void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size);
/**
* \brief Retrieve usart status
*
* \param[in] device The pointer to USART device instance
*/
uint32_t _usart_async_get_status(const struct _usart_async_device *const device);
/**
* \brief Write a byte to the given USART instance
*
* \param[in] device The pointer to USART device instance
* \param[in] data Data to write
*/
void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data);
/**
* \brief Check if USART is ready to send next byte
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the ready check.
* \retval true if the USART is ready to send next byte
* \retval false if the USART is not ready to send next byte
*/
bool _usart_async_is_byte_sent(const struct _usart_async_device *const device);
/**
* \brief Set the state of flow control pins
*
* \param[in] device The pointer to USART device instance
* \param[in] state - A state of flow control pins to set
*/
void _usart_async_set_flow_control_state(struct _usart_async_device *const device,
const union usart_flow_control_state state);
/**
* \brief Retrieve the state of flow control pins
*
* This function retrieves the of flow control pins.
*
* \return USART_FLOW_CONTROL_STATE_UNAVAILABLE.
*/
union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device);
/**
* \brief Enable data register empty interrupt
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device);
/**
* \brief Enable transmission complete interrupt
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device);
/**
* \brief Retrieve ordinal number of the given USART hardware instance
*
* \param[in] device The pointer to USART device instance
*
* \return The ordinal number of the given USART hardware instance
*/
uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device);
/**
* \brief Enable/disable USART interrupt
*
* param[in] device The pointer to USART device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type,
const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_USART_ASYNC_H_INCLUDED */

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/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SYNC_USART_H_INCLUDED
#define _HPL_SYNC_USART_H_INCLUDED
/**
* \addtogroup HPL USART SYNC
*
* \section hpl_usart_sync_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <hpl_usart.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART descriptor device structure
*/
struct _usart_sync_device {
void *hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous USART
*
* This function does low level USART configuration.
*
* \param[in] device The pointer to USART device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw);
/**
* \brief Deinitialize USART
*
* This function closes the given USART by disabling its clock.
*
* \param[in] device The pointer to USART device instance
*/
void _usart_sync_deinit(struct _usart_sync_device *const device);
/**
* \brief Enable usart module
*
* This function will enable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_sync_enable(struct _usart_sync_device *const device);
/**
* \brief Disable usart module
*
* This function will disable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_sync_disable(struct _usart_sync_device *const device);
/**
* \brief Calculate baud rate register value
*
* \param[in] baud Required baud rate
* \param[in] clock_rate clock frequency
* \param[in] samples The number of samples
* \param[in] mode USART mode
* \param[in] fraction A fraction value
*
* \return Calculated baud rate register value
*/
uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
const enum usart_baud_rate_mode mode, const uint8_t fraction);
/**
* \brief Set baud rate
*
* \param[in] device The pointer to USART device instance
* \param[in] baud_rate A baud rate to set
*/
void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate);
/**
* \brief Set data order
*
* \param[in] device The pointer to USART device instance
* \param[in] order A data order to set
*/
void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order);
/**
* \brief Set mode
*
* \param[in] device The pointer to USART device instance
* \param[in] mode A mode to set
*/
void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode);
/**
* \brief Set parity
*
* \param[in] device The pointer to USART device instance
* \param[in] parity A parity to set
*/
void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity);
/**
* \brief Set stop bits mode
*
* \param[in] device The pointer to USART device instance
* \param[in] stop_bits A stop bits mode to set
*/
void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits);
/**
* \brief Set character size
*
* \param[in] device The pointer to USART device instance
* \param[in] size A character size to set
*/
void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size);
/**
* \brief Retrieve usart status
*
* \param[in] device The pointer to USART device instance
*/
uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device);
/**
* \brief Write a byte to the given USART instance
*
* \param[in] device The pointer to USART device instance
* \param[in] data Data to write
*/
void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data);
/**
* \brief Read a byte from the given USART instance
*
* \param[in] device The pointer to USART device instance
* \param[in] data Data to write
*
* \return Data received via USART interface.
*/
uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device);
/**
* \brief Check if USART is ready to send next byte
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the ready check.
* \retval true if the USART is ready to send next byte
* \retval false if the USART is not ready to send next byte
*/
bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device);
/**
* \brief Check if USART transmitter has sent the byte
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the ready check.
* \retval true if the USART transmitter has sent the byte
* \retval false if the USART transmitter has not send the byte
*/
bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device);
/**
* \brief Check if there is data received by USART
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the data received check.
* \retval true if the USART has received a byte
* \retval false if the USART has not received a byte
*/
bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device);
/**
* \brief Set the state of flow control pins
*
* \param[in] device The pointer to USART device instance
* \param[in] state - A state of flow control pins to set
*/
void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device,
const union usart_flow_control_state state);
/**
* \brief Retrieve the state of flow control pins
*
* This function retrieves the of flow control pins.
*
* \return USART_FLOW_CONTROL_STATE_UNAVAILABLE.
*/
union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device);
/**
* \brief Retrieve ordinal number of the given USART hardware instance
*
* \param[in] device The pointer to USART device instance
*
* \return The ordinal number of the given USART hardware instance
*/
uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_SYNC_USART_H_INCLUDED */