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Nicolas Trimborn
2021-07-13 12:25:44 +02:00
parent a74d1a099d
commit 5b57fb9584
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354
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/hpl/cmcc/hpl_cmcc.c Normal file
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/**
* \file
*
* \brief Generic CMCC(Cortex M Cache Controller) related functionality.
*
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include <compiler.h>
#include <hpl_cmcc.h>
#include <hpl_cmcc_config.h>
/**
* \brief Initialize Cache Module
*
* This function does low level cache configuration.
*
* \return initialize status
*/
int32_t _cmcc_init(void)
{
int32_t return_value;
_cmcc_disable(CMCC);
if (_is_cache_disabled(CMCC)) {
hri_cmcc_write_CFG_reg(
CMCC,
(CMCC_CFG_CSIZESW(CONF_CMCC_CACHE_SIZE) | (CONF_CMCC_DATA_CACHE_DISABLE << CMCC_CFG_DCDIS_Pos)
| (CONF_CMCC_INST_CACHE_DISABLE << CMCC_CFG_ICDIS_Pos) | (CONF_CMCC_CLK_GATING_DISABLE)));
_cmcc_enable(CMCC);
return_value = _is_cache_enabled(CMCC) == true ? ERR_NONE : ERR_FAILURE;
} else {
return_value = ERR_NOT_INITIALIZED;
}
return return_value;
}
/**
* \brief Configure CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] cache configuration structure pointer
*
* \return status of operation
*/
int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl)
{
int32_t return_value;
_cmcc_disable(hw);
if (_is_cache_disabled(hw)) {
hri_cmcc_write_CFG_reg(
hw,
(CMCC_CFG_CSIZESW(cache_ctrl->cache_size) | (cache_ctrl->data_cache_disable << CMCC_CFG_DCDIS_Pos)
| (cache_ctrl->inst_cache_disable << CMCC_CFG_ICDIS_Pos) | (cache_ctrl->gclk_gate_disable)));
return_value = ERR_NONE;
} else {
return_value = ERR_NOT_INITIALIZED;
}
return return_value;
}
/**
* \brief Enable data cache in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache
*
* \return status of operation
*/
int32_t _cmcc_enable_data_cache(const void *hw, bool value)
{
uint32_t tmp;
int32_t ret;
tmp = hri_cmcc_read_CFG_reg(hw);
tmp &= ~CMCC_CFG_DCDIS;
tmp |= ((!value) << CMCC_CFG_DCDIS_Pos);
ret = _cmcc_disable(hw);
hri_cmcc_write_CFG_reg(hw, tmp);
ret = _cmcc_enable(hw);
return ret;
}
/**
* \brief Enable instruction cache in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache
*
* \return status of operation
*/
int32_t _cmcc_enable_inst_cache(const void *hw, bool value)
{
uint32_t tmp;
int32_t ret;
tmp = hri_cmcc_read_CFG_reg(hw);
tmp &= ~CMCC_CFG_ICDIS;
tmp |= ((!value) << CMCC_CFG_ICDIS_Pos);
ret = _cmcc_disable(hw);
hri_cmcc_write_CFG_reg(hw, tmp);
ret = _cmcc_enable(hw);
return ret;
}
/**
* \brief Enable clock gating in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate
*
* \return status of operation
*/
int32_t _cmcc_enable_clock_gating(const void *hw, bool value)
{
uint32_t tmp;
int32_t ret;
tmp = hri_cmcc_read_CFG_reg(hw);
tmp |= value;
ret = _cmcc_disable(hw);
hri_cmcc_write_CFG_reg(hw, tmp);
ret = _cmcc_enable(hw);
return ret;
}
/**
* \brief Configure the cache size in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from cache size configuration enumerator
* 0->1K, 1->2K, 2->4K(default)
*
* \return status of operation
*/
int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size)
{
uint32_t tmp;
int32_t ret;
tmp = hri_cmcc_read_CFG_reg(hw);
tmp &= (~CMCC_CFG_CSIZESW_Msk);
tmp |= (size << CMCC_CFG_CSIZESW_Pos);
ret = _cmcc_disable(hw);
hri_cmcc_write_CFG_reg(hw, tmp);
ret = _cmcc_enable(hw);
return ret;
}
/**
* \brief Lock the mentioned WAY in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num_index" enumerator
*
* \return status of operation
*/
int32_t _cmcc_lock_way(const void *hw, enum way_num_index num)
{
uint32_t tmp;
int32_t ret;
tmp = hri_cmcc_read_LCKWAY_reg(hw);
tmp |= CMCC_LCKWAY_LCKWAY(num);
ret = _cmcc_disable(hw);
hri_cmcc_write_LCKWAY_reg(hw, tmp);
ret = _cmcc_enable(hw);
return ret;
}
/**
* \brief Unlock the mentioned WAY in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num_index" enumerator
*
* \return status of operation
*/
int32_t _cmcc_unlock_way(const void *hw, enum way_num_index num)
{
uint32_t tmp;
int32_t ret;
tmp = hri_cmcc_read_LCKWAY_reg(hw);
tmp &= (~CMCC_LCKWAY_LCKWAY(num));
ret = _cmcc_disable(hw);
hri_cmcc_write_LCKWAY_reg(hw, tmp);
ret = _cmcc_enable(hw);
return ret;
}
/**
* \brief Invalidate the mentioned cache line in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num" enumerator (valid arg is 0-3)
* \param[in] line number (valid arg is 0-63 as each way will have 64 lines)
*
* \return status of operation
*/
int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num)
{
int32_t return_value;
if ((way_num < CMCC_WAY_NOS) && (line_num < CMCC_LINE_NOS)) {
_cmcc_disable(hw);
while (!(_is_cache_disabled(hw)))
;
hri_cmcc_write_MAINT1_reg(hw, (CMCC_MAINT1_INDEX(line_num) | CMCC_MAINT1_WAY(way_num)));
return_value = ERR_NONE;
} else {
return_value = ERR_INVALID_ARG;
}
return return_value;
}
/**
* \brief Invalidate entire cache entries in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_invalidate_all(const void *hw)
{
int32_t return_value;
_cmcc_disable(hw);
if (_is_cache_disabled(hw)) {
hri_cmcc_write_MAINT0_reg(hw, CMCC_MAINT0_INVALL);
return_value = ERR_NONE;
} else {
return_value = ERR_FAILURE;
}
return return_value;
}
/**
* \brief Configure cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from cache monitor configurations enumerator
*
* \return status of operation
*/
int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg)
{
hri_cmcc_write_MCFG_reg(hw, CMCC_MCFG_MODE(monitor_cfg));
return ERR_NONE;
}
/**
* \brief Enable cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_enable_monitor(const void *hw)
{
hri_cmcc_write_MEN_reg(hw, CMCC_MEN_MENABLE);
return ERR_NONE;
}
/**
* \brief Disable cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_disable_monitor(const void *hw)
{
hri_cmcc_write_MEN_reg(hw, (CMCC_MONITOR_DISABLE << CMCC_MEN_MENABLE_Pos));
return ERR_NONE;
}
/**
* \brief Reset cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_reset_monitor(const void *hw)
{
hri_cmcc_write_MCTRL_reg(hw, CMCC_MCTRL_SWRST);
return ERR_NONE;
}
/**
* \brief Get cache monitor event counter value from CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return event counter value
*/
uint32_t _cmcc_get_monitor_event_count(const void *hw)
{
return hri_cmcc_read_MSR_reg(hw);
}

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Examples/SPISLAVEDMA/SPISLAVEDMA(3)/hpl/core/hpl_core_m4.c Normal file
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/**
* \file
*
* \brief Core related functionality implementation.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_core.h>
#include <hpl_irq.h>
#ifndef _UNIT_TEST_
#include <utils.h>
#endif
#include <utils_assert.h>
#include <peripheral_clk_config.h>
#ifndef CONF_CPU_FREQUENCY
#define CONF_CPU_FREQUENCY 1000000
#endif
#if CONF_CPU_FREQUENCY < 1000
#define CPU_FREQ_POWER 3
#elif CONF_CPU_FREQUENCY < 10000
#define CPU_FREQ_POWER 4
#elif CONF_CPU_FREQUENCY < 100000
#define CPU_FREQ_POWER 5
#elif CONF_CPU_FREQUENCY < 1000000
#define CPU_FREQ_POWER 6
#elif CONF_CPU_FREQUENCY < 10000000
#define CPU_FREQ_POWER 7
#elif CONF_CPU_FREQUENCY < 100000000
#define CPU_FREQ_POWER 8
#elif CONF_CPU_FREQUENCY < 1000000000
#define CPU_FREQ_POWER 9
#endif
/**
* \brief The array of interrupt handlers
*/
struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn];
/**
* \brief Reset MCU
*/
void _reset_mcu(void)
{
NVIC_SystemReset();
}
/**
* \brief Put MCU to sleep
*/
void _go_to_sleep(void)
{
__DSB();
__WFI();
}
/**
* \brief Retrieve current IRQ number
*/
uint8_t _irq_get_current(void)
{
return (uint8_t)__get_IPSR() - 16;
}
/**
* \brief Disable the given IRQ
*/
void _irq_disable(uint8_t n)
{
NVIC_DisableIRQ((IRQn_Type)n);
}
/**
* \brief Set the given IRQ
*/
void _irq_set(uint8_t n)
{
NVIC_SetPendingIRQ((IRQn_Type)n);
}
/**
* \brief Clear the given IRQ
*/
void _irq_clear(uint8_t n)
{
NVIC_ClearPendingIRQ((IRQn_Type)n);
}
/**
* \brief Enable the given IRQ
*/
void _irq_enable(uint8_t n)
{
NVIC_EnableIRQ((IRQn_Type)n);
}
/**
* \brief Register IRQ handler
*/
void _irq_register(const uint8_t n, struct _irq_descriptor *const irq)
{
ASSERT(n < PERIPH_COUNT_IRQn);
_irq_table[n] = irq;
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Default_Handler(void)
{
while (1) {
}
}
/**
* \brief Retrieve the amount of cycles to delay for the given amount of us
*/
static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power)
{
switch (power) {
case 9:
return (us * (freq / 1000000) + 2) / 3;
case 8:
return (us * (freq / 100000) + 29) / 30;
case 7:
return (us * (freq / 10000) + 299) / 300;
case 6:
return (us * (freq / 1000) + 2999) / 3000;
case 5:
return (us * (freq / 100) + 29999) / 30000;
case 4:
return (us * (freq / 10) + 299999) / 300000;
default:
return (us * freq + 2999999) / 3000000;
}
}
/**
* \brief Retrieve the amount of cycles to delay for the given amount of us
*/
uint32_t _get_cycles_for_us(const uint16_t us)
{
return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER);
}
/**
* \brief Retrieve the amount of cycles to delay for the given amount of ms
*/
static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power)
{
switch (power) {
case 9:
return (ms * (freq / 1000000) + 2) / 3 * 1000;
case 8:
return (ms * (freq / 100000) + 2) / 3 * 100;
case 7:
return (ms * (freq / 10000) + 2) / 3 * 10;
case 6:
return (ms * (freq / 1000) + 2) / 3;
case 5:
return (ms * (freq / 100) + 29) / 30;
case 4:
return (ms * (freq / 10) + 299) / 300;
default:
return (ms * (freq / 1) + 2999) / 3000;
}
}
/**
* \brief Retrieve the amount of cycles to delay for the given amount of ms
*/
uint32_t _get_cycles_for_ms(const uint16_t ms)
{
return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER);
}
/**
* \brief Initialize delay functionality
*/
void _delay_init(void *const hw)
{
(void)hw;
}
/**
* \brief Delay loop to delay n number of cycles
*/
void _delay_cycles(void *const hw, uint32_t cycles)
{
#ifndef _UNIT_TEST_
(void)hw;
(void)cycles;
#if defined(__GNUC__) && (__ARMCOMPILER_VERSION > 6000000) /* Keil MDK with ARM Compiler 6 */
__asm(".align 3 \n"
"__delay:\n"
"subs r1, r1, #1\n"
"bhi __delay\n");
#elif defined __GNUC__
__asm(".syntax unified\n"
".align 3 \n"
"__delay:\n"
"subs r1, r1, #1\n"
"bhi __delay\n"
".syntax divided");
#elif defined __CC_ARM
__asm("__delay:\n"
"subs cycles, cycles, #1\n"
"bhi __delay\n");
#elif defined __ICCARM__
__asm("__delay:\n"
"subs r1, r1, #1\n"
"bhi.n __delay\n");
#endif
#endif
}

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Examples/SPISLAVEDMA/SPISLAVEDMA(3)/hpl/core/hpl_core_port.h Normal file
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/**
* \file
*
* \brief Core related functionality implementation.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_CORE_PORT_H_INCLUDED
#define _HPL_CORE_PORT_H_INCLUDED
#include <peripheral_clk_config.h>
/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR
* portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h),
* there will be assembling errors.
* So the following things are not included for assembling.
*/
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#ifndef _UNIT_TEST_
#include <compiler.h>
#endif
/**
* \brief Check if it's in ISR handling
* \return \c true if it's in ISR
*/
static inline bool _is_in_isr(void)
{
return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk);
}
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _HPL_CORE_PORT_H_INCLUDED */

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Examples/SPISLAVEDMA/SPISLAVEDMA(3)/hpl/core/hpl_init.c Normal file
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/**
* \file
*
* \brief HPL initialization related functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_gpio.h>
#include <hpl_init.h>
#include <hpl_gclk_base.h>
#include <hpl_mclk_config.h>
#include <hpl_dma.h>
#include <hpl_dmac_config.h>
#include <hpl_cmcc_config.h>
#include <hal_cache.h>
/* Referenced GCLKs (out of 0~11), should be initialized firstly
*/
#define _GCLK_INIT_1ST 0x00000000
/* Not referenced GCLKs, initialized last */
#define _GCLK_INIT_LAST 0x00000FFF
/**
* \brief Initialize the hardware abstraction layer
*/
void _init_chip(void)
{
hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
_osc32kctrl_init_sources();
_oscctrl_init_sources();
_mclk_init();
#if _GCLK_INIT_1ST
_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
#endif
_oscctrl_init_referenced_generators();
_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
#if CONF_DMAC_ENABLE
hri_mclk_set_AHBMASK_DMAC_bit(MCLK);
_dma_init();
#endif
#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3)
_port_event_init();
#endif
#if CONF_CMCC_ENABLE
cache_init();
#endif
}

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Examples/SPISLAVEDMA/SPISLAVEDMA(3)/hpl/dmac/hpl_dmac.c Normal file
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/**
* \file
*
* \brief Generic DMAC related functionality.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_dma.h>
#include <utils_assert.h>
#include <utils.h>
#include <hpl_dmac_config.h>
#include <utils_repeat_macro.h>
/* Section containing first descriptors for all DMAC channels */
COMPILER_ALIGNED(16)
DmacDescriptor _descriptor_section[DMAC_CH_NUM];
/* Section containing current descriptors for all DMAC channels */
COMPILER_ALIGNED(16)
DmacDescriptor _write_back_section[DMAC_CH_NUM];
/* Array containing callbacks for DMAC channels */
static struct _dma_resource _resources[DMAC_CH_NUM];
/* DMAC interrupt handler */
static void _dmac_handler(void);
/* This macro DMAC configuration */
#define DMAC_CHANNEL_CFG(i, n) \
{(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | DMAC_CHCTRLA_TRIGACT(CONF_DMAC_TRIGACT_##n) \
| DMAC_CHCTRLA_TRIGSRC(CONF_DMAC_TRIGSRC_##n), \
DMAC_CHPRILVL_PRILVL(CONF_DMAC_LVL_##n), \
(CONF_DMAC_EVIE_##n << DMAC_CHEVCTRL_EVIE_Pos) | (CONF_DMAC_EVOE_##n << DMAC_CHEVCTRL_EVOE_Pos) \
| (CONF_DMAC_EVACT_##n << DMAC_CHEVCTRL_EVACT_Pos), \
DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \
| (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \
| DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \
| DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)},
/* DMAC channel configuration */
struct dmac_channel_cfg {
uint32_t ctrla;
uint8_t prilvl;
uint8_t evctrl;
uint16_t btctrl;
};
/* DMAC channel configurations */
const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)};
/**
* \brief Initialize DMAC
*/
int32_t _dma_init(void)
{
uint8_t i;
hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC);
hri_dmac_clear_CRCCTRL_reg(DMAC, DMAC_CRCCTRL_CRCSRC_Msk);
hri_dmac_set_CTRL_SWRST_bit(DMAC);
while (hri_dmac_get_CTRL_SWRST_bit(DMAC))
;
hri_dmac_write_CTRL_reg(DMAC,
(CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos)
| (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos)
| (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos));
hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN);
hri_dmac_write_PRICTRL0_reg(
DMAC,
DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1)
| DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3)
| (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos)
| (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos));
hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section);
hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section);
for (i = 0; i < DMAC_CH_NUM; i++) {
hri_dmac_write_CHCTRLA_reg(DMAC, i, _cfgs[i].ctrla);
hri_dmac_write_CHPRILVL_reg(DMAC, i, _cfgs[i].prilvl);
hri_dmac_write_CHEVCTRL_reg(DMAC, i, _cfgs[i].evctrl);
hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl);
hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0);
}
for (i = 0; i < 5; i++) {
NVIC_DisableIRQ(DMAC_0_IRQn + i);
NVIC_ClearPendingIRQ(DMAC_0_IRQn + i);
NVIC_EnableIRQ(DMAC_0_IRQn + i);
}
hri_dmac_set_CTRL_DMAENABLE_bit(DMAC);
return ERR_NONE;
}
/**
* \brief Enable/disable DMA interrupt
*/
void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state)
{
if (DMA_TRANSFER_COMPLETE_CB == type) {
hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, channel, state);
} else if (DMA_TRANSFER_ERROR_CB == type) {
hri_dmac_write_CHINTEN_TERR_bit(DMAC, channel, state);
}
}
int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst)
{
hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst);
return ERR_NONE;
}
int32_t _dma_set_source_address(const uint8_t channel, const void *const src)
{
hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src);
return ERR_NONE;
}
int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel)
{
hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel],
(uint32_t)&_descriptor_section[next_channel]);
return ERR_NONE;
}
int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable)
{
hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable);
return ERR_NONE;
}
int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount)
{
uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]);
uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]);
if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) {
hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size));
}
address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]);
if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) {
hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size));
}
hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount);
return ERR_NONE;
}
int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger)
{
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]);
hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC, channel);
if (software_trigger) {
hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel);
}
return ERR_NONE;
}
int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel)
{
*resource = &_resources[channel];
return ERR_NONE;
}
int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable)
{
hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable);
return ERR_NONE;
}
/**
* \internal DMAC interrupt handler
*/
static void _dmac_handler(void)
{
uint8_t channel = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk);
struct _dma_resource *tmp_resource = &_resources[channel];
if (hri_dmac_get_INTPEND_TERR_bit(DMAC)) {
hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel);
tmp_resource->dma_cb.error(tmp_resource);
} else if (hri_dmac_get_INTPEND_TCMPL_bit(DMAC)) {
hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC, channel);
tmp_resource->dma_cb.transfer_done(tmp_resource);
}
}
/**
* \brief DMAC interrupt handler
*/
void DMAC_0_Handler(void)
{
_dmac_handler();
}
/**
* \brief DMAC interrupt handler
*/
void DMAC_1_Handler(void)
{
_dmac_handler();
}
/**
* \brief DMAC interrupt handler
*/
void DMAC_2_Handler(void)
{
_dmac_handler();
}
/**
* \brief DMAC interrupt handler
*/
void DMAC_3_Handler(void)
{
_dmac_handler();
}
/**
* \brief DMAC interrupt handler
*/
void DMAC_4_Handler(void)
{
_dmac_handler();
}

312
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/hpl/gclk/hpl_gclk.c Normal file
View File

@@ -0,0 +1,312 @@
/**
* \file
*
* \brief Generic Clock Controller related functionality.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_gclk_config.h>
#include <hpl_init.h>
#include <utils_assert.h>
/**
* \brief Initializes generators
*/
void _gclk_init_generators(void)
{
#if CONF_GCLK_GENERATOR_0_CONFIG == 1
hri_gclk_write_GENCTRL_reg(
GCLK,
0,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE);
#endif
#if CONF_GCLK_GENERATOR_1_CONFIG == 1
hri_gclk_write_GENCTRL_reg(
GCLK,
1,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE);
#endif
#if CONF_GCLK_GENERATOR_2_CONFIG == 1
hri_gclk_write_GENCTRL_reg(
GCLK,
2,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE);
#endif
#if CONF_GCLK_GENERATOR_3_CONFIG == 1
hri_gclk_write_GENCTRL_reg(
GCLK,
3,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE);
#endif
#if CONF_GCLK_GENERATOR_4_CONFIG == 1
hri_gclk_write_GENCTRL_reg(
GCLK,
4,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE);
#endif
#if CONF_GCLK_GENERATOR_5_CONFIG == 1
hri_gclk_write_GENCTRL_reg(
GCLK,
5,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE);
#endif
#if CONF_GCLK_GENERATOR_6_CONFIG == 1
hri_gclk_write_GENCTRL_reg(
GCLK,
6,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE);
#endif
#if CONF_GCLK_GENERATOR_7_CONFIG == 1
hri_gclk_write_GENCTRL_reg(
GCLK,
7,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE);
#endif
#if CONF_GCLK_GENERATOR_8_CONFIG == 1
hri_gclk_write_GENCTRL_reg(
GCLK,
8,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE);
#endif
#if CONF_GCLK_GENERATOR_9_CONFIG == 1
hri_gclk_write_GENCTRL_reg(
GCLK,
9,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE);
#endif
#if CONF_GCLK_GENERATOR_10_CONFIG == 1
hri_gclk_write_GENCTRL_reg(
GCLK,
10,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE);
#endif
#if CONF_GCLK_GENERATOR_11_CONFIG == 1
hri_gclk_write_GENCTRL_reg(
GCLK,
11,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE);
#endif
}
void _gclk_init_generators_by_fref(uint32_t bm)
{
#if CONF_GCLK_GENERATOR_0_CONFIG == 1
if (bm & (1ul << 0)) {
hri_gclk_write_GENCTRL_reg(
GCLK,
0,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE);
}
#endif
#if CONF_GCLK_GENERATOR_1_CONFIG == 1
if (bm & (1ul << 1)) {
hri_gclk_write_GENCTRL_reg(
GCLK,
1,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE);
}
#endif
#if CONF_GCLK_GENERATOR_2_CONFIG == 1
if (bm & (1ul << 2)) {
hri_gclk_write_GENCTRL_reg(
GCLK,
2,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE);
}
#endif
#if CONF_GCLK_GENERATOR_3_CONFIG == 1
if (bm & (1ul << 3)) {
hri_gclk_write_GENCTRL_reg(
GCLK,
3,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE);
}
#endif
#if CONF_GCLK_GENERATOR_4_CONFIG == 1
if (bm & (1ul << 4)) {
hri_gclk_write_GENCTRL_reg(
GCLK,
4,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE);
}
#endif
#if CONF_GCLK_GENERATOR_5_CONFIG == 1
if (bm & (1ul << 5)) {
hri_gclk_write_GENCTRL_reg(
GCLK,
5,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE);
}
#endif
#if CONF_GCLK_GENERATOR_6_CONFIG == 1
if (bm & (1ul << 6)) {
hri_gclk_write_GENCTRL_reg(
GCLK,
6,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE);
}
#endif
#if CONF_GCLK_GENERATOR_7_CONFIG == 1
if (bm & (1ul << 7)) {
hri_gclk_write_GENCTRL_reg(
GCLK,
7,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE);
}
#endif
#if CONF_GCLK_GENERATOR_8_CONFIG == 1
if (bm & (1ul << 8)) {
hri_gclk_write_GENCTRL_reg(
GCLK,
8,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE);
}
#endif
#if CONF_GCLK_GENERATOR_9_CONFIG == 1
if (bm & (1ul << 9)) {
hri_gclk_write_GENCTRL_reg(
GCLK,
9,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE);
}
#endif
#if CONF_GCLK_GENERATOR_10_CONFIG == 1
if (bm & (1ul << 10)) {
hri_gclk_write_GENCTRL_reg(
GCLK,
10,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE);
}
#endif
#if CONF_GCLK_GENERATOR_11_CONFIG == 1
if (bm & (1ul << 11)) {
hri_gclk_write_GENCTRL_reg(
GCLK,
11,
GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
| (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE);
}
#endif
}

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/**
* \file
*
* \brief Generic Clock Controller.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_GCLK_H_INCLUDED
#define _HPL_GCLK_H_INCLUDED
#include <compiler.h>
#ifdef _UNIT_TEST_
#include <hri_gclk1_v210_mock.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup gclk_group GCLK Hardware Proxy Layer
*
* \section gclk_hpl_rev Revision History
* - v0.0.0.1 Initial Commit
*
*@{
*/
/**
* \name HPL functions
*/
//@{
/**
* \brief Enable clock on the given channel with the given clock source
*
* This function maps the given clock source to the given clock channel
* and enables channel.
*
* \param[in] channel The channel to enable clock for
* \param[in] source The clock source for the given channel
*/
static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source)
{
hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN);
}
/**
* \brief Initialize GCLK generators by function references
* \param[in] bm Bit mapping for referenced generators,
* a bit 1 in position triggers generator initialization.
*/
void _gclk_init_generators_by_fref(uint32_t bm);
//@}
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HPL_GCLK_H_INCLUDED */

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Examples/SPISLAVEDMA/SPISLAVEDMA(3)/hpl/mclk/hpl_mclk.c Normal file
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/**
* \file
*
* \brief SAM Main Clock.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <compiler.h>
#include <hpl_mclk_config.h>
/**
* \brief Initialize master clock generator
*/
void _mclk_init(void)
{
void *hw = (void *)MCLK;
hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV));
}

82
Examples/SPISLAVEDMA/SPISLAVEDMA(3)/hpl/osc32kctrl/hpl_osc32kctrl.c Normal file
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/**
* \file
*
* \brief SAM 32k Oscillators Controller.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_init.h>
#include <hpl_osc32kctrl_config.h>
/**
* \brief Initialize 32 kHz clock sources
*/
void _osc32kctrl_init_sources(void)
{
void * hw = (void *)OSC32KCTRL;
uint16_t calib = 0;
#if CONF_XOSC32K_CONFIG == 1
hri_osc32kctrl_write_XOSC32K_reg(
hw,
OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
| (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
| (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos)
| (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) |
#ifdef CONF_XOSC32K_CGM
OSC32KCTRL_XOSC32K_CGM(CONF_XOSC32K_CGM) |
#endif
(CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos));
hri_osc32kctrl_write_CFDCTRL_reg(hw, (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos));
hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos));
#endif
#if CONF_OSCULP32K_CONFIG == 1
calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw);
hri_osc32kctrl_write_OSCULP32K_reg(hw,
#if CONF_OSCULP32K_CALIB_ENABLE == 1
OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB)
#else
OSC32KCTRL_OSCULP32K_CALIB(calib)
#endif
);
#endif
#if CONF_XOSC32K_CONFIG
#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0
while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw))
;
#endif
#endif
hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL));
(void)calib;
}

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/**
* \file
*
* \brief SAM Oscillators Controller.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_init.h>
#include <hpl_oscctrl_config.h>
#include <hpl_gclk_config.h>
/**
* \brief Initialize clock sources
*/
void _oscctrl_init_sources(void)
{
void *hw = (void *)OSCCTRL;
#if CONF_XOSC0_CONFIG == 1
hri_oscctrl_write_XOSCCTRL_reg(
hw,
0,
OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC0_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC0_STARTUP)
| (CONF_XOSC0_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC0_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos)
| (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC0_IMULT)
| OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC0_IPTAT) | (CONF_XOSC0_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos)
| (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC0_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)
| (CONF_XOSC0_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC0_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos));
#endif
#if CONF_XOSC0_CONFIG == 1
#if CONF_XOSC0_ENABLE == 1
while (!hri_oscctrl_get_STATUS_XOSCRDY0_bit(hw))
;
#endif
#if CONF_XOSC0_ENALC == 1
hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 0);
#endif
#if CONF_XOSC0_ONDEMAND == 1
hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 0);
#endif
#endif
#if CONF_XOSC1_CONFIG == 1
hri_oscctrl_write_XOSCCTRL_reg(
hw,
1,
OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC1_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC1_STARTUP)
| (CONF_XOSC1_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC1_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos)
| (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC1_IMULT)
| OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC1_IPTAT) | (CONF_XOSC1_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos)
| (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC1_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)
| (CONF_XOSC1_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC1_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos));
#endif
#if CONF_XOSC1_CONFIG == 1
#if CONF_XOSC1_ENABLE == 1
while (!hri_oscctrl_get_STATUS_XOSCRDY1_bit(hw))
;
#endif
#if CONF_XOSC1_ENALC == 1
hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 1);
#endif
#if CONF_XOSC1_ONDEMAND == 1
hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1);
#endif
#endif
(void)hw;
}
void _oscctrl_init_referenced_generators(void)
{
void *hw = (void *)OSCCTRL;
#if CONF_DFLL_CONFIG == 1
hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, GCLK_GENCTRL_SRC_OSCULP32K);
while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK))
;
uint8_t tmp;
hri_oscctrl_write_DFLLCTRLA_reg(hw, 0);
#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0
hri_gclk_write_PCHCTRL_reg(
GCLK, OSCCTRL_GCLK_ID_DFLL48, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK));
#endif
hri_oscctrl_write_DFLLMUL_reg(hw,
OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP)
| OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL));
while (hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(hw))
;
hri_oscctrl_write_DFLLCTRLB_reg(hw, 0);
while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw))
;
tmp = (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) | OSCCTRL_DFLLCTRLA_ENABLE;
hri_oscctrl_write_DFLLCTRLA_reg(hw, tmp);
while (hri_oscctrl_get_DFLLSYNC_ENABLE_bit(hw))
;
#if CONF_DFLL_OVERWRITE_CALIBRATION == 1
hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE));
#endif
hri_oscctrl_write_DFLLVAL_reg(hw, hri_oscctrl_read_DFLLVAL_reg(hw));
while (hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(hw))
;
tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRLB_BPLCKC_Pos)
| (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRLB_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRLB_CCDIS_Pos)
| (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRLB_USBCRM_Pos) | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRLB_LLAW_Pos)
| (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRLB_STABLE_Pos) | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRLB_MODE_Pos) | 0;
hri_oscctrl_write_DFLLCTRLB_reg(hw, tmp);
while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw))
;
#endif
#if CONF_FDPLL0_CONFIG == 1
#if CONF_FDPLL0_REFCLK == 0
hri_gclk_write_PCHCTRL_reg(
GCLK, OSCCTRL_GCLK_ID_FDPLL0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL0_GCLK));
#endif
hri_oscctrl_write_DPLLRATIO_reg(
hw, 0, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL0_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL0_LDR));
hri_oscctrl_write_DPLLCTRLB_reg(
hw,
0,
OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL0_DIV) | (CONF_FDPLL0_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos)
| OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL0_DCOFILTER)
| (CONF_FDPLL0_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL0_LTIME)
| OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL0_REFCLK) | (CONF_FDPLL0_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos)
| OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL0_FILTER));
hri_oscctrl_write_DPLLCTRLA_reg(hw,
0,
(CONF_FDPLL0_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
| (CONF_FDPLL0_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos));
#endif
#if CONF_FDPLL1_CONFIG == 1
#if CONF_FDPLL1_REFCLK == 0
hri_gclk_write_PCHCTRL_reg(
GCLK, OSCCTRL_GCLK_ID_FDPLL1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL1_GCLK));
#endif
hri_oscctrl_write_DPLLRATIO_reg(
hw, 1, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL1_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL1_LDR));
hri_oscctrl_write_DPLLCTRLB_reg(
hw,
1,
OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL1_DIV) | (CONF_FDPLL1_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos)
| OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL1_DCOFILTER)
| (CONF_FDPLL1_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL1_LTIME)
| OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL1_REFCLK) | (CONF_FDPLL1_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos)
| OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL1_FILTER));
hri_oscctrl_write_DPLLCTRLA_reg(hw,
1,
(CONF_FDPLL1_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
| (CONF_FDPLL1_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos));
#endif
#if CONF_DFLL_CONFIG == 1
if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(hw)) {
hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC;
while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask)
;
} else {
while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw))
;
}
#if CONF_DFLL_ONDEMAND == 1
hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(hw);
#endif
#endif
#if CONF_FDPLL0_CONFIG == 1
#if CONF_FDPLL0_ENABLE == 1
while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0)))
;
#endif
#if CONF_FDPLL0_ONDEMAND == 1
hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 0);
#endif
#endif
#if CONF_FDPLL1_CONFIG == 1
#if CONF_FDPLL1_ENABLE == 1
while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 1) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 1)))
;
#endif
#if CONF_FDPLL1_ONDEMAND == 1
hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 1);
#endif
#endif
#if CONF_DFLL_CONFIG == 1
while (hri_gclk_read_SYNCBUSY_reg(GCLK))
;
hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE);
while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK))
;
#endif
(void)hw;
}

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/**
* \file
*
* \brief SAM Power manager
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_sleep.h>
#include <hpl_init.h>
/**
* \brief Set the sleep mode for the device
*/
int32_t _set_sleep_mode(const uint8_t mode)
{
uint8_t delay = 10;
switch (mode) {
case 2:
case 4:
case 5:
case 6:
case 7:
hri_pm_write_SLEEPCFG_reg(PM, mode);
/* A small latency happens between the store instruction and actual
* writing of the SLEEPCFG register due to bridges. Software has to make
* sure the SLEEPCFG register reads the wanted value before issuing WFI
* instruction.
*/
do {
if (hri_pm_read_SLEEPCFG_reg(PM) == mode) {
break;
}
} while (--delay);
break;
default:
return ERR_INVALID_ARG;
}
return ERR_NONE;
}

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/**
* \file
*
* \brief SAM Power manager
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*/
#ifndef _HPL_PM_BASE_H_INCLUDED
#define _HPL_PM_BASE_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include <utils_assert.h>
#ifdef __cplusplus
}
#endif
#endif /* _HPL_PM_BASE_H_INCLUDED */

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/**
* \file
*
* \brief SAM PORT.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <compiler.h>
#include <hpl_gpio.h>
#include <utils_assert.h>
#include <hpl_port_config.h>
/**
* \brief Set direction on port with mask
*/
static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
const enum gpio_direction direction)
{
switch (direction) {
case GPIO_DIRECTION_OFF:
hri_port_clear_DIR_reg(PORT, port, mask);
hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff));
hri_port_write_WRCONFIG_reg(
PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16));
break;
case GPIO_DIRECTION_IN:
hri_port_clear_DIR_reg(PORT, port, mask);
hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff));
hri_port_write_WRCONFIG_reg(PORT,
port,
PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN
| ((mask & 0xffff0000) >> 16));
break;
case GPIO_DIRECTION_OUT:
hri_port_set_DIR_reg(PORT, port, mask);
hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff));
hri_port_write_WRCONFIG_reg(
PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16));
break;
default:
ASSERT(false);
}
}
/**
* \brief Set output level on port with mask
*/
static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level)
{
if (level) {
hri_port_set_OUT_reg(PORT, port, mask);
} else {
hri_port_clear_OUT_reg(PORT, port, mask);
}
}
/**
* \brief Change output level to the opposite with mask
*/
static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask)
{
hri_port_toggle_OUT_reg(PORT, port, mask);
}
/**
* \brief Get input levels on all port pins
*/
static inline uint32_t _gpio_get_level(const enum gpio_port port)
{
uint32_t tmp;
CRITICAL_SECTION_ENTER();
uint32_t dir_tmp = hri_port_read_DIR_reg(PORT, port);
tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp;
tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp;
CRITICAL_SECTION_LEAVE();
return tmp;
}
/**
* \brief Set pin pull mode
*/
static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin,
const enum gpio_pull_mode pull_mode)
{
switch (pull_mode) {
case GPIO_PULL_OFF:
hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin);
break;
case GPIO_PULL_UP:
hri_port_clear_DIR_reg(PORT, port, 1U << pin);
hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin);
hri_port_set_OUT_reg(PORT, port, 1U << pin);
break;
case GPIO_PULL_DOWN:
hri_port_clear_DIR_reg(PORT, port, 1U << pin);
hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin);
hri_port_clear_OUT_reg(PORT, port, 1U << pin);
break;
default:
ASSERT(false);
break;
}
}
/**
* \brief Set gpio pin function
*/
static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function)
{
uint8_t port = GPIO_PORT(gpio);
uint8_t pin = GPIO_PIN(gpio);
if (function == GPIO_PIN_FUNCTION_OFF) {
hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false);
} else {
hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true);
if (pin & 1) {
// Odd numbered pin
hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff);
} else {
// Even numbered pin
hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff);
}
}
}
static inline void _port_event_init()
{
hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL);
hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL);
hri_port_set_EVCTRL_reg(PORT, 2, CONF_PORTC_EVCTRL);
hri_port_set_EVCTRL_reg(PORT, 3, CONF_PORTD_EVCTRL);
}

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/**
* \file
*
* \brief Generic RAMECC related functionality.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <utils.h>
#include <utils_assert.h>
#include <hpl_ramecc.h>
/* RAMECC device descriptor */
struct _ramecc_device device;
/**
* \brief Initialize RAMECC
*/
int32_t _ramecc_init(void)
{
if (hri_ramecc_get_STATUS_ECCDIS_bit(RAMECC)) {
return ERR_ABORTED;
}
NVIC_DisableIRQ(RAMECC_IRQn);
NVIC_ClearPendingIRQ(RAMECC_IRQn);
NVIC_EnableIRQ(RAMECC_IRQn);
return ERR_NONE;
}
void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb)
{
if (RAMECC_DUAL_ERROR_CB == type) {
device.ramecc_cb.dual_bit_err = cb;
hri_ramecc_write_INTEN_DUALE_bit(RAMECC, NULL != cb);
} else if (RAMECC_SINGLE_ERROR_CB == type) {
device.ramecc_cb.single_bit_err = cb;
hri_ramecc_write_INTEN_SINGLEE_bit(RAMECC, NULL != cb);
}
}
/**
* \internal RAMECC interrupt handler
*/
void RAMECC_Handler(void)
{
struct _ramecc_device *dev = (struct _ramecc_device *)&device;
volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC);
if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) {
dev->ramecc_cb.dual_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
} else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) {
dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
} else {
return;
}
}

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