diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.env_conf b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.env_conf
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.env_conf
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.env_conf
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.gpdsc b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.gpdsc
new file mode 100644
index 0000000..0fee133
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.gpdsc
@@ -0,0 +1,240 @@
+
+ Atmel
+ My Project
+ Project generated by Atmel Start
+ http://start.atmel.com/
+
+ Initial version
+
+
+ Configuration Files generated by Atmel Start
+
+
+
+ Atmel Start
+
+ http://start.atmel.com/
+
+
+
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+
+ Dependency on CMSIS core and Device Startup components
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+ Atmel Start Framework
+ #define ATMEL_START
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diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/atmel_start_config.atstart b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/atmel_start_config.atstart
new file mode 100644
index 0000000..114dc77
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/atmel_start_config.atstart
@@ -0,0 +1,1665 @@
+format_version: '2'
+name: My Project
+versions:
+ api: '1.0'
+ backend: 1.8.580
+ commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c
+ content: unknown
+ content_pack_name: unknown
+ format: '2'
+ frontend: 1.8.580
+ packs_version_avr8: 1.0.1463
+ packs_version_qtouch: unknown
+ packs_version_sam: 1.0.1726
+ version_backend: 1.8.580
+ version_frontend: ''
+board:
+ identifier: SAME54XplainedPro
+ device: SAME54P20A-AU
+details: null
+application: null
+middlewares:
+ STDIO_REDIRECT_0:
+ user_label: STDIO_REDIRECT_0
+ configuration: {}
+ definition: Atmel:STDIO_redirect:0.0.1::STDIO_Redirect
+ functionality: STDIO_Redirect
+ api: STDIO:Redirect:IO
+ dependencies:
+ Target IO: TARGET_IO
+drivers:
+ CMCC:
+ user_label: CMCC
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC
+ functionality: System
+ api: HAL:HPL:CMCC
+ configuration:
+ cache_size: 4 KB
+ cmcc_advanced_configuration: false
+ cmcc_clock_gating_disable: false
+ cmcc_data_cache_disable: false
+ cmcc_enable: false
+ cmcc_inst_cache_disable: false
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ DMAC:
+ user_label: DMAC
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
+ functionality: System
+ api: HAL:HPL:DMAC
+ configuration:
+ dmac_beatsize_0: 8-bit bus transfer
+ dmac_beatsize_1: 8-bit bus transfer
+ dmac_beatsize_10: 8-bit bus transfer
+ dmac_beatsize_11: 8-bit bus transfer
+ dmac_beatsize_12: 8-bit bus transfer
+ dmac_beatsize_13: 8-bit bus transfer
+ dmac_beatsize_14: 8-bit bus transfer
+ dmac_beatsize_15: 8-bit bus transfer
+ dmac_beatsize_16: 8-bit bus transfer
+ dmac_beatsize_17: 8-bit bus transfer
+ dmac_beatsize_18: 8-bit bus transfer
+ dmac_beatsize_19: 8-bit bus transfer
+ dmac_beatsize_2: 8-bit bus transfer
+ dmac_beatsize_20: 8-bit bus transfer
+ dmac_beatsize_21: 8-bit bus transfer
+ dmac_beatsize_22: 8-bit bus transfer
+ dmac_beatsize_23: 8-bit bus transfer
+ dmac_beatsize_24: 8-bit bus transfer
+ dmac_beatsize_25: 8-bit bus transfer
+ dmac_beatsize_26: 8-bit bus transfer
+ dmac_beatsize_27: 8-bit bus transfer
+ dmac_beatsize_28: 8-bit bus transfer
+ dmac_beatsize_29: 8-bit bus transfer
+ dmac_beatsize_3: 8-bit bus transfer
+ dmac_beatsize_30: 8-bit bus transfer
+ dmac_beatsize_31: 8-bit bus transfer
+ dmac_beatsize_4: 8-bit bus transfer
+ dmac_beatsize_5: 8-bit bus transfer
+ dmac_beatsize_6: 8-bit bus transfer
+ dmac_beatsize_7: 8-bit bus transfer
+ dmac_beatsize_8: 8-bit bus transfer
+ dmac_beatsize_9: 8-bit bus transfer
+ dmac_blockact_0: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_1: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_10: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_11: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_12: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_13: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_14: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_15: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_16: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_17: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_18: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_19: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_2: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_20: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_21: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_22: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_23: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_24: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_25: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_26: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_27: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_28: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_29: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_3: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_30: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_31: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_4: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_5: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_6: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_7: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_8: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_9: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_channel_0_settings: false
+ dmac_channel_10_settings: false
+ dmac_channel_11_settings: false
+ dmac_channel_12_settings: false
+ dmac_channel_13_settings: false
+ dmac_channel_14_settings: false
+ dmac_channel_15_settings: false
+ dmac_channel_16_settings: false
+ dmac_channel_17_settings: false
+ dmac_channel_18_settings: false
+ dmac_channel_19_settings: false
+ dmac_channel_1_settings: false
+ dmac_channel_20_settings: false
+ dmac_channel_21_settings: false
+ dmac_channel_22_settings: false
+ dmac_channel_23_settings: false
+ dmac_channel_24_settings: false
+ dmac_channel_25_settings: false
+ dmac_channel_26_settings: false
+ dmac_channel_27_settings: false
+ dmac_channel_28_settings: false
+ dmac_channel_29_settings: false
+ dmac_channel_2_settings: true
+ dmac_channel_30_settings: false
+ dmac_channel_31_settings: false
+ dmac_channel_3_settings: true
+ dmac_channel_4_settings: false
+ dmac_channel_5_settings: false
+ dmac_channel_6_settings: false
+ dmac_channel_7_settings: false
+ dmac_channel_8_settings: false
+ dmac_channel_9_settings: false
+ dmac_dbgrun: false
+ dmac_dstinc_0: false
+ dmac_dstinc_1: false
+ dmac_dstinc_10: false
+ dmac_dstinc_11: false
+ dmac_dstinc_12: false
+ dmac_dstinc_13: false
+ dmac_dstinc_14: false
+ dmac_dstinc_15: false
+ dmac_dstinc_16: false
+ dmac_dstinc_17: false
+ dmac_dstinc_18: false
+ dmac_dstinc_19: false
+ dmac_dstinc_2: false
+ dmac_dstinc_20: false
+ dmac_dstinc_21: false
+ dmac_dstinc_22: false
+ dmac_dstinc_23: false
+ dmac_dstinc_24: false
+ dmac_dstinc_25: false
+ dmac_dstinc_26: false
+ dmac_dstinc_27: false
+ dmac_dstinc_28: false
+ dmac_dstinc_29: false
+ dmac_dstinc_3: true
+ dmac_dstinc_30: false
+ dmac_dstinc_31: false
+ dmac_dstinc_4: false
+ dmac_dstinc_5: false
+ dmac_dstinc_6: false
+ dmac_dstinc_7: false
+ dmac_dstinc_8: false
+ dmac_dstinc_9: false
+ dmac_enable: true
+ dmac_evact_0: No action
+ dmac_evact_1: No action
+ dmac_evact_10: No action
+ dmac_evact_11: No action
+ dmac_evact_12: No action
+ dmac_evact_13: No action
+ dmac_evact_14: No action
+ dmac_evact_15: No action
+ dmac_evact_16: No action
+ dmac_evact_17: No action
+ dmac_evact_18: No action
+ dmac_evact_19: No action
+ dmac_evact_2: No action
+ dmac_evact_20: No action
+ dmac_evact_21: No action
+ dmac_evact_22: No action
+ dmac_evact_23: No action
+ dmac_evact_24: No action
+ dmac_evact_25: No action
+ dmac_evact_26: No action
+ dmac_evact_27: No action
+ dmac_evact_28: No action
+ dmac_evact_29: No action
+ dmac_evact_3: No action
+ dmac_evact_30: No action
+ dmac_evact_31: No action
+ dmac_evact_4: No action
+ dmac_evact_5: No action
+ dmac_evact_6: No action
+ dmac_evact_7: No action
+ dmac_evact_8: No action
+ dmac_evact_9: No action
+ dmac_evie_0: false
+ dmac_evie_1: false
+ dmac_evie_10: false
+ dmac_evie_11: false
+ dmac_evie_12: false
+ dmac_evie_13: false
+ dmac_evie_14: false
+ dmac_evie_15: false
+ dmac_evie_16: false
+ dmac_evie_17: false
+ dmac_evie_18: false
+ dmac_evie_19: false
+ dmac_evie_2: false
+ dmac_evie_20: false
+ dmac_evie_21: false
+ dmac_evie_22: false
+ dmac_evie_23: false
+ dmac_evie_24: false
+ dmac_evie_25: false
+ dmac_evie_26: false
+ dmac_evie_27: false
+ dmac_evie_28: false
+ dmac_evie_29: false
+ dmac_evie_3: false
+ dmac_evie_30: false
+ dmac_evie_31: false
+ dmac_evie_4: false
+ dmac_evie_5: false
+ dmac_evie_6: false
+ dmac_evie_7: false
+ dmac_evie_8: false
+ dmac_evie_9: false
+ dmac_evoe_0: false
+ dmac_evoe_1: false
+ dmac_evoe_10: false
+ dmac_evoe_11: false
+ dmac_evoe_12: false
+ dmac_evoe_13: false
+ dmac_evoe_14: false
+ dmac_evoe_15: false
+ dmac_evoe_16: false
+ dmac_evoe_17: false
+ dmac_evoe_18: false
+ dmac_evoe_19: false
+ dmac_evoe_2: false
+ dmac_evoe_20: false
+ dmac_evoe_21: false
+ dmac_evoe_22: false
+ dmac_evoe_23: false
+ dmac_evoe_24: false
+ dmac_evoe_25: false
+ dmac_evoe_26: false
+ dmac_evoe_27: false
+ dmac_evoe_28: false
+ dmac_evoe_29: false
+ dmac_evoe_3: false
+ dmac_evoe_30: false
+ dmac_evoe_31: false
+ dmac_evoe_4: false
+ dmac_evoe_5: false
+ dmac_evoe_6: false
+ dmac_evoe_7: false
+ dmac_evoe_8: false
+ dmac_evoe_9: false
+ dmac_evosel_0: Event generation disabled
+ dmac_evosel_1: Event generation disabled
+ dmac_evosel_10: Event generation disabled
+ dmac_evosel_11: Event generation disabled
+ dmac_evosel_12: Event generation disabled
+ dmac_evosel_13: Event generation disabled
+ dmac_evosel_14: Event generation disabled
+ dmac_evosel_15: Event generation disabled
+ dmac_evosel_16: Event generation disabled
+ dmac_evosel_17: Event generation disabled
+ dmac_evosel_18: Event generation disabled
+ dmac_evosel_19: Event generation disabled
+ dmac_evosel_2: Event generation disabled
+ dmac_evosel_20: Event generation disabled
+ dmac_evosel_21: Event generation disabled
+ dmac_evosel_22: Event generation disabled
+ dmac_evosel_23: Event generation disabled
+ dmac_evosel_24: Event generation disabled
+ dmac_evosel_25: Event generation disabled
+ dmac_evosel_26: Event generation disabled
+ dmac_evosel_27: Event generation disabled
+ dmac_evosel_28: Event generation disabled
+ dmac_evosel_29: Event generation disabled
+ dmac_evosel_3: Event generation disabled
+ dmac_evosel_30: Event generation disabled
+ dmac_evosel_31: Event generation disabled
+ dmac_evosel_4: Event generation disabled
+ dmac_evosel_5: Event generation disabled
+ dmac_evosel_6: Event generation disabled
+ dmac_evosel_7: Event generation disabled
+ dmac_evosel_8: Event generation disabled
+ dmac_evosel_9: Event generation disabled
+ dmac_lvl_0: Channel priority 0
+ dmac_lvl_1: Channel priority 0
+ dmac_lvl_10: Channel priority 0
+ dmac_lvl_11: Channel priority 0
+ dmac_lvl_12: Channel priority 0
+ dmac_lvl_13: Channel priority 0
+ dmac_lvl_14: Channel priority 0
+ dmac_lvl_15: Channel priority 0
+ dmac_lvl_16: Channel priority 0
+ dmac_lvl_17: Channel priority 0
+ dmac_lvl_18: Channel priority 0
+ dmac_lvl_19: Channel priority 0
+ dmac_lvl_2: Channel priority 0
+ dmac_lvl_20: Channel priority 0
+ dmac_lvl_21: Channel priority 0
+ dmac_lvl_22: Channel priority 0
+ dmac_lvl_23: Channel priority 0
+ dmac_lvl_24: Channel priority 0
+ dmac_lvl_25: Channel priority 0
+ dmac_lvl_26: Channel priority 0
+ dmac_lvl_27: Channel priority 0
+ dmac_lvl_28: Channel priority 0
+ dmac_lvl_29: Channel priority 0
+ dmac_lvl_3: Channel priority 0
+ dmac_lvl_30: Channel priority 0
+ dmac_lvl_31: Channel priority 0
+ dmac_lvl_4: Channel priority 0
+ dmac_lvl_5: Channel priority 0
+ dmac_lvl_6: Channel priority 0
+ dmac_lvl_7: Channel priority 0
+ dmac_lvl_8: Channel priority 0
+ dmac_lvl_9: Channel priority 0
+ dmac_lvlen0: true
+ dmac_lvlen1: true
+ dmac_lvlen2: true
+ dmac_lvlen3: false
+ dmac_lvlpri0: 0
+ dmac_lvlpri1: 0
+ dmac_lvlpri2: 0
+ dmac_lvlpri3: 0
+ dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
+ dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
+ dmac_rrlvlen2: Round-robin arbitration scheme for channel with priority 2
+ dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
+ dmac_runstdby_0: false
+ dmac_runstdby_1: false
+ dmac_runstdby_10: false
+ dmac_runstdby_11: false
+ dmac_runstdby_12: false
+ dmac_runstdby_13: false
+ dmac_runstdby_14: false
+ dmac_runstdby_15: false
+ dmac_runstdby_16: false
+ dmac_runstdby_17: false
+ dmac_runstdby_18: false
+ dmac_runstdby_19: false
+ dmac_runstdby_2: false
+ dmac_runstdby_20: false
+ dmac_runstdby_21: false
+ dmac_runstdby_22: false
+ dmac_runstdby_23: false
+ dmac_runstdby_24: false
+ dmac_runstdby_25: false
+ dmac_runstdby_26: false
+ dmac_runstdby_27: false
+ dmac_runstdby_28: false
+ dmac_runstdby_29: false
+ dmac_runstdby_3: false
+ dmac_runstdby_30: false
+ dmac_runstdby_31: false
+ dmac_runstdby_4: false
+ dmac_runstdby_5: false
+ dmac_runstdby_6: false
+ dmac_runstdby_7: false
+ dmac_runstdby_8: false
+ dmac_runstdby_9: false
+ dmac_srcinc_0: false
+ dmac_srcinc_1: false
+ dmac_srcinc_10: false
+ dmac_srcinc_11: false
+ dmac_srcinc_12: false
+ dmac_srcinc_13: false
+ dmac_srcinc_14: false
+ dmac_srcinc_15: false
+ dmac_srcinc_16: false
+ dmac_srcinc_17: false
+ dmac_srcinc_18: false
+ dmac_srcinc_19: false
+ dmac_srcinc_2: true
+ dmac_srcinc_20: false
+ dmac_srcinc_21: false
+ dmac_srcinc_22: false
+ dmac_srcinc_23: false
+ dmac_srcinc_24: false
+ dmac_srcinc_25: false
+ dmac_srcinc_26: false
+ dmac_srcinc_27: false
+ dmac_srcinc_28: false
+ dmac_srcinc_29: false
+ dmac_srcinc_3: false
+ dmac_srcinc_30: false
+ dmac_srcinc_31: false
+ dmac_srcinc_4: false
+ dmac_srcinc_5: false
+ dmac_srcinc_6: false
+ dmac_srcinc_7: false
+ dmac_srcinc_8: false
+ dmac_srcinc_9: false
+ dmac_stepsel_0: Step size settings apply to the destination address
+ dmac_stepsel_1: Step size settings apply to the destination address
+ dmac_stepsel_10: Step size settings apply to the destination address
+ dmac_stepsel_11: Step size settings apply to the destination address
+ dmac_stepsel_12: Step size settings apply to the destination address
+ dmac_stepsel_13: Step size settings apply to the destination address
+ dmac_stepsel_14: Step size settings apply to the destination address
+ dmac_stepsel_15: Step size settings apply to the destination address
+ dmac_stepsel_16: Step size settings apply to the destination address
+ dmac_stepsel_17: Step size settings apply to the destination address
+ dmac_stepsel_18: Step size settings apply to the destination address
+ dmac_stepsel_19: Step size settings apply to the destination address
+ dmac_stepsel_2: Step size settings apply to the source address
+ dmac_stepsel_20: Step size settings apply to the destination address
+ dmac_stepsel_21: Step size settings apply to the destination address
+ dmac_stepsel_22: Step size settings apply to the destination address
+ dmac_stepsel_23: Step size settings apply to the destination address
+ dmac_stepsel_24: Step size settings apply to the destination address
+ dmac_stepsel_25: Step size settings apply to the destination address
+ dmac_stepsel_26: Step size settings apply to the destination address
+ dmac_stepsel_27: Step size settings apply to the destination address
+ dmac_stepsel_28: Step size settings apply to the destination address
+ dmac_stepsel_29: Step size settings apply to the destination address
+ dmac_stepsel_3: Step size settings apply to the destination address
+ dmac_stepsel_30: Step size settings apply to the destination address
+ dmac_stepsel_31: Step size settings apply to the destination address
+ dmac_stepsel_4: Step size settings apply to the destination address
+ dmac_stepsel_5: Step size settings apply to the destination address
+ dmac_stepsel_6: Step size settings apply to the destination address
+ dmac_stepsel_7: Step size settings apply to the destination address
+ dmac_stepsel_8: Step size settings apply to the destination address
+ dmac_stepsel_9: Step size settings apply to the destination address
+ dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_trifsrc_0: Only software/event triggers
+ dmac_trifsrc_1: Only software/event triggers
+ dmac_trifsrc_10: Only software/event triggers
+ dmac_trifsrc_11: Only software/event triggers
+ dmac_trifsrc_12: Only software/event triggers
+ dmac_trifsrc_13: Only software/event triggers
+ dmac_trifsrc_14: Only software/event triggers
+ dmac_trifsrc_15: Only software/event triggers
+ dmac_trifsrc_16: Only software/event triggers
+ dmac_trifsrc_17: Only software/event triggers
+ dmac_trifsrc_18: Only software/event triggers
+ dmac_trifsrc_19: Only software/event triggers
+ dmac_trifsrc_2: SERCOM4 TX Trigger
+ dmac_trifsrc_20: Only software/event triggers
+ dmac_trifsrc_21: Only software/event triggers
+ dmac_trifsrc_22: Only software/event triggers
+ dmac_trifsrc_23: Only software/event triggers
+ dmac_trifsrc_24: Only software/event triggers
+ dmac_trifsrc_25: Only software/event triggers
+ dmac_trifsrc_26: Only software/event triggers
+ dmac_trifsrc_27: Only software/event triggers
+ dmac_trifsrc_28: Only software/event triggers
+ dmac_trifsrc_29: Only software/event triggers
+ dmac_trifsrc_3: SERCOM4 RX Trigger
+ dmac_trifsrc_30: Only software/event triggers
+ dmac_trifsrc_31: Only software/event triggers
+ dmac_trifsrc_4: Only software/event triggers
+ dmac_trifsrc_5: Only software/event triggers
+ dmac_trifsrc_6: Only software/event triggers
+ dmac_trifsrc_7: Only software/event triggers
+ dmac_trifsrc_8: Only software/event triggers
+ dmac_trifsrc_9: Only software/event triggers
+ dmac_trigact_0: One trigger required for each block transfer
+ dmac_trigact_1: One trigger required for each block transfer
+ dmac_trigact_10: One trigger required for each block transfer
+ dmac_trigact_11: One trigger required for each block transfer
+ dmac_trigact_12: One trigger required for each block transfer
+ dmac_trigact_13: One trigger required for each block transfer
+ dmac_trigact_14: One trigger required for each block transfer
+ dmac_trigact_15: One trigger required for each block transfer
+ dmac_trigact_16: One trigger required for each block transfer
+ dmac_trigact_17: One trigger required for each block transfer
+ dmac_trigact_18: One trigger required for each block transfer
+ dmac_trigact_19: One trigger required for each block transfer
+ dmac_trigact_2: One trigger required for each beat transfer
+ dmac_trigact_20: One trigger required for each block transfer
+ dmac_trigact_21: One trigger required for each block transfer
+ dmac_trigact_22: One trigger required for each block transfer
+ dmac_trigact_23: One trigger required for each block transfer
+ dmac_trigact_24: One trigger required for each block transfer
+ dmac_trigact_25: One trigger required for each block transfer
+ dmac_trigact_26: One trigger required for each block transfer
+ dmac_trigact_27: One trigger required for each block transfer
+ dmac_trigact_28: One trigger required for each block transfer
+ dmac_trigact_29: One trigger required for each block transfer
+ dmac_trigact_3: One trigger required for each beat transfer
+ dmac_trigact_30: One trigger required for each block transfer
+ dmac_trigact_31: One trigger required for each block transfer
+ dmac_trigact_4: One trigger required for each block transfer
+ dmac_trigact_5: One trigger required for each block transfer
+ dmac_trigact_6: One trigger required for each block transfer
+ dmac_trigact_7: One trigger required for each block transfer
+ dmac_trigact_8: One trigger required for each block transfer
+ dmac_trigact_9: One trigger required for each block transfer
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ EVENT_SYSTEM_0:
+ user_label: EVENT_SYSTEM_0
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::EVSYS::driver_config_definition::Event.System::HAL:Driver:Event.system
+ functionality: Event_System
+ api: HAL:Driver:Event_system
+ configuration:
+ evsys_channel_0: No channel output selected
+ evsys_channel_1: No channel output selected
+ evsys_channel_10: Channel 0
+ evsys_channel_11: Channel 0
+ evsys_channel_12: Channel 0
+ evsys_channel_17: No channel output selected
+ evsys_channel_18: No channel output selected
+ evsys_channel_19: No channel output selected
+ evsys_channel_2: No channel output selected
+ evsys_channel_20: No channel output selected
+ evsys_channel_21: No channel output selected
+ evsys_channel_22: No channel output selected
+ evsys_channel_23: No channel output selected
+ evsys_channel_24: No channel output selected
+ evsys_channel_25: No channel output selected
+ evsys_channel_26: No channel output selected
+ evsys_channel_27: No channel output selected
+ evsys_channel_28: No channel output selected
+ evsys_channel_29: No channel output selected
+ evsys_channel_3: No channel output selected
+ evsys_channel_30: No channel output selected
+ evsys_channel_31: No channel output selected
+ evsys_channel_32: No channel output selected
+ evsys_channel_33: No channel output selected
+ evsys_channel_34: No channel output selected
+ evsys_channel_35: No channel output selected
+ evsys_channel_36: No channel output selected
+ evsys_channel_37: No channel output selected
+ evsys_channel_38: No channel output selected
+ evsys_channel_39: No channel output selected
+ evsys_channel_4: No channel output selected
+ evsys_channel_40: No channel output selected
+ evsys_channel_41: No channel output selected
+ evsys_channel_42: No channel output selected
+ evsys_channel_43: No channel output selected
+ evsys_channel_44: No channel output selected
+ evsys_channel_45: No channel output selected
+ evsys_channel_46: No channel output selected
+ evsys_channel_47: No channel output selected
+ evsys_channel_48: No channel output selected
+ evsys_channel_49: No channel output selected
+ evsys_channel_5: Channel 0
+ evsys_channel_50: No channel output selected
+ evsys_channel_51: No channel output selected
+ evsys_channel_52: No channel output selected
+ evsys_channel_53: No channel output selected
+ evsys_channel_54: No channel output selected
+ evsys_channel_55: No channel output selected
+ evsys_channel_56: No channel output selected
+ evsys_channel_57: No channel output selected
+ evsys_channel_58: No channel output selected
+ evsys_channel_59: No channel output selected
+ evsys_channel_6: Channel 0
+ evsys_channel_60: No channel output selected
+ evsys_channel_61: No channel output selected
+ evsys_channel_62: No channel output selected
+ evsys_channel_63: No channel output selected
+ evsys_channel_64: No channel output selected
+ evsys_channel_65: No channel output selected
+ evsys_channel_66: No channel output selected
+ evsys_channel_7: Channel 0
+ evsys_channel_8: Channel 0
+ evsys_channel_9: Channel 0
+ evsys_channel_setting_0: true
+ evsys_channel_setting_1: false
+ evsys_channel_setting_10: false
+ evsys_channel_setting_11: false
+ evsys_channel_setting_12: false
+ evsys_channel_setting_13: false
+ evsys_channel_setting_14: false
+ evsys_channel_setting_15: false
+ evsys_channel_setting_16: false
+ evsys_channel_setting_17: false
+ evsys_channel_setting_18: false
+ evsys_channel_setting_19: false
+ evsys_channel_setting_2: false
+ evsys_channel_setting_20: false
+ evsys_channel_setting_21: false
+ evsys_channel_setting_22: false
+ evsys_channel_setting_23: false
+ evsys_channel_setting_24: false
+ evsys_channel_setting_25: false
+ evsys_channel_setting_26: false
+ evsys_channel_setting_27: false
+ evsys_channel_setting_28: false
+ evsys_channel_setting_29: false
+ evsys_channel_setting_3: false
+ evsys_channel_setting_30: false
+ evsys_channel_setting_31: false
+ evsys_channel_setting_4: false
+ evsys_channel_setting_5: false
+ evsys_channel_setting_6: false
+ evsys_channel_setting_7: false
+ evsys_channel_setting_8: false
+ evsys_channel_setting_9: false
+ evsys_edgsel_0: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_1: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_10: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_11: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_12: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_13: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_14: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_15: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_16: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_17: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_18: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_19: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_2: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_20: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_21: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_22: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_23: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_24: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_25: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_26: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_27: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_28: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_29: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_3: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_30: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_31: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_4: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_5: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_6: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_7: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_8: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_9: No event output when using the resynchronized or synchronous
+ path
+ evsys_evd_0: false
+ evsys_evd_1: false
+ evsys_evd_10: false
+ evsys_evd_11: false
+ evsys_evd_12: false
+ evsys_evd_13: false
+ evsys_evd_14: false
+ evsys_evd_15: false
+ evsys_evd_16: false
+ evsys_evd_17: false
+ evsys_evd_18: false
+ evsys_evd_19: false
+ evsys_evd_2: false
+ evsys_evd_20: false
+ evsys_evd_21: false
+ evsys_evd_22: false
+ evsys_evd_23: false
+ evsys_evd_24: false
+ evsys_evd_25: false
+ evsys_evd_26: false
+ evsys_evd_27: false
+ evsys_evd_28: false
+ evsys_evd_29: false
+ evsys_evd_3: false
+ evsys_evd_30: false
+ evsys_evd_31: false
+ evsys_evd_4: false
+ evsys_evd_5: false
+ evsys_evd_6: false
+ evsys_evd_7: false
+ evsys_evd_8: false
+ evsys_evd_9: false
+ evsys_evgen_0: TC0 overflow
+ evsys_evgen_1: No event generator
+ evsys_evgen_10: No event generator
+ evsys_evgen_11: No event generator
+ evsys_evgen_12: No event generator
+ evsys_evgen_13: No event generator
+ evsys_evgen_14: No event generator
+ evsys_evgen_15: No event generator
+ evsys_evgen_16: No event generator
+ evsys_evgen_17: No event generator
+ evsys_evgen_18: No event generator
+ evsys_evgen_19: No event generator
+ evsys_evgen_2: No event generator
+ evsys_evgen_20: No event generator
+ evsys_evgen_21: No event generator
+ evsys_evgen_22: No event generator
+ evsys_evgen_23: No event generator
+ evsys_evgen_24: No event generator
+ evsys_evgen_25: No event generator
+ evsys_evgen_26: No event generator
+ evsys_evgen_27: No event generator
+ evsys_evgen_28: No event generator
+ evsys_evgen_29: No event generator
+ evsys_evgen_3: No event generator
+ evsys_evgen_30: No event generator
+ evsys_evgen_31: No event generator
+ evsys_evgen_4: No event generator
+ evsys_evgen_5: No event generator
+ evsys_evgen_6: No event generator
+ evsys_evgen_7: No event generator
+ evsys_evgen_8: No event generator
+ evsys_evgen_9: No event generator
+ evsys_ondemand_0: false
+ evsys_ondemand_1: false
+ evsys_ondemand_10: false
+ evsys_ondemand_11: false
+ evsys_ondemand_12: false
+ evsys_ondemand_13: false
+ evsys_ondemand_14: false
+ evsys_ondemand_15: false
+ evsys_ondemand_16: false
+ evsys_ondemand_17: false
+ evsys_ondemand_18: false
+ evsys_ondemand_19: false
+ evsys_ondemand_2: false
+ evsys_ondemand_20: false
+ evsys_ondemand_21: false
+ evsys_ondemand_22: false
+ evsys_ondemand_23: false
+ evsys_ondemand_24: false
+ evsys_ondemand_25: false
+ evsys_ondemand_26: false
+ evsys_ondemand_27: false
+ evsys_ondemand_28: false
+ evsys_ondemand_29: false
+ evsys_ondemand_3: false
+ evsys_ondemand_30: false
+ evsys_ondemand_31: false
+ evsys_ondemand_4: false
+ evsys_ondemand_5: false
+ evsys_ondemand_6: false
+ evsys_ondemand_7: false
+ evsys_ondemand_8: false
+ evsys_ondemand_9: false
+ evsys_ovr_0: false
+ evsys_ovr_1: false
+ evsys_ovr_10: false
+ evsys_ovr_11: false
+ evsys_ovr_12: false
+ evsys_ovr_13: false
+ evsys_ovr_14: false
+ evsys_ovr_15: false
+ evsys_ovr_16: false
+ evsys_ovr_17: false
+ evsys_ovr_18: false
+ evsys_ovr_19: false
+ evsys_ovr_2: false
+ evsys_ovr_20: false
+ evsys_ovr_21: false
+ evsys_ovr_22: false
+ evsys_ovr_23: false
+ evsys_ovr_24: false
+ evsys_ovr_25: false
+ evsys_ovr_26: false
+ evsys_ovr_27: false
+ evsys_ovr_28: false
+ evsys_ovr_29: false
+ evsys_ovr_3: false
+ evsys_ovr_30: false
+ evsys_ovr_31: false
+ evsys_ovr_4: false
+ evsys_ovr_5: false
+ evsys_ovr_6: false
+ evsys_ovr_7: false
+ evsys_ovr_8: false
+ evsys_ovr_9: false
+ evsys_path_0: Asynchronous path
+ evsys_path_1: Synchronous path
+ evsys_path_10: Synchronous path
+ evsys_path_11: Synchronous path
+ evsys_path_12: Synchronous path
+ evsys_path_13: Synchronous path
+ evsys_path_14: Synchronous path
+ evsys_path_15: Synchronous path
+ evsys_path_16: Synchronous path
+ evsys_path_17: Synchronous path
+ evsys_path_18: Synchronous path
+ evsys_path_19: Synchronous path
+ evsys_path_2: Synchronous path
+ evsys_path_20: Synchronous path
+ evsys_path_21: Synchronous path
+ evsys_path_22: Synchronous path
+ evsys_path_23: Synchronous path
+ evsys_path_24: Synchronous path
+ evsys_path_25: Synchronous path
+ evsys_path_26: Synchronous path
+ evsys_path_27: Synchronous path
+ evsys_path_28: Synchronous path
+ evsys_path_29: Synchronous path
+ evsys_path_3: Synchronous path
+ evsys_path_30: Synchronous path
+ evsys_path_31: Synchronous path
+ evsys_path_4: Synchronous path
+ evsys_path_5: Synchronous path
+ evsys_path_6: Synchronous path
+ evsys_path_7: Synchronous path
+ evsys_path_8: Synchronous path
+ evsys_path_9: Synchronous path
+ evsys_runstdby_0: false
+ evsys_runstdby_1: false
+ evsys_runstdby_10: false
+ evsys_runstdby_11: false
+ evsys_runstdby_12: false
+ evsys_runstdby_13: false
+ evsys_runstdby_14: false
+ evsys_runstdby_15: false
+ evsys_runstdby_16: false
+ evsys_runstdby_17: false
+ evsys_runstdby_18: false
+ evsys_runstdby_19: false
+ evsys_runstdby_2: false
+ evsys_runstdby_20: false
+ evsys_runstdby_21: false
+ evsys_runstdby_22: false
+ evsys_runstdby_23: false
+ evsys_runstdby_24: false
+ evsys_runstdby_25: false
+ evsys_runstdby_26: false
+ evsys_runstdby_27: false
+ evsys_runstdby_28: false
+ evsys_runstdby_29: false
+ evsys_runstdby_3: false
+ evsys_runstdby_30: false
+ evsys_runstdby_31: false
+ evsys_runstdby_4: false
+ evsys_runstdby_5: false
+ evsys_runstdby_6: false
+ evsys_runstdby_7: false
+ evsys_runstdby_8: false
+ evsys_runstdby_9: false
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: Channel 0
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 1
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 2
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 3
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 4
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 5
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 6
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 7
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 8
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 9
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 10
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 11
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ configuration:
+ evsys_clk_selection_0: Generic clock generator 0
+ evsys_clk_selection_1: Generic clock generator 0
+ evsys_clk_selection_10: Generic clock generator 0
+ evsys_clk_selection_11: Generic clock generator 0
+ evsys_clk_selection_2: Generic clock generator 0
+ evsys_clk_selection_3: Generic clock generator 0
+ evsys_clk_selection_4: Generic clock generator 0
+ evsys_clk_selection_5: Generic clock generator 0
+ evsys_clk_selection_6: Generic clock generator 0
+ evsys_clk_selection_7: Generic clock generator 0
+ evsys_clk_selection_8: Generic clock generator 0
+ evsys_clk_selection_9: Generic clock generator 0
+ GCLK:
+ user_label: GCLK
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
+ functionality: System
+ api: HAL:HPL:GCLK
+ configuration:
+ $input: 12000000
+ $input_id: External Crystal Oscillator 8-48MHz (XOSC1)
+ RESERVED_InputFreq: 12000000
+ RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1)
+ _$freq_output_Generic clock generator 0: 12000000
+ _$freq_output_Generic clock generator 1: 48000000
+ _$freq_output_Generic clock generator 10: 12000000
+ _$freq_output_Generic clock generator 11: 12000000
+ _$freq_output_Generic clock generator 2: 3000000
+ _$freq_output_Generic clock generator 3: 32768
+ _$freq_output_Generic clock generator 4: 12000000
+ _$freq_output_Generic clock generator 5: 12000000
+ _$freq_output_Generic clock generator 6: 12000000
+ _$freq_output_Generic clock generator 7: 12000000
+ _$freq_output_Generic clock generator 8: 12000000
+ _$freq_output_Generic clock generator 9: 12000000
+ enable_gclk_gen_0: true
+ enable_gclk_gen_0__externalclock: 1000000
+ enable_gclk_gen_1: false
+ enable_gclk_gen_10: false
+ enable_gclk_gen_10__externalclock: 1000000
+ enable_gclk_gen_11: false
+ enable_gclk_gen_11__externalclock: 1000000
+ enable_gclk_gen_1__externalclock: 1000000
+ enable_gclk_gen_2: false
+ enable_gclk_gen_2__externalclock: 1000000
+ enable_gclk_gen_3: false
+ enable_gclk_gen_3__externalclock: 1000000
+ enable_gclk_gen_4: false
+ enable_gclk_gen_4__externalclock: 1000000
+ enable_gclk_gen_5: false
+ enable_gclk_gen_5__externalclock: 1000000
+ enable_gclk_gen_6: false
+ enable_gclk_gen_6__externalclock: 1000000
+ enable_gclk_gen_7: false
+ enable_gclk_gen_7__externalclock: 1000000
+ enable_gclk_gen_8: false
+ enable_gclk_gen_8__externalclock: 1000000
+ enable_gclk_gen_9: false
+ enable_gclk_gen_9__externalclock: 1000000
+ gclk_arch_gen_0_enable: true
+ gclk_arch_gen_0_idc: false
+ gclk_arch_gen_0_oe: false
+ gclk_arch_gen_0_oov: false
+ gclk_arch_gen_0_runstdby: false
+ gclk_arch_gen_10_enable: false
+ gclk_arch_gen_10_idc: false
+ gclk_arch_gen_10_oe: false
+ gclk_arch_gen_10_oov: false
+ gclk_arch_gen_10_runstdby: false
+ gclk_arch_gen_11_enable: false
+ gclk_arch_gen_11_idc: false
+ gclk_arch_gen_11_oe: false
+ gclk_arch_gen_11_oov: false
+ gclk_arch_gen_11_runstdby: false
+ gclk_arch_gen_1_enable: false
+ gclk_arch_gen_1_idc: false
+ gclk_arch_gen_1_oe: false
+ gclk_arch_gen_1_oov: false
+ gclk_arch_gen_1_runstdby: false
+ gclk_arch_gen_2_enable: false
+ gclk_arch_gen_2_idc: false
+ gclk_arch_gen_2_oe: false
+ gclk_arch_gen_2_oov: false
+ gclk_arch_gen_2_runstdby: false
+ gclk_arch_gen_3_enable: false
+ gclk_arch_gen_3_idc: false
+ gclk_arch_gen_3_oe: false
+ gclk_arch_gen_3_oov: false
+ gclk_arch_gen_3_runstdby: false
+ gclk_arch_gen_4_enable: false
+ gclk_arch_gen_4_idc: false
+ gclk_arch_gen_4_oe: false
+ gclk_arch_gen_4_oov: false
+ gclk_arch_gen_4_runstdby: false
+ gclk_arch_gen_5_enable: false
+ gclk_arch_gen_5_idc: false
+ gclk_arch_gen_5_oe: false
+ gclk_arch_gen_5_oov: false
+ gclk_arch_gen_5_runstdby: false
+ gclk_arch_gen_6_enable: false
+ gclk_arch_gen_6_idc: false
+ gclk_arch_gen_6_oe: false
+ gclk_arch_gen_6_oov: false
+ gclk_arch_gen_6_runstdby: false
+ gclk_arch_gen_7_enable: false
+ gclk_arch_gen_7_idc: false
+ gclk_arch_gen_7_oe: false
+ gclk_arch_gen_7_oov: false
+ gclk_arch_gen_7_runstdby: false
+ gclk_arch_gen_8_enable: false
+ gclk_arch_gen_8_idc: false
+ gclk_arch_gen_8_oe: false
+ gclk_arch_gen_8_oov: false
+ gclk_arch_gen_8_runstdby: false
+ gclk_arch_gen_9_enable: false
+ gclk_arch_gen_9_idc: false
+ gclk_arch_gen_9_oe: false
+ gclk_arch_gen_9_oov: false
+ gclk_arch_gen_9_runstdby: false
+ gclk_gen_0_div: 1
+ gclk_gen_0_div_sel: false
+ gclk_gen_0_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_10_div: 1
+ gclk_gen_10_div_sel: false
+ gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_11_div: 1
+ gclk_gen_11_div_sel: false
+ gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_1_div: 1
+ gclk_gen_1_div_sel: false
+ gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M)
+ gclk_gen_2_div: 1
+ gclk_gen_2_div_sel: true
+ gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_3_div: 1
+ gclk_gen_3_div_sel: false
+ gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
+ gclk_gen_4_div: 1
+ gclk_gen_4_div_sel: false
+ gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_5_div: 1
+ gclk_gen_5_div_sel: false
+ gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_6_div: 1
+ gclk_gen_6_div_sel: false
+ gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_7_div: 1
+ gclk_gen_7_div_sel: false
+ gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_8_div: 1
+ gclk_gen_8_div_sel: false
+ gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_9_div: 1
+ gclk_gen_9_div_sel: false
+ gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ MCLK:
+ user_label: MCLK
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK
+ functionality: System
+ api: HAL:HPL:MCLK
+ configuration:
+ $input: 12000000
+ $input_id: Generic clock generator 0
+ RESERVED_InputFreq: 12000000
+ RESERVED_InputFreq_id: Generic clock generator 0
+ _$freq_output_CPU: 12000000
+ cpu_clock_source: Generic clock generator 0
+ cpu_div: '1'
+ enable_cpu_clock: true
+ mclk_arch_bupdiv: Divide by 8
+ mclk_arch_hsdiv: Divide by 1
+ mclk_arch_lpdiv: Divide by 4
+ nvm_wait_states: '0'
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: CPU
+ input: CPU
+ external: false
+ external_frequency: 0
+ configuration: {}
+ OSC32KCTRL:
+ user_label: OSC32KCTRL
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL
+ functionality: System
+ api: HAL:HPL:OSC32KCTRL
+ configuration:
+ $input: 32768
+ $input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+ RESERVED_InputFreq: 32768
+ RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+ _$freq_output_RTC source: 32768
+ enable_osculp32k: true
+ enable_rtc_source: false
+ enable_xosc32k: false
+ osculp32k_calib: 0
+ osculp32k_calib_enable: false
+ rtc_1khz_selection: false
+ rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+ xosc32k_arch_cfden: false
+ xosc32k_arch_cfdeo: false
+ xosc32k_arch_cgm: Standard mode
+ xosc32k_arch_en1k: false
+ xosc32k_arch_en32k: false
+ xosc32k_arch_enable: false
+ xosc32k_arch_ondemand: true
+ xosc32k_arch_runstdby: false
+ xosc32k_arch_startup: 62592us
+ xosc32k_arch_swben: false
+ xosc32k_arch_xtalen: true
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ OSCCTRL:
+ user_label: OSCCTRL
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL
+ functionality: System
+ api: HAL:HPL:OSCCTRL
+ configuration:
+ $input: 32768
+ $input_id: 32kHz External Crystal Oscillator (XOSC32K)
+ RESERVED_InputFreq: 32768
+ RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K)
+ _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
+ _$freq_output_Digital Phase Locked Loop (DPLL0): 47985664
+ _$freq_output_Digital Phase Locked Loop (DPLL1): 47985664
+ _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000
+ _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000
+ dfll_arch_bplckc: false
+ dfll_arch_calibration: false
+ dfll_arch_ccdis: false
+ dfll_arch_coarse: 31
+ dfll_arch_cstep: 1
+ dfll_arch_enable: false
+ dfll_arch_fine: 128
+ dfll_arch_fstep: 1
+ dfll_arch_llaw: false
+ dfll_arch_ondemand: false
+ dfll_arch_qldis: false
+ dfll_arch_runstdby: false
+ dfll_arch_stable: false
+ dfll_arch_usbcrm: false
+ dfll_arch_waitlock: true
+ dfll_mode: Open Loop Mode
+ dfll_mul: 0
+ dfll_ref_clock: Generic clock generator 3
+ enable_dfll: false
+ enable_fdpll0: false
+ enable_fdpll1: false
+ enable_xosc0: false
+ enable_xosc1: true
+ fdpll0_arch_dcoen: false
+ fdpll0_arch_enable: false
+ fdpll0_arch_filter: 0
+ fdpll0_arch_lbypass: false
+ fdpll0_arch_ltime: No time-out, automatic lock
+ fdpll0_arch_ondemand: false
+ fdpll0_arch_refclk: XOSC32K clock reference
+ fdpll0_arch_runstdby: false
+ fdpll0_arch_wuf: false
+ fdpll0_clock_dcofilter: 0
+ fdpll0_clock_div: 0
+ fdpll0_ldr: 1463
+ fdpll0_ldrfrac: 13
+ fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)
+ fdpll1_arch_dcoen: false
+ fdpll1_arch_enable: false
+ fdpll1_arch_filter: 0
+ fdpll1_arch_lbypass: false
+ fdpll1_arch_ltime: No time-out, automatic lock
+ fdpll1_arch_ondemand: false
+ fdpll1_arch_refclk: XOSC32K clock reference
+ fdpll1_arch_runstdby: false
+ fdpll1_arch_wuf: false
+ fdpll1_clock_dcofilter: 0
+ fdpll1_clock_div: 0
+ fdpll1_ldr: 1463
+ fdpll1_ldrfrac: 13
+ fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)
+ xosc0_arch_cfden: false
+ xosc0_arch_enable: false
+ xosc0_arch_enalc: false
+ xosc0_arch_lowbufgain: false
+ xosc0_arch_ondemand: false
+ xosc0_arch_runstdby: false
+ xosc0_arch_startup: 31us
+ xosc0_arch_swben: false
+ xosc0_arch_xtalen: false
+ xosc0_frequency: 12000000
+ xosc1_arch_cfden: false
+ xosc1_arch_enable: true
+ xosc1_arch_enalc: false
+ xosc1_arch_lowbufgain: false
+ xosc1_arch_ondemand: false
+ xosc1_arch_runstdby: false
+ xosc1_arch_startup: 31us
+ xosc1_arch_swben: false
+ xosc1_arch_xtalen: true
+ xosc1_frequency: 12000000
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ PORT:
+ user_label: PORT
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT
+ functionality: System
+ api: HAL:HPL:PORT
+ configuration:
+ enable_port_input_event_0: false
+ enable_port_input_event_1: false
+ enable_port_input_event_2: false
+ enable_port_input_event_3: false
+ porta_event_action_0: Output register of pin will be set to level of event
+ porta_event_action_1: Output register of pin will be set to level of event
+ porta_event_action_2: Output register of pin will be set to level of event
+ porta_event_action_3: Output register of pin will be set to level of event
+ porta_event_pin_identifier_0: 0
+ porta_event_pin_identifier_1: 0
+ porta_event_pin_identifier_2: 0
+ porta_event_pin_identifier_3: 0
+ porta_input_event_enable_0: false
+ porta_input_event_enable_1: false
+ porta_input_event_enable_2: false
+ porta_input_event_enable_3: false
+ portb_event_action_0: Output register of pin will be set to level of event
+ portb_event_action_1: Output register of pin will be set to level of event
+ portb_event_action_2: Output register of pin will be set to level of event
+ portb_event_action_3: Output register of pin will be set to level of event
+ portb_event_pin_identifier_0: 0
+ portb_event_pin_identifier_1: 0
+ portb_event_pin_identifier_2: 0
+ portb_event_pin_identifier_3: 0
+ portb_input_event_enable_0: false
+ portb_input_event_enable_1: false
+ portb_input_event_enable_2: false
+ portb_input_event_enable_3: false
+ portc_event_action_0: Output register of pin will be set to level of event
+ portc_event_action_1: Output register of pin will be set to level of event
+ portc_event_action_2: Output register of pin will be set to level of event
+ portc_event_action_3: Output register of pin will be set to level of event
+ portc_event_pin_identifier_0: 0
+ portc_event_pin_identifier_1: 0
+ portc_event_pin_identifier_2: 0
+ portc_event_pin_identifier_3: 0
+ portc_input_event_enable_0: false
+ portc_input_event_enable_1: false
+ portc_input_event_enable_2: false
+ portc_input_event_enable_3: false
+ portd_event_action_0: Output register of pin will be set to level of event
+ portd_event_action_1: Output register of pin will be set to level of event
+ portd_event_action_2: Output register of pin will be set to level of event
+ portd_event_action_3: Output register of pin will be set to level of event
+ portd_event_pin_identifier_0: 0
+ portd_event_pin_identifier_1: 0
+ portd_event_pin_identifier_2: 0
+ portd_event_pin_identifier_3: 0
+ portd_input_event_enable_0: false
+ portd_input_event_enable_1: false
+ portd_input_event_enable_2: false
+ portd_input_event_enable_3: false
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ QUAD_SPI_0:
+ user_label: QUAD_SPI_0
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::QSPI::driver_config_definition::QSPI.Master::HAL:Driver:QSPI.Sync
+ functionality: Quad_SPI
+ api: HAL:Driver:QSPI_Sync
+ configuration:
+ qspi_advanced: false
+ qspi_baud_rate: 6000000
+ qspi_cpha: Data is changed on the leading edge of SPCK and captured on the following
+ edge of SPCK.
+ qspi_cpol: The inactive state value of SPCK is logic level zero.
+ qspi_dlybs: 0
+ qspi_dlycs: 0
+ optional_signals:
+ - identifier: QUAD_SPI_0:CS
+ pad: PB11
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::QSPI.CS
+ name: QSPI/CS
+ label: CS
+ - identifier: QUAD_SPI_0:DATA/0
+ pad: PA08
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::QSPI.DATA.0
+ name: QSPI/DATA/0
+ label: DATA/0
+ - identifier: QUAD_SPI_0:DATA/1
+ pad: PA09
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::QSPI.DATA.1
+ name: QSPI/DATA/1
+ label: DATA/1
+ - identifier: QUAD_SPI_0:DATA/2
+ pad: PA10
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::QSPI.DATA.2
+ name: QSPI/DATA/2
+ label: DATA/2
+ - identifier: QUAD_SPI_0:DATA/3
+ pad: PA11
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::QSPI.DATA.3
+ name: QSPI/DATA/3
+ label: DATA/3
+ - identifier: QUAD_SPI_0:SCK
+ pad: PB10
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::QSPI.SCK
+ name: QSPI/SCK
+ label: SCK
+ variant: null
+ clocks:
+ domain_group: null
+ RAMECC:
+ user_label: RAMECC
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC
+ functionality: System
+ api: HAL:HPL:RAMECC
+ configuration: {}
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ TARGET_IO:
+ user_label: TARGET_IO
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Sync
+ functionality: USART
+ api: HAL:Driver:USART_Sync
+ configuration:
+ usart_advanced: false
+ usart_arch_clock_mode: USART with internal clock
+ usart_arch_cloden: false
+ usart_arch_dbgstop: Keep running
+ usart_arch_dord: LSB is transmitted first
+ usart_arch_enc: No encoding
+ usart_arch_fractional: 0
+ usart_arch_ibon: false
+ usart_arch_lin_slave_enable: Disable
+ usart_arch_runstdby: false
+ usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling)
+ usart_arch_sampr: 16x arithmetic
+ usart_arch_sfde: false
+ usart_baud_rate: 9600
+ usart_character_size: 8 bits
+ usart_parity: No parity
+ usart_rx_enable: true
+ usart_stop_bit: One stop bit
+ usart_tx_enable: true
+ optional_signals: []
+ variant:
+ specification: TXPO=0, RXPO=1, CMODE=0
+ required_signals:
+ - name: SERCOM2/PAD/0
+ pad: PB25
+ label: TX
+ - name: SERCOM2/PAD/1
+ pad: PB24
+ label: RX
+ clocks:
+ domain_group:
+ nodes:
+ - name: Core
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Slow
+ input: Generic clock generator 3
+ external: false
+ external_frequency: 0
+ configuration:
+ core_gclk_selection: Generic clock generator 0
+ slow_gclk_selection: Generic clock generator 3
+ SPI_0:
+ user_label: SPI_0
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM4::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.DMA
+ functionality: SPI
+ api: HAL:Driver:SPI_Master_DMA
+ configuration:
+ spi_master_advanced: false
+ spi_master_arch_cpha: Sample input on leading edge
+ spi_master_arch_cpol: SCK is low when idle
+ spi_master_arch_dbgstop: Keep running
+ spi_master_arch_dord: MSB first
+ spi_master_arch_ibon: In data stream
+ spi_master_arch_runstdby: false
+ spi_master_baud_rate: 1000000
+ spi_master_character_size: 8 bits
+ spi_master_dma_rx_channel: 3
+ spi_master_dma_tx_channel: 2
+ spi_master_dummybyte: 511
+ spi_master_rx_channel: true
+ spi_master_rx_enable: true
+ optional_signals: []
+ variant:
+ specification: TXPO=0, RXPO=3
+ required_signals:
+ - name: SERCOM4/PAD/0
+ pad: PB27
+ label: MOSI
+ - name: SERCOM4/PAD/1
+ pad: PB26
+ label: SCK
+ - name: SERCOM4/PAD/3
+ pad: PB29
+ label: MISO
+ clocks:
+ domain_group:
+ nodes:
+ - name: Core
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Slow
+ input: Generic clock generator 3
+ external: false
+ external_frequency: 0
+ configuration:
+ core_gclk_selection: Generic clock generator 0
+ slow_gclk_selection: Generic clock generator 3
+ TIMER_0:
+ user_label: TIMER_0
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC0::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer
+ functionality: Timer
+ api: Lite:TC:Timer
+ configuration:
+ cc_cc0: 12000
+ cc_cc1: 6000
+ cc_control: true
+ count_control: false
+ count_count: 0
+ ctrla_alock: false
+ ctrla_capten0: false
+ ctrla_capten1: false
+ ctrla_captmode0: DEFAULT
+ ctrla_captmode1: DEFAULT
+ ctrla_control: true
+ ctrla_copen0: false
+ ctrla_copen1: false
+ ctrla_enable: true
+ ctrla_mode: 0
+ ctrla_ondemand: false
+ ctrla_prescaler: DIV1
+ ctrla_prescsync: GCLK
+ ctrla_runstdby: false
+ ctrlbset_cmd: NONE
+ ctrlbset_control: false
+ ctrlbset_dir: false
+ ctrlbset_lupd: false
+ ctrlbset_oneshot: false
+ ctrlc_inven0: false
+ ctrlc_inven1: false
+ dbgctrl_control: false
+ dbgctrl_dbgrun: false
+ drvctrl_control: false
+ evctrl_control: true
+ evctrl_evact: 'OFF'
+ evctrl_mceo0: true
+ evctrl_mceo1: true
+ evctrl_ovfeo: true
+ evctrl_tcei: false
+ evctrl_tcinv: false
+ intenset_control: true
+ intenset_err: false
+ intenset_mc0: false
+ intenset_mc1: true
+ intenset_ovf: true
+ wave_control: true
+ wave_wavegen: MFRQ
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: TC
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ configuration:
+ tc_gclk_selection: Generic clock generator 0
+pads:
+ PA08:
+ name: PA08
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA08
+ mode: Advanced
+ user_label: PA08
+ configuration: null
+ PA09:
+ name: PA09
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA09
+ mode: Advanced
+ user_label: PA09
+ configuration: null
+ PA10:
+ name: PA10
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA10
+ mode: Advanced
+ user_label: PA10
+ configuration: null
+ PA11:
+ name: PA11
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA11
+ mode: Advanced
+ user_label: PA11
+ configuration: null
+ PB10:
+ name: PB10
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB10
+ mode: Digital input
+ user_label: PB10
+ configuration: null
+ PB11:
+ name: PB11
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB11
+ mode: Digital input
+ user_label: PB11
+ configuration: null
+ PB24:
+ name: PB24
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB24
+ mode: Peripheral IO
+ user_label: PB24
+ configuration: null
+ PB25:
+ name: PB25
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB25
+ mode: Peripheral IO
+ user_label: PB25
+ configuration: null
+ PB26:
+ name: PB26
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB26
+ mode: Digital output
+ user_label: PB26
+ configuration: null
+ PB27:
+ name: PB27
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB27
+ mode: Digital output
+ user_label: PB27
+ configuration: null
+ SPI_CS:
+ name: PB28
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB28
+ mode: Digital output
+ user_label: SPI_CS
+ configuration:
+ pad_initial_level: High
+ PB29:
+ name: PB29
+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB29
+ mode: Digital input
+ user_label: PB29
+ configuration: null
+toolchain_options: []
+static_files: []
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/RTE_Components.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/RTE_Components.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/RTE_Components.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/RTE_Components.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_cmcc_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_cmcc_config.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_cmcc_config.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_cmcc_config.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_dmac_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_dmac_config.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_dmac_config.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_dmac_config.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_evsys_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_evsys_config.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_evsys_config.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_evsys_config.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_gclk_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_gclk_config.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_gclk_config.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_gclk_config.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_mclk_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_mclk_config.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_mclk_config.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_mclk_config.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_osc32kctrl_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_osc32kctrl_config.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_osc32kctrl_config.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_osc32kctrl_config.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_oscctrl_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_oscctrl_config.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_oscctrl_config.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_oscctrl_config.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_port_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_port_config.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_port_config.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_port_config.h
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_qspi_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_qspi_config.h
new file mode 100644
index 0000000..040413f
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_qspi_config.h
@@ -0,0 +1,84 @@
+/* Auto-generated config file hpl_qspi_config.h */
+#ifndef HPL_QSPI_CONFIG_H
+#define HPL_QSPI_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include
+
+// Basic settings
+
+#ifndef CONF_CONF_QSPI_ENABLE
+#define CONF_CONF_QSPI_ENABLE 1
+#endif
+
+// Baud rate <1-150000000>
+// The SPI data transfer rate. Note: (fqspi_clock / baudrate) < 255
+// qspi_baud_rate
+#ifndef CONF_QSPI_BAUD
+#define CONF_QSPI_BAUD 6000000
+#endif
+
+// Clock Polarity
+// <0x0=>The inactive state value of SPCK is logic level zero.
+// <0x1=>The inactive state value of SPCK is logic level one.
+// Determines the inactive state value of the serial clock (SPCK).
+// qspi_cpol
+#ifndef CONF_QSPI_CPOL
+#define CONF_QSPI_CPOL 0x0
+#endif
+
+// Clock Phase
+// <0x0=>Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
+// <0x1=>Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
+// Determines which edge of SPCK causes data to change and which edge causes data to be captured.
+// qspi_cpha
+#ifndef CONF_QSPI_CPHA
+#define CONF_QSPI_CPHA 0x0
+#endif
+
+//
+
+// Advanced Configuration
+// qspi_advanced
+#ifndef CONF_QSPI_ADVANCED
+#define CONF_QSPI_ADVANCED 0
+#endif
+
+// Delay Before QSCK (ns) <0-255000>
+// This field defines the delay from QCS falling edge (activation) to the first valid QSCK transition (in ns).
+// qspi_dlybs
+#ifndef CONF_QSPI_DLY_BS
+#define CONF_QSPI_DLY_BS 0
+#endif
+
+// Minimum Inactive QCS Delay (ns) <0-8160000>
+// This field defines the minimum delay between the deactivation and the activation of QCS (in ns).
+// qspi_dlycs
+#ifndef CONF_QSPI_DLY_CS
+#define CONF_QSPI_DLY_CS 0
+#endif
+
+//
+
+/* Calculate baud register value from requested baudrate value */
+#ifndef CONF_QSPI_BAUD_RATE
+#define CONF_QSPI_BAUD_RATE ((CONF_CPU_FREQUENCY / CONF_QSPI_BAUD) - 1)
+#if CONF_QSPI_BAUD > CONF_CPU_FREQUENCY || CONF_QSPI_BAUD_RATE > 255
+#warning Invalid baudrate, please check.
+#endif
+#endif
+
+/* Calculates the value of the CSR DLYCS field given the desired delay (in ns) */
+#ifndef CONF_QSPI_DLYCS
+#define CONF_QSPI_DLYCS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_CS) / 1000)
+#endif
+
+/* Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
+#ifndef CONF_QSPI_DLYBS
+#define CONF_QSPI_DLYBS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_BS) / 1000)
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_QSPI_CONFIG_H
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_sercom_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_sercom_config.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_sercom_config.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_sercom_config.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/peripheral_clk_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/peripheral_clk_config.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/peripheral_clk_config.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/peripheral_clk_config.h
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/spi_slave_dma_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/spi_slave_dma_config.h
new file mode 100644
index 0000000..f24221b
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/spi_slave_dma_config.h
@@ -0,0 +1,47 @@
+/**
+ * \file
+ *
+ * \brief Application implement
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit Microchip Support
+ */
+
+#ifndef SPI_SLAVE_DMA_CONFIG_H
+#define SPI_SLAVE_DMA_CONFIG_H
+
+// Delay in Micro Seconds <1-1000>
+// Delay in microseconds to hold CS low after data transfer completion by DMA
+// delay_in_us_cs_low
+#ifndef CONF_DELAY_US
+#define CONF_DELAY_US 10
+#endif
+
+#endif
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/stdio_redirect_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/stdio_redirect_config.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/stdio_redirect_config.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/stdio_redirect_config.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Default.xml b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Default.xml
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Default.xml
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Default.xml
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_flash.ld b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_flash.ld
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_flash.ld
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_flash.ld
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_sram.ld b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_sram.ld
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_sram.ld
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_sram.ld
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/startup_same54.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/startup_same54.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/startup_same54.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/startup_same54.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/system_same54.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/system_same54.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/system_same54.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/system_same54.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.componentinfo.xml b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.componentinfo.xml
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.componentinfo.xml
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.componentinfo.xml
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj
new file mode 100644
index 0000000..f25e418
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj
@@ -0,0 +1,974 @@
+
+
+
+ 2.0
+ 7.0
+ com.Atmel.ARMGCC.C
+ dce6c7e3-ee26-4d79-826b-08594b9ad897
+ ATSAME54P20A
+ none
+ Executable
+ C
+ $(MSBuildProjectName)
+ .elf
+ $(MSBuildProjectDirectory)\$(Configuration)
+ Master_Slave_IF_TestMaster
+ Master_Slave_IF_TestMaster
+ Master_Slave_IF_TestMaster
+ Native
+ true
+ false
+ true
+ true
+
+
+ true
+
+ 2
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+ gcc
+ .atmelstart\atmel_start_config.atstart
+ .atmelstart\AtmelStart.gpdsc
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ True
+ True
+ True
+ True
+ True
+
+
+ NDEBUG
+
+
+
+
+ %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\
+ ../Config
+ ../
+ ../examples
+ ../hal/include
+ ../hal/utils/include
+ ../hpl/cmcc
+ ../hpl/core
+ ../hpl/dmac
+ ../hpl/evsys
+ ../hpl/gclk
+ ../hpl/mclk
+ ../hpl/osc32kctrl
+ ../hpl/oscctrl
+ ../hpl/pm
+ ../hpl/port
+ ../hpl/qspi
+ ../hpl/ramecc
+ ../hpl/sercom
+ ../hpl/tc
+ ../hri
+ ../stdio_redirect
+ %24(PackRepoDir)\atmel\SAME54_DFP\1.1.134\include
+
+
+ Optimize for size (-Os)
+ True
+ True
+ -std=gnu99 -mfloat-abi=softfp -mfpu=fpv4-sp-d16
+ True
+
+
+ libm
+
+
+
+
+ %24(ProjectDir)\Device_Startup
+
+
+ True
+ -Tsame54p20a_flash.ld
+
+
+ %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\
+ ../Config
+ ../
+ ../examples
+ ../hal/include
+ ../hal/utils/include
+ ../hpl/cmcc
+ ../hpl/core
+ ../hpl/dmac
+ ../hpl/evsys
+ ../hpl/gclk
+ ../hpl/mclk
+ ../hpl/osc32kctrl
+ ../hpl/oscctrl
+ ../hpl/pm
+ ../hpl/port
+ ../hpl/qspi
+ ../hpl/ramecc
+ ../hpl/sercom
+ ../hpl/tc
+ ../hri
+ ../stdio_redirect
+ %24(PackRepoDir)\atmel\SAME54_DFP\1.1.134\include
+
+
+
+
+ %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\
+ ../Config
+ ../
+ ../examples
+ ../hal/include
+ ../hal/utils/include
+ ../hpl/cmcc
+ ../hpl/core
+ ../hpl/dmac
+ ../hpl/evsys
+ ../hpl/gclk
+ ../hpl/mclk
+ ../hpl/osc32kctrl
+ ../hpl/oscctrl
+ ../hpl/pm
+ ../hpl/port
+ ../hpl/qspi
+ ../hpl/ramecc
+ ../hpl/sercom
+ ../hpl/tc
+ ../hri
+ ../stdio_redirect
+ %24(PackRepoDir)\atmel\SAME54_DFP\1.1.134\include
+
+
+
+
+
+
+
+
+ True
+ True
+ True
+ True
+ True
+
+
+ DEBUG
+
+
+
+
+ %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\
+ ../Config
+ ../
+ ../examples
+ ../hal/include
+ ../hal/utils/include
+ ../hpl/cmcc
+ ../hpl/core
+ ../hpl/dmac
+ ../hpl/evsys
+ ../hpl/gclk
+ ../hpl/mclk
+ ../hpl/osc32kctrl
+ ../hpl/oscctrl
+ ../hpl/pm
+ ../hpl/port
+ ../hpl/qspi
+ ../hpl/ramecc
+ ../hpl/sercom
+ ../hpl/tc
+ ../hri
+ ../stdio_redirect
+ %24(PackRepoDir)\atmel\SAME54_DFP\1.1.134\include
+
+
+ Optimize debugging experience (-Og)
+ True
+ Maximum (-g3)
+ True
+ -std=gnu99 -mfloat-abi=softfp -mfpu=fpv4-sp-d16
+ True
+
+
+ libm
+
+
+
+
+ %24(ProjectDir)\Device_Startup
+
+
+ True
+ -Tsame54p20a_flash.ld
+
+
+ %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\
+ ../Config
+ ../
+ ../examples
+ ../hal/include
+ ../hal/utils/include
+ ../hpl/cmcc
+ ../hpl/core
+ ../hpl/dmac
+ ../hpl/evsys
+ ../hpl/gclk
+ ../hpl/mclk
+ ../hpl/osc32kctrl
+ ../hpl/oscctrl
+ ../hpl/pm
+ ../hpl/port
+ ../hpl/qspi
+ ../hpl/ramecc
+ ../hpl/sercom
+ ../hpl/tc
+ ../hri
+ ../stdio_redirect
+ %24(PackRepoDir)\atmel\SAME54_DFP\1.1.134\include
+
+
+ Default (-g)
+
+
+ %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\
+ ../Config
+ ../
+ ../examples
+ ../hal/include
+ ../hal/utils/include
+ ../hpl/cmcc
+ ../hpl/core
+ ../hpl/dmac
+ ../hpl/evsys
+ ../hpl/gclk
+ ../hpl/mclk
+ ../hpl/osc32kctrl
+ ../hpl/oscctrl
+ ../hpl/pm
+ ../hpl/port
+ ../hpl/qspi
+ ../hpl/ramecc
+ ../hpl/sercom
+ ../hpl/tc
+ ../hri
+ ../stdio_redirect
+ %24(PackRepoDir)\atmel\SAME54_DFP\1.1.134\include
+
+
+ Default (-Wa,-g)
+
+
+
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
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+
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+
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+
+
+ compile
+
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+
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+
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+
+
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+
+
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+
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+
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+
+
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+
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+
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+
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+
+
+ compile
+
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+
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+
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+
+
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+
+
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+
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+
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+
+
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+
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+
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+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
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+
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+
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+
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+
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+
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+ compile
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+ compile
+
+
+ compile
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+
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+
+
+ compile
+
+
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+
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+
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+
+
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+
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+ compile
+
+
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+
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+
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+
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+
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+
+
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+
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+ compile
+
+
+ compile
+
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+
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+
\ No newline at end of file
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.h
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start_pins.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start_pins.h
new file mode 100644
index 0000000..57cbb24
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start_pins.h
@@ -0,0 +1,43 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+#ifndef ATMEL_START_PINS_H_INCLUDED
+#define ATMEL_START_PINS_H_INCLUDED
+
+#include
+
+// SAME54 has 14 pin functions
+
+#define GPIO_PIN_FUNCTION_A 0
+#define GPIO_PIN_FUNCTION_B 1
+#define GPIO_PIN_FUNCTION_C 2
+#define GPIO_PIN_FUNCTION_D 3
+#define GPIO_PIN_FUNCTION_E 4
+#define GPIO_PIN_FUNCTION_F 5
+#define GPIO_PIN_FUNCTION_G 6
+#define GPIO_PIN_FUNCTION_H 7
+#define GPIO_PIN_FUNCTION_I 8
+#define GPIO_PIN_FUNCTION_J 9
+#define GPIO_PIN_FUNCTION_K 10
+#define GPIO_PIN_FUNCTION_L 11
+#define GPIO_PIN_FUNCTION_M 12
+#define GPIO_PIN_FUNCTION_N 13
+
+#define PA08 GPIO(GPIO_PORTA, 8)
+#define PA09 GPIO(GPIO_PORTA, 9)
+#define PA10 GPIO(GPIO_PORTA, 10)
+#define PA11 GPIO(GPIO_PORTA, 11)
+#define PB10 GPIO(GPIO_PORTB, 10)
+#define PB11 GPIO(GPIO_PORTB, 11)
+#define PB24 GPIO(GPIO_PORTB, 24)
+#define PB25 GPIO(GPIO_PORTB, 25)
+#define PB26 GPIO(GPIO_PORTB, 26)
+#define PB27 GPIO(GPIO_PORTB, 27)
+#define SPI_CS GPIO(GPIO_PORTB, 28)
+#define PB29 GPIO(GPIO_PORTB, 29)
+
+#endif // ATMEL_START_PINS_H_INCLUDED
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/documentation/stdio.rst b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/documentation/stdio.rst
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/documentation/stdio.rst
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/documentation/stdio.rst
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.c
new file mode 100644
index 0000000..1a01e09
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.c
@@ -0,0 +1,369 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+
+#include "driver_init.h"
+#include
+#include
+#include
+
+struct qspi_sync_descriptor QUAD_SPI_0;
+
+struct usart_sync_descriptor TARGET_IO;
+
+struct spi_m_dma_descriptor SPI_0;
+
+void EVENT_SYSTEM_0_init(void)
+{
+ hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_0, CONF_GCLK_EVSYS_CHANNEL_0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+ hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);
+
+ event_system_init();
+}
+
+void QUAD_SPI_0_PORT_init(void)
+{
+
+ // Set pin direction to input
+ gpio_set_pin_direction(PB11, GPIO_DIRECTION_IN);
+
+ gpio_set_pin_pull_mode(PB11,
+ // Pull configuration
+ // pad_pull_config
+ // Off
+ // Pull-up
+ // Pull-down
+ GPIO_PULL_OFF);
+
+ gpio_set_pin_function(PB11, PINMUX_PB11H_QSPI_CS);
+
+ gpio_set_pin_direction(PA08,
+ // Pin direction
+ // pad_direction
+ // Off
+ // In
+ // Out
+ GPIO_DIRECTION_OUT);
+
+ gpio_set_pin_level(PA08,
+ // Initial level
+ // pad_initial_level
+ // Low
+ // High
+ false);
+
+ gpio_set_pin_pull_mode(PA08,
+ // Pull configuration
+ // pad_pull_config
+ // Off
+ // Pull-up
+ // Pull-down
+ GPIO_PULL_OFF);
+
+ gpio_set_pin_function(PA08,
+ // Pin function
+ // pad_function
+ // Auto : use driver pinmux if signal is imported by driver, else turn off function
+ // Auto
+ // Off
+ // A
+ // B
+ // C
+ // D
+ // E
+ // F
+ // G
+ // H
+ // I
+ // J
+ // K
+ // L
+ // M
+ // N
+ PINMUX_PA08H_QSPI_DATA0);
+
+ gpio_set_pin_direction(PA09,
+ // Pin direction
+ // pad_direction
+ // Off
+ // In
+ // Out
+ GPIO_DIRECTION_OUT);
+
+ gpio_set_pin_level(PA09,
+ // Initial level
+ // pad_initial_level
+ // Low
+ // High
+ false);
+
+ gpio_set_pin_pull_mode(PA09,
+ // Pull configuration
+ // pad_pull_config
+ // Off
+ // Pull-up
+ // Pull-down
+ GPIO_PULL_OFF);
+
+ gpio_set_pin_function(PA09,
+ // Pin function
+ // pad_function
+ // Auto : use driver pinmux if signal is imported by driver, else turn off function
+ // Auto
+ // Off
+ // A
+ // B
+ // C
+ // D
+ // E
+ // F
+ // G
+ // H
+ // I
+ // J
+ // K
+ // L
+ // M
+ // N
+ PINMUX_PA09H_QSPI_DATA1);
+
+ gpio_set_pin_direction(PA10,
+ // Pin direction
+ // pad_direction
+ // Off
+ // In
+ // Out
+ GPIO_DIRECTION_OUT);
+
+ gpio_set_pin_level(PA10,
+ // Initial level
+ // pad_initial_level
+ // Low
+ // High
+ false);
+
+ gpio_set_pin_pull_mode(PA10,
+ // Pull configuration
+ // pad_pull_config
+ // Off
+ // Pull-up
+ // Pull-down
+ GPIO_PULL_OFF);
+
+ gpio_set_pin_function(PA10,
+ // Pin function
+ // pad_function
+ // Auto : use driver pinmux if signal is imported by driver, else turn off function
+ // Auto
+ // Off
+ // A
+ // B
+ // C
+ // D
+ // E
+ // F
+ // G
+ // H
+ // I
+ // J
+ // K
+ // L
+ // M
+ // N
+ PINMUX_PA10H_QSPI_DATA2);
+
+ gpio_set_pin_direction(PA11,
+ // Pin direction
+ // pad_direction
+ // Off
+ // In
+ // Out
+ GPIO_DIRECTION_OUT);
+
+ gpio_set_pin_level(PA11,
+ // Initial level
+ // pad_initial_level
+ // Low
+ // High
+ false);
+
+ gpio_set_pin_pull_mode(PA11,
+ // Pull configuration
+ // pad_pull_config
+ // Off
+ // Pull-up
+ // Pull-down
+ GPIO_PULL_OFF);
+
+ gpio_set_pin_function(PA11,
+ // Pin function
+ // pad_function
+ // Auto : use driver pinmux if signal is imported by driver, else turn off function
+ // Auto
+ // Off
+ // A
+ // B
+ // C
+ // D
+ // E
+ // F
+ // G
+ // H
+ // I
+ // J
+ // K
+ // L
+ // M
+ // N
+ PINMUX_PA11H_QSPI_DATA3);
+
+ // Set pin direction to input
+ gpio_set_pin_direction(PB10, GPIO_DIRECTION_IN);
+
+ gpio_set_pin_pull_mode(PB10,
+ // Pull configuration
+ // pad_pull_config
+ // Off
+ // Pull-up
+ // Pull-down
+ GPIO_PULL_OFF);
+
+ gpio_set_pin_function(PB10, PINMUX_PB10H_QSPI_SCK);
+}
+
+void QUAD_SPI_0_CLOCK_init(void)
+{
+ hri_mclk_set_AHBMASK_QSPI_bit(MCLK);
+ hri_mclk_set_AHBMASK_QSPI_2X_bit(MCLK);
+ hri_mclk_set_APBCMASK_QSPI_bit(MCLK);
+}
+
+void QUAD_SPI_0_init(void)
+{
+ QUAD_SPI_0_CLOCK_init();
+ qspi_sync_init(&QUAD_SPI_0, QSPI);
+ QUAD_SPI_0_PORT_init();
+}
+
+void TARGET_IO_PORT_init(void)
+{
+
+ gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0);
+
+ gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1);
+}
+
+void TARGET_IO_CLOCK_init(void)
+{
+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+ hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
+}
+
+void TARGET_IO_init(void)
+{
+ TARGET_IO_CLOCK_init();
+ usart_sync_init(&TARGET_IO, SERCOM2, (void *)NULL);
+ TARGET_IO_PORT_init();
+}
+
+void SPI_0_PORT_init(void)
+{
+
+ gpio_set_pin_level(PB27,
+ // Initial level
+ // pad_initial_level
+ // Low
+ // High
+ false);
+
+ // Set pin direction to output
+ gpio_set_pin_direction(PB27, GPIO_DIRECTION_OUT);
+
+ gpio_set_pin_function(PB27, PINMUX_PB27D_SERCOM4_PAD0);
+
+ gpio_set_pin_level(PB26,
+ // Initial level
+ // pad_initial_level
+ // Low
+ // High
+ false);
+
+ // Set pin direction to output
+ gpio_set_pin_direction(PB26, GPIO_DIRECTION_OUT);
+
+ gpio_set_pin_function(PB26, PINMUX_PB26D_SERCOM4_PAD1);
+
+ // Set pin direction to input
+ gpio_set_pin_direction(PB29, GPIO_DIRECTION_IN);
+
+ gpio_set_pin_pull_mode(PB29,
+ // Pull configuration
+ // pad_pull_config
+ // Off
+ // Pull-up
+ // Pull-down
+ GPIO_PULL_OFF);
+
+ gpio_set_pin_function(PB29, PINMUX_PB29D_SERCOM4_PAD3);
+}
+
+void SPI_0_CLOCK_init(void)
+{
+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+ hri_mclk_set_APBDMASK_SERCOM4_bit(MCLK);
+}
+
+void SPI_0_init(void)
+{
+ SPI_0_CLOCK_init();
+ spi_m_dma_init(&SPI_0, SERCOM4);
+ SPI_0_PORT_init();
+}
+
+void TIMER_0_CLOCK_init(void)
+{
+ hri_mclk_set_APBAMASK_TC0_bit(MCLK);
+
+ hri_mclk_set_APBAMASK_TC1_bit(MCLK);
+ hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void system_init(void)
+{
+ init_mcu();
+
+ // GPIO on PB28
+
+ gpio_set_pin_level(SPI_CS,
+ // Initial level
+ // pad_initial_level
+ // Low
+ // High
+ true);
+
+ // Set pin direction to output
+ gpio_set_pin_direction(SPI_CS, GPIO_DIRECTION_OUT);
+
+ gpio_set_pin_function(SPI_CS, GPIO_PIN_FUNCTION_OFF);
+
+ EVENT_SYSTEM_0_init();
+
+ QUAD_SPI_0_init();
+
+ TARGET_IO_init();
+
+ SPI_0_init();
+
+ TIMER_0_CLOCK_init();
+
+ TIMER_0_init();
+}
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.h
new file mode 100644
index 0000000..46bf53e
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.h
@@ -0,0 +1,64 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+#ifndef DRIVER_INIT_INCLUDED
+#define DRIVER_INIT_INCLUDED
+
+#include "atmel_start_pins.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+
+#include
+
+#include
+#include
+
+extern struct qspi_sync_descriptor QUAD_SPI_0;
+
+extern struct usart_sync_descriptor TARGET_IO;
+
+extern struct spi_m_dma_descriptor SPI_0;
+
+void QUAD_SPI_0_PORT_init(void);
+void QUAD_SPI_0_CLOCK_init(void);
+void QUAD_SPI_0_init(void);
+
+void TARGET_IO_PORT_init(void);
+void TARGET_IO_CLOCK_init(void);
+void TARGET_IO_init(void);
+
+void SPI_0_PORT_init(void);
+void SPI_0_CLOCK_init(void);
+void SPI_0_init(void);
+
+void TIMER_0_CLOCK_init(void);
+
+int8_t TIMER_0_init(void);
+
+/**
+ * \brief Perform system initialization, initialize pins and clocks for
+ * peripherals
+ */
+void system_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif // DRIVER_INIT_INCLUDED
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/ethercat/ethercat_qspi.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/ethercat/ethercat_qspi.c
new file mode 100644
index 0000000..87732bd
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/ethercat/ethercat_qspi.c
@@ -0,0 +1,112 @@
+/*
+ * ethercat_qspi.c
+ *
+ * Created: 15/07/2021 19:30:41
+ * Author: Nick-XMG
+ */
+
+#include "ethercat_qspi.h"
+
+#define ECAT_SIZE_WR 64 //max fifo size
+#define ECAT_SIZE_RD ECAT_SIZE_WR
+#define ECAT_SIZE_WR_REG ECAT_SIZE_WR/4
+#define ECAT_SIZE_RD_REG ECAT_SIZE_WR/4
+
+#define SQI_READ (0x0B<<16)
+#define SQI_WRITE (0x02<<16)
+#define SQI_INC (0x40<<8)
+#define SQI_DEC (0x80<<8)
+#define ECAT_PRAM_RD_DATA 0x0000
+#define ECAT_PRAM_WR_DATA 0x0020
+#define HW_CFG 0x0074
+#define BYTE_TEST 0x0064
+#define ECAT_PRAM_RD_ADDR_LEN 0x0308
+#define ECAT_PRAM_RD_CMD 0x030C
+#define ECAT_PRAM_WR_ADDR_LEN 0x0310
+#define ECAT_PRAM_WR_CMD 0x0314
+
+#define LAN9252_RDY (1<<27)
+
+#define PDRAM_RD_ADDRESS 0x1100
+#define PDRAM_RD_LENGTH ECAT_SIZE_RD //do the math later to automatize. fixed to 64 for now.
+#define PDRAM_WR_ADDRESS 0x1800
+#define PDRAM_WR_LENGTH ECAT_SIZE_WR
+#define PDRAM_LENGTH_MAX 64
+#define PDRAM_LENGTH_SHORT 32
+#define FIFO_DEPTH 16
+#define PDRAM_REG_MAX PDRAM_LENGTH_SHORT/4
+#define PRAM_X_ABORT (1<<30)
+#define CSR_BUSY 0x80000000
+
+#define buffer_size 3*ECAT_SIZE_WR_REG //changed to double
+#define motor_buffer_size buffer_size/3
+
+uint32_t QSPI_tx_buffer[buffer_size]={0};
+uint32_t QSPI_rx_buffer[buffer_size]={0};
+
+
+struct SPI_Slave S1 = {
+ .SPI_Sn = &SPI_0,
+ .state = 0,
+ .SS_pin = SPI_CS,
+ .tx_buffer = &QSPI_rx_buffer[0],
+ .rx_buffer = &QSPI_tx_buffer[0],
+};
+
+uint32_t QSPI_cmds[]= {0,PRAM_X_ABORT,0,PRAM_X_ABORT,
+ ((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS,CSR_BUSY,
+ ((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX,CSR_BUSY,
+ ((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX*2, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX*2,CSR_BUSY,
+ };
+
+uint32_t zero[FIFO_DEPTH]={0};
+
+struct _qspi_command rd_cmd = {
+ .inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
+ .inst_frame.bits.inst_en = 0,
+ .inst_frame.bits.data_en = 1,
+ .inst_frame.bits.addr_en = 1,
+ .inst_frame.bits.dummy_cycles = 6,
+ .inst_frame.bits.tfr_type = QSPI_READMEM_ACCESS,
+};
+
+struct _qspi_command wr_cmd = {
+ .inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
+ .inst_frame.bits.inst_en = 0,
+ .inst_frame.bits.data_en = 1,
+ .inst_frame.bits.addr_en = 1,
+ .inst_frame.bits.dummy_cycles = 0,
+ .inst_frame.bits.tfr_type = QSPI_WRITEMEM_ACCESS,
+};
+
+struct _qspi_command qspi_cmd = {
+ .inst_frame.bits.width = QSPI_INST1_ADDR1_DATA1,
+ .inst_frame.bits.inst_en = 1,
+ .inst_frame.bits.data_en = 0,
+ .inst_frame.bits.addr_en = 0,
+ .inst_frame.bits.dummy_cycles = 0,
+ .instruction = 0x38,
+ .inst_frame.bits.tfr_type = QSPI_WRITE_ACCESS,
+};
+
+volatile uint8_t SPI_S1_SS_state = 0;
+volatile uint8_t* M1_tx_cnt = &QSPI_rx_buffer[0];
+volatile uint8_t* M1_rx_cnt = &QSPI_tx_buffer[0];
+uint8_t sync_rx_buffer[2*2*buffer_size/3]={0};
+uint8_t sync_tx_buffer[2*2*buffer_size/3]={0xED};
+volatile uint32_t status = 0;
+
+struct _qspi_command *spi_cmd= &wr_cmd;
+volatile uint8_t tx_complete=3;
+volatile uint32_t *ECAT_BYTE_TEST = QSPI_AHB+BYTE_TEST+SQI_READ;
+volatile uint32_t *ECAT_FIFO_RD_RD = QSPI_AHB+SQI_READ +ECAT_PRAM_RD_DATA;
+volatile uint32_t *ECAT_FIFO_WR_WR = QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_DATA;
+volatile uint32_t *ECAT_HW_CFG_RD = QSPI_AHB+SQI_READ+HW_CFG;
+volatile uint32_t *ECAT_FIFO_RD_ADLEN_WR = QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_RD_ADDR_LEN;
+volatile uint32_t *ECAT_FIFO_WR_ADLEN_WR = QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
+volatile uint32_t *ECAT_FIFO_WR_ADLEN_RD = QSPI_AHB+SQI_READ+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
+volatile uint32_t *ECAT_FIFO_WR_CMD_RD = QSPI_AHB+SQI_READ+ECAT_PRAM_WR_CMD;
+volatile uint32_t *ECAT_FIFO_WR_CMD_WR = QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_CMD;
+
+volatile enum ecat_states ecat_state = wait;
+volatile enum ecat_states next_ecat_state = wait;
\ No newline at end of file
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/ethercat/ethercat_qspi.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/ethercat/ethercat_qspi.h
new file mode 100644
index 0000000..c017c55
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/ethercat/ethercat_qspi.h
@@ -0,0 +1,69 @@
+/*
+ * ethercat_qspi.h
+ *
+ * Created: 15/07/2021 19:30:17
+ * Author: Nick-XMG
+ */
+
+#ifndef ETHERCAT_QSPI_H_
+#define ETHERCAT_QSPI_H_
+
+#include "atmel_start.h"
+#include "math.h"
+
+
+extern uint32_t QSPI_tx_buffer[];
+extern uint32_t QSPI_rx_buffer[];
+
+struct SPI_Slave {
+ struct spi_m_dma_descriptor *SPI_Sn;
+ uint8_t state;
+ uint32_t SS_pin;
+ uint32_t *tx_buffer;
+ uint32_t *rx_buffer;
+};
+
+COMPILER_ALIGNED(16)
+DmacDescriptor dummy_rx_descriptor;
+DmacDescriptor dummy_tx_descriptor;
+
+volatile uint8_t SPI_S1_SS_state;
+volatile uint8_t *M1_tx_cnt;
+volatile uint8_t *M1_rx_cnt;
+extern uint8_t sync_rx_buffer[];
+extern uint8_t sync_tx_buffer[];
+extern uint32_t QSPI_cmds[];
+extern uint32_t zero[];
+
+struct _qspi_command *spi_cmd;
+
+volatile uint32_t *INPUT_ADDRESS ;
+volatile uint32_t *OUTPUT_ADDRESS;
+
+volatile uint32_t read_buffer =0;
+volatile uint8_t ecat_length= 0;
+
+struct io_descriptor *SPI_S1_io;
+
+enum ecat_states {
+ abort_fifo,
+ dlt_rdram,
+ cf_dlt_rdram,
+ write_fifo,
+ config_fifo,
+ read_fifo,
+ wait,
+ wait2,
+ en_SQI,
+ temp,rd_rdy
+};
+
+volatile enum ecat_states ecat_state;
+volatile enum ecat_states next_ecat_state;
+
+volatile uint8_t wr_cnt = 0;
+volatile uint8_t rd_cnt = 0;
+volatile init_timer =0;
+volatile bool run_ECAT = false;
+
+#endif /* ETHERCAT_QSPI_H_ */
\ No newline at end of file
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.c
new file mode 100644
index 0000000..7dcbf25
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.c
@@ -0,0 +1,72 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+
+#include "driver_examples.h"
+#include "driver_init.h"
+#include "utils.h"
+
+/**
+ * Example of using QUAD_SPI_0 to get N25Q256A status value,
+ * and check bit 0 which indicate embedded operation is busy or not.
+ */
+void QUAD_SPI_0_example(void)
+{
+ uint8_t status = 0xFF;
+ struct _qspi_command cmd = {
+ .inst_frame.bits.inst_en = 1,
+ .inst_frame.bits.data_en = 1,
+ .inst_frame.bits.tfr_type = QSPI_READ_ACCESS,
+ .instruction = 0x05,
+ .buf_len = 1,
+ .rx_buf = &status,
+ };
+
+ qspi_sync_enable(&QUAD_SPI_0);
+ while (status & (1 << 0)) {
+ qspi_sync_serial_run_command(&QUAD_SPI_0, &cmd);
+ }
+ qspi_sync_deinit(&QUAD_SPI_0);
+}
+
+/**
+ * Example of using TARGET_IO to write "Hello World" using the IO abstraction.
+ */
+void TARGET_IO_example(void)
+{
+ struct io_descriptor *io;
+ usart_sync_get_io_descriptor(&TARGET_IO, &io);
+ usart_sync_enable(&TARGET_IO);
+
+ io_write(io, (uint8_t *)"Hello World!", 12);
+}
+
+/**
+ * Example of using SPI_0 to write "Hello World" using the IO abstraction.
+ *
+ * Since the driver is asynchronous we need to use statically allocated memory for string
+ * because driver initiates transfer and then returns before the transmission is completed.
+ *
+ * Once transfer has been completed the tx_cb function will be called.
+ */
+
+static uint8_t example_SPI_0[12] = "Hello World!";
+
+static void tx_complete_cb_SPI_0(struct _dma_resource *resource)
+{
+ /* Transfer completed */
+}
+
+void SPI_0_example(void)
+{
+ struct io_descriptor *io;
+ spi_m_dma_get_io_descriptor(&SPI_0, &io);
+
+ spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_TX_DONE, tx_complete_cb_SPI_0);
+ spi_m_dma_enable(&SPI_0);
+ io_write(io, example_SPI_0, 12);
+}
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.h
new file mode 100644
index 0000000..6839523
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.h
@@ -0,0 +1,24 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+#ifndef DRIVER_EXAMPLES_H_INCLUDED
+#define DRIVER_EXAMPLES_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void QUAD_SPI_0_example(void);
+
+void TARGET_IO_example(void);
+
+void SPI_0_example(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif // DRIVER_EXAMPLES_H_INCLUDED
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/evsys.rst b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/evsys.rst
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/evsys.rst
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/evsys.rst
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/quad_spi_sync.rst b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/quad_spi_sync.rst
new file mode 100644
index 0000000..a126e62
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/quad_spi_sync.rst
@@ -0,0 +1,43 @@
+The Quad SPI Synchronous Driver
+=================================
+
+The Quad SPI Interface (QSPI) is a synchronous serial data link that provides
+communication with external devices in master mode.
+
+The driver can be used for SPI serial memory middleware which support flash
+earse, program and read.
+
+
+Features
+--------
+
+* Initialization/de-initialization
+* Enabling/disabling
+* Execute command in Serial Memory Mode
+
+Applications
+------------
+
+They are commonly used in an application for using serial flash memory operating
+in single-bit SPI, Dual SPI and Quad SPI.
+
+Dependencies
+------------
+
+Serial NOR flash with Multiple I/O hardware
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+N.A
+
+Known issues and workarounds
+----------------------------
+
+N/A
+
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/spi_master_dma.rst b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/spi_master_dma.rst
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/spi_master_dma.rst
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/spi_master_dma.rst
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/usart_sync.rst b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/usart_sync.rst
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/usart_sync.rst
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/usart_sync.rst
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_atomic.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_atomic.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_atomic.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_atomic.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_cache.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_cache.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_cache.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_cache.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_delay.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_delay.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_delay.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_delay.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_evsys.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_evsys.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_evsys.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_evsys.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_gpio.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_gpio.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_gpio.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_gpio.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_init.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_init.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_init.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_init.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_io.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_io.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_io.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_io.h
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_qspi_sync.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_qspi_sync.h
new file mode 100644
index 0000000..de80199
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_qspi_sync.h
@@ -0,0 +1,122 @@
+/**
+ * \file
+ *
+ * \brief Quad QSPI related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_QSPI_INCLUDED
+#define _HAL_QSPI_INCLUDED
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_quad_spi_sync
+ *
+ *@{
+ */
+
+/**
+ * \brief QSPI descriptor structure
+ */
+struct qspi_sync_descriptor {
+ struct _qspi_sync_dev dev;
+};
+
+/**
+ * \brief Initialize QSPI low level driver.
+ *
+ * \param[in] qspi Pointer to the QSPI device instance
+ * \param[in] hw Pointer to the hardware base
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success
+ */
+int32_t qspi_sync_init(struct qspi_sync_descriptor *qspi, void *hw);
+
+/**
+ * \brief Deinitialize QSPI low level driver.
+ *
+ * \param[in] qspi Pointer to the QSPI device instance
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success
+ */
+int32_t qspi_sync_deinit(struct qspi_sync_descriptor *qspi);
+
+/**
+ * \brief Enable QSPI for access without interrupts
+ *
+ * \param[in] qspi Pointer to the QSPI device instance
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success
+ */
+int32_t qspi_sync_enable(struct qspi_sync_descriptor *qspi);
+
+/**
+ * \brief Disable QSPI for access without interrupts
+ *
+ * Disable QSPI. Deactivate all CS pins if it works as master.
+ *
+ * \param[in] qspi Pointer to the QSPI device instance
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success
+ */
+int32_t qspi_sync_disable(struct qspi_sync_descriptor *qspi);
+
+/** \brief Execute command in Serial Memory Mode.
+ *
+ * \param[in] qspi Pointer to the HAL QSPI instance
+ * \param[in] cmd Pointer to the command structure
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success
+ */
+int32_t qspi_sync_serial_run_command(struct qspi_sync_descriptor *qspi, const struct _qspi_command *cmd);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t qspi_sync_get_version(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_QSPI_INCLUDED */
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_sleep.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_sleep.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_sleep.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_sleep.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_spi_m_dma.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_spi_m_dma.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_spi_m_dma.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_spi_m_dma.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_usart_sync.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_usart_sync.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_usart_sync.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_usart_sync.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_cmcc.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_cmcc.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_cmcc.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_cmcc.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_core.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_core.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_core.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_core.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_delay.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_delay.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_delay.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_delay.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_dma.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_dma.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_dma.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_dma.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_evsys.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_evsys.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_evsys.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_evsys.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_gpio.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_gpio.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_gpio.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_gpio.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_async.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_async.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_async.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_async.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_sync.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_sync.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_sync.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_sync.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_async.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_async.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_async.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_async.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_sync.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_sync.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_sync.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_sync.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_init.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_init.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_init.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_init.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_irq.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_irq.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_irq.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_irq.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_missing_features.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_missing_features.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_missing_features.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_missing_features.h
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_qspi.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_qspi.h
new file mode 100644
index 0000000..f95ac3b
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_qspi.h
@@ -0,0 +1,149 @@
+/**
+ * \file
+ *
+ * \brief Quad SPI related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_QSPI_H_INCLUDED
+#define _HPL_QSPI_H_INCLUDED
+
+#include "compiler.h"
+
+/**
+ * \addtogroup hpl_qspi HPL QSPI
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Qspi access modes
+ */
+enum qspi_access {
+ /* Read access */
+ QSPI_READ_ACCESS = 0,
+ /* Read memory access */
+ QSPI_READMEM_ACCESS,
+ /* Write access */
+ QSPI_WRITE_ACCESS,
+ /* Write memory access */
+ QSPI_WRITEMEM_ACCESS
+};
+
+/**
+ * \brief QSPI command instruction/address/data width
+ */
+enum qspi_cmd_width {
+ /** Instruction: Single-bit, Address: Single-bit, Data: Single-bit */
+ QSPI_INST1_ADDR1_DATA1,
+ /** Instruction: Single-bit, Address: Single-bit, Data: Dual-bit */
+ QSPI_INST1_ADDR1_DATA2,
+ /** Instruction: Single-bit, Address: Single-bit, Data: Quad-bit */
+ QSPI_INST1_ADDR1_DATA4,
+ /** Instruction: Single-bit, Address: Dual-bit, Data: Dual-bit */
+ QSPI_INST1_ADDR2_DATA2,
+ /** Instruction: Single-bit, Address: Quad-bit, Data: Quad-bit */
+ QSPI_INST1_ADDR4_DATA4,
+ /** Instruction: Dual-bit, Address: Dual-bit, Data: Dual-bit */
+ QSPI_INST2_ADDR2_DATA2,
+ /** Instruction: Quad-bit, Address: Quad-bit, Data: Quad-bit */
+ QSPI_INST4_ADDR4_DATA4
+};
+
+/**
+ * \brief QSPI command option code length in bits
+ */
+enum qspi_cmd_opt_len {
+ /** The option code is 1 bit long */
+ QSPI_OPT_1BIT,
+ /** The option code is 2 bits long */
+ QSPI_OPT_2BIT,
+ /** The option code is 4 bits long */
+ QSPI_OPT_4BIT,
+ /** The option code is 8 bits long */
+ QSPI_OPT_8BIT
+};
+
+/**
+ * \brief Qspi command structure
+ */
+struct _qspi_command {
+ union {
+ struct {
+ /* Width of QSPI Addr , inst data */
+ uint32_t width : 3;
+ /* Reserved */
+ uint32_t reserved0 : 1;
+ /* Enable Instruction */
+ uint32_t inst_en : 1;
+ /* Enable Address */
+ uint32_t addr_en : 1;
+ /* Enable Option */
+ uint32_t opt_en : 1;
+ /* Enable Data */
+ uint32_t data_en : 1;
+ /* Option Length */
+ uint32_t opt_len : 2;
+ /* Address Length */
+ uint32_t addr_len : 1;
+ /* Option Length */
+ uint32_t reserved1 : 1;
+ /* Transfer type */
+ uint32_t tfr_type : 2;
+ /* Continuous read mode */
+ uint32_t continues_read : 1;
+ /* Enable Double Data Rate */
+ uint32_t ddr_enable : 1;
+ /* Dummy Cycles Length */
+ uint32_t dummy_cycles : 5;
+ /* Reserved */
+ uint32_t reserved3 : 11;
+ } bits;
+ uint32_t word;
+ } inst_frame;
+
+ uint8_t instruction;
+ uint8_t option;
+ uint32_t address;
+
+ size_t buf_len;
+ const void *tx_buf;
+ void * rx_buf;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_QSPI_H_INCLUDED */
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_qspi_dma.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_qspi_dma.h
new file mode 100644
index 0000000..7c6019a
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_qspi_dma.h
@@ -0,0 +1,146 @@
+/**
+ * \file
+ *
+ * \brief Quad SPI dma related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_QSPI_DMA_H_INCLUDED
+#define _HPL_QSPI_DMA_H_INCLUDED
+
+#include
+#include "hpl_irq.h"
+#include "hpl_dma.h"
+
+/**
+ * \addtogroup hpl_qspi_dma HPL QSPI
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** The callback types */
+enum _qspi_dma_cb_type {
+ /** Callback type for DMA transfer done */
+ QSPI_DMA_CB_XFER_DONE,
+ /** Callback type for DMA errors */
+ QSPI_DMA_CB_ERROR,
+};
+
+/**
+ * \brief QSPI DMA callback type
+ */
+typedef void (*_qspi_dma_cb_t)(struct _dma_resource *resource);
+
+/**
+ * \brief The callbacks offered by QSPI driver
+ */
+struct _qspi_dma_callbacks {
+ _qspi_dma_cb_t xfer_done;
+ _qspi_dma_cb_t error;
+};
+
+/**
+ * QSPI dma driver instance.
+ */
+struct _qspi_dma_dev {
+ /** Pointer to private data or hardware base */
+ void *prvt;
+ /**
+ * Pointer to the callback functions so that initialize the driver to
+ * handle interrupts.
+ */
+ struct _qspi_dma_callbacks cb;
+ /** DMA resource */
+ struct _dma_resource *resource;
+};
+
+/**
+ * \brief Initialize QSPI for access without interrupts
+ * It will load default hardware configuration and software struct.
+ * \param[in, out] dev Pointer to the QSPI device instance.
+ * \param[in] hw Pointer to the hardware base.
+ * \return Operation status.
+ * \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_dma_init(struct _qspi_dma_dev *dev, void *const hw);
+
+/**
+ * \brief Deinitialize QSPI
+ * Disable, reset the hardware and the software struct.
+ * \param[in, out] dev Pointer to the QSPI device instance.
+ * \return Operation status.
+ * \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_dma_deinit(struct _qspi_dma_dev *dev);
+
+/**
+ * \brief Enable QSPI for access without interrupts
+ * \param[in, out] dev Pointer to the QSPI device instance.
+ * \return Operation status.
+ * \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_dma_enable(struct _qspi_dma_dev *dev);
+
+/**
+ * \brief Disable QSPI for access without interrupts
+ * \param[in, out] dev Pointer to the QSPI device instance.
+ * \return Operation status.
+ * \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_dma_disable(struct _qspi_dma_dev *dev);
+
+/**
+ * \brief Execute command in Serial Memory Mode.
+ *
+ * \param[in] dev The pointer to QSPI device instance
+ * \param[in] cmd The pointer to the command information
+ * \return Operation status.
+ * \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_dma_serial_run_command(struct _qspi_dma_dev *dev, const struct _qspi_command *cmd);
+
+/**
+ * \brief Register the QSPI device callback
+ * \param[in] dev Pointer to the SPI device instance.
+ * \param[in] type The callback type.
+ * \param[in] cb The callback function to register. NULL to disable callback.
+ * \return Always 0.
+ */
+void _qspi_dma_register_callback(struct _qspi_dma_dev *dev, const enum _qspi_dma_cb_type type, _qspi_dma_cb_t cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_QSPI_DMA_H_INCLUDED */
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_qspi_sync.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_qspi_sync.h
new file mode 100644
index 0000000..6958e10
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_qspi_sync.h
@@ -0,0 +1,105 @@
+/**
+ * \file
+ *
+ * \brief Quad SPI Sync related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_QSPI_SYNC_H_INCLUDED
+#define _HPL_QSPI_SYNC_H_INCLUDED
+
+#include
+
+/**
+ * \addtogroup hpl_qspi HPL QSPI
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Quad SPI polling driver instance. */
+struct _qspi_sync_dev {
+ /** Pointer to private data or hardware base */
+ void *prvt;
+};
+
+/**
+ * \brief Initialize QSPI for access without interrupts
+ * It will load default hardware configuration and software struct.
+ * \param[in, out] dev Pointer to the QSPI device instance.
+ * \param[in] hw Pointer to the hardware base.
+ * \return Operation status.
+ * \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_sync_init(struct _qspi_sync_dev *dev, void *const hw);
+
+/**
+ * \brief Deinitialize QSPI
+ * Disable, reset the hardware and the software struct.
+ * \param[in, out] dev Pointer to the QSPI device instance.
+ * \return Operation status.
+ * \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_sync_deinit(struct _qspi_sync_dev *dev);
+
+/**
+ * \brief Enable QSPI for access without interrupts
+ * \param[in, out] dev Pointer to the QSPI device instance.
+ * \return Operation status.
+ * \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_sync_enable(struct _qspi_sync_dev *dev);
+
+/**
+ * \brief Disable QSPI for access without interrupts
+ * \param[in, out] dev Pointer to the QSPI device instance.
+ * \return Operation status.
+ * \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_sync_disable(struct _qspi_sync_dev *dev);
+
+/**
+ * \brief Execute command in Serial Memory Mode.
+ *
+ * \param[in] dev The pointer to QSPI device instance
+ * \param[in] cmd The pointer to the command information
+ * \return Operation status.
+ * \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_sync_serial_run_command(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_QSPI_SYNC_H_INCLUDED */
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_ramecc.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_ramecc.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_ramecc.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_ramecc.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_reset.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_reset.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_reset.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_reset.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_sleep.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_sleep.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_sleep.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_sleep.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_async.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_async.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_async.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_async.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_dma.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_dma.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_dma.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_dma.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_async.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_async.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_async.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_async.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_dma.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_dma.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_dma.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_dma.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_sync.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_sync.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_sync.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_sync.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_async.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_async.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_async.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_async.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_sync.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_sync.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_sync.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_sync.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_sync.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_sync.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_sync.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_sync.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_async.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_async.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_async.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_async.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_sync.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_sync.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_sync.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_sync.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_atomic.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_atomic.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_atomic.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_atomic.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_cache.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_cache.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_cache.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_cache.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_delay.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_delay.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_delay.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_delay.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_evsys.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_evsys.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_evsys.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_evsys.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_gpio.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_gpio.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_gpio.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_gpio.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_init.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_init.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_init.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_init.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_io.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_io.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_io.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_io.c
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_qspi_sync.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_qspi_sync.c
new file mode 100644
index 0000000..0e62532
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_qspi_sync.c
@@ -0,0 +1,89 @@
+/**
+ * \file
+ *
+ * \brief Quad SPI related functionality implementation.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_qspi_sync.h"
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Driver version
+ */
+#define QSPI_SYNC_DRIVER_VERSION 0x00000001u
+
+int32_t qspi_sync_init(struct qspi_sync_descriptor *qspi, void *const hw)
+{
+ ASSERT(qspi && hw);
+
+ return _qspi_sync_init(&qspi->dev, hw);
+}
+
+int32_t qspi_sync_deinit(struct qspi_sync_descriptor *qspi)
+{
+ ASSERT(qspi);
+
+ return _qspi_sync_deinit(&qspi->dev);
+}
+
+int32_t qspi_sync_enable(struct qspi_sync_descriptor *qspi)
+{
+ ASSERT(qspi);
+
+ return _qspi_sync_enable(&qspi->dev);
+}
+
+int32_t qspi_sync_disable(struct qspi_sync_descriptor *qspi)
+{
+ ASSERT(qspi);
+
+ return _qspi_sync_disable(&qspi->dev);
+}
+
+int32_t qspi_sync_serial_run_command(struct qspi_sync_descriptor *qspi, const struct _qspi_command *cmd)
+{
+ ASSERT(qspi && cmd);
+
+ return _qspi_sync_serial_run_command(&qspi->dev, cmd);
+}
+
+uint32_t qspi_sync_get_version(void)
+{
+ return QSPI_SYNC_DRIVER_VERSION;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_sleep.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_sleep.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_sleep.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_sleep.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_spi_m_dma.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_spi_m_dma.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_spi_m_dma.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_spi_m_dma.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_usart_sync.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_usart_sync.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_usart_sync.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_usart_sync.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/compiler.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/compiler.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/compiler.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/compiler.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/err_codes.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/err_codes.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/err_codes.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/err_codes.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/events.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/events.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/events.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/events.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/parts.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/parts.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/parts.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/parts.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_assert.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_assert.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_assert.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_assert.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_event.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_event.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_event.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_event.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_increment_macro.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_increment_macro.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_increment_macro.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_increment_macro.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_list.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_list.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_list.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_list.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_repeat_macro.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_repeat_macro.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_repeat_macro.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_repeat_macro.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_assert.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_assert.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_assert.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_assert.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_event.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_event.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_event.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_event.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_list.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_list.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_list.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_list.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_syscalls.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_syscalls.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_syscalls.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/src/utils_syscalls.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/cmcc/hpl_cmcc.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/cmcc/hpl_cmcc.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/cmcc/hpl_cmcc.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/cmcc/hpl_cmcc.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_core_m4.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_core_m4.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_core_m4.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_core_m4.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_core_port.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_core_port.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_core_port.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_core_port.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_init.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_init.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_init.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_init.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/dmac/hpl_dmac.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/dmac/hpl_dmac.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/dmac/hpl_dmac.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/dmac/hpl_dmac.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/doc_lite/tc.rst b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/doc_lite/tc.rst
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/doc_lite/tc.rst
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/doc_lite/tc.rst
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/evsys/hpl_evsys.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/evsys/hpl_evsys.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/evsys/hpl_evsys.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/evsys/hpl_evsys.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/gclk/hpl_gclk.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/gclk/hpl_gclk.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/gclk/hpl_gclk.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/gclk/hpl_gclk.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/gclk/hpl_gclk_base.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/gclk/hpl_gclk_base.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/gclk/hpl_gclk_base.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/gclk/hpl_gclk_base.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/mclk/hpl_mclk.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/mclk/hpl_mclk.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/mclk/hpl_mclk.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/mclk/hpl_mclk.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/osc32kctrl/hpl_osc32kctrl.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/osc32kctrl/hpl_osc32kctrl.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/osc32kctrl/hpl_osc32kctrl.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/osc32kctrl/hpl_osc32kctrl.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/oscctrl/hpl_oscctrl.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/oscctrl/hpl_oscctrl.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/oscctrl/hpl_oscctrl.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/oscctrl/hpl_oscctrl.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/pm/hpl_pm.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/pm/hpl_pm.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/pm/hpl_pm.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/pm/hpl_pm.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/pm/hpl_pm_base.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/pm/hpl_pm_base.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/pm/hpl_pm_base.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/pm/hpl_pm_base.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/port/hpl_gpio_base.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/port/hpl_gpio_base.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/port/hpl_gpio_base.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/port/hpl_gpio_base.h
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/qspi/hpl_qspi.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/qspi/hpl_qspi.c
new file mode 100644
index 0000000..351b3ea
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/qspi/hpl_qspi.c
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief QSPI Driver
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include
+#include
+#include
+
+/**
+ * \brief Memory copy function.
+ *
+ * \param dst Pointer to destination buffer.
+ * \param src Pointer to source buffer.
+ * \param count Bytes to be copied.
+ */
+static void _qspi_memcpy(uint8_t *dst, uint8_t *src, uint32_t count)
+{
+ while (count--) {
+ *dst++ = *src++;
+ }
+}
+
+/**
+ * \brief Ends ongoing transfer by releasing CS of QSPI peripheral.
+ *
+ * \param qspi Pointer to an Qspi instance.
+ */
+static inline void _qspi_end_transfer(void *hw)
+{
+ hri_qspi_write_CTRLA_reg(hw, QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER);
+}
+
+int32_t _qspi_sync_init(struct _qspi_sync_dev *dev, void *const hw)
+{
+ ASSERT(dev && hw);
+ dev->prvt = hw;
+ hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_SWRST);
+
+ hri_qspi_write_CTRLB_reg(hw,
+ QSPI_CTRLB_MODE_MEMORY | QSPI_CTRLB_CSMODE_LASTXFER | QSPI_CTRLB_DATALEN(0)
+ | QSPI_CTRLB_DLYBCT(0) | QSPI_CTRLB_DLYCS(CONF_QSPI_DLYCS));
+
+ hri_qspi_write_BAUD_reg(hw,
+ CONF_QSPI_CPOL << QSPI_BAUD_CPOL_Pos | CONF_QSPI_CPHA << QSPI_BAUD_CPHA_Pos
+ | QSPI_BAUD_BAUD(CONF_QSPI_BAUD_RATE) | QSPI_BAUD_DLYBS(CONF_QSPI_DLYBS));
+ return ERR_NONE;
+}
+
+int32_t _qspi_sync_deinit(struct _qspi_sync_dev *dev)
+{
+ hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_SWRST);
+ return ERR_NONE;
+}
+
+int32_t _qspi_sync_enable(struct _qspi_sync_dev *dev)
+{
+ hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_ENABLE);
+ return ERR_NONE;
+}
+
+int32_t _qspi_sync_disable(struct _qspi_sync_dev *dev)
+{
+ hri_qspi_write_CTRLA_reg(dev->prvt, 0);
+ return ERR_NONE;
+}
+
+/**
+ * \brief Set instruction frame param.
+ */
+static void _qspi_sync_command_set_ifr(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd)
+{
+ void *hw = dev->prvt;
+ if (cmd->inst_frame.bits.addr_en) {
+ hri_qspi_write_INSTRADDR_reg(hw, cmd->address);
+ }
+
+ if (cmd->inst_frame.bits.inst_en) {
+ hri_qspi_write_INSTRCTRL_INSTR_bf(hw, cmd->instruction);
+ }
+
+ if (cmd->inst_frame.bits.opt_en) {
+ hri_qspi_write_INSTRCTRL_OPTCODE_bf(hw, cmd->option);
+ }
+
+ hri_qspi_write_INSTRFRAME_reg(hw, cmd->inst_frame.word);
+}
+
+/**
+ * \brief Access QSPI mapping memory via AHB.
+ */
+static void _qspi_sync_run_transfer(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd)
+{
+ void * hw = dev->prvt;
+ uint8_t *qspi_mem = (uint8_t *)QSPI_AHB;
+ if (cmd->inst_frame.bits.addr_en)
+ qspi_mem += cmd->address;
+
+ /* To synchronize system bus accesses */
+ hri_qspi_read_INSTRFRAME_reg(hw);
+
+ ASSERT(cmd->tx_buf || cmd->rx_buf);
+
+ if (cmd->tx_buf) {
+ _qspi_memcpy((uint8_t *)qspi_mem, (uint8_t *)cmd->tx_buf, cmd->buf_len);
+ } else {
+ _qspi_memcpy((uint8_t *)cmd->rx_buf, (uint8_t *)qspi_mem, cmd->buf_len);
+ }
+
+ __DSB();
+ __ISB();
+}
+
+int32_t _qspi_sync_serial_run_command(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd)
+{
+ _qspi_sync_command_set_ifr(dev, cmd);
+
+ if (cmd->inst_frame.bits.data_en) {
+ _qspi_sync_run_transfer(dev, cmd);
+ }
+
+ _qspi_end_transfer(dev->prvt);
+
+ while (!hri_qspi_get_INTFLAG_INSTREND_bit(dev->prvt))
+ ;
+ hri_qspi_clear_INTFLAG_INSTREND_bit(dev->prvt);
+ return ERR_NONE;
+}
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/ramecc/hpl_ramecc.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/ramecc/hpl_ramecc.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/ramecc/hpl_ramecc.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/ramecc/hpl_ramecc.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/sercom/hpl_sercom.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/sercom/hpl_sercom.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/sercom/hpl_sercom.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/sercom/hpl_sercom.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ac_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ac_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ac_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ac_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_adc_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_adc_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_adc_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_adc_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_aes_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_aes_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_aes_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_aes_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_can_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_can_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_can_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_can_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ccl_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ccl_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ccl_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ccl_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_cmcc_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_cmcc_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_cmcc_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_cmcc_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dac_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dac_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dac_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dac_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dmac_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dmac_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dmac_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dmac_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dsu_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dsu_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dsu_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_dsu_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_e54.h
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rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_e54.h
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diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_eic_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_eic_e54.h
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rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_eic_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_eic_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_evsys_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_evsys_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_evsys_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_evsys_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_freqm_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_freqm_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_freqm_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_freqm_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_gclk_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_gclk_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_gclk_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_gclk_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_gmac_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_gmac_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_gmac_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_gmac_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_hmatrixb_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_hmatrixb_e54.h
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diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_i2s_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_i2s_e54.h
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diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_icm_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_icm_e54.h
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rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_icm_e54.h
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diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_mclk_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_mclk_e54.h
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rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_mclk_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_mclk_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_nvmctrl_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_nvmctrl_e54.h
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rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_nvmctrl_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_nvmctrl_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_osc32kctrl_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_osc32kctrl_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_osc32kctrl_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_osc32kctrl_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_oscctrl_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_oscctrl_e54.h
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rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_oscctrl_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_oscctrl_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pac_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pac_e54.h
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rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pac_e54.h
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diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pcc_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pcc_e54.h
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rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pcc_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pcc_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pdec_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pdec_e54.h
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rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pdec_e54.h
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diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pm_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pm_e54.h
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rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pm_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_pm_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_port_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_port_e54.h
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rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_port_e54.h
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diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_qspi_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_qspi_e54.h
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rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_qspi_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_qspi_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ramecc_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_ramecc_e54.h
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diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_rstc_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_rstc_e54.h
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diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_rtc_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_rtc_e54.h
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rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_rtc_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_rtc_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_sdhc_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_sdhc_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_sdhc_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_sdhc_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_sercom_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_sercom_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_sercom_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_sercom_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_supc_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_supc_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_supc_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_supc_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_tc_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_tc_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_tc_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_tc_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_tcc_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_tcc_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_tcc_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_tcc_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_trng_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_trng_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_trng_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_trng_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_usb_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_usb_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_usb_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_usb_e54.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_wdt_e54.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_wdt_e54.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_wdt_e54.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hri/hri_wdt_e54.h
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c
new file mode 100644
index 0000000..6ea9ff3
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c
@@ -0,0 +1,120 @@
+#include
+#include "spi_slave_dma_config.h"
+
+/* Buffer length to transfer/receive */
+#define BUFFER_LEN (6)
+#define SLAVE_BUFFER_SIZE 64
+
+#define CONF_SERCOM_4_TRANSMIT_DMA_CHANNEL 2
+#define CONF_SERCOM_4_RECEIVE_DMA_CHANNEL 3
+
+/* DMA channel Descriptor */
+extern DmacDescriptor _descriptor_section[DMAC_CH_NUM];
+extern DmacDescriptor _write_back_section[DMAC_CH_NUM];
+
+/* IO descriptor for SPI master */
+struct io_descriptor *io_spi_master;
+
+volatile uint8_t spi_master_tx_complete = 0;
+volatile uint8_t spi_master_rx_complete = 0;
+volatile uint8_t cs_pulled_high = 0;
+volatile uint8_t received_data_len = 0;
+
+//static uint8_t rx_buffer[BUFFER_LEN] = {0};
+//static uint8_t tx_buffer[BUFFER_LEN] = "Hell0";
+
+static uint8_t rx_buffer[SLAVE_BUFFER_SIZE] = {0};
+static uint8_t tx_buffer[SLAVE_BUFFER_SIZE] = {63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48,47,46,45,44,43,42,
+ 41,40,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,
+ 19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
+
+
+
+/* DMA Transfer complete callback for SPI master TX */
+static void spi_master_tx_complete_cb(struct _dma_resource *resource)
+{
+ /* Transfer completed */
+ delay_us(CONF_DELAY_US);
+ gpio_set_pin_level(SPI_CS, true);
+ spi_master_tx_complete = true;
+}
+
+/* DMA Transfer complete callback for SPI master RX */
+static void spi_master_rx_complete_cb(struct _dma_resource *resource)
+{
+ /* Transfer completed */
+ gpio_set_pin_level(SPI_CS, true);
+ spi_master_rx_complete = true;
+}
+
+/* Start SPI master data transfer */
+void spi_master_tx(uint8_t *buffer, uint8_t length)
+{
+ //spi_m_dma_enable(&SPI_0);
+ gpio_set_pin_level(SPI_CS, false);
+ //io_write(io_spi_master, buffer, length);
+ spi_m_dma_transfer(&SPI_0,tx_buffer,rx_buffer,SLAVE_BUFFER_SIZE);
+
+}
+
+/* Start SPI master data Reception from Slave */
+void spi_master_rx(uint8_t *buffer, uint8_t length)
+{
+ spi_m_dma_enable(&SPI_0);
+ gpio_set_pin_level(SPI_CS, false);
+ io_read(io_spi_master, buffer, length);
+}
+
+/* SPI master IO and Callback Initialization */
+void spi_master_init(void)
+{
+ spi_m_dma_get_io_descriptor(&SPI_0, &io_spi_master);
+ spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_TX_DONE, spi_master_tx_complete_cb);
+ spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_RX_DONE, spi_master_rx_complete_cb);
+}
+
+
+int main(void)
+{
+ /* Initializes MCU, drivers and middleware */
+ atmel_start_init();
+ /* Initialize SPI master IO and Callback */
+ spi_master_init();
+ spi_m_dma_enable(&SPI_0);
+
+ /* Start SPI Master data transfer using DMA */
+ //spi_master_rx(rx_buffer, BUFFER_LEN);
+ spi_master_tx(tx_buffer, SLAVE_BUFFER_SIZE);
+ /* Start SPI Master data reception using DMA */
+ //spi_master_rx(tx_buffer, BUFFER_LEN);
+ printf("Init Complete\n\r");
+ /* Replace with your application code */
+ while (1) {
+ delay_ms(500);
+ //tx_buffer[4] = tx_buffer[4]+1;
+ //spi_master_rx(rx_buffer, BUFFER_LEN);
+ tx_buffer[63] += 1;
+ spi_master_tx(tx_buffer, SLAVE_BUFFER_SIZE);
+
+ if (spi_master_tx_complete) {
+ spi_master_rx_complete = false;
+ printf("Master Sent DATA = ");
+ /* Print Received data by SPI Master from SPI Slave on Console */
+ for (int i = 0; i < SLAVE_BUFFER_SIZE; i++) {
+ printf("%u, ", tx_buffer[i]);
+ }
+ printf("\n\r");
+
+ }
+ /* Check for SPI Master is received data from SPI Slave */
+ if (spi_master_rx_complete) {
+ spi_master_rx_complete = false;
+ printf("Master Recieved DATA = ");
+ /* Print Received data by SPI Master from SPI Slave on Console */
+ for (int i = 0; i < SLAVE_BUFFER_SIZE; i++) {
+ printf("%u, ", rx_buffer[i]);
+ }
+ printf("\n\r");
+ }
+ }
+}
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/gcc/read.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/gcc/read.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/gcc/read.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/gcc/read.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/gcc/write.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/gcc/write.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/gcc/write.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/gcc/write.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/stdio_io.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/stdio_io.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/stdio_io.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/stdio_io.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/stdio_io.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/stdio_io.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/stdio_io.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_redirect/stdio_io.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_start.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_start.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_start.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_start.c
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_start.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_start.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_start.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/stdio_start.h
diff --git a/Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_Test_Master.atsln b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_Test_Master.atsln
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_Test_Master.atsln
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_Test_Master.atsln
diff --git a/Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave.atsln b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave.atsln
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave.atsln
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave.atsln
diff --git a/Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/.atmelstart/AtmelStart.env_conf b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/.atmelstart/AtmelStart.env_conf
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/.atmelstart/AtmelStart.env_conf
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/.atmelstart/AtmelStart.env_conf
diff --git a/Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/.atmelstart/AtmelStart.gpdsc b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/.atmelstart/AtmelStart.gpdsc
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/.atmelstart/AtmelStart.gpdsc
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/.atmelstart/AtmelStart.gpdsc
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/.atmelstart/atmel_start_config.atstart b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/.atmelstart/atmel_start_config.atstart
new file mode 100644
index 0000000..d9bd40e
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/.atmelstart/atmel_start_config.atstart
@@ -0,0 +1,723 @@
+format_version: '2'
+name: My Project
+versions:
+ api: '1.0'
+ backend: 1.8.580
+ commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c
+ content: unknown
+ content_pack_name: unknown
+ format: '2'
+ frontend: 1.8.580
+ packs_version_avr8: 1.0.1463
+ packs_version_qtouch: unknown
+ packs_version_sam: 1.0.1726
+ version_backend: 1.8.580
+ version_frontend: ''
+board:
+ identifier: SAMC21XplainedPro
+ device: SAMC21J18A-AN
+details: null
+application: null
+middlewares:
+ STDIO_REDIRECT_0:
+ user_label: STDIO_REDIRECT_0
+ configuration: {}
+ definition: Atmel:STDIO_redirect:0.0.1::STDIO_Redirect
+ functionality: STDIO_Redirect
+ api: STDIO:Redirect:IO
+ dependencies:
+ Target IO: TARGET_IO
+drivers:
+ DMAC:
+ user_label: DMAC
+ definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
+ functionality: System
+ api: HAL:HPL:DMAC
+ configuration:
+ dmac_beatsize_0: 8-bit bus transfer
+ dmac_beatsize_1: 8-bit bus transfer
+ dmac_beatsize_10: 8-bit bus transfer
+ dmac_beatsize_11: 8-bit bus transfer
+ dmac_beatsize_12: 8-bit bus transfer
+ dmac_beatsize_13: 8-bit bus transfer
+ dmac_beatsize_14: 8-bit bus transfer
+ dmac_beatsize_15: 8-bit bus transfer
+ dmac_beatsize_2: 8-bit bus transfer
+ dmac_beatsize_3: 8-bit bus transfer
+ dmac_beatsize_4: 8-bit bus transfer
+ dmac_beatsize_5: 8-bit bus transfer
+ dmac_beatsize_6: 8-bit bus transfer
+ dmac_beatsize_7: 8-bit bus transfer
+ dmac_beatsize_8: 8-bit bus transfer
+ dmac_beatsize_9: 8-bit bus transfer
+ dmac_blockact_0: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_1: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_10: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_11: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_12: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_13: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_14: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_15: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_2: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_3: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_4: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_5: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_6: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_7: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_8: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_9: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_channel_0_settings: false
+ dmac_channel_10_settings: false
+ dmac_channel_11_settings: false
+ dmac_channel_12_settings: false
+ dmac_channel_13_settings: false
+ dmac_channel_14_settings: false
+ dmac_channel_15_settings: false
+ dmac_channel_1_settings: false
+ dmac_channel_2_settings: true
+ dmac_channel_3_settings: true
+ dmac_channel_4_settings: false
+ dmac_channel_5_settings: false
+ dmac_channel_6_settings: false
+ dmac_channel_7_settings: false
+ dmac_channel_8_settings: false
+ dmac_channel_9_settings: false
+ dmac_dbgrun: false
+ dmac_dqos: Background (no sensitive operation)
+ dmac_dstinc_0: false
+ dmac_dstinc_1: false
+ dmac_dstinc_10: false
+ dmac_dstinc_11: false
+ dmac_dstinc_12: false
+ dmac_dstinc_13: false
+ dmac_dstinc_14: false
+ dmac_dstinc_15: false
+ dmac_dstinc_2: true
+ dmac_dstinc_3: false
+ dmac_dstinc_4: false
+ dmac_dstinc_5: false
+ dmac_dstinc_6: false
+ dmac_dstinc_7: false
+ dmac_dstinc_8: false
+ dmac_dstinc_9: false
+ dmac_enable: true
+ dmac_enable_0: false
+ dmac_enable_1: false
+ dmac_enable_10: false
+ dmac_enable_11: false
+ dmac_enable_12: false
+ dmac_enable_13: false
+ dmac_enable_14: false
+ dmac_enable_15: false
+ dmac_enable_2: true
+ dmac_enable_3: true
+ dmac_enable_4: false
+ dmac_enable_5: false
+ dmac_enable_6: false
+ dmac_enable_7: false
+ dmac_enable_8: false
+ dmac_enable_9: false
+ dmac_evact_0: No action
+ dmac_evact_1: No action
+ dmac_evact_10: No action
+ dmac_evact_11: No action
+ dmac_evact_12: No action
+ dmac_evact_13: No action
+ dmac_evact_14: No action
+ dmac_evact_15: No action
+ dmac_evact_2: No action
+ dmac_evact_3: No action
+ dmac_evact_4: No action
+ dmac_evact_5: No action
+ dmac_evact_6: No action
+ dmac_evact_7: No action
+ dmac_evact_8: No action
+ dmac_evact_9: No action
+ dmac_evie_0: false
+ dmac_evie_1: false
+ dmac_evie_10: false
+ dmac_evie_11: false
+ dmac_evie_12: false
+ dmac_evie_13: false
+ dmac_evie_14: false
+ dmac_evie_15: false
+ dmac_evie_2: false
+ dmac_evie_3: false
+ dmac_evie_4: false
+ dmac_evie_5: false
+ dmac_evie_6: false
+ dmac_evie_7: false
+ dmac_evie_8: false
+ dmac_evie_9: false
+ dmac_evoe_0: false
+ dmac_evoe_1: false
+ dmac_evoe_10: false
+ dmac_evoe_11: false
+ dmac_evoe_12: false
+ dmac_evoe_13: false
+ dmac_evoe_14: false
+ dmac_evoe_15: false
+ dmac_evoe_2: false
+ dmac_evoe_3: false
+ dmac_evoe_4: false
+ dmac_evoe_5: false
+ dmac_evoe_6: false
+ dmac_evoe_7: false
+ dmac_evoe_8: false
+ dmac_evoe_9: false
+ dmac_evosel_0: Event generation disabled
+ dmac_evosel_1: Event generation disabled
+ dmac_evosel_10: Event generation disabled
+ dmac_evosel_11: Event generation disabled
+ dmac_evosel_12: Event generation disabled
+ dmac_evosel_13: Event generation disabled
+ dmac_evosel_14: Event generation disabled
+ dmac_evosel_15: Event generation disabled
+ dmac_evosel_2: Event generation disabled
+ dmac_evosel_3: Event generation disabled
+ dmac_evosel_4: Event generation disabled
+ dmac_evosel_5: Event generation disabled
+ dmac_evosel_6: Event generation disabled
+ dmac_evosel_7: Event generation disabled
+ dmac_evosel_8: Event generation disabled
+ dmac_evosel_9: Event generation disabled
+ dmac_fqos: Background (no sensitive operation)
+ dmac_lvl_0: Channel priority 0
+ dmac_lvl_1: Channel priority 0
+ dmac_lvl_10: Channel priority 0
+ dmac_lvl_11: Channel priority 0
+ dmac_lvl_12: Channel priority 0
+ dmac_lvl_13: Channel priority 0
+ dmac_lvl_14: Channel priority 0
+ dmac_lvl_15: Channel priority 0
+ dmac_lvl_2: Channel priority 0
+ dmac_lvl_3: Channel priority 0
+ dmac_lvl_4: Channel priority 0
+ dmac_lvl_5: Channel priority 0
+ dmac_lvl_6: Channel priority 0
+ dmac_lvl_7: Channel priority 0
+ dmac_lvl_8: Channel priority 0
+ dmac_lvl_9: Channel priority 0
+ dmac_lvlen0: true
+ dmac_lvlen1: true
+ dmac_lvlen2: true
+ dmac_lvlen3: false
+ dmac_lvlpri0: 0
+ dmac_lvlpri1: 0
+ dmac_lvlpri2: 0
+ dmac_lvlpri3: 0
+ dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
+ dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
+ dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
+ dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
+ dmac_runstdby_0: false
+ dmac_runstdby_1: false
+ dmac_runstdby_10: false
+ dmac_runstdby_11: false
+ dmac_runstdby_12: false
+ dmac_runstdby_13: false
+ dmac_runstdby_14: false
+ dmac_runstdby_15: false
+ dmac_runstdby_2: false
+ dmac_runstdby_3: false
+ dmac_runstdby_4: false
+ dmac_runstdby_5: false
+ dmac_runstdby_6: false
+ dmac_runstdby_7: false
+ dmac_runstdby_8: false
+ dmac_runstdby_9: false
+ dmac_srcinc_0: false
+ dmac_srcinc_1: false
+ dmac_srcinc_10: false
+ dmac_srcinc_11: false
+ dmac_srcinc_12: false
+ dmac_srcinc_13: false
+ dmac_srcinc_14: false
+ dmac_srcinc_15: false
+ dmac_srcinc_2: false
+ dmac_srcinc_3: true
+ dmac_srcinc_4: false
+ dmac_srcinc_5: false
+ dmac_srcinc_6: false
+ dmac_srcinc_7: false
+ dmac_srcinc_8: false
+ dmac_srcinc_9: false
+ dmac_stepsel_0: Step size settings apply to the destination address
+ dmac_stepsel_1: Step size settings apply to the destination address
+ dmac_stepsel_10: Step size settings apply to the destination address
+ dmac_stepsel_11: Step size settings apply to the destination address
+ dmac_stepsel_12: Step size settings apply to the destination address
+ dmac_stepsel_13: Step size settings apply to the destination address
+ dmac_stepsel_14: Step size settings apply to the destination address
+ dmac_stepsel_15: Step size settings apply to the destination address
+ dmac_stepsel_2: Step size settings apply to the destination address
+ dmac_stepsel_3: Step size settings apply to the source address
+ dmac_stepsel_4: Step size settings apply to the destination address
+ dmac_stepsel_5: Step size settings apply to the destination address
+ dmac_stepsel_6: Step size settings apply to the destination address
+ dmac_stepsel_7: Step size settings apply to the destination address
+ dmac_stepsel_8: Step size settings apply to the destination address
+ dmac_stepsel_9: Step size settings apply to the destination address
+ dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_trifsrc_0: Only software/event triggers
+ dmac_trifsrc_1: Only software/event triggers
+ dmac_trifsrc_10: Only software/event triggers
+ dmac_trifsrc_11: Only software/event triggers
+ dmac_trifsrc_12: Only software/event triggers
+ dmac_trifsrc_13: Only software/event triggers
+ dmac_trifsrc_14: Only software/event triggers
+ dmac_trifsrc_15: Only software/event triggers
+ dmac_trifsrc_2: SERCOM5 RX Trigger
+ dmac_trifsrc_3: SERCOM5 TX Trigger
+ dmac_trifsrc_4: Only software/event triggers
+ dmac_trifsrc_5: Only software/event triggers
+ dmac_trifsrc_6: Only software/event triggers
+ dmac_trifsrc_7: Only software/event triggers
+ dmac_trifsrc_8: Only software/event triggers
+ dmac_trifsrc_9: Only software/event triggers
+ dmac_trigact_0: One trigger required for each block transfer
+ dmac_trigact_1: One trigger required for each block transfer
+ dmac_trigact_10: One trigger required for each block transfer
+ dmac_trigact_11: One trigger required for each block transfer
+ dmac_trigact_12: One trigger required for each block transfer
+ dmac_trigact_13: One trigger required for each block transfer
+ dmac_trigact_14: One trigger required for each block transfer
+ dmac_trigact_15: One trigger required for each block transfer
+ dmac_trigact_2: One trigger required for each beat transfer
+ dmac_trigact_3: One trigger required for each beat transfer
+ dmac_trigact_4: One trigger required for each block transfer
+ dmac_trigact_5: One trigger required for each block transfer
+ dmac_trigact_6: One trigger required for each block transfer
+ dmac_trigact_7: One trigger required for each block transfer
+ dmac_trigact_8: One trigger required for each block transfer
+ dmac_trigact_9: One trigger required for each block transfer
+ dmac_wrbqos: Background (no sensitive operation)
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ GCLK:
+ user_label: GCLK
+ definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
+ functionality: System
+ api: HAL:HPL:GCLK
+ configuration:
+ $input: 24000000
+ $input_id: 48MHz Internal Oscillator (OSC48M)
+ RESERVED_InputFreq: 24000000
+ RESERVED_InputFreq_id: 48MHz Internal Oscillator (OSC48M)
+ _$freq_output_Generic clock generator 0: 24000000
+ _$freq_output_Generic clock generator 1: 400000
+ _$freq_output_Generic clock generator 2: 400000
+ _$freq_output_Generic clock generator 3: 400000
+ _$freq_output_Generic clock generator 4: 400000
+ _$freq_output_Generic clock generator 5: 400000
+ _$freq_output_Generic clock generator 6: 400000
+ _$freq_output_Generic clock generator 7: 400000
+ enable_gclk_gen_0: true
+ enable_gclk_gen_0__externalclock: 1000000
+ enable_gclk_gen_1: false
+ enable_gclk_gen_1__externalclock: 1000000
+ enable_gclk_gen_2: false
+ enable_gclk_gen_2__externalclock: 1000000
+ enable_gclk_gen_3: false
+ enable_gclk_gen_3__externalclock: 1000000
+ enable_gclk_gen_4: false
+ enable_gclk_gen_4__externalclock: 1000000
+ enable_gclk_gen_5: false
+ enable_gclk_gen_5__externalclock: 1000000
+ enable_gclk_gen_6: false
+ enable_gclk_gen_6__externalclock: 1000000
+ enable_gclk_gen_7: false
+ enable_gclk_gen_7__externalclock: 1000000
+ gclk_arch_gen_0_enable: true
+ gclk_arch_gen_0_idc: false
+ gclk_arch_gen_0_oe: false
+ gclk_arch_gen_0_oov: false
+ gclk_arch_gen_0_runstdby: false
+ gclk_arch_gen_1_enable: false
+ gclk_arch_gen_1_idc: false
+ gclk_arch_gen_1_oe: false
+ gclk_arch_gen_1_oov: false
+ gclk_arch_gen_1_runstdby: false
+ gclk_arch_gen_2_enable: false
+ gclk_arch_gen_2_idc: false
+ gclk_arch_gen_2_oe: false
+ gclk_arch_gen_2_oov: false
+ gclk_arch_gen_2_runstdby: false
+ gclk_arch_gen_3_enable: false
+ gclk_arch_gen_3_idc: false
+ gclk_arch_gen_3_oe: false
+ gclk_arch_gen_3_oov: false
+ gclk_arch_gen_3_runstdby: false
+ gclk_arch_gen_4_enable: false
+ gclk_arch_gen_4_idc: false
+ gclk_arch_gen_4_oe: false
+ gclk_arch_gen_4_oov: false
+ gclk_arch_gen_4_runstdby: false
+ gclk_arch_gen_5_enable: false
+ gclk_arch_gen_5_idc: false
+ gclk_arch_gen_5_oe: false
+ gclk_arch_gen_5_oov: false
+ gclk_arch_gen_5_runstdby: false
+ gclk_arch_gen_6_enable: false
+ gclk_arch_gen_6_idc: false
+ gclk_arch_gen_6_oe: false
+ gclk_arch_gen_6_oov: false
+ gclk_arch_gen_6_runstdby: false
+ gclk_arch_gen_7_enable: false
+ gclk_arch_gen_7_idc: false
+ gclk_arch_gen_7_oe: false
+ gclk_arch_gen_7_oov: false
+ gclk_arch_gen_7_runstdby: false
+ gclk_gen_0_div: 1
+ gclk_gen_0_div_sel: false
+ gclk_gen_0_oscillator: 48MHz Internal Oscillator (OSC48M)
+ gclk_gen_1_div: 1
+ gclk_gen_1_div_sel: false
+ gclk_gen_1_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
+ gclk_gen_2_div: 1
+ gclk_gen_2_div_sel: false
+ gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
+ gclk_gen_3_div: 1
+ gclk_gen_3_div_sel: false
+ gclk_gen_3_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
+ gclk_gen_4_div: 1
+ gclk_gen_4_div_sel: false
+ gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
+ gclk_gen_5_div: 1
+ gclk_gen_5_div_sel: false
+ gclk_gen_5_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
+ gclk_gen_6_div: 1
+ gclk_gen_6_div_sel: false
+ gclk_gen_6_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
+ gclk_gen_7_div: 1
+ gclk_gen_7_div_sel: false
+ gclk_gen_7_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ MCLK:
+ user_label: MCLK
+ definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK
+ functionality: System
+ api: HAL:HPL:MCLK
+ configuration:
+ $input: 24000000
+ $input_id: Generic clock generator 0
+ RESERVED_InputFreq: 24000000
+ RESERVED_InputFreq_id: Generic clock generator 0
+ _$freq_output_CPU: 24000000
+ cpu_clock_source: Generic clock generator 0
+ cpu_div: '1'
+ enable_cpu_clock: true
+ nvm_wait_states: '0'
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: CPU
+ input: CPU
+ external: false
+ external_frequency: 0
+ configuration: {}
+ OSC32KCTRL:
+ user_label: OSC32KCTRL
+ definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL
+ functionality: System
+ api: HAL:HPL:OSC32KCTRL
+ configuration:
+ $input: 32768
+ $input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+ RESERVED_InputFreq: 32768
+ RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+ _$freq_output_RTC source: 32768
+ enable_osc32k: false
+ enable_osculp32k: true
+ enable_rtc_source: false
+ enable_xosc32k: false
+ osc32k_arch_calib: 0
+ osc32k_arch_calib_enable: false
+ osc32k_arch_en1k: false
+ osc32k_arch_en32k: false
+ osc32k_arch_enable: false
+ osc32k_arch_ondemand: false
+ osc32k_arch_runstdby: false
+ osc32k_arch_startup: 92us
+ osculp32k_calib: 0
+ osculp32k_calib_enable: false
+ rtc_1khz_selection: false
+ rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+ xosc32k_arch_cfden: false
+ xosc32k_arch_cfdeo: false
+ xosc32k_arch_en1k: false
+ xosc32k_arch_en32k: false
+ xosc32k_arch_enable: false
+ xosc32k_arch_ondemand: true
+ xosc32k_arch_runstdby: false
+ xosc32k_arch_startup: 122us
+ xosc32k_arch_swben: false
+ xosc32k_arch_xtalen: true
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ OSCCTRL:
+ user_label: OSCCTRL
+ definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL
+ functionality: System
+ api: HAL:HPL:OSCCTRL
+ configuration:
+ $input: 48000000
+ $input_id: 32kHz External Crystal Oscillator (XOSC32K)
+ RESERVED_InputFreq: 48000000
+ RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K)
+ _$freq_output_48MHz Internal Oscillator (OSC48M): 24000000
+ _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000
+ _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 47998976
+ enable_fdpll96m: false
+ enable_osc48m: true
+ enable_xosc: false
+ fdpll96m_arch_enable: false
+ fdpll96m_arch_filter: Default filter mode
+ fdpll96m_arch_lbypass: false
+ fdpll96m_arch_lpen: false
+ fdpll96m_arch_ltime: No time-out, automatic lock
+ fdpll96m_arch_ondemand: true
+ fdpll96m_arch_runstdby: false
+ fdpll96m_arch_wuf: false
+ fdpll96m_clock_div: 0
+ fdpll96m_ldr: 1463
+ fdpll96m_ldrfrac: 13
+ fdpll96m_presc: '1'
+ fdpll96m_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)
+ osc48m_arch_enable: true
+ osc48m_arch_ondemand: true
+ osc48m_arch_runstdby: false
+ osc48m_arch_startup: 21.333us
+ osc48m_div: 1
+ xosc_arch_ampgc: false
+ xosc_arch_cfden: false
+ xosc_arch_cfdeo: false
+ xosc_arch_enable: false
+ xosc_arch_gain: 2MHz
+ xosc_arch_ondemand: true
+ xosc_arch_runstdby: false
+ xosc_arch_startup: 31us
+ xosc_arch_swben: false
+ xosc_arch_xtalen: false
+ xosc_frequency: 400000
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ PORT:
+ user_label: PORT
+ definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::PORT::driver_config_definition::PORT::HAL:HPL:PORT
+ functionality: System
+ api: HAL:HPL:PORT
+ configuration:
+ enable_port_input_event_0: false
+ enable_port_input_event_1: false
+ enable_port_input_event_2: false
+ enable_port_input_event_3: false
+ porta_event_action_0: Output register of pin will be set to level of event
+ porta_event_action_1: Output register of pin will be set to level of event
+ porta_event_action_2: Output register of pin will be set to level of event
+ porta_event_action_3: Output register of pin will be set to level of event
+ porta_event_pin_identifier_0: 0
+ porta_event_pin_identifier_1: 0
+ porta_event_pin_identifier_2: 0
+ porta_event_pin_identifier_3: 0
+ porta_input_event_enable_0: false
+ porta_input_event_enable_1: false
+ porta_input_event_enable_2: false
+ porta_input_event_enable_3: false
+ portb_event_action_0: Output register of pin will be set to level of event
+ portb_event_action_1: Output register of pin will be set to level of event
+ portb_event_action_2: Output register of pin will be set to level of event
+ portb_event_action_3: Output register of pin will be set to level of event
+ portb_event_pin_identifier_0: 0
+ portb_event_pin_identifier_1: 0
+ portb_event_pin_identifier_2: 0
+ portb_event_pin_identifier_3: 0
+ portb_input_event_enable_0: false
+ portb_input_event_enable_1: false
+ portb_input_event_enable_2: false
+ portb_input_event_enable_3: false
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ TARGET_IO:
+ user_label: TARGET_IO
+ definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::SERCOM4::driver_config_definition::UART::HAL:Driver:USART.Sync
+ functionality: USART
+ api: HAL:Driver:USART_Sync
+ configuration:
+ usart_advanced: false
+ usart_arch_clock_mode: USART with internal clock
+ usart_arch_cloden: false
+ usart_arch_dbgstop: Keep running
+ usart_arch_dord: LSB is transmitted first
+ usart_arch_enc: No encoding
+ usart_arch_fractional: 0
+ usart_arch_ibon: false
+ usart_arch_lin_slave_enable: Disable
+ usart_arch_runstdby: false
+ usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling)
+ usart_arch_sampr: 16x arithmetic
+ usart_arch_sfde: false
+ usart_baud_rate: 9600
+ usart_character_size: 8 bits
+ usart_parity: No parity
+ usart_rx_enable: true
+ usart_stop_bit: One stop bit
+ usart_tx_enable: true
+ optional_signals: []
+ variant:
+ specification: TXPO=1, RXPO=3, CMODE=0
+ required_signals:
+ - name: SERCOM4/PAD/2
+ pad: PB10
+ label: TX
+ - name: SERCOM4/PAD/3
+ pad: PB11
+ label: RX
+ clocks:
+ domain_group:
+ nodes:
+ - name: Core
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Slow
+ input: Generic clock generator 3
+ external: false
+ external_frequency: 0
+ configuration:
+ core_gclk_selection: Generic clock generator 0
+ slow_gclk_selection: Generic clock generator 3
+ SPI_0:
+ user_label: SPI_0
+ definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::SERCOM5::driver_config_definition::SPI.Slave::HAL:Driver:SPI.Slave.Sync
+ functionality: SPI
+ api: HAL:Driver:SPI_Slave_Sync
+ configuration:
+ spi_slave_advanced: true
+ spi_slave_arch_addr: 0
+ spi_slave_arch_addrmask: 0
+ spi_slave_arch_amode: Address mask
+ spi_slave_arch_amode_en: false
+ spi_slave_arch_cpha: Sample input on leading edge
+ spi_slave_arch_cpol: SCK is low when idle
+ spi_slave_arch_dbgstop: Keep running
+ spi_slave_arch_dord: MSB first
+ spi_slave_arch_ibon: In data stream
+ spi_slave_arch_ploaden: false
+ spi_slave_arch_runstdby: false
+ spi_slave_arch_ssde: false
+ spi_slave_character_size: 8 bits
+ spi_slave_rx_enable: true
+ optional_signals: []
+ variant:
+ specification: TXPO=3, RXPO=2
+ required_signals:
+ - name: SERCOM5/PAD/0
+ pad: PB02
+ label: MISO
+ - name: SERCOM5/PAD/1
+ pad: PB03
+ label: _SS
+ - name: SERCOM5/PAD/2
+ pad: PB00
+ label: MOSI
+ - name: SERCOM5/PAD/3
+ pad: PB01
+ label: SCK
+ clocks:
+ domain_group:
+ nodes:
+ - name: Core
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Slow
+ input: Generic clock generator 3
+ external: false
+ external_frequency: 0
+ configuration:
+ core_gclk_selection: Generic clock generator 0
+ slow_gclk_selection: Generic clock generator 3
+pads:
+ PB10:
+ name: PB10
+ definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB10
+ mode: Peripheral IO
+ user_label: PB10
+ configuration: null
+ PB11:
+ name: PB11
+ definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB11
+ mode: Peripheral IO
+ user_label: PB11
+ configuration: null
+ PB00:
+ name: PB00
+ definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB00
+ mode: Digital input
+ user_label: PB00
+ configuration: null
+ PB01:
+ name: PB01
+ definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB01
+ mode: Digital output
+ user_label: PB01
+ configuration: null
+ PB02:
+ name: PB02
+ definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB02
+ mode: Digital output
+ user_label: PB02
+ configuration: null
+ PB03:
+ name: PB03
+ definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB03
+ mode: Digital input
+ user_label: PB03
+ configuration: null
+toolchain_options: []
+static_files: []
diff --git a/Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Default.xml b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Default.xml
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Default.xml
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Default.xml
diff --git a/Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/samc21j18a_flash.ld b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/samc21j18a_flash.ld
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/samc21j18a_flash.ld
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/samc21j18a_flash.ld
diff --git a/Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/samc21j18a_sram.ld b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/samc21j18a_sram.ld
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/samc21j18a_sram.ld
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/samc21j18a_sram.ld
diff --git a/Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/startup_samc21.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/startup_samc21.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/startup_samc21.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/startup_samc21.c
diff --git a/Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/system_samc21.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/system_samc21.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/system_samc21.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Device_Startup/system_samc21.c
diff --git a/Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave.componentinfo.xml b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave.componentinfo.xml
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave.componentinfo.xml
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave.componentinfo.xml
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave.cproj b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave.cproj
new file mode 100644
index 0000000..aabbe69
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave.cproj
@@ -0,0 +1,838 @@
+
+
+
+ 2.0
+ 7.0
+ com.Atmel.ARMGCC.C
+ dce6c7e3-ee26-4d79-826b-08594b9ad897
+ ATSAMC21J18A
+ none
+ Executable
+ C
+ $(MSBuildProjectName)
+ .elf
+ $(MSBuildProjectDirectory)\$(Configuration)
+ Master_Slave_IF_Test_Slave
+ Master_Slave_IF_Test_Slave
+ Master_Slave_IF_Test_Slave
+ Native
+ true
+ false
+ true
+ true
+
+
+ true
+
+ 2
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+ gcc
+ .atmelstart\atmel_start_config.atstart
+ .atmelstart\AtmelStart.gpdsc
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ True
+ True
+ True
+ True
+ True
+
+
+ NDEBUG
+
+
+
+
+ %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\
+ ../Config
+ ../
+ ../examples
+ ../hal/include
+ ../hal/utils/include
+ ../hpl/core
+ ../hpl/divas
+ ../hpl/dmac
+ ../hpl/gclk
+ ../hpl/mclk
+ ../hpl/osc32kctrl
+ ../hpl/oscctrl
+ ../hpl/pm
+ ../hpl/port
+ ../hpl/sercom
+ ../hri
+ ../stdio_redirect
+ %24(PackRepoDir)\atmel\SAMC21_DFP\1.2.176\samc21\include
+
+
+ Optimize for size (-Os)
+ True
+ True
+ True
+
+
+ libm
+
+
+
+
+ %24(ProjectDir)\Device_Startup
+
+
+ True
+ -Tsamc21j18a_flash.ld
+
+
+ %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\
+ ../Config
+ ../
+ ../examples
+ ../hal/include
+ ../hal/utils/include
+ ../hpl/core
+ ../hpl/divas
+ ../hpl/dmac
+ ../hpl/gclk
+ ../hpl/mclk
+ ../hpl/osc32kctrl
+ ../hpl/oscctrl
+ ../hpl/pm
+ ../hpl/port
+ ../hpl/sercom
+ ../hri
+ ../stdio_redirect
+ %24(PackRepoDir)\atmel\SAMC21_DFP\1.2.176\samc21\include
+
+
+
+
+ %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\
+ ../Config
+ ../
+ ../examples
+ ../hal/include
+ ../hal/utils/include
+ ../hpl/core
+ ../hpl/divas
+ ../hpl/dmac
+ ../hpl/gclk
+ ../hpl/mclk
+ ../hpl/osc32kctrl
+ ../hpl/oscctrl
+ ../hpl/pm
+ ../hpl/port
+ ../hpl/sercom
+ ../hri
+ ../stdio_redirect
+ %24(PackRepoDir)\atmel\SAMC21_DFP\1.2.176\samc21\include
+
+
+
+
+
+
+
+
+ True
+ True
+ True
+ True
+ True
+
+
+ DEBUG
+
+
+
+
+ %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\
+ ../Config
+ ../
+ ../examples
+ ../hal/include
+ ../hal/utils/include
+ ../hpl/core
+ ../hpl/divas
+ ../hpl/dmac
+ ../hpl/gclk
+ ../hpl/mclk
+ ../hpl/osc32kctrl
+ ../hpl/oscctrl
+ ../hpl/pm
+ ../hpl/port
+ ../hpl/sercom
+ ../hri
+ ../stdio_redirect
+ %24(PackRepoDir)\atmel\SAMC21_DFP\1.2.176\samc21\include
+
+
+ Optimize debugging experience (-Og)
+ True
+ Maximum (-g3)
+ True
+ True
+
+
+ libm
+
+
+
+
+ %24(ProjectDir)\Device_Startup
+
+
+ True
+ -Tsamc21j18a_flash.ld
+
+
+ %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\
+ ../Config
+ ../
+ ../examples
+ ../hal/include
+ ../hal/utils/include
+ ../hpl/core
+ ../hpl/divas
+ ../hpl/dmac
+ ../hpl/gclk
+ ../hpl/mclk
+ ../hpl/osc32kctrl
+ ../hpl/oscctrl
+ ../hpl/pm
+ ../hpl/port
+ ../hpl/sercom
+ ../hri
+ ../stdio_redirect
+ %24(PackRepoDir)\atmel\SAMC21_DFP\1.2.176\samc21\include
+
+
+ Default (-g)
+
+
+ %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\
+ ../Config
+ ../
+ ../examples
+ ../hal/include
+ ../hal/utils/include
+ ../hpl/core
+ ../hpl/divas
+ ../hpl/dmac
+ ../hpl/gclk
+ ../hpl/mclk
+ ../hpl/osc32kctrl
+ ../hpl/oscctrl
+ ../hpl/pm
+ ../hpl/port
+ ../hpl/sercom
+ ../hri
+ ../stdio_redirect
+ %24(PackRepoDir)\atmel\SAMC21_DFP\1.2.176\samc21\include
+
+
+ Default (-Wa,-g)
+
+
+
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+ compile
+
+
+
+
\ No newline at end of file
diff --git a/Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/atmel_start.c b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/atmel_start.c
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/atmel_start.c
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/atmel_start.c
diff --git a/Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/atmel_start.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/atmel_start.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/atmel_start.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/atmel_start.h
diff --git a/Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/atmel_start_pins.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/atmel_start_pins.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/atmel_start_pins.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/atmel_start_pins.h
diff --git a/Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/config/RTE_Components.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/config/RTE_Components.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/config/RTE_Components.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/config/RTE_Components.h
diff --git a/Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/config/hpl_divas_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/config/hpl_divas_config.h
similarity index 100%
rename from Examples/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/config/hpl_divas_config.h
rename to Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/config/hpl_divas_config.h
diff --git a/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/config/hpl_dmac_config.h b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/config/hpl_dmac_config.h
new file mode 100644
index 0000000..31dbf5d
--- /dev/null
+++ b/Examples/Buffer Transfer Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/config/hpl_dmac_config.h
@@ -0,0 +1,3474 @@
+/* Auto-generated config file hpl_dmac_config.h */
+#ifndef HPL_DMAC_CONFIG_H
+#define HPL_DMAC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// DMAC enable
+// Indicates whether dmac is enabled or not
+// dmac_enable
+#ifndef CONF_DMAC_ENABLE
+#define CONF_DMAC_ENABLE 1
+#endif
+
+// Priority Level 0
+// Indicates whether Priority Level 0 is enabled or not
+// dmac_lvlen0
+#ifndef CONF_DMAC_LVLEN0
+#define CONF_DMAC_LVLEN0 1
+#endif
+
+// Level 0 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 0
+// <1=> Round-robin arbitration scheme for channel with priority 0
+// Defines Level 0 Arbitration for DMA channels
+// dmac_rrlvlen0
+#ifndef CONF_DMAC_RRLVLEN0
+#define CONF_DMAC_RRLVLEN0 0
+#endif
+
+// Level 0 Channel Priority Number <0x00-0xFF>
+// dmac_lvlpri0
+#ifndef CONF_DMAC_LVLPRI0
+#define CONF_DMAC_LVLPRI0 0
+#endif
+
+// Priority Level 1
+// Indicates whether Priority Level 1 is enabled or not
+// dmac_lvlen1
+#ifndef CONF_DMAC_LVLEN1
+#define CONF_DMAC_LVLEN1 1
+#endif
+
+// Level 1 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 1
+// <1=> Round-robin arbitration scheme for channel with priority 1
+// Defines Level 1 Arbitration for DMA channels
+// dmac_rrlvlen1
+#ifndef CONF_DMAC_RRLVLEN1
+#define CONF_DMAC_RRLVLEN1 0
+#endif
+
+// Level 1 Channel Priority Number <0x00-0xFF>
+// dmac_lvlpri1
+#ifndef CONF_DMAC_LVLPRI1
+#define CONF_DMAC_LVLPRI1 0
+#endif
+
+// Priority Level 2
+// Indicates whether Priority Level 2 is enabled or not
+// dmac_lvlen2
+#ifndef CONF_DMAC_LVLEN2
+#define CONF_DMAC_LVLEN2 1
+#endif
+
+// Level 2 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 2
+// <1=> Round-robin arbitration scheme for channel with priority 2
+// Defines Level 2 Arbitration for DMA channels
+// dmac_rrlvlen2
+#ifndef CONF_DMAC_RRLVLEN2
+#define CONF_DMAC_RRLVLEN2 0
+#endif
+
+// Level 2 Channel Priority Number <0x00-0xFF>
+// dmac_lvlpri2
+#ifndef CONF_DMAC_LVLPRI2
+#define CONF_DMAC_LVLPRI2 0
+#endif
+
+// Priority Level 3
+// Indicates whether Priority Level 3 is enabled or not
+// dmac_lvlen3
+#ifndef CONF_DMAC_LVLEN3
+#define CONF_DMAC_LVLEN3 0
+#endif
+
+// Level 3 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 3
+// <1=> Round-robin arbitration scheme for channel with priority 3
+// Defines Level 3 Arbitration for DMA channels
+// dmac_rrlvlen3
+#ifndef CONF_DMAC_RRLVLEN3
+#define CONF_DMAC_RRLVLEN3 0
+#endif
+
+// Level 3 Channel Priority Number <0x00-0xFF>
+// dmac_lvlpri3
+#ifndef CONF_DMAC_LVLPRI3
+#define CONF_DMAC_LVLPRI3 0
+#endif
+
+// Data Transfer Quality of Service
+// <0=> Background (no sensitive operation)
+// <1=> Sensitive bandwidth
+// <2=> Sensitive latency
+// <3=> Critical latency
+// Defines the memory priority access during the data transfer operation
+// dmac_dqos
+#ifndef CONF_DMAC_DQOS
+#define CONF_DMAC_DQOS 0
+#endif
+
+// Fetch Quality of Service
+// <0=> Background (no sensitive operation)
+// <1=> Sensitive bandwidth
+// <2=> Sensitive latency
+// <3=> Critical latency
+// Defines the memory priority access during the fetch operation
+// dmac_fqos
+#ifndef CONF_DMAC_FQOS
+#define CONF_DMAC_FQOS 0
+#endif
+
+// Write-Back Quality of Service
+// <0=> Background (no sensitive operation)
+// <1=> Sensitive bandwidth
+// <2=> Sensitive latency
+// <3=> Critical latency
+// Defines the memory priority access during the write-back operation
+// dmac_wrbqos
+#ifndef CONF_DMAC_WRBQOS
+#define CONF_DMAC_WRBQOS 0
+#endif
+
+// Debug Run
+// Indicates whether Debug Run is enabled or not
+// dmac_dbgrun
+#ifndef CONF_DMAC_DBGRUN
+#define CONF_DMAC_DBGRUN 0
+#endif
+
+// Channel 0 settings
+// dmac_channel_0_settings
+#ifndef CONF_DMAC_CHANNEL_0_SETTINGS
+#define CONF_DMAC_CHANNEL_0_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 0 is enabled or not
+// dmac_enable_0
+#ifndef CONF_DMAC_ENABLE_0
+#define CONF_DMAC_ENABLE_0 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 0 is running in standby mode or not
+// dmac_runstdby_0
+#ifndef CONF_DMAC_RUNSTDBY_0
+#define CONF_DMAC_RUNSTDBY_0 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_0
+#ifndef CONF_DMAC_TRIGACT_0
+#define CONF_DMAC_TRIGACT_0 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> TSENS Result Ready Trigger
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> CAN0 Debug Trigger
+// <0x0F=> CAN1 Debug Trigger
+// <0x10=> TCC0 Overflow Trigger
+// <0x11=> TCC0 Match/Compare 0 Trigger
+// <0x12=> TCC0 Match/Compare 1 Trigger
+// <0x13=> TCC0 Match/Compare 2 Trigger
+// <0x14=> TCC0 Match/Compare 3 Trigger
+// <0x15=> TCC1 Overflow Trigger
+// <0x16=> TCC1 Match/Compare 0 Trigger
+// <0x17=> TCC1 Match/Compare 1 Trigger
+// <0x18=> TCC2 Overflow Trigger
+// <0x19=> TCC2 Match/Compare 0 Trigger
+// <0x1A=> TCC2 Match/Compare 1 Trigger
+// <0x1B=> TC0 Overflow Trigger
+// <0x1C=> TC0 Match/Compare 0 Trigger
+// <0x1D=> TC0 Match/Compare 1 Trigger
+// <0x1E=> TC1 Overflow Trigger
+// <0x1F=> TC1 Match/Compare 0 Trigger
+// <0x20=> TC1 Match/Compare 1 Trigger
+// <0x21=> TC2 Overflow Trigger
+// <0x22=> TC2 Match/Compare 0 Trigger
+// <0x23=> TC2 Match/Compare 1 Trigger
+// <0x24=> TC3 Overflow Trigger
+// <0x25=> TC3 Match/Compare 0 Trigger
+// <0x26=> TC3 Match/Compare 1 Trigger
+// <0x27=> TC4 Overflow Trigger
+// <0x28=> TC4 Match/Compare 0 Trigger
+// <0x29=> TC4 Match/Compare 1 Trigger
+// <0x2A=> ADC0 Result Ready Trigger
+// <0x2B=> ADC1 Result Ready Trigger
+// <0x2C=> SDADC Result Ready Trigger
+// <0x2D=> DAC Empty Trigger
+// <0x2E=> PTC End of Conversion Trigger
+// <0x2F=> PTC Window Compare Trigger
+// <0x30=> PTC Sequence Trigger
+// <0x31=> SERCOM6 RX Trigger
+// <0x32=> SERCOM6 TX Trigger
+// <0x33=> SERCOM7 RX Trigger
+// <0x34=> SERCOM7 TX Trigger
+// <0x35=> TC5 Overflow Trigger
+// <0x36=> TC5 Match/Compare 0 Trigger
+// <0x37=> TC5 Match/Compare 1 Trigger
+// <0x38=> TC6 Overflow Trigger
+// <0x39=> TC6 Match/Compare 0 Trigger
+// <0x3A=> TC6 Match/Compare 1 Trigger
+// <0x3B=> TC7 Overflow Trigger
+// <0x3C=> TC7 Match/Compare 0 Trigger
+// <0x3D=> TC7 Match/Compare 1 Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_0
+#ifndef CONF_DMAC_TRIGSRC_0
+#define CONF_DMAC_TRIGSRC_0 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_0
+#ifndef CONF_DMAC_LVL_0
+#define CONF_DMAC_LVL_0 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+//