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fixing hall issue

This commit is contained in:
Nicolas Trimborn 2021-08-03 22:53:26 +02:00
parent 7938bfa26c
commit 79b54f286c
22 changed files with 15255 additions and 109 deletions
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3
2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/AtmelStart.gpdsc
View File

@ -111,6 +111,7 @@
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hpl/doc_lite/tc.rst"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_e51.h"/>
@ -201,6 +202,8 @@
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>

211
2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart
View File

@ -88,11 +88,11 @@ drivers:
functionality: ADC
api: HAL:Driver:ADC_Sync
configuration:
adc_advanced_settings: false
adc_advanced_settings: true
adc_arch_adjres: 0
adc_arch_corren: false
adc_arch_dbgrun: false
adc_arch_event_settings: false
adc_arch_event_settings: true
adc_arch_flushei: false
adc_arch_flushinv: false
adc_arch_gaincorr: 0
@ -101,9 +101,9 @@ drivers:
adc_arch_offsetcorr: 0
adc_arch_ondemand: false
adc_arch_refcomp: false
adc_arch_resrdyeo: false
adc_arch_resrdyeo: true
adc_arch_runstdby: false
adc_arch_samplen: 0
adc_arch_samplen: 3
adc_arch_samplenum: 1 sample
adc_arch_seqen: 0
adc_arch_startei: false
@ -112,11 +112,11 @@ drivers:
adc_arch_winmode: No window mode
adc_arch_winmoneo: false
adc_arch_winut: 0
adc_differential_mode: true
adc_differential_mode: false
adc_freerunning_mode: false
adc_pinmux_negative: ADC AIN0 pin
adc_pinmux_positive: ADC AIN1 pin
adc_prescaler: Peripheral clock divided by 2
adc_pinmux_negative: Internal ground
adc_pinmux_positive: ADC AIN6 pin
adc_prescaler: Peripheral clock divided by 8
adc_reference: External reference A
adc_resolution: 12-bit
optional_signals:
@ -189,24 +189,24 @@ drivers:
ccl_arch_invei_1: false
ccl_arch_invei_2: false
ccl_arch_invei_3: false
ccl_arch_lutctrl0: false
ccl_arch_lutctrl0: true
ccl_arch_lutctrl1: false
ccl_arch_lutctrl2: false
ccl_arch_lutctrl2: true
ccl_arch_lutctrl3: false
ccl_arch_lutei_0: false
ccl_arch_lutei_1: false
ccl_arch_lutei_2: false
ccl_arch_lutei_3: false
ccl_arch_luteo_0: false
ccl_arch_luteo_0: true
ccl_arch_luteo_1: false
ccl_arch_luteo_2: false
ccl_arch_luteo_3: false
ccl_arch_runstdby: false
ccl_arch_seqsel_0: Sequential logic is disabled
ccl_arch_seqsel_1: Sequential logic is disabled
ccl_arch_truth_0: 0
ccl_arch_truth_0: 150
ccl_arch_truth_1: 0
ccl_arch_truth_2: 0
ccl_arch_truth_2: 150
ccl_arch_truth_3: 0
ccl_e_persistance_0: ''
ccl_e_persistance_1: ''
@ -303,7 +303,7 @@ drivers:
dmac_beatsize_17: 8-bit bus transfer
dmac_beatsize_18: 8-bit bus transfer
dmac_beatsize_19: 8-bit bus transfer
dmac_beatsize_2: 8-bit bus transfer
dmac_beatsize_2: 32-bit bus transfer
dmac_beatsize_20: 8-bit bus transfer
dmac_beatsize_21: 8-bit bus transfer
dmac_beatsize_22: 8-bit bus transfer
@ -314,7 +314,7 @@ drivers:
dmac_beatsize_27: 8-bit bus transfer
dmac_beatsize_28: 8-bit bus transfer
dmac_beatsize_29: 8-bit bus transfer
dmac_beatsize_3: 8-bit bus transfer
dmac_beatsize_3: 16-bit bus transfer
dmac_beatsize_30: 8-bit bus transfer
dmac_beatsize_31: 8-bit bus transfer
dmac_beatsize_4: 8-bit bus transfer
@ -347,8 +347,7 @@ drivers:
in the transaction
dmac_blockact_19: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_2: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_2: Channel suspend operation is complete
dmac_blockact_20: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_21: Channel will be disabled if it is the last block transfer
@ -370,7 +369,7 @@ drivers:
dmac_blockact_29: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_3: Channel will be disabled if it is the last block transfer in
the transaction
the transaction and block interrupt
dmac_blockact_30: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_31: Channel will be disabled if it is the last block transfer
@ -409,10 +408,10 @@ drivers:
dmac_channel_27_settings: false
dmac_channel_28_settings: false
dmac_channel_29_settings: false
dmac_channel_2_settings: false
dmac_channel_2_settings: true
dmac_channel_30_settings: false
dmac_channel_31_settings: false
dmac_channel_3_settings: false
dmac_channel_3_settings: true
dmac_channel_4_settings: false
dmac_channel_5_settings: false
dmac_channel_6_settings: false
@ -443,7 +442,7 @@ drivers:
dmac_dstinc_27: false
dmac_dstinc_28: false
dmac_dstinc_29: false
dmac_dstinc_3: false
dmac_dstinc_3: true
dmac_dstinc_30: false
dmac_dstinc_31: false
dmac_dstinc_4: false
@ -452,7 +451,7 @@ drivers:
dmac_dstinc_7: false
dmac_dstinc_8: false
dmac_dstinc_9: false
dmac_enable: false
dmac_enable: true
dmac_evact_0: No action
dmac_evact_1: No action
dmac_evact_10: No action
@ -465,7 +464,7 @@ drivers:
dmac_evact_17: No action
dmac_evact_18: No action
dmac_evact_19: No action
dmac_evact_2: No action
dmac_evact_2: Channel resume operation
dmac_evact_20: No action
dmac_evact_21: No action
dmac_evact_22: No action
@ -497,7 +496,7 @@ drivers:
dmac_evie_17: false
dmac_evie_18: false
dmac_evie_19: false
dmac_evie_2: false
dmac_evie_2: true
dmac_evie_20: false
dmac_evie_21: false
dmac_evie_22: false
@ -669,7 +668,7 @@ drivers:
dmac_srcinc_17: false
dmac_srcinc_18: false
dmac_srcinc_19: false
dmac_srcinc_2: false
dmac_srcinc_2: true
dmac_srcinc_20: false
dmac_srcinc_21: false
dmac_srcinc_22: false
@ -701,7 +700,7 @@ drivers:
dmac_stepsel_17: Step size settings apply to the destination address
dmac_stepsel_18: Step size settings apply to the destination address
dmac_stepsel_19: Step size settings apply to the destination address
dmac_stepsel_2: Step size settings apply to the destination address
dmac_stepsel_2: Step size settings apply to the source address
dmac_stepsel_20: Step size settings apply to the destination address
dmac_stepsel_21: Step size settings apply to the destination address
dmac_stepsel_22: Step size settings apply to the destination address
@ -765,7 +764,7 @@ drivers:
dmac_trifsrc_17: Only software/event triggers
dmac_trifsrc_18: Only software/event triggers
dmac_trifsrc_19: Only software/event triggers
dmac_trifsrc_2: Only software/event triggers
dmac_trifsrc_2: ADC1 Sequencing Trigger
dmac_trifsrc_20: Only software/event triggers
dmac_trifsrc_21: Only software/event triggers
dmac_trifsrc_22: Only software/event triggers
@ -776,7 +775,7 @@ drivers:
dmac_trifsrc_27: Only software/event triggers
dmac_trifsrc_28: Only software/event triggers
dmac_trifsrc_29: Only software/event triggers
dmac_trifsrc_3: Only software/event triggers
dmac_trifsrc_3: ADC1 Result Ready Trigger
dmac_trifsrc_30: Only software/event triggers
dmac_trifsrc_31: Only software/event triggers
dmac_trifsrc_4: Only software/event triggers
@ -797,7 +796,7 @@ drivers:
dmac_trigact_17: One trigger required for each block transfer
dmac_trigact_18: One trigger required for each block transfer
dmac_trigact_19: One trigger required for each block transfer
dmac_trigact_2: One trigger required for each block transfer
dmac_trigact_2: One trigger required for each beat transfer
dmac_trigact_20: One trigger required for each block transfer
dmac_trigact_21: One trigger required for each block transfer
dmac_trigact_22: One trigger required for each block transfer
@ -808,7 +807,7 @@ drivers:
dmac_trigact_27: One trigger required for each block transfer
dmac_trigact_28: One trigger required for each block transfer
dmac_trigact_29: One trigger required for each block transfer
dmac_trigact_3: One trigger required for each block transfer
dmac_trigact_3: One trigger required for each beat transfer
dmac_trigact_30: One trigger required for each block transfer
dmac_trigact_31: One trigger required for each block transfer
dmac_trigact_4: One trigger required for each block transfer
@ -1031,10 +1030,10 @@ drivers:
evsys_channel_64: No channel output selected
evsys_channel_65: No channel output selected
evsys_channel_66: No channel output selected
evsys_channel_7: No channel output selected
evsys_channel_7: Channel 0
evsys_channel_8: No channel output selected
evsys_channel_9: No channel output selected
evsys_channel_setting_0: false
evsys_channel_setting_0: true
evsys_channel_setting_1: false
evsys_channel_setting_10: false
evsys_channel_setting_11: false
@ -1162,7 +1161,7 @@ drivers:
evsys_evd_7: false
evsys_evd_8: false
evsys_evd_9: false
evsys_evgen_0: No event generator
evsys_evgen_0: TCC0 overflow
evsys_evgen_1: No event generator
evsys_evgen_10: No event generator
evsys_evgen_11: No event generator
@ -1258,7 +1257,7 @@ drivers:
evsys_ovr_7: false
evsys_ovr_8: false
evsys_ovr_9: false
evsys_path_0: Synchronous path
evsys_path_0: Asynchronous path
evsys_path_1: Synchronous path
evsys_path_10: Synchronous path
evsys_path_11: Synchronous path
@ -1957,6 +1956,126 @@ drivers:
external_frequency: 0
configuration:
tc_gclk_selection: Generic clock generator 0
TC_SPEED_M1:
user_label: TC_SPEED_M1
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::TC2::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer
functionality: Timer
api: Lite:TC:Timer
configuration:
cc_cc0: 0
cc_cc1: 0
cc_control: false
count_control: false
count_count: 0
ctrla_alock: false
ctrla_capten0: true
ctrla_capten1: true
ctrla_captmode0: DEFAULT
ctrla_captmode1: DEFAULT
ctrla_control: true
ctrla_copen0: false
ctrla_copen1: false
ctrla_enable: true
ctrla_mode: 2
ctrla_ondemand: false
ctrla_prescaler: DIV4
ctrla_prescsync: GCLK
ctrla_runstdby: false
ctrlbset_cmd: NONE
ctrlbset_control: false
ctrlbset_dir: false
ctrlbset_lupd: false
ctrlbset_oneshot: false
ctrlc_inven0: false
ctrlc_inven1: false
dbgctrl_control: false
dbgctrl_dbgrun: false
drvctrl_control: false
evctrl_control: true
evctrl_evact: PPW
evctrl_mceo0: false
evctrl_mceo1: false
evctrl_ovfeo: true
evctrl_tcei: true
evctrl_tcinv: false
intenset_control: true
intenset_err: false
intenset_mc0: false
intenset_mc1: false
intenset_ovf: true
wave_control: true
wave_wavegen: NFRQ
optional_signals: []
variant: null
clocks:
domain_group:
nodes:
- name: TC
input: Generic clock generator 0
external: false
external_frequency: 0
configuration:
tc_gclk_selection: Generic clock generator 0
TC_SPEED_M2:
user_label: TC_SPEED_M2
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::TC4::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer
functionality: Timer
api: Lite:TC:Timer
configuration:
cc_cc0: 0
cc_cc1: 0
cc_control: false
count_control: false
count_count: 0
ctrla_alock: false
ctrla_capten0: true
ctrla_capten1: true
ctrla_captmode0: DEFAULT
ctrla_captmode1: DEFAULT
ctrla_control: true
ctrla_copen0: false
ctrla_copen1: false
ctrla_enable: true
ctrla_mode: 2
ctrla_ondemand: false
ctrla_prescaler: DIV4
ctrla_prescsync: GCLK
ctrla_runstdby: false
ctrlbset_cmd: NONE
ctrlbset_control: false
ctrlbset_dir: false
ctrlbset_lupd: false
ctrlbset_oneshot: false
ctrlc_inven0: false
ctrlc_inven1: false
dbgctrl_control: false
dbgctrl_dbgrun: false
drvctrl_control: false
evctrl_control: true
evctrl_evact: PPW
evctrl_mceo0: false
evctrl_mceo1: false
evctrl_ovfeo: true
evctrl_tcei: true
evctrl_tcinv: false
intenset_control: true
intenset_err: false
intenset_mc0: false
intenset_mc1: false
intenset_ovf: true
wave_control: true
wave_wavegen: NFRQ
optional_signals: []
variant: null
clocks:
domain_group:
nodes:
- name: TC
input: Generic clock generator 0
external: false
external_frequency: 0
configuration:
tc_gclk_selection: Generic clock generator 0
PWM_0:
user_label: PWM_0
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::TCC0::driver_config_definition::PWM::HAL:Driver:PWM
@ -1983,7 +2102,7 @@ drivers:
tcc_arch_dbgrun: false
tcc_arch_evact0: Event action disabled
tcc_arch_evact1: Event action disabled
tcc_arch_lupd: true
tcc_arch_lupd: false
tcc_arch_mcei0: false
tcc_arch_mcei1: false
tcc_arch_mcei2: false
@ -1996,21 +2115,21 @@ drivers:
tcc_arch_mceo3: false
tcc_arch_mceo4: false
tcc_arch_mceo5: false
tcc_arch_ovfeo: false
tcc_arch_ovfeo: true
tcc_arch_prescsync: Reload or reset counter on next GCLK
tcc_arch_runstdby: false
tcc_arch_sel_ch: 1
tcc_arch_sel_ch: 2
tcc_arch_tcei0: false
tcc_arch_tcei1: false
tcc_arch_tceinv0: false
tcc_arch_tceinv1: false
tcc_arch_trgeo: false
tcc_arch_wave_duty_val: 500
tcc_arch_wave_per_val: 1000
tcc_arch_wavegen: Single-slope PWM
tcc_arch_wave_per_val: 48
tcc_arch_wavegen: Dual-slope, interrupt/event at ZERO (DSBOTTOM)
tcc_per: 10000
tcc_prescaler: Divide by 8
timer_event_control: false
tcc_prescaler: Divide by 2
timer_event_control: true
optional_signals:
- identifier: PWM_0:WO/0
pad: PB12
@ -2097,21 +2216,21 @@ drivers:
tcc_arch_mceo1: false
tcc_arch_mceo2: false
tcc_arch_mceo3: false
tcc_arch_ovfeo: false
tcc_arch_ovfeo: true
tcc_arch_prescsync: Reload or reset counter on next GCLK
tcc_arch_runstdby: false
tcc_arch_sel_ch: 1
tcc_arch_sel_ch: 2
tcc_arch_tcei0: false
tcc_arch_tcei1: false
tcc_arch_tceinv0: false
tcc_arch_tceinv1: false
tcc_arch_trgeo: false
tcc_arch_wave_duty_val: 500
tcc_arch_wave_per_val: 1000
tcc_arch_wave_per_val: 48
tcc_arch_wavegen: Single-slope PWM
tcc_per: 10000
tcc_prescaler: Divide by 8
timer_event_control: false
tcc_prescaler: Divide by 2
timer_event_control: true
optional_signals:
- identifier: PWM_1:WO/0
pad: PA16

16
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_adc_config.h
View File

@ -339,7 +339,7 @@
// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
// <id> adc_prescaler
#ifndef CONF_ADC_1_PRESCALER
#define CONF_ADC_1_PRESCALER 0x0
#define CONF_ADC_1_PRESCALER 0x2
#endif
// <q> Free Running Mode
@ -353,7 +353,7 @@
// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
// <id> adc_differential_mode
#ifndef CONF_ADC_1_DIFFMODE
#define CONF_ADC_1_DIFFMODE 1
#define CONF_ADC_1_DIFFMODE 0
#endif
// <o> Positive Mux Input Selection
@ -383,7 +383,7 @@
// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
// <id> adc_pinmux_positive
#ifndef CONF_ADC_1_MUXPOS
#define CONF_ADC_1_MUXPOS 0x1
#define CONF_ADC_1_MUXPOS 0x6
#endif
// <o> Negative Mux Input Selection
@ -399,7 +399,7 @@
// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
// <id> adc_pinmux_negative
#ifndef CONF_ADC_1_MUXNEG
#define CONF_ADC_1_MUXNEG 0x0
#define CONF_ADC_1_MUXNEG 0x18
#endif
// </h>
@ -407,7 +407,7 @@
// <e> Advanced Configuration
// <id> adc_advanced_settings
#ifndef CONF_ADC_1_ADVANCED
#define CONF_ADC_1_ADVANCED 0
#define CONF_ADC_1_ADVANCED 1
#endif
// <q> Run in standby
@ -502,7 +502,7 @@
// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
// <id> adc_arch_samplen
#ifndef CONF_ADC_1_SAMPLEN
#define CONF_ADC_1_SAMPLEN 0
#define CONF_ADC_1_SAMPLEN 3
#endif
// <o> Window Monitor Mode
@ -543,7 +543,7 @@
// <e> Event Control
// <id> adc_arch_event_settings
#ifndef CONF_ADC_1_EVENT_CONTROL
#define CONF_ADC_1_EVENT_CONTROL 0
#define CONF_ADC_1_EVENT_CONTROL 1
#endif
// <q> Window Monitor Event Out
@ -557,7 +557,7 @@
// <i> Enables event output on result ready event (RESRDEO)
// <id> adc_arch_resrdyeo
#ifndef CONF_ADC_1_RESRDYEO
#define CONF_ADC_1_RESRDYEO 0
#define CONF_ADC_1_RESRDYEO 1
#endif
// <q> Invert flush Event Signal

10
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_ccl_config.h
View File

@ -32,14 +32,14 @@
// <i> Enable and setup the lookup table module 0
// <id> ccl_arch_lutctrl0
#ifndef CONF_CCL_LUTCTRL_EN_0
#define CONF_CCL_LUTCTRL_EN_0 0
#define CONF_CCL_LUTCTRL_EN_0 1
#endif
// <o> Truth Table <0x00-0xFF>
// <i> Define the value of truth logic according to inputs IN[2:0]
// <id> ccl_arch_truth_0
#ifndef CONF_CCL_TRUTH_0
#define CONF_CCL_TRUTH_0 0x0
#define CONF_CCL_TRUTH_0 0x96
#endif
// <o> Input Source Selection 0
@ -110,7 +110,7 @@
// <q> Event output enable
// <id> ccl_arch_luteo_0
#ifndef CONF_CCL_LUTEO_0
#define CONF_CCL_LUTEO_0 0
#define CONF_CCL_LUTEO_0 1
#endif
// <q> Event input enable
@ -258,14 +258,14 @@
// <i> Enable and setup the lookup table module 2
// <id> ccl_arch_lutctrl2
#ifndef CONF_CCL_LUTCTRL_EN_2
#define CONF_CCL_LUTCTRL_EN_2 0
#define CONF_CCL_LUTCTRL_EN_2 1
#endif
// <o> Truth Table <0x00-0xFF>
// <i> Define the value of truth logic according to inputs IN[2:0]
// <id> ccl_arch_truth_2
#ifndef CONF_CCL_TRUTH_2
#define CONF_CCL_TRUTH_2 0x0
#define CONF_CCL_TRUTH_2 0x96
#endif
// <o> Input Source Selection 0

32
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_dmac_config.h
View File

@ -8,7 +8,7 @@
// <i> Indicates whether dmac is enabled or not
// <id> dmac_enable
#ifndef CONF_DMAC_ENABLE
#define CONF_DMAC_ENABLE 0
#define CONF_DMAC_ENABLE 1
#endif
// <q> Priority Level 0
@ -553,7 +553,7 @@
// <e> Channel 2 settings
// <id> dmac_channel_2_settings
#ifndef CONF_DMAC_CHANNEL_2_SETTINGS
#define CONF_DMAC_CHANNEL_2_SETTINGS 0
#define CONF_DMAC_CHANNEL_2_SETTINGS 1
#endif
// <q> Channel Run in Standby
@ -570,7 +570,7 @@
// <i> Defines the trigger action used for a transfer
// <id> dmac_trigact_2
#ifndef CONF_DMAC_TRIGACT_2
#define CONF_DMAC_TRIGACT_2 0
#define CONF_DMAC_TRIGACT_2 2
#endif
// <o> Trigger source
@ -662,7 +662,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_2
#ifndef CONF_DMAC_TRIGSRC_2
#define CONF_DMAC_TRIGSRC_2 0
#define CONF_DMAC_TRIGSRC_2 71
#endif
// <o> Channel Arbitration Level
@ -687,7 +687,7 @@
// <i> Indicates whether channel event reception is enabled or not
// <id> dmac_evie_2
#ifndef CONF_DMAC_EVIE_2
#define CONF_DMAC_EVIE_2 0
#define CONF_DMAC_EVIE_2 1
#endif
// <o> Event Input Action
@ -701,7 +701,7 @@
// <i> Defines the event input action
// <id> dmac_evact_2
#ifndef CONF_DMAC_EVACT_2
#define CONF_DMAC_EVACT_2 0
#define CONF_DMAC_EVACT_2 5
#endif
// <o> Address Increment Step Size
@ -725,14 +725,14 @@
// <i> Defines whether source or destination addresses are using the step size settings
// <id> dmac_stepsel_2
#ifndef CONF_DMAC_STEPSEL_2
#define CONF_DMAC_STEPSEL_2 0
#define CONF_DMAC_STEPSEL_2 1
#endif
// <q> Source Address Increment
// <i> Indicates whether the source address incrementation is enabled or not
// <id> dmac_srcinc_2
#ifndef CONF_DMAC_SRCINC_2
#define CONF_DMAC_SRCINC_2 0
#define CONF_DMAC_SRCINC_2 1
#endif
// <q> Destination Address Increment
@ -749,7 +749,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_2
#ifndef CONF_DMAC_BEATSIZE_2
#define CONF_DMAC_BEATSIZE_2 0
#define CONF_DMAC_BEATSIZE_2 2
#endif
// <o> Block Action
@ -760,7 +760,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_2
#ifndef CONF_DMAC_BLOCKACT_2
#define CONF_DMAC_BLOCKACT_2 0
#define CONF_DMAC_BLOCKACT_2 2
#endif
// <o> Event Output Selection
@ -777,7 +777,7 @@
// <e> Channel 3 settings
// <id> dmac_channel_3_settings
#ifndef CONF_DMAC_CHANNEL_3_SETTINGS
#define CONF_DMAC_CHANNEL_3_SETTINGS 0
#define CONF_DMAC_CHANNEL_3_SETTINGS 1
#endif
// <q> Channel Run in Standby
@ -794,7 +794,7 @@
// <i> Defines the trigger action used for a transfer
// <id> dmac_trigact_3
#ifndef CONF_DMAC_TRIGACT_3
#define CONF_DMAC_TRIGACT_3 0
#define CONF_DMAC_TRIGACT_3 2
#endif
// <o> Trigger source
@ -886,7 +886,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_3
#ifndef CONF_DMAC_TRIGSRC_3
#define CONF_DMAC_TRIGSRC_3 0
#define CONF_DMAC_TRIGSRC_3 70
#endif
// <o> Channel Arbitration Level
@ -963,7 +963,7 @@
// <i> Indicates whether the destination address incrementation is enabled or not
// <id> dmac_dstinc_3
#ifndef CONF_DMAC_DSTINC_3
#define CONF_DMAC_DSTINC_3 0
#define CONF_DMAC_DSTINC_3 1
#endif
// <o> Beat Size
@ -973,7 +973,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_3
#ifndef CONF_DMAC_BEATSIZE_3
#define CONF_DMAC_BEATSIZE_3 0
#define CONF_DMAC_BEATSIZE_3 1
#endif
// <o> Block Action
@ -984,7 +984,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_3
#ifndef CONF_DMAC_BLOCKACT_3
#define CONF_DMAC_BLOCKACT_3 0
#define CONF_DMAC_BLOCKACT_3 1
#endif
// <o> Event Output Selection

8
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_evsys_config.h
View File

@ -7,7 +7,7 @@
// <e> Channel 0 settings
// <id> evsys_channel_setting_0
#ifndef CONF_EVSYS_CHANNEL_SETTINGS_0
#define CONF_EVSYS_CHANNEL_SETTINGS_0 0
#define CONF_EVSYS_CHANNEL_SETTINGS_0 1
#endif
// <y> Edge detection
@ -28,7 +28,7 @@
// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
// <id> evsys_path_0
#ifndef CONF_PATH_0
#define CONF_PATH_0 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
#define CONF_PATH_0 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
#endif
// <o> Event generator
@ -152,7 +152,7 @@
// <0x77=>CCL LUT output 3
// <id> evsys_evgen_0
#ifndef CONF_EVGEN_0
#define CONF_EVGEN_0 0
#define CONF_EVGEN_0 41
#endif
// <q> Overrun channel interrupt
@ -6122,7 +6122,7 @@
// <id> evsys_channel_7
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_7
#define CONF_CHANNEL_7 0
#define CONF_CHANNEL_7 1
#endif
// <o> Channel selection for DMAC channel 3

24
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_tcc_config.h
View File

@ -26,7 +26,7 @@
// <i> This defines the TCC0 prescaler value
// <id> tcc_prescaler
#ifndef CONF_TCC0_PRESCALER
#define CONF_TCC0_PRESCALER TCC_CTRLA_PRESCALER_DIV8_Val
#define CONF_TCC0_PRESCALER TCC_CTRLA_PRESCALER_DIV2_Val
#endif
// <hidden>
@ -44,7 +44,7 @@
// <i> The unit of this value is us.
// <id> tcc_arch_wave_per_val
#ifndef CONF_TCC0_WAVE_PER_VAL
#define CONF_TCC0_WAVE_PER_VAL 0x3e8
#define CONF_TCC0_WAVE_PER_VAL 0x30
#endif
// <o> TCC0 Waveform Duty Value (0.1%) <0x00-0x03E8>
@ -59,7 +59,7 @@
// <i> Give index of the Compare Channel register here in 0x00-0x05 range.
// <id> tcc_arch_sel_ch
#ifndef CONF_TCC0_SEL_CH
#define CONF_TCC0_SEL_CH 0x1
#define CONF_TCC0_SEL_CH 0x2
#endif
/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
@ -111,7 +111,7 @@
// <TCC_WAVE_WAVEGEN_DSTOP_Val"> Dual-slope, interrupt/event at Top (DSTOP)
// <id> tcc_arch_wavegen
#ifndef CONF_TCC0_WAVEGEN
#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_NPWM_Val
#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_DSBOTTOM_Val
#endif
// <q> TCC0 Auto Lock
// <i> Indicates whether the TCC0 Auto Lock is enabled or not
@ -183,7 +183,7 @@
// <i> Indicates whether the TCC0 Lock update is enabled or not
// <id> tcc_arch_lupd
#ifndef CONF_TCC0_LUPD
#define CONF_TCC0_LUPD 1
#define CONF_TCC0_LUPD 0
#endif
/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL B register.
@ -266,7 +266,7 @@
// <e> Event control
// <id> timer_event_control
#ifndef CONF_TCC0_EVENT_CONTROL_ENABLE
#define CONF_TCC0_EVENT_CONTROL_ENABLE 0
#define CONF_TCC0_EVENT_CONTROL_ENABLE 1
#endif
// <q> Match or Capture Channel 0 Event Output
@ -393,7 +393,7 @@
// <i> This bit is used to enable enable event on overflow/underflow.
//<id> tcc_arch_ovfeo
#ifndef CONF_TCC0_OVFEO
#define CONF_TCC0_OVFEO 0
#define CONF_TCC0_OVFEO 1
#endif
// <o> Timer/Counter Interrupt and Event Output Selection
@ -603,7 +603,7 @@
// <i> This defines the TCC1 prescaler value
// <id> tcc_prescaler
#ifndef CONF_TCC1_PRESCALER
#define CONF_TCC1_PRESCALER TCC_CTRLA_PRESCALER_DIV8_Val
#define CONF_TCC1_PRESCALER TCC_CTRLA_PRESCALER_DIV2_Val
#endif
// <hidden>
@ -621,7 +621,7 @@
// <i> The unit of this value is us.
// <id> tcc_arch_wave_per_val
#ifndef CONF_TCC1_WAVE_PER_VAL
#define CONF_TCC1_WAVE_PER_VAL 0x3e8
#define CONF_TCC1_WAVE_PER_VAL 0x30
#endif
// <o> TCC1 Waveform Duty Value (0.1%) <0x00-0x03E8>
@ -636,7 +636,7 @@
// <i> Give index of the Compare Channel register here in 0x00-0x03 range.
// <id> tcc_arch_sel_ch
#ifndef CONF_TCC1_SEL_CH
#define CONF_TCC1_SEL_CH 0x1
#define CONF_TCC1_SEL_CH 0x2
#endif
/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
@ -845,7 +845,7 @@
// <e> Event control
// <id> timer_event_control
#ifndef CONF_TCC1_EVENT_CONTROL_ENABLE
#define CONF_TCC1_EVENT_CONTROL_ENABLE 0
#define CONF_TCC1_EVENT_CONTROL_ENABLE 1
#endif
// <q> Match or Capture Channel 0 Event Output
@ -946,7 +946,7 @@
// <i> This bit is used to enable enable event on overflow/underflow.
//<id> tcc_arch_ovfeo
#ifndef CONF_TCC1_OVFEO
#define CONF_TCC1_OVFEO 0
#define CONF_TCC1_OVFEO 1
#endif
// <o> Timer/Counter Interrupt and Event Output Selection

80
2_Motor_Master/Motor_Master/Motor_Master/Config/peripheral_clk_config.h
View File

@ -944,6 +944,86 @@
#define CONF_GCLK_TC0_FREQUENCY 120000000
#endif
// <y> TC Clock Source
// <id> tc_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for TC.
#ifndef CONF_GCLK_TC2_SRC
#define CONF_GCLK_TC2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_TC2_FREQUENCY
* \brief TC2's Clock frequency
*/
#ifndef CONF_GCLK_TC2_FREQUENCY
#define CONF_GCLK_TC2_FREQUENCY 120000000
#endif
// <y> TC Clock Source
// <id> tc_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for TC.
#ifndef CONF_GCLK_TC4_SRC
#define CONF_GCLK_TC4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_TC4_FREQUENCY
* \brief TC4's Clock frequency
*/
#ifndef CONF_GCLK_TC4_FREQUENCY
#define CONF_GCLK_TC4_FREQUENCY 120000000
#endif
// <y> TCC Clock Source
// <id> tcc_gclk_selection

57
2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj
View File

@ -150,8 +150,8 @@
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@ -293,10 +295,12 @@
<armgcc.linker.libraries.Libraries>
<ListValues>
<Value>libm</Value>
<Value>libarm_cortexM4lf_math.a</Value>
</ListValues>
</armgcc.linker.libraries.Libraries>
<armgcc.linker.libraries.LibrarySearchPaths>
<ListValues>
<Value>C:\Users\Nick-XMG\Documents\github\bldc_control_thesis\bldc_firmware_thesis\2_Motor_Master\Motor_Master\Motor_Master\cmsis</Value>
<Value>%24(ProjectDir)\Device_Startup</Value>
</ListValues>
</armgcc.linker.libraries.LibrarySearchPaths>
@ -376,11 +380,13 @@
<armgcc.compiler.symbols.DefSymbols>
<ListValues>
<Value>DEBUG</Value>
<Value>ARM_MATH_CM4=1</Value>
</ListValues>
</armgcc.compiler.symbols.DefSymbols>
<armgcc.compiler.directories.IncludePaths>
<ListValues>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -405,30 +411,33 @@
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
</ListValues>
</armgcc.compiler.directories.IncludePaths>
<armgcc.compiler.optimization.level>Optimize debugging experience (-Og)</armgcc.compiler.optimization.level>
<armgcc.compiler.optimization.level>Optimize (-O1)</armgcc.compiler.optimization.level>
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<Value>libarm_cortexM4lf_math.a</Value>
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<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
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<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -453,13 +462,13 @@
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
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</armgcc.assembler.general.IncludePaths>
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<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
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<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -484,7 +493,6 @@
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
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@ -492,6 +500,9 @@
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<ItemGroup>
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<SubType>compile</SubType>
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@ -507,6 +518,9 @@
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@ -909,6 +923,12 @@
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@ -1023,6 +1043,9 @@
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<SubType>compile</SubType>
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<Compile Include="main.c">
<SubType>compile</SubType>
</Compile>
@ -1044,6 +1067,7 @@
<Folder Include="hpl\cmcc\" />
<Folder Include="hpl\core\" />
<Folder Include="hpl\dmac\" />
<Folder Include="hpl\doc_lite\" />
<Folder Include="hpl\eic\" />
<Folder Include="hpl\evsys\" />
<Folder Include="hpl\gclk\" />
@ -1093,6 +1117,9 @@
<None Include="hal\documentation\timer.rst">
<SubType>compile</SubType>
</None>
<None Include="hpl\doc_lite\tc.rst">
<SubType>compile</SubType>
</None>
</ItemGroup>
<Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
</Project>

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69
2_Motor_Master/Motor_Master/Motor_Master/bldc.h
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@ -9,6 +9,73 @@
#ifndef BLDC_H_
#define BLDC_H_
// ----------------------------------------------------------------------
// header files
// ----------------------------------------------------------------------
#include "atmel_start.h"
#include "arm_math.h"
static uint32_t adc_seq_regs[5] = {0x1800, 0x1806, 0x1807, 0x1808, 0x1809};
static volatile uint16_t adc_res[5] = {0};
static volatile bool adc_dma_done = 0;
struct _dma_resource *adc_sram_dma_resource;
struct _dma_resource *adc_dmac_sequence_resource;
// ----------------------------------------------------------------------
// Type Definitions
// ----------------------------------------------------------------------
volatile typedef struct
{
volatile float32_t A; // Phase A
volatile float32_t B; // Phase B
volatile float32_t C; // Phase C
volatile float32_t Bus; // Currently Active Phase Current
} MOTOR_3PHASES_t;
volatile typedef struct
{
volatile int16_t A; // Phase A measured offset
volatile int16_t B; // Phase B measured offset
} MOTOR_phase_offset_t;
volatile typedef struct timerflags
{
volatile bool pwm_cycle_tic;
volatile bool current_loop_tic;
volatile bool control_loop_tic;
volatile bool adc_readings_ready_tic;
volatile bool motor_telemetry_flag;
} TIMERflags_t;
volatile typedef struct
{
volatile uint8_t desiredDirection; //! The desired direction of rotation.
volatile uint8_t directionOffset;
volatile float32_t desired_torque;
volatile int16_t desired_speed;
volatile int16_t desired_position;
volatile float32_t max_torque;
volatile float32_t max_current;
volatile int16_t max_velocity;
} MOTOR_Setpoints;
volatile typedef struct
{
volatile uint8_t actualDirection; //! The actual direction of rotation.
volatile uint16_t duty_cycle;
volatile float32_t calc_rpm;
volatile int32_t Num_Steps;
/* Hall States */
volatile uint8_t prevHallPattern;
volatile uint8_t currentHallPattern;
volatile uint8_t nextHallPattern;
/* Commutation State */
volatile uint8_t cur_comm_step;
volatile uint8_t prev_comm_step;
} MOTOR_Status;
// ----------------------------------------------------------------------
// M1 Hall Parameters
// ----------------------------------------------------------------------
@ -86,7 +153,7 @@ static inline uint8_t readM2Hall(void)
volatile uint8_t b = gpio_get_pin_level(M2_HALL_B_PIN);
volatile uint8_t c = gpio_get_pin_level(M2_HALL_C_PIN);
return ((a << 2) |
return ((a << 2) |
(b << 1) |
(c << 0));
}

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BIN
2_Motor_Master/Motor_Master/Motor_Master/cmsis/libarm_cortexM4lf_math.a Normal file
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119
2_Motor_Master/Motor_Master/Motor_Master/configuration.h Normal file
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@ -0,0 +1,119 @@
/*
* configuration.h
*
* Created: 02/08/2021 21:15:49
* Author: Nick-XMG
*/
#ifndef CONFIGURATION_H_
#define CONFIGURATION_H_
// ----------------------------------------------------------------------
// Header Files
// ----------------------------------------------------------------------
#include "bldc.h"
#include "interrupts.h"
#define DMAC_CHANNEL_ADC_SEQ 2U
#define DMAC_CHANNEL_ADC_SRAM 3U
inline static void configure_tcc_pwm(void)
{
/* TCC0 */
//hri_tcc_set_WEXCTRL_OTMX_bf(TCC0, 0);
//hri_tcc_set_WAVE_POL0_bit(TCC0);
//hri_tcc_set_WAVE_POL1_bit(TCC0);
//hri_tcc_set_WAVE_POL2_bit(TCC0);
//hri_tcc_set_WAVE_POL3_bit(TCC0);
//hri_tcc_set_WAVE_POL4_bit(TCC0);
//hri_tcc_set_WAVE_POL5_bit(TCC0);
//hri_tcc_write_CC_CC_bf(TCC0, 0, 0);
//hri_tcc_write_CC_CC_bf(TCC0, 1, 0);
//hri_tcc_write_CC_CC_bf(TCC0, 2, 0);
//hri_tcc_write_CC_CC_bf(TCC0, 3, 0);
//hri_tcc_write_CC_CC_bf(TCC0, 4, 0);
//hri_tcc_write_CC_CC_bf(TCC0, 5, 0);
hri_tcc_write_PER_reg(TCC0,1200);
hri_tcc_write_CTRLA_ENABLE_bit(TCC0, 1 << TCC_CTRLA_ENABLE_Pos);
/* TCC1 */
//hri_tcc_set_WEXCTRL_OTMX_bf(TCC1, 3);
//hri_tcc_write_CC_CC_bf(TCC1, 0, 0);
//hri_tcc_write_CC_CC_bf(TCC1, 1, 0);
//hri_tcc_write_CC_CC_bf(TCC1, 2, 0);
//hri_tcc_write_CC_CC_bf(TCC1, 3, 0);
////hri_tcc_write_CC_CC_bf(TCC1, 0, 0);
//
////pwm_set_parameters(&TCC_PWM, 1000, 250);
//hri_tcc_set_WAVE_POL0_bit(TCC1);
//hri_tcc_set_WAVE_POL1_bit(TCC1);
//hri_tcc_set_WAVE_POL2_bit(TCC1);
//hri_tcc_set_WAVE_POL3_bit(TCC1);
//hri_tcc_set_WAVE_POL4_bit(TCC1);
//hri_tcc_set_WAVE_POL5_bit(TCC1);
hri_tcc_write_PER_reg(TCC1,1200);
hri_tcc_clear_CTRLA_ENABLE_bit(TCC1);
hri_tcc_write_CTRLA_MSYNC_bit(TCC1, true);
//hri_tcc_write_CTRLA_ENABLE_bit(TCC1, 1 << TCC_CTRLA_ENABLE_Pos); /* Enable: enabled */
//pwm_register_callback(&PWM_0, PWM_PERIOD_CB, pwm_cb);
pwm_enable(&PWM_0);
pwm_enable(&PWM_1);
}
inline void configure_adc(void)
{
adc_sync_enable_channel(&ADC_1, 0);
//adc_sync_enable_channel(&ADC_1, 0);
//adc_async_register_callback(&ADC_0, 0, ADC_ASYNC_CONVERT_CB, adc_cb);
//adc_async_register_callback(&ADC_1, 0, ADC_ASYNC_CONVERT_CB, convert_cb_ADC_1);
//adc_async_start_conversion(&ADC_0);
//adc_async_start_conversion(&ADC_1);
}
inline static void adc_init_dma(void)
{
adc_sram_dmac_init();
adc_dmac_sequence_init();
hri_adc_set_DSEQCTRL_INPUTCTRL_bit(ADC1);
hri_adc_set_DSEQCTRL_AUTOSTART_bit(ADC1);
}
inline void adc_dmac_sequence_init()
{
/* Configure the DMAC source address, destination address,
* next descriptor address, data count and Enable the DMAC Channel
*/
_dma_set_source_address(DMAC_CHANNEL_ADC_SEQ, (const void *)adc_seq_regs);
_dma_set_destination_address(DMAC_CHANNEL_ADC_SEQ, (const void *)&ADC1->DSEQDATA.reg);
_dma_set_data_amount(DMAC_CHANNEL_ADC_SEQ, 5);
_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SEQ, DMAC_CHANNEL_ADC_SEQ);
_dma_enable_transaction(DMAC_CHANNEL_ADC_SEQ, false);
//_dma_get_channel_resource(&adc_dmac_sequence_resource, DMAC_CHANNEL_ADC_SEQ);
//adc_dmac_sequence_resource[0].dma_cb.error = dummy2;
//adc_dmac_sequence_resource[0].dma_cb.suspend = dummy3;
//adc_dmac_sequence_resource[0].dma_cb.transfer_done = dummy4;
hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[DMAC_CHANNEL_ADC_SEQ], 0x01); //Suspend
}
inline void adc_sram_dmac_init()
{
/* Configure the DMAC source address, destination address,
* next descriptor address, data count and Enable the DMAC Channel */
_dma_set_source_address(DMAC_CHANNEL_ADC_SRAM, (const void *)&ADC1->RESULT.reg);
_dma_set_destination_address(DMAC_CHANNEL_ADC_SRAM, (const void *)adc_res);
_dma_set_data_amount(DMAC_CHANNEL_ADC_SRAM, 5);
_dma_set_irq_state(DMAC_CHANNEL_ADC_SRAM, DMA_TRANSFER_COMPLETE_CB, true);
_dma_get_channel_resource(&adc_sram_dma_resource, DMAC_CHANNEL_ADC_SRAM);
adc_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback;
_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SRAM, DMAC_CHANNEL_ADC_SRAM);
_dma_enable_transaction(DMAC_CHANNEL_ADC_SRAM, false);
}
#endif /* CONFIGURATION_H_ */

31
2_Motor_Master/Motor_Master/Motor_Master/driver_init.c
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@ -98,16 +98,22 @@ void DIGITAL_GLUE_LOGIC_0_PORT_init(void)
{
gpio_set_pin_function(M1_HALLA, PINMUX_PA04N_CCL_IN0);
gpio_set_pin_pull_mode(M1_HALLA, GPIO_PULL_UP);
gpio_set_pin_function(M1_HALLB, PINMUX_PA05N_CCL_IN1);
gpio_set_pin_pull_mode(M1_HALLB, GPIO_PULL_UP);
gpio_set_pin_function(M1_HALLC, PINMUX_PA06N_CCL_IN2);
gpio_set_pin_pull_mode(M1_HALLC, GPIO_PULL_UP);
gpio_set_pin_function(M2_HALLA, PINMUX_PA22N_CCL_IN6);
gpio_set_pin_pull_mode(M2_HALLA, GPIO_PULL_UP);
gpio_set_pin_function(M2_HALLB, PINMUX_PA23N_CCL_IN7);
gpio_set_pin_pull_mode(M2_HALLB, GPIO_PULL_UP);
gpio_set_pin_function(M2_HALLC, PINMUX_PA24N_CCL_IN8);
gpio_set_pin_pull_mode(M2_HALLC, GPIO_PULL_UP);
}
void DIGITAL_GLUE_LOGIC_0_CLOCK_init(void)
@ -172,6 +178,7 @@ void EXTERNAL_IRQ_0_init(void)
void EVENT_SYSTEM_0_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_0, CONF_GCLK_EVSYS_CHANNEL_0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);
@ -583,6 +590,22 @@ static void TIMER_0_init(void)
timer_init(&TIMER_0, TC0, _tc_get_timer());
}
void TC_SPEED_M1_CLOCK_init(void)
{
hri_mclk_set_APBBMASK_TC2_bit(MCLK);
hri_mclk_set_APBBMASK_TC3_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TC2_GCLK_ID, CONF_GCLK_TC2_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}
void TC_SPEED_M2_CLOCK_init(void)
{
hri_mclk_set_APBCMASK_TC4_bit(MCLK);
hri_mclk_set_APBCMASK_TC5_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TC4_GCLK_ID, CONF_GCLK_TC4_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}
void PWM_0_PORT_init(void)
{
@ -720,6 +743,14 @@ void system_init(void)
SPI_3_init();
TIMER_0_init();
TC_SPEED_M1_CLOCK_init();
TC_SPEED_M1_init();
TC_SPEED_M2_CLOCK_init();
TC_SPEED_M2_init();
PWM_0_init();
PWM_1_init();

10
2_Motor_Master/Motor_Master/Motor_Master/driver_init.h
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@ -39,6 +39,8 @@ extern "C" {
#include <hal_spi_m_sync.h>
#include <hal_timer.h>
#include <hpl_tc_base.h>
#include <tc_lite.h>
#include <tc_lite.h>
#include <hal_pwm.h>
#include <hpl_tcc.h>
@ -89,6 +91,14 @@ void SPI_3_PORT_init(void);
void SPI_3_CLOCK_init(void);
void SPI_3_init(void);
void TC_SPEED_M1_CLOCK_init(void);
int8_t TC_SPEED_M1_init(void);
void TC_SPEED_M2_CLOCK_init(void);
int8_t TC_SPEED_M2_init(void);
void PWM_0_PORT_init(void);
void PWM_0_CLOCK_init(void);
void PWM_0_init(void);

39
2_Motor_Master/Motor_Master/Motor_Master/hpl/doc_lite/tc.rst Normal file
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@ -0,0 +1,39 @@
=========
TC driver
=========
The TC consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to count events, or it can be configured to count clock pulses. The counter, together with the compare/capture channels, can be configured to timestamp input events, allowing capture of frequency and pulse width. It can also perform waveform generation, such as frequency generation and pulse-width modulation (PWM)
The timer/counter is clocked by the peripheral clock with optional prescaling or from the event system.
Features
--------
* Initialization
Applications
------------
* Frequency Generation
* Single-slope PWM (pulse width modulation)
* Dual-slope PWM
* Count on event
* Quadrature decoding
Dependencies
------------
* CLK for clock
* CPUINT/PMIC for Interrupt
* EVSYS for events
* UPDI/PDI/JTAG for debug
* PORT for Waveform Generation
Concurrency
-----------
N/A
Limitations
-----------
N/A
Knows issues and workarounds
----------------------------
N/A

10
2_Motor_Master/Motor_Master/Motor_Master/hpl/tc/hpl_tc.c
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@ -127,6 +127,10 @@ static struct tc_configuration _tcs[] = {
static struct _timer_device *_tc0_dev = NULL;
static struct _pwm_device *_tc2_dev = NULL;
static struct _pwm_device *_tc4_dev = NULL;
static int8_t get_tc_index(const void *const hw);
static void _tc_init_irq_param(const void *const hw, void *dev);
static inline uint8_t _get_hardware_offset(const void *const hw);
@ -325,6 +329,12 @@ static void _tc_init_irq_param(const void *const hw, void *dev)
if (hw == TC0) {
_tc0_dev = (struct _timer_device *)dev;
}
if (hw == TC2) {
_tc2_dev = (struct _pwm_device *)dev;
}
if (hw == TC4) {
_tc4_dev = (struct _pwm_device *)dev;
}
}
/**

171
2_Motor_Master/Motor_Master/Motor_Master/hpl/tc/tc_lite.c Normal file
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@ -0,0 +1,171 @@
/**
* \file
*
* \brief TC related functionality implementation.
*
* Copyright (c) 2017 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "tc_lite.h"
/**
* \brief Initialize TC interface
*/
int8_t TC_SPEED_M1_init()
{
if (!hri_tc_is_syncing(TC2, TC_SYNCBUSY_SWRST)) {
if (hri_tc_get_CTRLA_reg(TC2, TC_CTRLA_ENABLE)) {
hri_tc_clear_CTRLA_ENABLE_bit(TC2);
hri_tc_wait_for_sync(TC2, TC_SYNCBUSY_ENABLE);
}
hri_tc_write_CTRLA_reg(TC2, TC_CTRLA_SWRST);
}
hri_tc_wait_for_sync(TC2, TC_SYNCBUSY_SWRST);
hri_tc_write_CTRLA_reg(TC2,
0 << TC_CTRLA_CAPTMODE0_Pos /* Capture mode Channel 0: 0 */
| 0 << TC_CTRLA_CAPTMODE1_Pos /* Capture mode Channel 1: 0 */
| 0 << TC_CTRLA_COPEN0_Pos /* Capture Pin 0 Enable: disabled */
| 0 << TC_CTRLA_COPEN1_Pos /* Capture Pin 1 Enable: disabled */
| 1 << TC_CTRLA_CAPTEN0_Pos /* Capture Channel 0 Enable: enabled */
| 1 << TC_CTRLA_CAPTEN1_Pos /* Capture Channel 1 Enable: enabled */
| 0 << TC_CTRLA_ALOCK_Pos /* Auto Lock: disabled */
| 0 << TC_CTRLA_PRESCSYNC_Pos /* Prescaler and Counter Synchronization: 0 */
| 0 << TC_CTRLA_ONDEMAND_Pos /* Clock On Demand: disabled */
| 0 << TC_CTRLA_RUNSTDBY_Pos /* Run in Standby: disabled */
| 2 << TC_CTRLA_PRESCALER_Pos /* Setting: 2 */
| 0x2 << TC_CTRLA_MODE_Pos); /* Operating Mode: 0x2 */
hri_tc_write_CTRLB_reg(TC2,
0 << TC_CTRLBSET_CMD_Pos /* Command: 0 */
| 0 << TC_CTRLBSET_ONESHOT_Pos /* One-Shot: disabled */
| 0 << TC_CTRLBCLR_LUPD_Pos /* Setting: disabled */
| 0 << TC_CTRLBSET_DIR_Pos); /* Counter Direction: disabled */
// hri_tc_write_WAVE_reg(TC2,0); /* Waveform Generation Mode: 0 */
// hri_tc_write_DRVCTRL_reg(TC2,0 << TC_DRVCTRL_INVEN1_Pos /* Output Waveform 1 Invert Enable: disabled */
// | 0 << TC_DRVCTRL_INVEN0_Pos); /* Output Waveform 0 Invert Enable: disabled */
// hri_tc_write_DBGCTRL_reg(TC2,0); /* Run in debug: 0 */
// hri_tccount32_write_CC_reg(TC2, 0 ,0x0); /* Compare/Capture Value: 0x0 */
// hri_tccount32_write_CC_reg(TC2, 1 ,0x0); /* Compare/Capture Value: 0x0 */
// hri_tccount32_write_COUNT_reg(TC2,0x0); /* Counter Value: 0x0 */
hri_tc_write_EVCTRL_reg(
TC2,
0 << TC_EVCTRL_MCEO0_Pos /* Match or Capture Channel 0 Event Output Enable: disabled */
| 0 << TC_EVCTRL_MCEO1_Pos /* Match or Capture Channel 1 Event Output Enable: disabled */
| 1 << TC_EVCTRL_OVFEO_Pos /* Overflow/Underflow Event Output Enable: enabled */
| 1 << TC_EVCTRL_TCEI_Pos /* TC Event Input: enabled */
| 0 << TC_EVCTRL_TCINV_Pos /* TC Inverted Event Input: disabled */
| 5); /* Event Action: 5 */
hri_tc_write_INTEN_reg(TC2,
0 << TC_INTENSET_MC0_Pos /* Match or Capture Channel 0 Interrupt Enable: disabled */
| 0 << TC_INTENSET_MC1_Pos /* Match or Capture Channel 1 Interrupt Enable: disabled */
| 0 << TC_INTENSET_ERR_Pos /* Error Interrupt Enable: disabled */
| 1 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: enabled */
hri_tc_write_CTRLA_ENABLE_bit(TC2, 1 << TC_CTRLA_ENABLE_Pos); /* Enable: enabled */
return 0;
}
/**
* \brief Initialize TC interface
*/
int8_t TC_SPEED_M2_init()
{
if (!hri_tc_is_syncing(TC4, TC_SYNCBUSY_SWRST)) {
if (hri_tc_get_CTRLA_reg(TC4, TC_CTRLA_ENABLE)) {
hri_tc_clear_CTRLA_ENABLE_bit(TC4);
hri_tc_wait_for_sync(TC4, TC_SYNCBUSY_ENABLE);
}
hri_tc_write_CTRLA_reg(TC4, TC_CTRLA_SWRST);
}
hri_tc_wait_for_sync(TC4, TC_SYNCBUSY_SWRST);
hri_tc_write_CTRLA_reg(TC4,
0 << TC_CTRLA_CAPTMODE0_Pos /* Capture mode Channel 0: 0 */
| 0 << TC_CTRLA_CAPTMODE1_Pos /* Capture mode Channel 1: 0 */
| 0 << TC_CTRLA_COPEN0_Pos /* Capture Pin 0 Enable: disabled */
| 0 << TC_CTRLA_COPEN1_Pos /* Capture Pin 1 Enable: disabled */
| 1 << TC_CTRLA_CAPTEN0_Pos /* Capture Channel 0 Enable: enabled */
| 1 << TC_CTRLA_CAPTEN1_Pos /* Capture Channel 1 Enable: enabled */
| 0 << TC_CTRLA_ALOCK_Pos /* Auto Lock: disabled */
| 0 << TC_CTRLA_PRESCSYNC_Pos /* Prescaler and Counter Synchronization: 0 */
| 0 << TC_CTRLA_ONDEMAND_Pos /* Clock On Demand: disabled */
| 0 << TC_CTRLA_RUNSTDBY_Pos /* Run in Standby: disabled */
| 2 << TC_CTRLA_PRESCALER_Pos /* Setting: 2 */
| 0x2 << TC_CTRLA_MODE_Pos); /* Operating Mode: 0x2 */
hri_tc_write_CTRLB_reg(TC4,
0 << TC_CTRLBSET_CMD_Pos /* Command: 0 */
| 0 << TC_CTRLBSET_ONESHOT_Pos /* One-Shot: disabled */
| 0 << TC_CTRLBCLR_LUPD_Pos /* Setting: disabled */
| 0 << TC_CTRLBSET_DIR_Pos); /* Counter Direction: disabled */
// hri_tc_write_WAVE_reg(TC4,0); /* Waveform Generation Mode: 0 */
// hri_tc_write_DRVCTRL_reg(TC4,0 << TC_DRVCTRL_INVEN1_Pos /* Output Waveform 1 Invert Enable: disabled */
// | 0 << TC_DRVCTRL_INVEN0_Pos); /* Output Waveform 0 Invert Enable: disabled */
// hri_tc_write_DBGCTRL_reg(TC4,0); /* Run in debug: 0 */
// hri_tccount32_write_CC_reg(TC4, 0 ,0x0); /* Compare/Capture Value: 0x0 */
// hri_tccount32_write_CC_reg(TC4, 1 ,0x0); /* Compare/Capture Value: 0x0 */
// hri_tccount32_write_COUNT_reg(TC4,0x0); /* Counter Value: 0x0 */
hri_tc_write_EVCTRL_reg(
TC4,
0 << TC_EVCTRL_MCEO0_Pos /* Match or Capture Channel 0 Event Output Enable: disabled */
| 0 << TC_EVCTRL_MCEO1_Pos /* Match or Capture Channel 1 Event Output Enable: disabled */
| 1 << TC_EVCTRL_OVFEO_Pos /* Overflow/Underflow Event Output Enable: enabled */
| 1 << TC_EVCTRL_TCEI_Pos /* TC Event Input: enabled */
| 0 << TC_EVCTRL_TCINV_Pos /* TC Inverted Event Input: disabled */
| 5); /* Event Action: 5 */
hri_tc_write_INTEN_reg(TC4,
0 << TC_INTENSET_MC0_Pos /* Match or Capture Channel 0 Interrupt Enable: disabled */
| 0 << TC_INTENSET_MC1_Pos /* Match or Capture Channel 1 Interrupt Enable: disabled */
| 0 << TC_INTENSET_ERR_Pos /* Error Interrupt Enable: disabled */
| 1 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: enabled */
hri_tc_write_CTRLA_ENABLE_bit(TC4, 1 << TC_CTRLA_ENABLE_Pos); /* Enable: enabled */
return 0;
}

70
2_Motor_Master/Motor_Master/Motor_Master/hpl/tc/tc_lite.h Normal file
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@ -0,0 +1,70 @@
/**
* \file
*
* \brief TC related functionality declaration.
*
* Copyright (c) 2017 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _TC_H_INCLUDED
#define _TC_H_INCLUDED
#include <compiler.h>
#include <utils_assert.h>
/**
* \addtogroup tc driver
*
* \section tc Revision History
* - v0.0.0.1 Initial Commit
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Initialize tc interface
* \return Initialization status.
*/
int8_t TC_SPEED_M1_init();
/**
* \brief Initialize tc interface
* \return Initialization status.
*/
int8_t TC_SPEED_M2_init();
#ifdef __cplusplus
}
#endif
#endif /* _TC_H_INCLUDED */

68
2_Motor_Master/Motor_Master/Motor_Master/interrupts.h Normal file
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@ -0,0 +1,68 @@
/*
* interrupts.h
*
* Created: 02/08/2021 21:54:14
* Author: Nick-XMG
*/
#ifndef INTERRUPTS_H_
#define INTERRUPTS_H_
// ----------------------------------------------------------------------
// ADC Callback for Motor Phase Current Measurement.
// Phase A & B Sampled and converted from LSB to Process Unit PU(Amps)
// ----------------------------------------------------------------------
static void pwm_cb(const struct pwm_descriptor *const descr)
{
//tic_port(DEBUG_2_PORT);
volatile uint8_t x = 1;
}
void adc_sram_dma_callback(struct _dma_resource *adc_dma_res)
{
volatile uint8_t x = 1;
//tic_port(DEBUG_2_PORT);
//Motor1.timerflags.adc_readings_ready_tic = true;
//tic_port(DEBUG_2_PORT);
//toc_port(DEBUG_2_PORT);
//tic_port(DEBUG_3_PORT);
//tic_port(DEBUG_3_PORT);
//volatile int16_t phase_A_current_raw;
//volatile int16_t phase_B_current_raw;
//
///* Motor 1 */
//phase_A_current_raw = (adc_res[0] - Motor1.Voffset_lsb.A);
//phase_B_current_raw = (adc_res[1] - Motor1.Voffset_lsb.B)*-1;
//// Covert from LSB to PU (A) and filter out small readings
//Motor1.Iphase_pu.A = phase_A_current_raw * LSB_TO_PU;
//Motor1.Iphase_pu.B = phase_B_current_raw * LSB_TO_PU;
//// i_c = -i_a - i_b because i_a + i_b + i_c = 0
//Motor1.Iphase_pu.C = -Motor1.Iphase_pu.A - Motor1.Iphase_pu.B;
/* Motor 2 */
//phase_A_current_raw = (adc_res[2] - Motor2.Voffset_lsb.A);
//phase_B_current_raw = (adc_res[3] - Motor2.Voffset_lsb.B)*-1;
//Motor2.Iphase_pu.A = phase_A_current_raw * LSB_TO_PU;
//Motor2.Iphase_pu.B = phase_B_current_raw * LSB_TO_PU;
//// i_c = -i_a - i_b because i_a + i_b + i_c = 0
//Motor2.Iphase_pu.C = -Motor2.Iphase_pu.A - Motor2.Iphase_pu.B;
//
///* Motor 3 */
//phase_A_current_raw = (adc_res[4] - Motor3.Voffset_lsb.A);
//phase_B_current_raw = (adc_res[5] - Motor3.Voffset_lsb.B)*-1;
//Motor3.Iphase_pu.A = phase_A_current_raw * LSB_TO_PU;
//Motor3.Iphase_pu.B = phase_B_current_raw * LSB_TO_PU;
//// i_c = -i_a - i_b because i_a + i_b + i_c = 0
//Motor3.Iphase_pu.C = -Motor3.Iphase_pu.A - Motor3.Iphase_pu.B;
// Set Current Loop Flag
//Motor1.timerflags.current_loop_tic = true;
//toc_port(DEBUG_3_PORT);
}
#endif /* INTERRUPTS_H_ */

22
2_Motor_Master/Motor_Master/Motor_Master/main.c
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@ -1,7 +1,13 @@
#include <atmel_start.h>
// ----------------------------------------------------------------------
// Header Files
// ----------------------------------------------------------------------
#include "bldc.h"
#include "EtherCAT_QSPI.h"
#include "EtherCAT_SlaveDef.h"
#include "configuration.h"
#include "interrupts.h"
/**
* Example of using TIMER_0.
@ -25,6 +31,15 @@ void One_ms_timer_init(void)
timer_start(&TIMER_0);
}
void enable_NVIC_IRQ(void)
{
//NVIC_EnableIRQ(TC7_IRQn); // TC7: TC_ECAT
//NVIC_EnableIRQ(TC0_IRQn); // TC0: TC_SPEED
NVIC_EnableIRQ(DMAC_0_IRQn);
NVIC_EnableIRQ(TCC1_0_IRQn);
NVIC_EnableIRQ(TCC1_0_IRQn);
//NVIC_EnableIRQ(EIC_5_IRQn);
}
int main(void)
{
@ -32,9 +47,12 @@ int main(void)
/* Initializes MCU, drivers and middleware */
atmel_start_init();
config_qspi();
ECAT_STATE_MACHINE();
One_ms_timer_init();
configure_tcc_pwm();
adc_sync_enable_channel(&ADC_1, 0);
adc_init_dma();
ECAT_STATE_MACHINE();
enable_NVIC_IRQ();
/* Replace with your application code */
while (1) {